JP4830619B2 - Integrated semiconductor optical device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an integrated semiconductor optical device in which a plurality of semiconductor optical devices are integrated, and a manufacturing method thereof.

In an integrated semiconductor optical device, a plurality of integrated semiconductor optical devices are required to be optically coupled and electrically separated. Each optical element has an active layer, an n-type cladding layer and a p-type cladding layer sandwiching the active layer, and operates as a light emitting device by applying a forward bias voltage, or receives light by applying a reverse bias voltage. Operate as a device or modulation device. When an n-type InP substrate is used as a substrate on which these layers are mounted, a common n-type electrode is provided on the lower surface of the substrate, and a p-type electrode for each optical element is formed on the p-type cladding layer of each optical element. Are formed individually. At this time, the p-type claddings of the respective optical elements need to be electrically separated from each other, but need to be optically continuous. For this reason, techniques for electrically separating the p-type cladding layer have been proposed in the past (see, for example, Patent Documents 1 and 2).
JP-A-8-335745 JP-A 64-28984

  In Patent Document 1, ions such as protons and Fe are implanted into one region of a single p-type semiconductor layer to form defect levels, and carriers in that region are deactivated to increase resistance. The two p-type cladding layers separated from each other are formed. However, if ion implantation is performed, defects are introduced into the semiconductor crystal and reliability is impaired.

  In Patent Document 2, a recess (isolation region) is provided in a p-type semiconductor crystal such as Fe-doped InP, and two electrically isolated p-type cladding layers are formed by embedding and growing a high-resistance semiconductor in the recess. Form. However, the refractive index discontinuity occurs in the waveguide structure in the process of etching for forming the isolation region and buried growth, and the optical scattering loss increases. In addition, since the number of crystal growth steps increases, the manufacturing process becomes complicated.

  Therefore, an object of the present invention is to provide an integrated semiconductor optical device that can be manufactured by a simple process and that can easily obtain high reliability and low light scattering loss, and a manufacturing method thereof.

  One aspect of the present invention relates to an integrated semiconductor optical device comprising a substrate and first and second semiconductor optical devices provided on the substrate. The first semiconductor optical device has a first active layer formed on one main surface of the substrate. The second semiconductor optical device has a second active layer formed on the main surface and adjacent to the first active layer. On the first and second active layers, an InP layer having a lower refractive index than that of the first and second active layers and doped with Zn is formed. The InP layer includes a first p-type cladding region that at least partially covers the first active layer, a second p-type cladding region that at least partially covers the second active layer, and first and second And an element isolation region interposed between the p-type cladding regions. This element isolation region contains Zn combined with H, and has a higher resistance than each of the first and second p-type cladding regions.

In this integrated semiconductor optical device, a plurality of regions in the InP layer doped with Zn are the first and second p-type cladding regions and the element isolation region. For this reason, a continuous InP layer doped with Zn is formed on the first and second active layers, and H is bonded to Zn in a region to be an element isolation region of the InP layer. An isolation region and first and second p-type cladding regions can be formed. The introduction of H can be realized by exposing only the portion of the InP layer to be the element isolation region to AsH ₃ and heating it at an appropriate temperature. Since there is no need to use a process of introducing crystal defects into the InP layer, such as ion implantation, this integrated semiconductor optical device can easily obtain high reliability. Further, in order to form the element isolation region, it is not necessary to form a groove in the InP layer to be the clad or to grow a high resistance semiconductor layer in the groove. Therefore, this integrated semiconductor optical device can be manufactured by a simple process and without causing a refractive index discontinuity in the waveguide structure, and therefore it is easy to suppress light scattering loss.

  The integrated semiconductor optical device according to the present invention may further include an n-type semiconductor layer formed on the device isolation region.

  Since this n-type semiconductor layer suppresses the desorption of H from the element isolation region made of the p-type semiconductor, the integrated semiconductor optical device is less likely to decrease the resistance of the element isolation region even when exposed to high temperatures. Excellent thermal stability. When a relatively large amount of Zn not bonded to H is contained in the element isolation region, the element isolation region may behave as a weak p-type semiconductor. However, even in this case, a pn junction is formed between the n-type semiconductor layer on the element isolation region and the element isolation region, and the element isolation region is depleted, so that the resistance of the element isolation region is sufficiently high. As a result, the first p-type cladding layer and the second p-type cladding layer can be electrically separated satisfactorily.

Another aspect of the present invention relates to a method of manufacturing an integrated semiconductor optical device having a first semiconductor optical device including a first active layer and a second semiconductor optical device including a second active layer. In this method, a first active layer and a second active layer are formed adjacent to each other on one main surface of a substrate, and the first active layer and the second active layer are formed on the first active layer and the second active layer. Forming a Zn-doped InP layer having a low refractive index, element isolation regions of the InP layer are disposed on both sides of the region, and the first and second active layers are respectively formed And a step of increasing the resistance higher than each of the first and second regions that are at least partially covered. The step of increasing the resistance of the element isolation region includes a step of heating the element isolation region to a temperature of 500 ° C. or lower while exposing the region for element isolation to AsH ₃ gas or PH ₃ gas.

When an element isolation region is exposed to AsH ₃ gas or PH ₃ gas and heated, H is introduced into the region, and the H is combined with Zn to deactivate Zn. As a result, the element isolation region has a high resistance, so that the first and second regions located on both sides of the element isolation region can be electrically isolated. Thus, the first and second regions can be used as the p-type cladding layers for the first and second semiconductor optical devices, respectively. Since it is not necessary to use a process for introducing defects into the InP layer, such as ion implantation, in order to introduce H into the InP layer, an integrated semiconductor optical device having high reliability can be manufactured. Further, it is not necessary to form a groove in the InP layer to be the cladding or to grow a high resistance semiconductor layer in the groove in order to obtain a device isolation region with a high resistance. For this reason, an integrated semiconductor optical device can be manufactured by a simple process and without causing a refractive index discontinuity in the waveguide structure, and light scattering loss can be easily suppressed.

  In the method according to the present invention, after the step of forming the InP layer and before the step of increasing the resistance of the element isolation region, the metal first p is formed on the InP layer above the first active layer. The method may further include forming a mold electrode and forming a metal second p-type electrode spaced apart from the first p-type electrode on the InP layer and above the second active layer. In the step of increasing the resistance of the element isolation region, the region exposed from the gap between the first and second p-type electrodes in the InP layer may be heated as the element isolation region.

  Since the metal blocks H, by using a metal p-type electrode as a mask, H can be introduced only into the element isolation region and the resistance can be increased. Since it is not necessary to form a mask separately from the first and second p-type electrodes, the integrated semiconductor optical device can be manufactured with fewer steps.

  The step of increasing the resistance of the element isolation region includes heating the element isolation region and then forming an n-type semiconductor layer on the element isolation region. A step of desorbing H from the first and second regions described above while suppressing desorption of H from the region.

  Due to the desorption of H from the first and second regions, the element isolation region has a higher resistance than the first and second regions. Since the n-type semiconductor layer suppresses the desorption of H from the element isolation region, the integrated semiconductor optical device having excellent thermal stability can be obtained without decreasing the resistance of the region even when exposed to a high temperature. It is done. When a relatively large amount of Zn that is not bonded to H is contained in the element isolation region, the region may behave as a weak p-type semiconductor. However, even in this case, since a pn junction is formed between the n-type semiconductor layer on the element isolation region and the element isolation region, and the region is depleted, the resistance of the region becomes sufficiently high. . As a result, it is possible to obtain two p-type cladding layers that are electrically well separated. Therefore, an integrated semiconductor optical device having a sufficiently high isolation resistance can be manufactured with a high yield.

  In this method, after the step of increasing the resistance of the element isolation region, the first p-type electrode located above the first active layer and the second p-type located above the second active layer You may further provide the process of forming an electrode on an InP layer. The first and second p-type electrodes are separated from each other so as to sandwich an element isolation region when the first and second p-type electrodes are viewed along a direction perpendicular to the main surface of the substrate. You may do it.

  By forming the first and second p-type electrodes so as to sandwich the element isolation region, the first and second semiconductor optical devices can be appropriately electrically separated.

  According to the present invention, it is possible to provide an integrated semiconductor optical device that can be manufactured by a simple process and that can easily obtain high reliability and low light scattering loss, and a manufacturing method thereof.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

First Embodiment FIG. 1 is a perspective view showing an integrated semiconductor optical device 100 according to a first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view taken along line AA of FIG. This integrated semiconductor optical device 100 has a structure in which two semiconductor optical devices 21 and 22 are integrated on the same substrate 11. Both of these semiconductor optical elements have a waveguide structure, and transmit light from one optical element to the other optical element. Examples of the semiconductor optical elements 21 and 22 include a semiconductor laser element, a photodetector, and an optical modulator.

  The first semiconductor optical device 21 has an active layer 12a, a p-type cladding layer 14a, and a contact layer 15a that are sequentially formed on one main surface (hereinafter, “upper surface”) of the substrate 11. Similarly, the second semiconductor optical device 22 includes an active layer 12b, a p-type cladding layer 14b, and a contact layer 15b that are sequentially formed on the upper surface of the substrate 11. The p-type cladding layers 14a and 14b are two regions separated from each other in the continuous InP layer 14 that covers the entire upper surfaces of the active layers 12a and 12b. Between the p-type cladding layers 14a and 14b, an element isolation region 14c having a higher resistance than those of the cladding layers 14a and 14b is interposed. The element isolation region 14c is disposed on the active layer 12b.

  Each of these active layers, InP layers, and contact layers has a stripe shape. The active layers 12 a and 12 b are adjacent to each other on the upper surface of the substrate 11 with their end faces facing each other. The p-type cladding layer 14a entirely covers the active layer 12a, but the p-type cladding layer 14b covers a portion of the active layer 12b excluding the end adjacent to the active layer 12a. The contact layers 15 a and 15 b are separated from each other through the groove 33. As shown in FIG. 1, semi-insulating buried layers 16 are provided on both sides of a laminated structure composed of these active layers, cladding layers, and contact layers.

  The substrate 11 is made of n-type InP doped with Sn as an n-type impurity (donor). The active layers 12a and 12b are made of compound semiconductors suitable for the optical elements 21 and 22, respectively. The InP layer 14 (and the regions 14a to 14c in the InP layer 14) is made of p-type InP doped with Zn as a p-type impurity (acceptor). Both contact layers 15a and 15b are made of p-type GaInAs doped with Zn as an acceptor. The buried layer 16 is made of InP doped with Fe. Hereinafter, Zn-doped InP is represented as Zn—InP, Zn-doped GaInAs is represented as Zn—GaInAs, and Fe-doped InP is represented as Fe—InP.

  The InP layer 14 has a uniform refractive index. Therefore, the refractive indexes of the p-type cladding layers 14a and 14b and the element isolation region 14c are the same. The active layer 12a and the active layer 12b also have substantially the same refractive index, and both are optically coupled to each other. The active layers 12 a and 12 b have a higher refractive index than the substrate 11 and the InP layer 14. The p-type cladding layer 14a and the surface layer portion of the substrate 11 located below the active layer 12a function as an upper cladding and a lower cladding, respectively, and exert an optical confinement effect with the active layer 12a sandwiched from above and below. Therefore, these upper clad and lower clad and the active layer 12a constitute an optical waveguide. Similarly, the p-type cladding layer 14b and the surface layer portion of the substrate 11 located below the active layer 12b function as an upper cladding and a lower cladding that exert an optical confinement function with the active layer 12b sandwiched from above and below, These upper clad and lower clad and the active layer 12b constitute an optical waveguide. These two optical waveguides are optically coupled to each other.

Upper surface of the contact layer 15a is covered with the protective film 17a made of SiO _2. The protective film 17a is provided with an opening 34a that penetrates the protective film 17a. A p-type electrode 18a is formed on the protective film 17a so as to fill the opening 34 and come into contact with the contact layer 15a. Similarly, the upper surface of the contact layer 15b is covered by a protective film 17b made of SiO _2, the on the protective film 17b, as to fill the opening 34b extending through the protective film 17b in contact with the contact layer 15b A p-type electrode 18b is formed. The protective films 17a and 17b are insulative and are separated from each other. The p-type electrodes 18a and 18b are also separated from each other and are therefore electrically separated. The p-type electrodes 18a and 18b are both made of metal. This metal may be an alloy.

  On the other main surface (hereinafter referred to as “lower surface”) of the substrate 11, an n-type electrode 20 that covers substantially the entire lower surface is formed. The n-type electrode 20 continuously extends so as to overlap both the p-type electrodes 18a and 18b when the n-type electrode 20 is viewed along a direction perpendicular to the lower surface of the substrate 11. The n-type electrode 20 is made of metal. This metal may be an alloy.

  As described above, the element isolation region 14c for electrically isolating the first semiconductor optical element 21 and the second semiconductor optical element 22 is interposed between the p-type cladding layers 14a and 14b. . In the present embodiment, the element isolation region 14c is formed on the end of the active layer 12b adjacent to the active layer 12a. The element isolation region 14c is made of InP containing Zn bonded to H. That is, in the InP layer 14 doped with Zn, the region where H is bonded to Zn is the element isolation region 14c. Hereinafter, Zn—InP into which H has been introduced is referred to as Zn—H—InP.

  Since Zn as an acceptor is inactivated by bonding with H, the element isolation region 14c has an electric resistance sufficiently higher than each of the p-type cladding layers 14a and 14b in which H is not bonded to Zn. Have. For this reason, the p-type cladding layers 14a and 14b are electrically isolated by the element isolation region 14c.

As described above, the integrated semiconductor optical device 100 has a sufficiently high isolation resistance between the first semiconductor optical device 21 and the second semiconductor optical device 22. In the present embodiment, the element isolation region 14c has an approximate thickness of 2 μm, a width of 2 μm, and a length of 30 μm. Generally, when the doping density of Zn in the p-type InP layer is 2 × 10 ¹⁸ cm ⁻³ , the resistance of the region of this dimension in the p-type InP layer is about 4 kΩ. When the doping density becomes 2 × 10 ¹⁷ cm ⁻³ due to inactivation of Zn by H, the resistance in that region increases to 40 kΩ. If the potential difference between the two semiconductor optical elements 21 and 22 is 2 V, the current flowing between these optical elements is 0.05 mA. This means that the current flowing between the two optical elements can be suppressed to about 1/100 of the driving current of the semiconductor laser element.

  In the integrated semiconductor optical device 100, three regions in the Zn—InP layer 14 are p-type cladding regions 14a and 14b and an element isolation region 14c. For this reason, a continuous Zn—InP layer is formed on the active layers 12a and 12b, and H is bonded to Zn only in a region of the Zn—InP layer that is to be the element isolation region 14c. 14c and p-type cladding regions 14a and 14b can be formed. As will be described later, since the introduction of H into the Zn—InP layer does not require the use of a process for introducing crystal defects into the InP layer, such as ion implantation, the integrated semiconductor optical device 100 has high reliability. Cheap. Further, it is not necessary to form a groove in the InP layer or to grow a high-resistance semiconductor layer in the groove in order to form the element isolation region 14c. Therefore, the integrated semiconductor optical device 100 can be manufactured by a simple process and without causing a refractive index discontinuity in the waveguide structure, and therefore it is easy to suppress light scattering loss.

  Below, the manufacturing method of the integrated semiconductor optical element 100 is demonstrated, referring FIGS. 3-11. Here, FIGS. 3 to 5, 8, 10, and 11 are longitudinal sectional views showing the manufacturing process, and FIGS. 6, 7, and 9 are perspective views showing the manufacturing process. Reference is also made to FIG. 1 and FIG. 2 as necessary.

First, as shown in FIG. 3, after the active layer 12 having the same structure as that of the active layer 12a for the first semiconductor optical device 21 is grown on the entire upper surface of the substrate 11, only the portion for forming the active layer 12a is formed. A mask layer 30 made of SiO ₂ is formed on the active layer 12 so as to cover it. Next, as shown in FIG. 4, a portion of the active layer 12 that is not covered with the mask layer 30 is removed by etching, and the second semiconductor optical device 22 is formed on the upper surface of the substrate 11 exposed by the etching. The active layer 12b is grown. Subsequently, as shown in FIG. 5, after removing the mask layer 30, the Zn—InP layer 14 and the Zn—GaInAs layer 15 are continuously grown so as to cover the entire upper surfaces of the active layers 12 a and 12 b.

  In order to satisfactorily optically couple the semiconductor optical device 21 and the semiconductor optical device 22, it is preferable that there is no change in the refractive index in the Zn-InP layer 14 to be the cladding layer. Therefore, the Zn—InP layer 14 is desirably grown with a uniform thickness by a single growth process.

Next, as shown in FIG. 6, a striped SiO ₂ mask layer 31 is formed across both active layers 12 a and 12 b, and the upper surface of the substrate 11 is exposed at a portion not covered by the mask layer 31. Etch until Thus, a stripe-shaped semiconductor multilayer structure 24 is formed. The semiconductor multilayer structure 24 includes an optical waveguide extending from one end of the substrate 11 to the other end.

  Thereafter, as shown in FIG. 7, semi-insulating Fe—InP is grown on both sides of the semiconductor multilayer structure 24 on the upper surface of the substrate 11 to form a buried layer 16. The upper surface of the buried layer 16 is substantially flush with the upper surface of the Zn—GaInAs layer 15.

The buried layer 16 is grown at a temperature of about 600 ° C. using a vapor phase growth apparatus. During this growth, PH ₃ gas is supplied to the reaction chamber of the apparatus together with other source gas and H ₂ gas (carrier gas). Thereafter, in order to prevent the desorption of P from the buried layer 16, the temperature in the device is lowered to about 300 ° C. while continuing the inflow of PH ₃ and H ₂ . PH ₃ has a property of supplying H bonded to Zn in InP, but the property is weaker than AsH ₃ described later. For this reason, the degree of inactivation of Zn in the Zn-InP layer 14 by H during the growth of the buried layer 16 is relatively small. Therefore, a predetermined region of the Zn-InP layer 14 has a sufficient electric conductivity. A high p-type cladding can be obtained.

In order to suppress the inactivation due to H as much as possible, it is desirable to stop the supply of PH ₃ when the temperature falls to 500 ° C., and lower the temperature while supplying only H ₂ into the reaction chamber. This is because H is easily introduced into the InP layer 14 at a temperature of 500 ° C. or lower.

Next, after forming a SiO ₂ film on the entire top surface of the Zn—GaInAs layer 15, as shown in FIG. 8, a groove 32 is formed so as to divide the SiO ₂ film, and the protective films 17a and 17b described above are formed. Get. The groove 32 is located above the end of the active layer 12b adjacent to the active layer 12a, and one end of the groove 32 is disposed almost directly above the boundary between the active layer 12a and the active layer 12b. .

  Subsequently, as illustrated in FIG. 9, rectangular openings 34 a and 34 b are formed in the protective films 17 a and 17 b, respectively, and the upper surface of the Zn—GaInAs layer 15 is exposed. The openings 34a and 34b extend along the longitudinal direction of the active layers 12a and 12b, respectively. As shown in FIG. 10, p-type electrodes 18a and 18b are formed on the protective films 17a and 17b, respectively, so as to fill the openings 34a and 34b. These p-type electrodes 18a and 18b are in contact with the upper surface of the Zn—GaInAs layer 15 through the openings 34a and 34b.

  Further, as shown in FIG. 10, a portion of the Zn—GaInAs layer 15 exposed from the groove 32 is removed by etching. For this etching, an etchant having selectivity with InP, that is, an etchant that etches GaInAs but does not etch InP is used. Examples of such an etching solution include a mixed solution of phosphoric acid, hydrogen peroxide solution, and water. By this etching, the above-described groove 33 is formed in the Zn—GaInAs layer 15, and the Zn—GaInAs layer 15 is divided into two, thereby obtaining contact layers 15a and 15b.

Thereafter, the substrate 11 is carried into a heating furnace, and the Zn—InP layer 14 is heated at a temperature of 300 ° C. to 500 ° C. in an AsH ₃ atmosphere. By such heat treatment, H separated from AsH ₃ enters the Zn—InP crystal and is bonded to the Zn atom in the Zn—InP crystal to form a Zn—H bond. Almost the same number of H atoms as Zn doped therein are introduced into the InP crystal, and accordingly, the carrier concentration of the InP crystal is reduced by about one digit. This is because Zn bonded to H is inactivated and does not function as an acceptor. According to this heat treatment, excess H is not introduced, and crystal defects that occur during ion implantation do not occur, so the reliability of the InP crystal can be maintained.

In the present embodiment, the region exposed from the trench 33 in the Zn—InP layer 14 is heated while being exposed to the AsH ₃ gas. Accordingly, H is introduced into the region, the H and Zn are combined to deactivate Zn, and the resistance of the region is increased. Thus, the element isolation region 14c is formed as shown in FIG.

  Introduction of H into the Zn—InP layer 14 excluding the element isolation region 14c is blocked by the metal p-type electrodes 18a and 18b. Therefore, H is not introduced into the regions 14a and 14b covered with the p-type electrodes 18a and 18b in the Zn—InP layer 14, and high electrical conductivity is maintained. Thus, the p-type cladding layers 14a and 14b spatially and electrically separated by the element isolation region 14c are formed below the p-type electrodes 18a and 18b, respectively (see FIG. 11).

  Thereafter, as shown in FIG. 2, the n-type electrode 20 is formed on almost the entire lower surface of the substrate 11. Note that when Zn—H—InP is heated at a temperature higher than 500 ° C., H is easily detached from Zn—H—InP. Accordingly, when the n-type electrode 20 is subjected to heat treatment, the temperature of the heat treatment is desirably 500 ° C. or less, and if it is 300 ° C. or less, desorption of H can be prevented more reliably.

  Below, the advantage of the manufacturing method of this embodiment is demonstrated. In this method, since the element isolation region 14c is formed by increasing the resistance of a part of Zn—InP by introducing H, the integrated semiconductor optical device 100 having a sufficiently high isolation resistance can be manufactured. Since this method of forming the element isolation region 14c does not require a step of introducing crystal defects into the InP layer such as ion implantation, the integrated semiconductor optical device 100 having high reliability can be manufactured. Further, in order to form the element isolation region 14c, it is not necessary to form a groove in the InP layer to be the clad or to grow a high resistance semiconductor layer in the groove. For this reason, the integrated semiconductor optical device 100 can be manufactured by a simple process and without causing a refractive index discontinuity in the waveguide structure, and therefore, the light scattering loss of the integrated semiconductor optical device 100 can be easily suppressed.

  Furthermore, in this embodiment, since the p-type electrodes 18a and 18b are used as a mask for preventing introduction of H into the p-type cladding layers 14a and 14b, the number of steps is smaller than that of a method of separately forming a mask. The integrated semiconductor optical device 100 can be manufactured.

Second Embodiment FIG. 12 is a perspective view showing an integrated semiconductor optical device 200 according to a second embodiment of the present invention, and FIG. 13 is a longitudinal sectional view taken along line AA of FIG. In the integrated semiconductor optical device 200, the n-type semiconductor layer 40 is formed on the upper surface of the element isolation region 14c, and the continuous protective film 17 is formed instead of the protective films 17a and 17b that are separated from each other. Different from the integrated semiconductor optical device 100. The n-type semiconductor layer 40 is made of GaInAs doped with Si. Other configurations are the same as those of the integrated semiconductor optical device 100.

  The integrated semiconductor optical device 200 has the following advantages in addition to the same advantages as the integrated semiconductor optical device 100. In general, when Zn—H—InP introduced with high resistance by introducing H is exposed to a high-temperature environment, H is desorbed and the resistance is reduced. However, in the present embodiment, the n-type semiconductor layer 40 covering the element isolation region 14c suppresses the desorption of H from the element isolation region 14c. For this reason, the integrated semiconductor optical device 200 is less likely to decrease the resistance of the element isolation region 14c even when exposed to high temperatures, and is excellent in thermal stability.

  It has been confirmed by experiments that the n-type semiconductor provided on the p-type InP suppresses the desorption of H from the p-type InP. The principle has not been completely elucidated so far, but the present inventor believes that the cause is that the donor contained in the n-type semiconductor emits electrons to become positive ions.

  Further, the n-type semiconductor layer 40 forms a pn junction with the element isolation region 14c which is a p-type semiconductor. For this reason, even when the element isolation region 14c behaves as a weak p-type semiconductor due to the presence of Zn that is not bonded to H, the element isolation region 14c is depleted by this pn junction, so that the resistance of the element isolation region 14c Can be made high enough. As a result, the p-type cladding layers 14a and 14b can be electrically separated satisfactorily.

  Hereinafter, a method of manufacturing the integrated semiconductor optical device 200 will be described with reference to FIGS. 14 to 19 in addition to FIGS. 14 to 18 are longitudinal sectional views showing the manufacturing process, and FIG. 19 is a perspective view showing the manufacturing process. Reference is also made to FIG. 12 and FIG. 13 as necessary.

First, the process described above with reference to FIGS. 3 to 7 is performed to obtain the structure shown in FIG. Next, after forming an SiO ₂ layer on the entire top surface of the Zn—GaInAs layer 15, as shown in FIG. 14, a groove 37 for dividing the SiO ₂ layer is formed to obtain mask layers 36a and 36b. The groove 37 is located above the end of the active layer 12b adjacent to the active layer 12a, and one end of the groove 37 is disposed almost directly above the boundary between the active layer 12a and the active layer 12b. .

  As shown in FIG. 15, a portion of the Zn—GaInAs layer 15 exposed from the groove 37 is removed, and a groove 38 that divides the Zn—GaInAs layer 15 is formed. The groove 38 is formed by etching the Zn—GaInAs layer 15. As the etchant, an etchant having selectivity with InP, that is, an etchant that etches Zn—GaInAs but does not etch InP is used. The Zn-GaInAs layer 15 is divided into two by the groove 38, and contact layers 15a and 15b are formed.

Next, the substrate 11 is carried into the reaction chamber of the vapor phase growth apparatus, the temperature in the reaction chamber is raised to 450 ° C. while flowing AsH ₃ gas together with H ₂ as a carrier gas into the reaction chamber, and Zn— The InP layer 14 is heated. By this heat treatment, the region exposed from the groove 38 in the Zn—InP layer 14 is heated while being exposed to the AsH ₃ gas. Accordingly, H is introduced into the region, the H and Zn are combined to deactivate Zn, and the resistance of the region is increased. Thus, the element isolation region 14c is formed as shown in FIG.

Since the mask layers 36a and 36b made of SiO ₂ have a low ability to block H, H is introduced to some extent in the regions 14a and 14b of the Zn-InP layer 14 covered with the mask layers 36a and 36b. Will be. This H is removed from the regions 14a and 14b by a dehydrogenation process described later.

Next, GaInAs doped with Si (hereinafter referred to as “Si—GaInAs”) is selectively grown only on the element isolation region 14 c in the reaction chamber, and the trench 38 is filled with the Si—GaInAs. As a result, as shown in FIG. 17, the n-type semiconductor layer 40 is directly formed on the element isolation region 14c. When the n-type semiconductor layer 40 is grown, the mask layers 36a and 36b are used as a selective growth mask. In order to prevent As from escaping from the grown GaInAs, AsH ₃ gas is supplied into the reaction chamber together with H ₂ gas even during the growth of the n-type semiconductor layer 40. In order to sufficiently suppress the desorption of H from the element isolation region 14c, it is preferable to set the temperature in the reaction chamber to 500 ° C. or less until the growth of the n-type semiconductor layer 40 is started. However, since the n-type semiconductor layer 40 suppresses the desorption of H after the start of the growth of the n-type semiconductor layer 40, the temperature in the reaction chamber may exceed 500 ° C.

  As a suitable material for the n-type semiconductor layer 40, besides Si—GaInAs used in the present embodiment, an n-type semiconductor such as InP doped with Si or GaInAsP doped with Si can be cited. .

Thereafter, the supply of AsH ₃ gas is stopped, and the temperature in the reaction chamber is lowered under an H ₂ or N ₂ atmosphere. By stopping the AsH ₃ gas that has introduced H into the regions 14a and 14b, H in the regions 14a and 14b passes through the contact layers 15a and 15b and the mask layers 36a and 36b and is desorbed. As a result, the resistances of the regions 14a and 14b are reduced. On the other hand, since H in the element isolation region 14c is blocked by the n-type semiconductor layer 40, the element isolation region 14c is maintained at a high resistance. In this way, as shown in FIG. 18, p-type cladding layers 14a and 14b spatially and electrically separated by the element isolation region 14c are obtained.

Next, after removing the mask layers 36a and 36b, as shown in FIG. 19, a protective film 17 made of SiO ₂ is formed on the entire upper surfaces of the contact layers 15a and 15b and the n-type semiconductor layer 40. Although different from the present embodiment, the mask layers 36a and 36b can be used as they are as protective films without being removed.

  Subsequently, as shown in FIG. 19, square openings 34a and 34b penetrating the protective film 17 are formed, and the upper surfaces of the contact layers 15a and 15b are exposed. Thereafter, as shown in FIGS. 12 and 13, p-type electrodes 18a and 18b are formed on the protective film 17 so as to fill the openings 34a and 34b. The p-type electrodes 18a and 18b are separated from each other so as to sandwich the element isolation region 14c when the p-type electrodes 18a and 18b are viewed along the direction perpendicular to the upper surface of the substrate 11. And 15b are in contact with the upper surfaces, respectively. Thereafter, the n-type electrode 20 is formed on almost the entire lower surface of the substrate 11. Thus, the integrated semiconductor optical device 200 is completed.

  The manufacturing method of the present embodiment has the following advantages in addition to the advantages of the manufacturing method of the first embodiment. In this embodiment, since the n-type semiconductor layer 40 that suppresses the desorption of H from the element isolation region 14c is formed, an integrated semiconductor optical device having excellent thermal stability can be manufactured. Even when the element isolation region 14c behaves as a weak p-type semiconductor due to Zn not bonded to H, the element isolation region 14c is depleted by the pn junction between the element isolation region 14c and the n-type semiconductor layer 40. And high resistance. As a result, two p-type cladding layers 14a and 14b that are electrically well separated can be obtained. As a result, the integrated semiconductor optical device 200 having a sufficiently high separation resistance can be manufactured with a high yield.

  In addition, after the formation of the element isolation region 14c, the p-type electrodes 18a and 18b are formed so as to be separated so as to sandwich the element isolation region 14c, so that the semiconductor optical elements 21 and 22 can be appropriately electrically isolated. it can.

  The present invention has been described in detail based on the embodiments. However, the present invention is not limited to the above embodiment. The present invention can be variously modified without departing from the gist thereof.

In the above embodiment, AsH ₃ is used as a gas for introducing H into the element isolation region 14c, but PH ₃ may be used instead. Regardless of which gas is used, in order to suppress the desorption of H from the element isolation region 14c, it is preferable to set the heating temperature at the time of introduction of H to 500 ° C. or less. In order to introduce H well, the heating temperature is preferably set to 300 ° C. or higher.

  In the above embodiment, the p-type cladding layer 14a entirely covers the active layer 12a, and the p-type cladding layer 14b partially covers the active layer 12b. However, the p-type cladding layer 14a may partially cover the active layer 12a, the p-type cladding layer 14b may entirely cover the active layer 12b, or the p-type cladding layers 14a and 14b may be the active layers 12a and 12b. May be partially covered. In the above embodiment, the element isolation region 14c covers only the second active layer 12b, but instead, it may cover only the first active layer 12a, or both active layers 12a and 12b may be covered. It may be spread across.

  In the above embodiment, the surface layer portion of the substrate 11 functions as the n-type cladding layer of the semiconductor optical devices 21 and 22, but an n-type cladding layer may be separately provided on the upper surface of the substrate 11.

It is a perspective view which shows 1st Embodiment. It is a longitudinal cross-sectional view along the AA line of FIG. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a perspective view which shows the manufacturing process of 1st Embodiment. It is a perspective view which shows the manufacturing process of 1st Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a perspective view which shows the manufacturing process of 1st Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 1st Embodiment. It is a perspective view which shows 2nd Embodiment. It is a longitudinal cross-sectional view along the AA line of FIG. It is a longitudinal cross-sectional view which shows the manufacturing process of 2nd Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 2nd Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 2nd Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 2nd Embodiment. It is a longitudinal cross-sectional view which shows the manufacturing process of 2nd Embodiment. It is a perspective view which shows the manufacturing process of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12a, 12b ... Active layer, 14 ... Zn dope InP layer, 14a, 14b ... P-type clad layer, 14c ... Element isolation region, 15a, 15b ... Contact layer, 17, 17a, 17b ... Protective film, 18a , 18b ... p-type electrode, 20 ... n-type electrode, 21, 22 ... semiconductor optical device, 100, 200 ... integrated semiconductor optical device

Claims (3)

A method of manufacturing an integrated semiconductor optical device having a first semiconductor optical device including a first active layer and a second semiconductor optical device including a second active layer, the method comprising:
Forming the first and second active layers adjacent to each other on one main surface of the substrate;
Forming a Zn-doped InP layer having a lower refractive index than the first and second active layers on the first and second active layers;
The isolation region of the InP layer is disposed on both sides of the region, and has a higher resistance than each of the first and second regions that at least partially cover the first and second active layers, respectively. And a process of
With
A step of high resistance regions for the isolation includes a step of heating at 500 ° C. below the temperature while exposing the AsH ₃ gas or PH ₃ gas region for the isolation,
The step of increasing the resistance of the element isolation region includes:
Forming an n-type semiconductor layer on the element isolation region after heating the element isolation region;
Desorbing H from the first and second regions while suppressing desorption of H from the element isolation region by the n-type semiconductor layer;
An integrated semiconductor optical device manufacturing method, further comprising : After the step of forming the InP layer, before the step of increasing the resistance of the element isolation region, a metal first p-type is formed on the InP layer above the first active layer. Forming a second p-type electrode made of metal and spaced apart from the first p-type electrode above the second active layer on the InP layer,
Wherein the step of high resistance regions for the device isolation, as a region for the isolation, heating the area exposed from the gap between the first and second p-type electrode of the InP layer, wherein Item 14. A method for manufacturing an integrated semiconductor optical device according to Item 1 . After the step of increasing the resistance of the element isolation region, a first p-type electrode located above the first active layer and a second p-type located above the second active layer Further comprising forming an electrode on the InP layer;
When the first and second p-type electrodes are viewed along the direction perpendicular to the one main surface of the substrate, the first and second p-type electrodes form the element isolation region. The method of manufacturing an integrated semiconductor optical device according to claim 1 , wherein the integrated semiconductor optical devices are spaced apart from each other.

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