JP4830142B2 - Switching circuit - Google Patents

Description

  The present invention relates to a switching circuit including a transistor.

  A switching circuit that switches between a state of supplying power to a load and a state of not supplying power by connecting a power source and a load in series between a pair of main electrodes of the transistor and switching the transistor on and off is known. Yes. For example, the inverter circuit has a built-in switching circuit, converts the DC power into AC power by switching on / off of the transistor, and supplies the converted AC power to a motor (an example of a load).

  Patent Document 1 discloses an example of this type of switching circuit. The switching circuit of Patent Document 1 includes a series circuit in which a Zener diode and a diode are connected in series while being connected between a gate electrode and a drain electrode of a transistor. The Zener diode is set so that when a surge voltage is generated in the wiring on the drain electrode side of the transistor, breakdown occurs due to the surge voltage. The diode prevents a gate current flowing toward the gate electrode of the transistor from flowing to the wiring on the drain electrode side of the transistor through the series circuit when the transistor is turned on.

In the switching circuit of Patent Document 1, when a surge voltage larger than the total voltage (V _ZD + V _F ) of the breakdown voltage V _ZD of the Zener diode and the forward voltage V _F of the diode is generated in the wiring on the drain electrode side of the transistor, the Zener The diode breaks down. When the Zener diode breaks down, a current flows from the wiring on the drain electrode side of the transistor through the series circuit toward the gate electrode of the transistor, the voltage of the gate electrode rises, and the transistor is turned on. The switching circuit of Patent Document 1 can operate so as to release surge energy to the outside through a transistor by momentarily turning on the transistor when a surge voltage is generated.

JP-A-6-326579

However, the breakdown voltage V _ZD of the Zener diode has a variation of about ± 10% due to manufacturing tolerances. For this reason, in the switching circuit of Patent Document 1, the timing at which the Zener diode breakdown varies depending on the Zener diode used. As a result, the switching circuit of Patent Document 1 has a problem that the timing for releasing the surge energy to the outside cannot be set with high accuracy.

  The inventors of the present invention have created a technique that uses a capacitor instead of a Zener diode in the above series circuit. The present inventors have found that the surge voltage can be kept low even if a capacitor is used instead of the Zener diode. As shown in FIG. 11, the switching circuit 110 proposed by the present inventors includes a transistor 150 that is used by connecting a power source 180 and a load 170 in series between a drain electrode D and a source electrode S, and a gate electrode of the transistor. A control circuit 140 connected to G and a series circuit 130 connected between the gate electrode G and the drain electrode D of the transistor 150 and a capacitor 132 and a diode 134 connected in series are provided. Reference numeral 160 is a parasitic inductance. The switching circuit 110 can suppress the surge voltage by the following action. In order to explain a phenomenon that is originally described by an expression in a language, the explanation may not be perfect.

When the control circuit 140 outputs a voltage for turning off the transistor 150, a voltage (Vdd−V _F ) obtained by subtracting the forward voltage V _F of the diode 134 from the power supply voltage Vdd is applied to the capacitor 132. The charging voltage is (Vdd−V _F ).
Next, when the control circuit 140 outputs a voltage for turning on the transistor 150, the voltage of the drain electrode D of the transistor 150 drops. Since a reverse bias voltage is applied to the diode 134, the capacitor 132 cannot be discharged, and the charge voltage (Vdd−V _F ) from before is maintained.
Next, when the control circuit 140 outputs a voltage for turning off the transistor 150, the voltage of the drain electrode D of the transistor 150 increases. Since the parasitic inductance 160 exists, the voltage of the drain electrode D rises exceeding the power supply voltage Vdd. A so-called surge voltage is generated.
When the voltage of the drain electrode D of the transistor 150 exceeds the total voltage of the charging voltage (Vdd−V _F ) of the capacitor 132 and the forward voltage V _F of the diode 134, that is, the power supply voltage Vdd, the forward voltage acts on the diode 134. Then, a charging current starts to flow through the capacitor 132. For this reason, when the discharge rate of the gate electrode G of the transistor 150 is slowed down, the rate of change of the drain current of the transistor 150 is slowed down, and a steep rise in the voltage of the drain electrode D of the transistor 150 is suppressed, and the surge voltage is kept low. be able to.
In the above, a series circuit in which a capacitor is disposed on the gate electrode (control electrode) side and a diode is disposed on the drain electrode (main voltage main electrode) side is illustrated, but a diode is disposed on the gate electrode side. Even if a series circuit in which a capacitor is arranged on the drain electrode side is used, the surge voltage can be kept low.

  While the breakdown voltage of the Zener diode varies by about ± 10% due to manufacturing tolerances, according to the technology using the capacitor, when the voltage of the drain electrode of the transistor exceeds the power supply voltage Vdd, the rate of decrease of the voltage of the gate electrode of the transistor Is slowed down, and the rate of decrease in the drain current of the transistor is slowed down, so that it is possible to mass-produce switching circuits with small variations in the ability to suppress surge voltage.

As described above, when using the capacitor, when the voltage of the drain electrode of the transistor exceeds the power supply voltage, the rate of decrease in the voltage of the gate electrode of the transistor is slowed down, and the rate of decrease in the drain current of the transistor is slowed down. Surge voltage suppression capability is stable.
However, when a capacitor is used, unless the drain electrode voltage exceeds the power supply voltage, the gate electrode voltage reduction rate is not slowed down, the transistor drain current drop rate is not slowed down, and the surge voltage is suppressed. There are cases where it cannot be completed.
Therefore, the present invention not only stabilizes the timing of slowing the change rate of the voltage of the control electrode of the transistor, but also increases the transistor timing at a timing earlier than the voltage of the main electrode on the high voltage side of the transistor exceeds the power supply voltage. It was developed to provide a switching circuit with improved surge voltage suppression capability by slowing down the voltage change rate of the control electrode.

The present invention can be embodied in a switching circuit including a transistor. The switching circuit of the present invention alternately outputs a transistor used by connecting a power source and a load between a pair of main electrodes, a voltage for turning on and off the transistor connected to the control electrode of the transistor. And a series circuit that is connected between the control electrode of the transistor and the main electrode on the high voltage side and in which a first capacitor and a first diode are connected in series. The cathode of the first diode is connected to the control electrode side of the transistor, and the anode of the first diode is connected to the main electrode side on the high voltage side of the transistor. The switching circuit of the present invention is further connected to a connection line between the first capacitor and the first diode, and further includes a voltage adjustment circuit for adjusting the voltage of the connection line.
In the series circuit of the first capacitor and the first diode, the first capacitor may be disposed on the control electrode side of the transistor, and the first diode may be disposed on the main electrode side on the high voltage side of the transistor, or the position thereof. The relationship may be reversed.

In the above device, when the forward voltage starts to act on the first diode when the transistor is turned off, the charging current starts to flow to the first capacitor, and thereafter, the change rate of the voltage of the control electrode of the transistor is slowed down. Thus, the change rate of the main current of the transistor is slowed down, the voltage change of the main electrode on the high voltage side of the transistor is slowed down, and the surge voltage appearing on the main electrode on the high voltage side of the transistor can be suppressed low.
Without the voltage adjustment circuit, the timing at which the forward voltage starts to act on the first diode is fixed at the timing at which the voltage of the main electrode on the high voltage side of the transistor rises to the power supply voltage.
On the other hand, when a voltage adjustment circuit is added, the forward voltage can start to act on the first diode at an earlier timing than the voltage of the main electrode on the high voltage side of the transistor rises to the power supply voltage. The change speed of the voltage of the control electrode of the transistor can be slowed at an earlier timing, the change speed of the main current of the transistor can be slowed at an earlier timing, and the higher voltage side of the transistor can be The voltage change of the main electrode can be slowed down, and the surge voltage appearing at the main electrode on the high voltage side of the transistor can be kept low.
If necessary, the forward voltage can start to act on the first diode when the voltage of the main electrode on the high voltage side of the transistor rises above the power supply voltage, and the voltage of the control electrode of the transistor can be controlled at a later timing. The change rate can be slowed, the change rate of the main current of the transistor can be slowed at a slow timing, and the voltage change of the main electrode on the high voltage side of the transistor can be slowed at a slow timing. In this case, the switching loss of the transistor can be reduced.

In the switching circuit of the present invention, the voltage adjustment circuit is connected between the connection line connecting the first capacitor and the first diode and the anode of the first diode, and the second capacitor and the second diode are connected in series. and that that has a circuit. In this case, the cathode of the second diode is connected to the anode side of the first diode, and the anode of the second diode is connected to the connection line side. That is, the second capacitor and the second diode provide a path that bypasses the first diode.
In this voltage adjustment circuit, when the transistor is turned on and the voltage of the main electrode on the high voltage side of the transistor drops, a forward voltage acts on the second diode. As a result, a part of the charge that has charged the first capacitor moves so as to charge the second capacitor, and the voltage of the connection line connecting the first capacitor and the first diode decreases. The voltage of the connection line is high when the transistor is off, and low when the transistor is on.
In this case, the forward voltage can start to act on the first diode at an earlier timing than the voltage of the main electrode on the high voltage side of the transistor rises to the power supply voltage, and the voltage of the control electrode of the transistor can be obtained at an earlier timing. The rate of change of the transistor can be slowed, the rate of change of the drain current of the transistor can be slowed at an earlier timing, and the rate of change of the voltage on the main electrode on the high voltage side of the transistor can be delayed at an earlier timing. Thus, the surge voltage appearing at the main electrode on the high voltage side of the transistor can be kept low.

In the switching circuit of the present invention, it is preferable that the capacitance of the second capacitor is equal to or less than the capacitance of the first capacitor.
If the capacitance of the second capacitor is too large, the amount of charge stored in the first capacitor becomes too small, and the charging voltage of the first capacitor becomes too small. If the charging voltage of the first capacitor becomes too small, the forward voltage starts to act on the first diode from the beginning of the transition period in which the transistor is turned off, and the turn-off loss increases. If the capacitance of the second capacitor is set to be equal to or lower than the capacitance of the first capacitor, it is possible to suppress the charging voltage of the first capacitor from becoming too small. As a result, the surge voltage can be suppressed while suppressing an increase in turn-off loss.

According to the present invention, the voltage adjustment circuit can be used to adjust the timing for slowing the rate of change of the voltage generated at the control electrode of the transistor when the transistor is turned off. If this timing is adjusted early, the surge voltage can be kept low.
According to the present invention, in the early stage when the transistor is turned off, the turn-off loss is suppressed by increasing the rate of change of the voltage generated at the control electrode of the transistor (in the early stage, since the voltage between the main electrodes of the transistor is low, the surge voltage is reduced). Is not excessive and the speed of change of the voltage of the control electrode can be increased), the end of the transistor turn-off (the period during which the voltage between the main electrodes of the transistor is rising and the surge voltage can be excessive) ), The surge voltage can be kept low by slowing the rate of change of the voltage generated at the control electrode of the transistor.
Generally, the turn-off loss and the surge voltage are in a trade-off relationship. If the turn-off loss is suppressed, the surge voltage becomes excessive, and if the surge voltage is suppressed, the turn-off loss becomes excessive. In the present invention, both the turn-off loss and the surge voltage can be suppressed in order to slow down the rate of change of the voltage generated at the control electrode of the transistor during the turn-off.

Preferred forms of the present invention are listed.
(First Embodiment) The switching circuit of the present invention uses a field effect transistor.
(Second Embodiment) The switching circuit of the present invention uses a MOSFET.
(3rd form) The surge voltage suppression circuit and the transistor are built in the same semiconductor substrate.

FIG. 1 shows a circuit diagram of a switching circuit 10 including a field effect transistor 50 (n-type MOSFET). The transistor 50 is used with a power supply 80 and a load 70 connected in series between the drain electrode D and the source electrode S. A parasitic inductance 60 exists in the wiring between the transistor 50 and the load 70. The switching circuit 10 switches on / off of the transistor 50 based on the drive voltage Vin output from the control circuit 40. The drive voltage Vin is input to the gate electrode G.
The switching circuit 10 switches between a state in which the power supply voltage Vdd supplied from the power supply 80 is supplied to the load 70 and a state in which the power supply 80 is not supplied by switching on and off the transistor 50.
The drain electrode D is a main electrode on the high voltage side, the source electrode S is a main electrode on the low voltage side and is grounded, and the gate electrode G is a control electrode.

  The switching circuit 10 includes a transistor 50, a control circuit 40, and a surge voltage countermeasure circuit 12. The control circuit 40 is connected to the gate electrode G of the transistor 50, and outputs to the gate electrode G of the transistor 50 a rectangular wave drive voltage Vin in which a voltage for turning on and off the transistor 50 appears alternately. The surge voltage countermeasure circuit 12 includes a series circuit 30 and a voltage adjustment circuit 20. One end of the series circuit 30 is connected to a first connection point 41 between the gate electrode G of the transistor 50 and the control circuit 40. The other end of the series circuit 30 is connected to a second connection point 51 between the drain electrode D of the transistor 50 and the load 70. The series circuit 30 includes a first capacitor 32 and a first diode 34 connected in series. The cathode of the first diode 34 is connected to the first connection point 41 side, and the anode of the first diode 34 is connected to the second connection point 51 side. The voltage adjustment circuit 20 is connected to a third connection point 33 of a connection line connecting the first capacitor 32 and the first diode 34. The voltage adjustment circuit 20 reduces the voltage at the third connection point 33 when the transistor 50 is on compared to when the transistor 50 is off. The voltage adjustment circuit 20 may be said to lower the charging voltage of the first capacitor 32 when the transistor 50 is on compared to when the transistor 50 is off. The surge voltage countermeasure circuit 12 including the series circuit 30 is built on the same semiconductor substrate as the transistor 50.

  Next, the operation of the switching circuit 10 will be described with reference to FIG. FIG. 2 shows a change pattern of the voltage VD of the drain electrode D of the transistor 50, and shows a change with time of the voltage VD in a transition period in which the transistor 50 is turned off. FIG. 2A shows a comparative example in which the surge voltage countermeasure circuit 12 is not provided. FIG. 2B shows a comparative example in which only the series circuit 30 of the surge voltage countermeasure circuit 12 is provided. FIG. 2C shows the case of the switching circuit 10 of this embodiment.

A case where the surge voltage countermeasure circuit 12 is not provided will be described with reference to FIG.
When the surge voltage countermeasure circuit 12 is not provided, the voltage VD of the drain electrode D rises when the transistor 50 is turned off at the timing of Toff. At the end of the turn-off transition period, a surge voltage is generated due to the drain current ID of the transistor 50 and the parasitic inductance 60.

Next, the case where only the series circuit 30 of the surge voltage countermeasure circuit 12 is provided will be described with reference to FIG.
First, consider a state in which transistor 50 is off and stable. In the switching circuit of this comparative example, when the transistor 50 is off and stable, a voltage (Vdd−V _F ) obtained by subtracting the forward voltage V _F of the first diode 34 from the power supply voltage Vdd is applied to the first capacitor 32. Applied. The first capacitor 32 is charged to a voltage of (Vdd−V _F ) when the transistor 50 is off and stable. That is, the voltage V1 at the third connection point 33 is (Vdd−V _F ).
Next, when the transistor 50 is turned on, the voltage VD of the drain electrode D drops. For this reason, since a reverse bias voltage is applied to the first diode 34, the first diode 34 cannot be discharged, and the charge voltage of the first capacitor 32 is charged before the transistor 50 is on. The voltage is maintained at (Vdd−V _F ).
Next, when the transistor 50 is turned off at the timing of Toff, the voltage VD of the drain electrode D rises. The voltage VD of the drain electrode D is the sum of the voltage V1 (Vdd−V _F ) of the third connection point 33 and the forward voltage V _F of the first diode 34 (V1 + V _F = Vdd−V _F + V _F = Vdd), When the power supply voltage Vdd is exceeded, a forward voltage is applied to the first diode 34 (timing Tb in FIG. 2B). When a forward voltage is applied to the first diode 34 at the timing of Tb, a charging current starts to flow through the first capacitor 32, and thereafter, the rate of decrease in the voltage of the gate electrode G of the transistor 50 is reduced, and the drain current of the transistor 50 ID drop speed is slowed down. For this reason, after the timing Tb, a sharp rise in the voltage VD of the drain electrode D is suppressed, and the surge voltage is suppressed low.

  However, if the voltage adjustment circuit 20 does not exist, the voltage decrease rate of the gate electrode G is slowed down, the drain current ID drop rate of the transistor 50 is slowed down, and the voltage change rate of the drain electrode D is slowed down. The timing at which the drain electrode D is equal to the power supply voltage Vdd is fixed at the timing Tb, and the surge voltage may not be sufficiently suppressed.

Next, a case where the voltage adjustment circuit 20 is provided will be described with reference to FIG.
As described with reference to FIG. 2B, the timing when the charging current starts to flow through the first capacitor 32 is the timing when the forward voltage starts to act on the first diode 34. Timing a forward voltage begins to act on the first diode 34, the voltage VD of the drain electrode D, exceeds the voltage V1 of the third connection point 33 the total of the forward voltage V _F of the first diode 34 a (V1 + V _F) When Therefore, if the voltage V1 at the third connection point 33 is adjusted to be low, the timing at which the forward voltage starts to act on the first diode 32 is accelerated, and the charging current is supplied to the first capacitor 32 when the voltage VD at the drain electrode D is low. Can start to flow.

The voltage adjustment circuit 20 reduces the charge charged in the first capacitor 32 when the transistor 50 is off, and reduces the voltage V1 at the third connection point 33 to the voltage Vt (see FIG. 2 (see (C)). The voltage Vt may have a predetermined magnitude or a different magnitude each time switching is repeated. When the voltage V1 at the third connection point 33 when the transistor 50 is on decreases to the voltage Vt, the timing Tc at which the charging current starts to flow through the first capacitor 32 is advanced as shown in FIG. That is, when the voltage VD of the drain electrode D is low, the charging current begins to flow through the first capacitor 32, the rate of decrease in the voltage of the gate electrode G of the transistor 50 is slowed down, and the rate of decrease in the drain current ID of the transistor 50 is slowed down. As a result, the change rate of the voltage of the drain electrode D is reduced. That is, the charging current starts to flow through the first capacitor 32 at a timing sufficiently earlier than the timing at which the surge voltage peaks, the rate of decrease in the voltage of the gate electrode G is delayed, and the rate of decrease in the drain current ID of the transistor 50 is decreased. The voltage change rate of the drain electrode D is slowed down. As a result, an increase in surge voltage can be significantly suppressed.
The first capacitor 32 is disposed on the drain electrode D side of the transistor 50, the first diode 34 is disposed on the gate electrode G side of the transistor 50, and when the voltage adjustment circuit 20 is added, the surge voltage peaks. A charging current begins to flow through the first capacitor 32 at a timing sufficiently earlier than the timing, the rate at which the voltage at the gate electrode G decreases, and the rate at which the voltage at the drain electrode D changes is reduced, resulting in a surge voltage. Can be significantly suppressed.

FIG. 3 shows a specific circuit diagram of the voltage adjustment circuit 20.
The voltage adjustment circuit 20 is connected between the third connection point 33 connecting the first capacitor 32 and the first diode 24 and the anode of the first diode 34. The voltage adjustment circuit 20 includes a circuit in which a second capacitor 22 and a second diode 24 are connected in series. The cathode of the second diode 24 is connected to the anode side of the first diode, and the anode of the second diode 24 is connected to the third connection point 33 side.

FIG. 4 shows a simulation result when the transistor 50 is driven using the switching circuit 10 of FIG. 4A shows changes over time in the voltage VG of the gate electrode G, the voltage VD of the drain electrode D, and the voltages V1 and V2 of the transistor 50. FIG. The voltage V 1 is the voltage at the third connection point 33, and the voltage V 2 is the voltage on the connection line between the second diode 22 and the second capacitor 24. FIG. 4B shows changes over time in the drain current ID of the transistor 50 and the currents I1 and I2. The current I1 is a current flowing through the first diode 34, and the current I2 is a current flowing through the second diode 24. In FIG. 4, the capacitance C1 of the first capacitor 32 is 1 nF, the capacitance C2 of the second capacitor 22 is 0.5 nF, the power supply voltage Vdd is 100 V, the first diode 32 and the second diode 22. forward voltage V _F of the result when the 0.8V.

First, consider a period T1 in which the transistor 50 is off and stable. In the switching circuit 10, when the transistor 50 is off and stable, a voltage (Vdd−V _F ) obtained by subtracting the forward voltage V _F of the first diode 34 from the power supply voltage Vdd is the first capacitor 32 and the second capacitor. 22 is applied. When the transistor 50 is off, the charging voltage of the first capacitor 32 is (Vdd−V _F ), and the voltage V1 at the third connection point 33 is (Vdd−V _F ). The voltage V2 between the second capacitor 22 and the second diode 24 is also (Vdd−V _F ). That is, the second capacitor 22 is not charged. As shown in FIG. 4, the voltage V1 and the voltage V2 in the period T1 are approximately 100V.

Next, consider a period T2 during which the transistor 50 is turned on. In the period T2, first, the voltage VG of the gate electrode G of the transistor 50 rises. The voltages V1 and V2 increase following the increase of the gate voltage VG. When the voltage VG of the gate electrode G exceeds the threshold value, the drain current ID flows between the drain electrode D and the source electrode S of the transistor 50, and the transistor 50 is turned on. When the transistor 50 is turned on, the voltage VD of the drain electrode D drops. When the voltage VD of the drain electrode D drops, a reverse bias voltage is applied to the first diode 34, so that the first diode 34 is cut off. On the other hand, a forward voltage is applied to the second diode 24. The difference between the voltage VD of the voltage V2 and the drain electrode D, exceeds the forward voltage V _F of the second diode 24, second diode 24 becomes conductive.

  The phenomenon at this time will be described in more detail with reference to FIG. When the transistor 50 is off, the first capacitor 32 existing between the third connection point 33 and the first connection point 41 is charged. The third connection point 33 is on the high voltage side, and the first connection point 41 is on the low voltage side. At this time, the potential V1 of the third connection point 33 is equal to the potential V2 of the connection line between the second capacitor 22 and the second diode 24, and the charging voltage of the second capacitor 22 is zero. Next, when the transistor 50 is turned on, as described above, the second diode 24 becomes conductive, and a part of the charge that has charged the first capacitor 32 moves to the second capacitor 22 and charges the second capacitor 24. To do. At this time, since the transistor 50 is on, the second connection point 51 is on the low voltage side with respect to the third connection point 33. Therefore, it can be evaluated that when the transistor 50 is turned on, a parallel circuit of the first capacitor 32 and the second capacitor 22 is formed. That is, the capacitance between the first connection point 41 and the second connection point 51 becomes the series capacitance of the first capacitor 32 and the second capacitor 22. As a result, the voltage V1 at the third connection point 33 drops. In other words, a part of the charge that has charged the first capacitor 32 moves to the second capacitor 22, and as a result, the voltage V1 at the third connection point 33 drops. As shown in FIG. 4B, in the transition period in which the transistor 50 is turned on, the current I2 flows through the first capacitor 32, the second capacitor 22, the second diode 24, and the second connection point 51, and the third connection is established. The voltage V1 at point 33 drops. It can be seen that the amount of decrease in the voltage V1 at the third connection point 33 can be adjusted by adjusting the capacitance ratio of the first capacitor 32 and the second capacitor 22.

  In the period T3 in which the transistor 50 is completely turned on, both the first diode 32 and the second diode 22 are turned off, and the voltage V1 and the voltage V2 are maintained.

Next, a period T4 in which the transistor 50 is turned off will be described. When the transistor 50 is turned off, the voltage VD of the drain electrode D increases. When the voltage VD of the drain electrode D exceeds the sum (V1 + V _F = Vt + V _F ) of the charging voltage V1 charged in the first capacitor 32 and the forward voltage V _F of the first diode 34, the first diode 34 becomes conductive. . When the first diode 34 is turned on, the current I1 begins to flow through the first capacitor 32, the rate of decrease in the voltage of the gate electrode G of the transistor 50 is decreased, and the rate of decrease in the drain current ID of the transistor 50 is decreased. For this reason, thereafter, a sharp rise in the voltage VD of the drain electrode D can be suppressed, and the surge voltage can be suppressed low.
By repeating these operations, the switching circuit 10 can drive the transistor 50 while suppressing the surge voltage.

FIG. 5 shows the fluctuation of the voltage VD of the drain electrode D of the transistor 50 in the transition period when it is turned off. The results when the capacitance C1 of the first capacitor 32 and the capacitance C2 of the second capacitor 22 are changed are also shown. “No countermeasure” is the result when the surge voltage countermeasure circuit 12 is not provided.
As shown in FIG. 5, comparing the case where the capacitance C1 of the first capacitor 32 is 1 nF and the case where it is 0.5 nF, it can be seen that the slope of the voltage VD of the drain electrode D is different. The magnitude of the capacitance C1 of the first capacitor 32 determines the slope of the voltage VD of the drain electrode D.
As shown in FIG. 5, when the ratio of the capacitance of the first capacitor 32 and the second capacitor 22 is 1: 1 and 1: 0.5, the timing at which the voltage VD of the drain electrode D starts to tilt is different. . The ratio of the capacitances of the first capacitor 32 and the second capacitor 22 determines the timing at which the voltage VD of the drain electrode D begins to tilt.

FIG. 6 shows the fluctuation of the drain current ID of the transistor 50 in the transition period when it is turned off.
As shown in FIG. 6, comparing the cases where the capacitance C1 of the first capacitor 32 is 1 nF and 0.5 nF, it can be seen that the slope of the drain current ID of the transistor 50 is different. The magnitude of the capacitance C1 of the first capacitor 32 determines the slope of the drain current ID of the transistor 50.
As shown in FIG. 6, when the ratio of the capacitances of the first capacitor 32 and the second capacitor 22 is 1: 1 and 1: 0.5, the timing at which the drain current ID of the transistor 50 starts to tilt is different. . The ratio of the capacitances of the first capacitor 32 and the second capacitor 22 determines the timing at which the drain current ID of the transistor 50 begins to tilt.

From the results of FIGS. 5 and 6, it can be seen that adjusting the capacitances of the first capacitor 32 and the second capacitor 22 improves the characteristics in the transition period in which the transistor 50 is turned off.
In particular, as shown in FIG. 5, the switching circuit 10 of the present embodiment causes the voltage VD of the drain electrode D to change sharply at the beginning of the transition period when the transistor 50 is turned off, and the voltage of the drain electrode D at the end of the transition period. VD can be changed slowly. Therefore, the increase in turn-off loss is suppressed by abruptly changing the voltage VD of the drain electrode D in the early stage of the transition period, and the surge voltage is controlled by slowly changing the voltage VD of the drain electrode D in the end of the transition period. The increase can be suppressed.

FIG. 7 shows a trade-off curve between the turn-off loss and the surge voltage existing when driving the transistor 50. The broken line in the figure is a trade-off curve in the case of “no countermeasure”.
As shown in FIG. 7, it can be seen that the switching circuit 10 of the present embodiment can reduce the surge voltage with almost no increase in turn-off loss. The switching circuit 10 of this embodiment can break the trade-off relationship that exists between the turn-off loss and the surge voltage.

In the following comparative example, a simulation result in the case where an extremely large capacitance value is employed for the first capacitor 32 or the second capacitor 22 is shown. The configuration of the switching circuit of the following comparative example is the same as that of the switching circuit 10 shown in FIG.
(Comparative Example 1)
The result of FIG. 8 is a case where the capacitance C1 of the first capacitor 32 is 1 nF and the capacitance C2 of the second capacitor 22 is 0.1 pF. The capacitance C2 of the second capacitor 22 is extremely small. Therefore, Comparative Example 1 is substantially equivalent to the case where the second capacitor 22 is not present.
As shown in FIG. 8, in the comparative example 1, the current I2 does not flow during the transition period in which the transistor 50 is turned on. For this reason, the voltage V1 at the third connection point 33 does not drop.

(Comparative Example 2)
The result of FIG. 9 is the case where the capacitance C1 of the first capacitor 32 is 0.1 pF and the capacitance C2 of the second capacitor 22 is 1 nF. The capacitance C1 of the first capacitor 32 is extremely small.
As shown in FIG. 9, in Comparative Example 2, the current I2 does not flow during the transition period in which the transistor 50 is turned on. Further, the current I1 does not flow even in the transition period in which the transistor 50 is turned off. Therefore, it can be evaluated that Comparative Example 2 is equivalent to the case where the surge voltage countermeasure circuit 12 is not provided.

(Comparative Example 3)
The result of FIG. 10 is a case where the capacitance C1 of the first capacitor 32 is 1 nF and the capacitance C2 of the second capacitor 22 is 10 nF. The capacitance C2 of the second capacitor 22 is extremely large.
As shown in FIG. 10, in Comparative Example 3, an excessive current I2 flows during a transition period in which the transistor 50 is turned on, and the voltage V1 at the third connection point 33 is too low. For this reason, in the transition period in which the transistor 50 is turned off, the voltage VD at the second connection point slopes from the beginning. The switching circuit of Comparative Example 3 has a large off loss.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in the switching circuit 10 of FIG. 3, the series circuit of the second capacitor 22 and the second diode 24, the parallel circuit formed of the first diode 34, and the first capacitor 32 are connected to the first connection point 41 and the second circuit. The positional relationship between the connection points 51 may be reversed.
Further, the arrangement order of the second capacitor 22 and the second diode 24 may be reversed.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

A basic circuit diagram of a switching circuit is shown. (A) In a switching circuit that is not provided with a surge voltage countermeasure circuit, the fluctuation of the voltage of the drain electrode of the transistor is shown. (B) In a switching circuit in which only a series circuit is provided in a surge voltage countermeasure circuit, the fluctuation of the voltage of the drain electrode of the transistor is shown. (C) In the switching circuit of this embodiment, the fluctuation of the voltage of the drain electrode of the transistor is shown. A specific circuit diagram of the switching circuit is shown. (A) In the switching circuit of this embodiment, changes over time in the voltage VG of the gate electrode of the transistor, the voltage VD of the drain electrode D, and the voltages V1 and V2 are shown. (B) In the switching circuit of the present embodiment, changes in the drain current ID and currents I1 and I2 of the transistor over time are shown. The fluctuation of the voltage of the drain electrode in the transition period when turned off is shown. It shows the fluctuation of the drain current during the transition period when it is turned off. The relationship between the off loss and the surge voltage of the switching circuit of a present Example is shown. (A) In the switching circuit of Comparative Example 1, changes over time in the voltage VG of the gate electrode of the transistor, the voltage VD of the drain electrode D, and the voltages V1 and V2 are shown. (B) In the switching circuit of Comparative Example 1, changes in the drain current ID of the transistor and the currents I1 and I2 over time are shown. (A) In the switching circuit of Comparative Example 2, changes over time in the voltage VG of the gate electrode of the transistor, the voltage VD of the drain electrode D, and the voltages V1 and V2 are shown. (B) In the switching circuit of Comparative Example 2, changes in the drain current ID of the transistor and the currents I1 and I2 over time are shown. (A) In the switching circuit of Comparative Example 3, changes over time in the voltage VG of the gate electrode of the transistor, the voltage VD of the drain electrode D, and the voltages V1 and V2 are shown. (B) In the switching circuit of Comparative Example 3, changes in the drain current ID of the transistor and the currents I1 and I2 over time are shown. The circuit diagram of the switching circuit in which only a series circuit is provided is shown.

Explanation of symbols

10: switching circuit 12: surge voltage countermeasure circuit 20: voltage regulator circuit 22: second capacitor 24: second diode 30: series circuit 32: first capacitor 34: first diode 40: control circuit 50: transistor 60: parasitic Inductance 70: Load 80: Power supply

Claims (2)

A switching circuit comprising a transistor;
A transistor used by connecting a power source and a load in series between a pair of main electrodes;
A control circuit connected to the control electrode of the transistor and alternately outputting a voltage for turning on and off the transistor;
The circuit is connected between the control electrode of the transistor and the main electrode on the high voltage side, and the first capacitor and the first diode are connected in series, the cathode of the first diode being the control electrode side A series circuit in which the anode of the first diode is connected to the main electrode side on the high voltage side;
A voltage adjustment circuit that is connected to a connection line connecting the first capacitor and the first diode and adjusts a voltage of the connection line ;
The voltage adjustment circuit includes a circuit connected between a connection line connecting the first capacitor and the first diode and the anode of the first diode, and the second capacitor and the second diode connected in series. And
A switching circuit in which the cathode of the second diode is connected to the anode side of the first diode, and the anode of the second diode is connected to the connection line side . 2. The switching circuit according to claim 1, wherein the capacitance of the second capacitor is equal to or less than the capacitance of the first capacitor.

Images