JP4826971B2 - Manufacturing method of semiconductor device using high dielectric constant thin film - Google Patents

Description

  The present invention relates to a method of forming a high dielectric constant thin film and a method of manufacturing a semiconductor device using the high dielectric constant thin film, and in particular, is essential for high integration and high speed of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The present invention relates to a method for forming a high dielectric constant thin film suitable for use in forming a very thin gate insulating film layer and a method for manufacturing a semiconductor device using the high dielectric constant thin film.

  A silicon oxide film has process stability and excellent insulating properties, and is used as a gate insulating film material for MOSFETs. With the recent miniaturization of devices, the gate insulating film is becoming thinner, and when the gate length is about 100 nm or less, the thickness of the silicon oxide film, which is the gate insulating film, is 1.5 nm or less due to the demand of scaling law. Is required. However, when such an ultra-thin insulating film is used, the tunnel current through the insulating layer when the gate bias is applied becomes a value that cannot be ignored with respect to the source / drain current, and the high performance and low power consumption of the MOSFET It has become a big issue.

  Therefore, research and development are underway to make the effective gate insulating film thinner and to keep the tunnel current within the allowable range in device design. One method is to add nitrogen to the silicon oxide film to increase the dielectric constant compared to a pure silicon oxide film, and an effective gate insulating layer without reducing the physical film thickness. However, it has been pointed out that there is a limit to increasing the dielectric constant by adding nitrogen to the silicon oxide film.

In the second method, instead of a silicon oxide film having a dielectric constant of 3.9, a thin film material having a dielectric constant of 10 or more or a silicate thin film which is a composite material of these materials and silicon is used for the gate insulating film. It is a method. As such high dielectric constant thin films, rare earth element oxides such as Al ₂ O ₃ , ZrO ₂ , HfO ₂ , and Y ₂ O ₃ , and oxides of lanthanoid elements have been studied as candidate materials. If these high dielectric constant films are used, the gate insulating film can be made to have a thickness that can prevent a tunnel current while maintaining the gate insulating film capacity in accordance with the scaling rule even if the gate length is made fine.

  Regardless of the type of gate insulating film, assuming that the gate insulating film material is a silicon oxide film, the film thickness of the silicon oxide film obtained by calculating backward from the gate capacitance is referred to as the equivalent silicon oxide film thickness. That is, when the relative dielectric constants of the insulating film and the silicon oxide film are εh and εo, respectively, and the thickness of the insulating film is dh, the equivalent silicon oxide film thickness de is given by Equation 1.

  Formula 1 shows that if a material having a dielectric constant εh larger than εo is used, even if the insulating film is thick, it can be equivalent to a thin silicon oxide film. That is, since the relative dielectric constant εo of the silicon oxide film is about 3.9, for example, if a high dielectric film of εh = 39 is used, even if the thickness is 15 nm, the equivalent film thickness of the silicon oxide film is 1.5 nm. The current can be drastically reduced.

  However, as described above, various high dielectric constant thin films have excellent characteristics as gate insulating films. However, silicon oxide is formed at the interface with the silicon substrate during the high dielectric constant thin film deposition and in the heating process after film deposition. There is a problem that an interface transition layer mainly composed of a film is formed.

  In the production of a gate insulating film in a MOSFET, if an interface layer (silicon oxide film layer) having a lower dielectric constant than a high dielectric constant thin film is formed, the effective insulating layer thickness increases. This is a major problem in the development of an ultra-thin gate insulating film having a converted film thickness of 1.5 nm or less. For example, when a silicon oxide film having a relative dielectric constant εo exists under a high dielectric having a thickness dh and a relative dielectric constant εh, the capacitance per unit area is expressed by Equation 2.

  εe is an effective relative dielectric constant when the composite film is regarded as a single film. Accordingly, the equivalent silicon oxide film thickness is as shown in Equation 3.

  Here, if there is no silicon oxide film (do = 0) and a high dielectric constant film of εh = 39 is adopted to obtain a converted film thickness of 1.5 nm, the thickness should be 15 nm. However, when a 1 nm silicon oxide film is present at the interface, the film thickness of the high dielectric constant film must be 5 nm. If εh is even smaller, the film thickness becomes smaller if a silicon oxide film is sandwiched, and tunnel current cannot be prevented.

  In the formation of a high dielectric constant thin film, since the uniformity of film thickness and film quality are generally poorer than that of a silicon oxide film, there is a limit to the thinning of the high dielectric constant thin film itself. As a result, excellent characteristics cannot be expected unless the interfacial silicon oxide film layer is thinned and the film thickness of the high dielectric constant layer is set relatively large. Therefore, unless the increase / decrease of the interface silicon oxide film layer is controlled at the atomic layer level, it becomes substantially difficult to control the equivalent silicon oxide film thickness de between the rods in the manufacturing process, within the rods, and between the wafers.

  Although the interface layer control at the atomic layer level is required in this way, the MOSFET manufacturing process requires a heat treatment at around 1000 ° C. to activate the dopant, and the conventional technology has the thermal stability of the interface layer. It is difficult to secure. In addition, it has been reported that a reaction layer (oxide film layer) is formed at the interface with the substrate even when a high dielectric constant thin film is formed, which is a major problem in device development along with the thermal stability described above. .

  As a countermeasure to avoid the high-temperature heat treatment step after the formation of the high dielectric constant film, a high-dielectric gate is formed after the dummy gate is removed by performing a high-temperature heat treatment for dopant activation after the dummy gate electrode is manufactured. Methods for depositing thin films are being considered. However, this method not only complicates the manufacturing process, but also causes problems such as contamination that occurs during the dummy gate removal step. Therefore, in order to take advantage of the conventional MOSFET manufacturing process, it is necessary to ensure thermal stability of the interface between the high dielectric constant gate thin film and the silicon substrate at a high temperature.

  On the other hand, while the understanding of the interface characteristics between the high dielectric constant thin film and the silicon substrate is insufficient, the interface between silicon and the silicon oxide film has a low electrical defect level density, and the silicon oxide film has a high density. Since the band gap is larger than that of the dielectric thin film, it is desirable that the silicon oxide film layer exists at the interface with the high dielectric constant thin film from the viewpoint of device characteristics. However, as described above, in order to realize an extremely thin gate insulating layer, the thickness of the silicon oxide film layer (interface layer) having a low dielectric constant is required to be about several atomic layers.

  Considering the above points comprehensively, regardless of whether or not a process in which a silicon oxide film layer is intentionally inserted at the interface between the silicon substrate and the high dielectric constant thin film is employed, In subsequent processing steps, it is important to establish a technique for controlling and suppressing the formation and growth of the interface transition layer (oxide film layer) at the atomic layer level.

  The present invention has been made in view of the above-mentioned problems, and its main purpose is to control and suppress the growth of the interface reaction layer during various processes after the formation of the high dielectric constant thin film and after the film formation. Another object of the present invention is to provide a method for forming a high dielectric constant thin film having excellent electrical characteristics and a method for manufacturing a semiconductor device using the high dielectric constant thin film.

In order to achieve the above object, according to the present invention, a metal layer oxidation treatment step for forming a high dielectric constant thin film and / or a treatment step after the formation of the high dielectric constant thin film is formed at the silicon substrate interface. Both the residual oxygen partial pressure and the residual moisture pressure can be controlled to the atomic layer level in an atmosphere of 1 × 10 ⁻⁴ Torr or less.

  In the present invention, it is preferable that the treatment after the film formation includes a dopant activation treatment.

  In the present invention, it is preferable that the film formation of the high dielectric constant thin film or the treatment after the film formation is performed in a reduced pressure atmosphere or an atmosphere containing an inert gas.

  As described above, according to the present invention, the growth of the interface transition layer (silicon oxide film layer) between the high dielectric constant thin film and the silicon substrate can be controlled and suppressed by the above configuration, and the effective gate insulating film thickness is reduced. As a result, the tunnel current flowing through the gate layer can be drastically reduced, and a high performance and low power consumption MOSFET can be manufactured.

  As described above, according to the film formation method and the processing method of the high dielectric thin film of the present invention, by reducing the residual oxygen partial pressure and the residual moisture pressure during film formation and processing to a predetermined value or less, There is an effect that the growth of the interface transition layer (silicon oxide film layer) between the high dielectric constant thin film and the silicon substrate can be controlled and suppressed. By reducing the effective gate insulating film thickness to the 1 nm level, the tunnel current flowing through the gate layer can be drastically reduced, and a high performance and low power consumption MOSFET can be manufactured. There is an effect.

It is sectional drawing which shows typically a mode that a silicon oxide film is formed on a silicon substrate. It shows a process step in the case of producing a ZrO ₂ / SiO ₂ / Si multilayer gate structure according to an embodiment of the present invention. It is sectional drawing which shows the example of the process apparatus which forms the high dielectric material thin film of this invention.

In a preferred embodiment of the method for forming a high dielectric constant thin film according to the present invention, the residual oxygen partial pressure and the residual moisture pressure in the atmosphere are formed in the high dielectric constant thin film forming step or the processing step after the film forming. The film thickness of the interface reaction film formed at the silicon substrate interface by reducing the amount of oxygen supplied to the interface with the silicon substrate through the high dielectric constant thin film from the gas phase by setting it to a predetermined value or less. Is controlled at the atomic layer level and the film thickness of a high dielectric constant thin film such as ZrO ₂ used as a gate insulating film is increased to reduce the tunnel current flowing through the gate layer.

Specifically, during the formation of a high dielectric constant thin film, the growth of the interface reaction layer (oxide layer) is suppressed to 1 nm or less by reducing the residual oxygen partial pressure in the atmosphere to 1 × 10 ⁻⁴ Torr or less. By reducing the residual oxygen partial pressure to 5 × 10 ⁻⁶ Torr or less, the growth of the interfacial reaction layer can be suppressed to 0.3 nm or less, and the deposition process of the high dielectric constant thin film is reduced. Even when the reaction is performed in a lower atmosphere or an atmosphere containing an inert gas, the growth of the interface reaction layer can be suppressed by reducing the residual oxygen partial pressure and the water pressure as described above.

In the processing step after the formation of the high dielectric constant thin film, the interface reaction can be stopped by setting the residual oxygen partial pressure and the water pressure to 1 × 10 ⁻⁸ Torr or less, and these partial pressures are reduced to 5 ×. By setting it to 10 ⁻⁶ Torr or less, the interface reaction layer can be suppressed to 0.3 nm or less, and by setting it to 1 × 10 ⁻⁴ Torr or less, the interface reaction layer can be suppressed to 1 nm or less. Furthermore, even when this high dielectric constant thin film processing step is performed under reduced pressure or in an atmosphere containing an inert gas, by performing the processing under the low residual oxygen partial pressure and low residual moisture pressure conditions as described above, It is possible to stop or suppress the growth of the interface reaction layer. In particular, since the progress of the interfacial reaction becomes remarkable at high temperatures, the effect of reducing the residual oxygen partial pressure and the water pressure becomes remarkable for the heat treatment process.

Here, the effect of reducing the residual oxygen partial pressure and the moisture pressure will be described below with reference to FIG. It has been reported that an interface transition layer (which may be a silicate layer) mainly composed of a silicon oxide film is formed at the interface between a silicon substrate and a high dielectric constant thin film such as ZrO ₂ or HfO ₂ . As shown in FIG. 1, an important matter in improving the process to solve this problem is that oxygen causing interfacial oxidation is not supplied from the high dielectric constant thin film layer 103, but the residual oxygen 106 in the gas phase is high. The point is that the oxidation reaction of the silicon substrate 101 proceeds by passing through the dielectric thin film layer 103 and reaching the interface with the silicon substrate 101 and bonding with the silicon atoms 104.

This phenomenon occurs when an interface oxide layer grows when a sample in which a high dielectric constant thin film 103 such as ZrO ₂ is deposited on a silicon substrate 101 is heat-treated in an atmosphere where residual oxygen (residual moisture) exists. It is clear from the experimental fact that when the heat treatment is performed in an ultrahigh vacuum of 1 × 10 ⁻⁸ Torr or less, the interface oxide film layer does not grow at all.

  In general, it is well known that residual oxygen and residual moisture in the atmosphere cause oxidation of the silicon substrate in various heat treatment processes. However, with respect to the silicon oxide film, even if residual oxygen is present, there is no problem that the silicon oxide film thickness increases even if heat treatment at 1000 ° C. or higher for dopant activation is performed. This is because the amount of oxygen that permeates through the silicon oxide film layer is very small compared to the amount of oxygen that permeates through the above-described high dielectric constant film. This is because the oxidation reaction does not proceed at the interface. Therefore, when the above-described high dielectric constant thin film is used, it is important to control the residual oxygen partial pressure and the residual moisture pressure in the process atmosphere with a much higher accuracy than in the prior art.

  Furthermore, the same phenomenon applies when a part of the high dielectric constant thin film layer is exposed to the processing atmosphere during film formation processes such as the formation of a high dielectric constant thin film or subsequent electrode formation. On the other hand, even when residual oxygen or moisture that does not cause a problem exists in the gas phase, a fatal problem arises due to the growth of the interfacial oxide film layer in the manufacturing process of a device having a high dielectric constant thin film.

  Considering the above effects, in the manufacturing process of a device having a high dielectric constant thin film, it is possible to grasp the allowable value as the increase amount of the interface oxide film layer and control the residual oxygen partial pressure during each process. is necessary. For example, in a process where the insulating layer thickness has not yet been reduced to the atomic level, such as a capacitor, an interface reaction layer of about 1 nm may be allowed to grow. In particular, when an ultra-thin gate having a silicon oxide equivalent film thickness of less than 1.5 nm is produced, the growth of the interface oxide layer of several atomic layers greatly affects the device characteristics. Strict control of residual oxygen partial pressure and moisture pressure is required.

  In addition, in order to improve the interfacial electrical characteristics, even in a structure in which a silicon oxide film having an atomic layer thickness is inserted at the interface between the high dielectric constant thin film and the silicon substrate, the interface oxide film thickness can be changed from the initial stacked structure by various process steps. The increase in atomic layers must be precisely controlled.

  As described above, the level of residual oxidation partial pressure required varies depending on the allowable increase in the thickness of the insulating layer.In the present invention, however, the silicon oxide equivalent film thickness is set in consideration of the film thickness controllability of the high dielectric constant thin film. Typical process conditions that can be 1.5 nm or less are illustrated. Specifically, the residual oxygen partial pressure and the residual moisture pressure at which the film thickness of the interfacial oxide film layer becomes approximately 1 nm and approximately 0.3 nm are respectively defined and used as an index for forming an ultrathin gate insulating film.

  In order to describe the above-described embodiment of the present invention in more detail, an example of the present invention will be described with reference to FIGS. FIG. 2 is a flow chart showing the film formation process of the high dielectric constant thin film of this embodiment in the order of steps, and FIG. 3 is a cross section showing an example of a process apparatus used for film formation of the high dielectric constant thin film of this embodiment. FIG.

In the following, an example in which a MOSFET device having a high dielectric gate insulating layer having a ZrO ₂ / SiO ₂ / Si laminated structure is manufactured by the film forming method of this embodiment will be described with reference to the flowchart of FIG. This embodiment shows a film forming process when a silicon oxide film layer 203 having a thickness of three atomic layers is intentionally inserted into the interface between the silicon substrate 201 and the high dielectric constant thin film layer 205. This silicon oxide film Formation of the ZrO ₂ film on the layer 203 was performed by oxidizing the metal layer in a reduced-pressure oxygen atmosphere after depositing the metal Zr layer. In FIG. 2, only the element manufacturing region is schematically shown for simplification.

  First, as shown in FIG. 2A, a silicon substrate 201 whose surface is terminated with hydrogen atoms 202 by a hydrofluoric acid solution treatment after cleaning the silicon wafer is used as a sample of the ultrathin gate insulating film forming apparatus shown in FIG. Introduced into the exchange room. Then, after the exchange chamber was evacuated, the silicon substrate 201 was transferred to the processing chamber and subjected to heat treatment in vacuum at 500 ° C., and hydrogen that had terminated the surface was desorbed to obtain a clean silicon surface. Furthermore, the heat treatment temperature was raised to 850 ° C., and the device fabrication region was planarized by surface diffusion and sublimation reaction of silicon atoms at a high temperature while being held in a vacuum (see FIG. 2B). By this step, the surface roughness index RMS measured with an atomic force microscope was 0.17 nm or less, and it was confirmed that a flat surface was formed at the atomic level.

In the process of intentionally forming the silicon oxide film layer 203 at the atomic layer level on the surface of the silicon substrate 201, the oxidation process for each atomic layer was performed by changing the oxidation conditions in a stepwise manner as follows. First, the silicon substrate 201 that has completed hydrogen desorption and planarization is oxidized at a substrate temperature of 635 ° C. and an oxygen partial pressure of 2 × 10 ⁻⁶ Torr for 10 minutes to oxidize the surface to the second atomic layer, Thereafter, the treatment was carried out for 20 minutes while changing the oxidation conditions to a substrate temperature of 720 ° C. and an oxygen partial pressure of 4 × 10 ⁻⁵ Torr to complete the oxidation up to the third atomic layer (see FIG. 2C).

  This step is based on the previously reported oxidation conditions for each atomic layer on the silicon surface, and the silicon oxide film layer 203 having a three atomic layer thickness (about 0.6 nm) is formed by the above steps. It was confirmed by X-ray photoelectron spectroscopy and electron microscopy.

Subsequent to the oxide film forming step, after the substrate temperature is lowered to room temperature and oxygen gas is sufficiently exhausted, a Zr metal source is supplied onto the silicon oxide film layer 203 by an electron beam evaporation method to form a Zr deposited layer. 204 was formed (see FIG. 2D). Thereafter, oxygen gas was again introduced into the processing chamber, and the Zr deposited layer 204 was oxidized under the conditions of a substrate temperature of 550 ° C. and an oxygen partial pressure of 1 × 10 ⁻⁴ Torr to form a ZrO ₂ layer 205 (FIG. 2). (See (e)).

  In the above oxidation treatment, since the substrate temperature was as low as 550 ° C., it was confirmed from the observation of the cross-sectional structure by photoelectron spectroscopy and an electron microscope that the interfacial silicon oxide film layer 203 did not increase from the initial film thickness. Moreover, the film thickness of the interfacial silicon oxide film layer does not increase by reducing the residual partial pressure of oxygen in the source gas other than the high dielectric constant thin film manufacturing method in which the metal film deposition and the oxidation process are separated as described above. This was confirmed by a similar method.

On the other hand, when the oxidation process after the deposition of the Zr film 204 is performed at a substrate temperature of 700 ° C. (oxygen partial pressure of 1 × 10 ⁻⁴ Torr), the interface oxidation between the ZrO ₂ layer 205 and the silicon substrate 201 is performed. The reaction progressed and the silicon oxide film thickness increased from 0.6 nm to about 1 nm.

After that, the ZrO ₂ layer 205 (about 2 nm) / silicon oxide film layer 203 (0.6 nm) / silicon substrate 201 obtained by oxidizing the Zr deposited layer 204 at 550 ° C. is used as an ultra-thin gate insulating film forming apparatus. Then, polysilicon gate formation and ion implantation of the source / drain regions 207 and 208 were performed (see FIG. 2 (f)). Also in these film forming and ion implantation processes, when the wafer sample is heated, the residual oxygen partial pressure and the residual moisture pressure in the atmosphere are reduced to 1 × 10 ⁻⁶ Torr or less, thereby interfacial silicon oxidation. It has been confirmed that the growth of the film layer 203 can be suppressed.

Further, in the activation process of the dopant of the samples, 1 × 10 ^-6 Torr or less high vacuum, or the residual oxygen partial pressure and the residual moisture pressure 1 × 10 ^-6 Torr or less of a high-purity inert gas atmosphere Then, a heat treatment at 1050 ° C. was performed. As a result, the increase in the interfacial silicon oxide film layer was successfully suppressed to less than 0.2 nm. On the other hand, when a heat treatment furnace that does not intentionally reduce the residual oxygen partial pressure or moisture pressure, such as an open-type quartz furnace in which entanglement oxidation occurs in the above heat treatment process, the high dielectric constant gate thin film is not removed. The effect of the present invention was confirmed by observing an increase in the interfacial silicon oxide film layer at the edge of the gate in contact with the phase.

As a result of measuring the MOS capacitance of the MOSFET fabricated in this step, the effective gate insulating film thickness converted to a silicon oxide film was about 1.1 nm. As a result of current-voltage measurement, the tunnel current flowing between the insulating layers when 1 V was applied was less than 0.05 A / cm ² .

The above-mentioned examples showed ZrO ₂ which is a typical high dielectric constant thin film, but other high dielectric constant thin film material candidates include Ta ₂ O ₅ , Nb ₂ O ₅ , Al ₂ O ₃ , ScO ₃ and Y ₂ O ₃ which are oxides of HfO ₂ and rare earth elements, and La ₂ O ₃ , CeO ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ and Sm ₂ O ₃ which are oxides of lanthanoid elements , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , these A typical dielectric constant is about 10-30. Further, the ternary material thin film of the above material and silicon is also considered to be applied as a high dielectric constant thin film. In these material systems as well, the formation of an interface reaction layer by oxygen permeation in the high dielectric constant thin film shown in this example is a serious problem, and the residual oxygen partial pressure and residual moisture pressure during film formation and processing are reduced. It is an effective technique to suppress (stop) the growth of the interfacial reaction layer (oxide film layer).

As described above, in the film formation process of the high dielectric constant thin film according to this example, the residual oxygen partial pressure and the residual moisture pressure are less than or equal to predetermined values during the heat treatment such as oxidation treatment and dopant activation treatment of the metal layer 204 ( 1 × 10 ⁻⁴ Torr, 1 × 10 ⁻⁶ Torr, etc.), the growth of the interface transition layer (silicon oxide film layer) formed between the high dielectric constant thin film layer 205 and the silicon substrate 201 is reduced. This makes it possible to manufacture high performance and low power consumption MOSFET devices that suppress and drastically reduce the tunnel current flowing through the gate layer.

  In this embodiment, the process for forming the silicon oxide film 203 having a thickness of several atomic layers has been described in advance. However, even if the silicon oxide film 203 is not provided, the equivalent silicon oxide film thickness may be 1.5 nm or less. it can. The high dielectric constant thin film layer 205 is formed by depositing the metal layer 204 and then oxidizing it, but the high dielectric constant thin film layer 205 may be formed directly. Further, in this embodiment, an example in which the high dielectric constant thin film layer 205 is used as a gate insulating film has been described. However, the present invention is not limited to the above embodiment, and a high dielectric constant thin film other than the gate insulating film is required. It is obvious that the high dielectric constant thin film of the present invention may be formed at the site.

DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Interface silicon oxide film layer 103 High dielectric constant thin film layer 104 Silicon atom 105 Oxygen atom 106 Residual oxygen in gas phase 201 Silicon substrate 202 Surface hydrogen 203 Silicon oxide film layer 204 Metal (Zr) deposition layer 205 High dielectric constant thin film (ZrO ₂ ) layer 206 Gate electrode 207 Source region 208 Drain region 301 Sample introduction chamber 302 Processing chamber 303 Transport system 304 Substrate heating mechanism 305 Silicon wafer 306 Electron beam deposition device 307 Oxygen gas introduction mechanism 308 Vacuum exhaust system

Claims (5)

The thickness of the interfacial reaction film formed at the silicon substrate interface is the atomic layer level in the oxidation process of the metal layer for forming the high dielectric constant thin film and / or the treatment process after the film formation of the high dielectric constant thin film. A method for manufacturing a semiconductor device, characterized in that both the residual oxygen partial pressure and the residual moisture pressure are controlled in an atmosphere of 1 × 10 ⁻⁴ Torr or less. The treatment after film formation, a heat treatment, a method of manufacturing a semiconductor device according to claim 1, wherein. The treatment after film formation, including activation of the dopant, a manufacturing method of a semiconductor device according to claim 1, wherein. Manufacturing method of the process after the film formation, the semiconductor device according to any one of claims 1 to 3, characterized in that in an atmosphere containing a reduced pressure atmosphere or an inert gas. A method for manufacturing a semiconductor device, comprising the process according to claim 1 at least once .

Images