JP4822249B2 - Solid-state imaging device and identification information providing method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device and a method for providing identification information thereof, and relates to a technique that is effective when used for an identification information providing technique for a CCD type or MOS type area sensor.

In recent years, with the development of large-capacity and inexpensive storage devices and high-speed communication infrastructure, image data such as still images and moving images can be easily handled, and image data has been handled in various industrial and consumer fields. ing. For example, there are a mobile phone with a camera, a monitoring device for crime prevention, a safety confirmation of a moving body such as an automobile, and a device for detecting a danger. For these, a solid-state imaging device generally called an image sensor such as a CCD type or a MOS type is used. Japanese Patent Application Laid-Open No. 2004-297613 discloses a technique in which a wireless tag is provided in a solid-state image pickup device and information about an image pickup element is acquired even after being mounted on a device. Examples of providing an identification information circuit in a semiconductor integrated circuit device include JP-T-2002-537646, JP-A-2003-332452, and JP-A-2005-005432.
JP 2004-297613 A JP 2002-537646 Gazette Japanese Patent Laid-Open No. 2003-332452 JP 2005-005432 A

  While the applications of the image sensor have expanded, recent digital cameras have also developed an imaging device that uses a solid-state imaging device with over 10 million pixels to achieve a resolution comparable to a so-called Ginyuan camera. I came. In such a solid-state imaging device with a large number of pixels, it is necessary to miniaturize the manufacturing process, and in the solid-state imaging device mounted on a mobile phone, there is an increasing demand for miniaturizing the device for miniaturization. However, reducing the pixel itself reduces the performance margin, but the output image is ultimately determined by the human senses, so there are slight noise, defects, unevenness, fluctuations, It becomes severe due to deterioration. Therefore, in such a solid-state imaging device, the maintenance and improvement of the yield due to the increase in the number of pixels and the size increase, the quality such as the homogenization and uniformity of the image quality and performance, and the reliability as a device for in-vehicle applications. Therefore, quality control at a higher level than other semiconductor devices is required.

  However, the image sensor does not have a concept of so-called redundancy repair in which a defective pixel such as a memory is replaced with a spare one. Defects are only relieved by complementation by image processing technology, and can only deal with defects in pixel units called white spots or black spots, so the problem of yield is serious. Due to the above-described background, in the solid-state image sensor, in order to manage yield, quality, and reliability, there is an increasing need for individual management of so-called individual solid-state image sensors. In order to perform single item management, it is necessary to assign a unique identification number to each solid-state imaging device.

  In Patent Document 1, a technique for mounting a wireless tag is disclosed. However, an identification number, a manufacturing number, an overflow drain voltage, a reset voltage, a light receiving element sensitivity, the number of defective pixels, and defective pixels are individually provided on a solid-state imaging device chip. A separate wireless tag storing the address, etc. is required, and it is difficult to find out if the wireless tag is written in the wireless tag corresponding to each solid-state image sensor and if the wireless tag is accidentally attached to another solid-state image sensor. Therefore, the number of assembling steps such as the necessity of correctly attaching the wireless tag corresponding to each solid-state imaging device and the cost increase are not practical.

  Patent Documents 2 to 4 are mainly suitable for a large-scale LSI having a CMOS configuration, and it is theoretically possible to mount the LSI directly on a CCD type or MOS type solid-state imaging device. However, in order to form the identification information circuit, it is necessary to add a process such as forming a new element and a special semiconductor structure, or to add a terminal only for extracting identification information. Occurs.

  In a normal semiconductor device, arbitrary identification information may be given to the semiconductor device by cutting a fuse made of metal or polysilicon using laser light. However, the fuse cutting process causes scattering of dust due to the cutting, so that it is difficult to apply to the solid-state imaging device because it deters dust on the imaging surface. In addition, in a semiconductor device including a nonvolatile memory element such as an EPROM, arbitrary identification information and information related to the device are written into the element. However, such an element is newly added to the solid-state imaging element. The mounting is not practical because it increases the cost as described above.

  An object of the present invention is to provide a solid-state imaging device including an identification information source that is easy to manufacture and a method for providing the identification information. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A plurality of MOSFETs (hereinafter referred to as MOS) formed in the same form in the same manufacturing process on a solid-state imaging device having a signal transmission circuit that sequentially transmits signals corresponding to photoelectric conversion signals by a plurality of photodiodes according to timing signals A first circuit for taking out a gate-source voltage of a transistor as a first voltage is provided. A second circuit for sequentially outputting the plurality of first voltages formed by the first circuit is provided. An identification information source is constituted by the first circuit and the second circuit.

  As a method for providing identification information of a solid-state imaging device including a signal transmission circuit that sequentially transmits signals corresponding to photoelectric conversion signals by a plurality of photodiodes according to a timing signal, a plurality of the same forms are used in the same manufacturing process. There are provided a first circuit for taking out the voltage between the gate and source of the MOSFET as a first voltage, and a second circuit for sequentially outputting signals corresponding to the plurality of first voltages. The result of comparing the magnitude levels of the signals output from the second circuit is used as identification information of the solid-state image sensor.

  It is possible to realize an identification information source and an identification information providing method using element variation in a manufacturing process of a solid-state imaging element.

  FIG. 1 shows a schematic block diagram of an embodiment of a solid-state imaging device according to the present invention. This embodiment is directed to a CCD type solid-state imaging device. The detailed circuit and operation description of the CCD type solid-state imaging device itself is left to a technical book, but is roughly as follows. That is, the electric charges photoelectrically converted and accumulated by the photodiode 100 are transferred to the vertical CCDs 101 arranged adjacent to each other. In the vertical CCD 101, the signals are transferred toward the horizontal CCD 102 sequentially one row at a time by the vertical transfer signals Vφ1, Vφ2, Vφ3, and Vφ4.

  The horizontal CCD 102 sequentially transfers signal charges for one row transferred from the vertical CCD 101 to the amplifier 103 in response to horizontal transfer signals Hφ 1 and Hφ 2 during a transfer period for one row in the vertical CCD 101. In this way, all signal charges photoelectrically converted by the photodiode 100 arranged in the horizontal and vertical directions one by one in the region between the OG electrode and the φRG electrode, that is, the voltage signal in the floating diffusion region FD. Is converted to The converted voltage signal is amplified by the amplifier 103 and then output from the output terminal VOUT. The φRG electrode resets the voltage signal corresponding to the read signal charge to the voltage RG.

  In this embodiment, an identification information generation source suitable for assigning a unique identification number to the CCD type solid-state imaging device as described above is provided. A unit identification information source 301 is provided on the first stage in the transfer direction of the vertical CCD 101, that is, on the side opposite to the output side corresponding to the junction with the horizontal CCD. The identification voltage Va formed by the unit identification information source 301 is in the form of electric charge and is transmitted to the input stage of each vertical CCD 101 by the VG electrode. In this way, the plurality of identification voltages Va are transferred in parallel to the horizontal CCD 102 through the vertical CCDs 101 in the form of electric charges. In the horizontal CCD 102, charges corresponding to a plurality of identification voltages Va transferred in parallel from the plurality of vertical CCDs 101 are sequentially transferred.

  In the output section of the horizontal CCD 102, each charge transferred in the floating diffusion region FD is converted into a voltage signal in the same manner as the normal pixel signal output operation. The converted voltage signal is amplified by the amplifier 103 and then output from the output terminal VOUT. Since the identification voltage Va formed by the identification information source 301 is an analog signal, the voltage signal output from the output terminal VOUT is also in the form of an analog signal. Such an analog signal is converted into a digital signal as a unique identification information signal by signal processing to be described later. In this embodiment, the unit identification information source 301 is regarded as a solid-state imaging device added to the first stage side of the vertical CCD 101. As a result, it is possible to provide a circuit for generating identification information and outputting it without adding a special control mechanism to the CCD solid-state imaging device.

  FIG. 2 shows a circuit diagram of an embodiment of the unit identification information source 301 of FIG. In this embodiment, an N channel MOS transistor Q1 is used as a unit identification information source. This MOSFET Q1 is so-called diode-connected with its drain and gate short-circuited, and a resistor R1 is connected in series. The gate-source voltage Va of the NMOS transistor is approximately the voltage of the threshold voltage Vth + α of the NMOS transistor Q1. The above α depends on the drain current of the NMOS transistor Q1, but when the transistor is in the saturation operation region, the voltage Va is a value mainly reflecting random variations in the threshold voltage Vth of the NMOS transistor Q1. A plurality of unit identification information sources 301 similar to the above are provided corresponding to the plurality of vertical CCDs 101. Accordingly, the plurality of unit identification information sources 301 are formed in the same form with the same manufacturing process.

  FIGS. 3 and 4 are explanatory views of the charge transfer mechanism according to the vertical CCD of FIG. 3 and 4, (a) shows a vertical sectional structure of the vertical CCD 101, and (b) shows an example of a potential distribution corresponding to the sectional structure. FIG. 3 shows an example in which charges from the photodiode 100 not handling the identification information are normally transferred, and FIG. 4 shows an example in which identification information is transferred.

  In FIG. 3, VF = L (low level) is set, and no current flows through the unit identification information source including the resistor R and the NMOS transistor Q1, and therefore the voltage Va reflected on the threshold voltage Vth as described above is not generated. The identification information transfer gate VG is set to a low voltage and the gate is turned off, and the charge of the N + diffusion layer is maintained as it is and is not transferred to the vertical CCD 101. As described above, during the normal imaging operation, no current flows through the unit identification information source 301, so that wasteful current consumption can be suppressed.

  In FIG. 3, the vertical transfer operation is performed by the combination of the vertical transfer signals Vφ4 = H / L, Vφ3 = H / L, Vφ2 = H / L, and Vφ1 = H / L shown at times t1 to t6. That is, in the same figure, from time t1 to time t7, it is shown that the signal charge due to photoelectric conversion formed by the photodiodes under the Vφ3 and Vφ2 electrodes moves to the right and down to the Vφ4 and Vφ3 electrodes. ing.

  In FIG. 4, VF = H (high level) is set, and a current flows through the unit identification information source including the resistor R and the NMOS transistor Q1, and thus the voltage Va reflected on the threshold voltage Vth is generated. The identification information transfer gate VG is at a high voltage and the gate is turned on. Therefore, the potential of the output Va of the unit identification information source 301 is transferred to the vertical CCD 101 region via the identification information transfer gate VG. To reach. In the same state, when a vertical transfer operation is performed using normal vertical transfer signals Vφ1, Vφ2, Vφ3, and Vφ4, a so-called potential well in the first stage portion of the vertical CCD 101 extends from the unit identification information source 301 from time t1 to time t6. It becomes equal to the potential of the output Va. In the state at time t7, the output Va of the unit identification information source 301 and the vertical CCD 101 are separated by a low voltage of Vφ4, and charges corresponding to the potential of the voltage Va remain in the vertical CCD 101. Thereafter, a charge vertical transfer operation corresponding to the voltage Va of the unit identification information source 301 is performed by normal vertical transfer signals Vφ1, Vφ2, Vφ3, and Vφ4.

  The unit identification information source 301 and the transfer gate region for converting the potential Va of the unit identification information source 301 into the charge amount are important regions responsible for generation of the identification information source, and therefore, for example, avoid the influence of light. For the purpose, the region may be covered with an aluminum layer. In order to use the normal CCD operation as it is, the signal charge from the photodiode is also transferred to each stage of the vertical CCD. However, these signals are ignored (discarded) when the voltage Va of the identification information source is read. That is, after sweeping out signal charges for one normal screen, the voltage Va of the unit identification information source 301 is output for one horizontal.

  FIG. 5 shows an explanatory diagram of an embodiment of the identification information providing method according to the present invention. 1 are output from the output terminal VUOT of the solid-state imaging device of FIG. 1 as shown in FIG. The analog voltage amounts 9, 6, 4, 13, 8,... Indicate examples of digital amounts that are analog-to-digital converted by a measuring device such as a tester (not shown). The digital quantity values 9, 6, 4, 13, 8,... Are obtained by analog-digital conversion of the voltage of the output Va of the unit identification information source 301 by the measuring device. The digital quantity is affected by variations in the threshold voltage Vth of the NMOS transistor Q1, and shows different values and changes for each solid-state imaging device. That is, the digital quantity can be handled as identification information unique to each solid-state imaging device by performing the following signal processing.

  FIG. 5B shows an explanatory diagram of an embodiment of a highly reliable identification information providing method while reducing the amount of data handled by processing the digital value shown in FIG. 5A. Yes. As shown in FIG. 5A, if the digital quantity after analog-digital conversion is handled as it is, for example, if the digital quantity is represented by 8 bits, one unit identification information source 301 is The amount of data related to the identification information simply increases by 8 bits, and the influence on the charge transfer path is reflected as it is. Therefore, an increase in the data amount is suppressed by obtaining a continuous change amount of the digital amount and binarizing it according to the sign of the change amount. That is, when the digital amount increases, it is defined as “1”, and when it decreases, it is defined as “0”.

  This configuration is reflected in the difference in threshold voltage between the NMOS transistors Q1, and the influence on the charge transfer path can be greatly reduced. That is, in this embodiment, the difference between the threshold voltages of a plurality of MOSFETs formed in the same form in the same manufacturing process is reflected in the identification information. That is, each of the plurality of MOSFETs is configured to have the same structure and the same size. Needless to say, these elements are manufactured according to the characteristics of the semiconductor integrated circuit device in which the same elements are manufactured together under the same process. As a result, the plurality of MOSFETs Q1 are equally affected by manufacturing variations such as variations in processing dimensions in manufacturing the semiconductor integrated circuit device, thickness variations of various layers, impurity concentration variations, and the like.

  As described above, the gate-source voltage of the MOSFET whose gate and drain are short-circuited becomes equal to the threshold voltage Vth. If all MOSFETs have completely the same electrical characteristics, the threshold voltages Vth of the plurality of MOSFETs are equal. However, this is an ideal state, and in an actual semiconductor element, there is a slight difference in characteristics, so that a difference occurs in the threshold voltage Vth of the MOSFET. As the cause of the variation in the threshold voltage Vth of the MOSFET, the gate width of the MOS transistor, the gate insulating film thickness, the conductivity determining impurity concentration and its distribution can be cited. These variations can be divided into macro parts and micro parts. The macro portion includes variations in gate width between a plurality of wafers in the same lot.

  In the present invention, the variation of the micro part is mainly used, and the variation in the elements arranged at relatively close positions is used. This is because such microscopic variations are observed to occur randomly between elements that are relatively close to each other. That is, the variation in the threshold voltage Vth of the MOSFET Q1 in FIG. 2 is considered to be random. The variation in the threshold voltage Vth is a basis for extracting the characteristic characteristic variation of the semiconductor element, which is one feature of the present application, as unique identification information. In order to extract such characteristic variation of the semiconductor element as unique identification information, it is defined as “1” when the digital amount as described above is increased and defined as “0” when it is decreased. It corresponds to that.

  FIG. 5 (c) shows an explanatory diagram of an embodiment of the identification information providing method in consideration of the digital quantity having the behavior of specific change behavior. The behavior of a specific change means that, for example, the continuous digital quantity has a tendency to increase or decrease in one direction as a whole, or has a periodicity such that an even number is larger than an odd number. . These behaviors may occur under the influence of the arrangement of the unit identification information source 301 and the surrounding layout environment. If there is such a habit, since the obtained identification information includes a bias, the randomness is lowered. Therefore, a further change amount of the continuous digital amount change amount (referred to as a double digital amount change amount) is obtained and binarized according to the sign of the change amount. That is, it is defined as “1” when the change in the double digital quantity continuously increases, and defined as “0” when it decreases. As a result, the above behavior can be removed from the change in the digital quantity, and identification information having high-quality randomness can be obtained.

  FIG. 5D shows an explanatory diagram of another embodiment of the identification information providing method for processing the digital quantity into identification information. In this embodiment, the two digital quantities are combined by combining two digital quantities and defined as “1” when the difference value is positive and defined as “0” when negative. This also removes the above behavior from the change in the digital quantity, and can obtain identification information having high-quality randomness.

  FIG. 5 (e) shows an explanatory diagram of still another embodiment of the identification information providing method for processing in consideration of the digital quantity having the behavior of specific change behavior. A change amount of a difference obtained by combining the plurality of digital amounts two by two and comparing both digital amounts is obtained, and binarized according to a sign of the change amount. That is, when the change amount of the double difference increases, it is defined as “1”, and when it decreases, it is defined as “0”. As a result, the above behavior can be removed from the change in the digital quantity, and identification information having high-quality randomness can be obtained. In the above embodiment, the analog amount is once converted into a digital amount, but of course, the analog amount itself may be compared in size using a comparator circuit or the like to perform similar signal processing. Good.

  FIG. 6 is a schematic block diagram showing another embodiment of the solid-state imaging device according to the present invention. In the embodiment of FIG. 1, the unit identification information source 301 is arranged on the first stage side (endmost part) of the vertical CCD 101. Therefore, it is necessary to pass through the vertical CCD 101 and the horizontal CCD 102 before the amount of charge corresponding to the voltage Va of the unit identification information source 301 is led to the amplifier 103, and it is easily affected by various noises. Therefore, in this embodiment, charges corresponding to the voltage Va of the unit identification information source 301 are directly transferred to the horizontal CCD without the vertical CCD 101. For this reason, the vertical CCD 101 and the unit identification information source 301 are distributed and provided across the horizontal CCD 102. That is, the unit identification information source 301 is arranged on the side opposite to the side where the vertical CCD 101 is provided, and the transfer gate electrode VG is arranged correspondingly. With this configuration, in this embodiment, the path of the vertical CCD 101 can be omitted, so that the influence of the noise can be reduced.

  FIG. 7 is a schematic block diagram showing still another embodiment of the solid-state imaging device according to the present invention. In this embodiment, a dummy vertical CCD 1011 is provided. The dummy vertical CCD 1011 is newly added in order to guide the electric charge corresponding to each voltage Va to the horizontal CCD 102 with the unit identification information source 301 arranged in the vertical direction correspondingly. For this reason, the horizontal CCD 102 is added by one stage corresponding to the dummy vertical CCD 1011. The potential of the output Va of the plurality of unit identification information sources 301 is a charge corresponding to Va to the dummy vertical CCD 1011 via an identification information transfer gate under the VG electrode turned on by a high voltage of VG and Vφ1 or Vφ3. Accumulated as a quantity. Thereafter, the images are sequentially transferred in the vertical direction according to the normal vertical CCD transfer method. Then, it is transferred to the amplifier 103 via the horizontal CCD 102. In this figure, the vertical CCD 1011 is disposed at the far end of the horizontal CCD as viewed from the output terminal VOUT, but it may be the near end on the opposite side.

  8 and 9 are circuit diagrams showing another embodiment of the unit identification information source according to the present invention. The CCD has a structure suitable for the essential function of transferring pixel information of the image sensor. Therefore, the manufacturing process of the CCD type solid-state image sensor pursues optimization of the performance of the photodiode and the CCD as much as possible. It is. It can be said that elements other than those necessary for the purpose of imaging are not mounted. Therefore, the active element normally used in the CCD type solid-state imaging device is only an NMOS transistor based on a CCD structure generally used for the source follower type amplifier 103. Therefore, the unit identification information source 301 mounted on the CCD type solid-state imaging device needs to be constituted by an NMOS transistor and a resistor using an N type diffusion layer for constituting the CCD.

  FIG. 8A shows the resistance load R1 in the circuit of FIG. 2 changed to a load by the NMOS transistor Q2. That is, the enhancement type NMOS transistor Q2 has its gate and drain connected to operate as a resistance element. In selecting the diffusion layer resistor R1 as described above or the NMOS transistor Q2 as in this embodiment as the load resistor, each process variation, layout area, and the like are considered. Although not particularly noted, it is possible to replace the resistance element with an NMOS transistor in the following embodiments. The NOS transistor may be a depletion type. In the depletion type MOS transistor, for example, a gate and a source are connected.

  FIG. 8B shows an example of a complementary unit identification information source using a difference in threshold voltage Vth between two NMOS transistors Q1 and Q3. This circuit is a so-called constant current source circuit. When the left and right NMOS transistors Q1 and Q2 and the resistors R1 and R2 have the same characteristics, that is, when the left and right NMOS transistors are ideally targeted, The same current flows through Q2 and the resistors R1 and R2, and the voltages Va and Vb are at the same potential. Here, if the threshold voltage Vth of the NMOS transistor Q1 is slightly higher than that of the NMOS transistor Q3 by ΔVth, the drain and gate potential of the NMOS transistor Q1, that is, the voltage Vb, rises substantially by ΔVth. As a result, the current of the NMOS transistor Q3 increases and the voltage Va drops. The change amount ΔVa is approximately ΔVa = (− gm · R) ΔVth. That is, a potential difference of gm · R times the Vth difference between the left and right transistors Q1 and Q3 is generated between the voltages Va and Vb. Here, R is the value of the load resistors R1 and R2, and gm is the mutual conductance of the NMOS transistors Q1 and Q3, which depends on the constants (channel width / channel length) of the NMOS transistors Q1 and Q3 and the steady current.

FIG. 8C shows another example using the difference in threshold voltage Vth between two NMOS transistors. This circuit is provided with an NMOS transistor Q4 to which the drain voltage (Vb) of the NMOS transistor Q3 is supplied to the gate and a load resistor R3. The voltages Vb and Va are obtained from the drains of the NMOS transistors Q3 and Q4. Thus, the current mirror circuit is double-connected. When there is a ΔVth difference between the NMOS transistors Q1 and Q3, a potential difference of gm · R times ΔVth is generated between the voltages Vb and Vc. Furthermore, a potential difference of (gm · R) ² times ΔVth is generated between Va and Vb. For example, assuming that gm · R is 10 times and the Vth difference is 10 mV, the output potential difference is 1V. Since the amplitude of the video signal output of the CCD type solid-state imaging device is generally 1 to 2V, 1V is a sufficiently large value.

  FIG. 8 (d) shows the NMOS transistors Q11 and Q12 having two stages of diode connections. As a result, the steady value of the voltage Va is doubled in the case of simple calculation rather than one stage. Furthermore, since the variance, which is the fluctuation range of the voltage Va, is twice and the standard deviation is √2 times (1.4 times), identification information with clearer variation can be generated. When the number of NMOS transistors is three, the value of the output Va is three times in the case of simple calculation, and the variance of Vth is three times, and the standard deviation is √3 times (1.7 times). Become.

  In FIG. 8 (e), two stages of diode connections of the NMOS transistors Q11 and Q12 are provided, and two stages of NMOS transistors Q31 and Q32 are provided correspondingly, and the difference in threshold voltage Vth between the two NMOS transistors is used. ing. That is, it is a cascade type constant current source circuit in which the above-described FIGS. 8B and 8C are combined.

  FIG. 8F shows a current mirror circuit in which NMOS transistors are diode-connected in two stages and are double-coupled in combination with the configuration shown in FIG. This further increases the potential difference between the voltages Va and Vb.

  FIG. 9A shows a case where the NMOS transistors Q11 and Q12 have two stages of diode connections and are based on the drain. The potential of the voltage Va is VF− (2 × Vth). By controlling the voltage of the operating voltage VF, it is relatively easy to arbitrarily set the steady potential of the voltage Va.

  FIG. 9B is a modification of FIG. 8E, and among the two-stage connected NMOS transistors Q11, Q12 and Q31, Q32, the NMOS transistors Q11 and Q32 are diode-connected. NMOS transistors Q11 and Q31 are connected in a diode form, and NMOS transistors Q32 and Q12 are connected in a diode form. That is, a Wilson type constant current source circuit is formed.

  In FIG. 9C, switches SW1 and SW2 are provided in parallel to the NMOS transistors Q1 and Q3, respectively. Thereby, arbitrary fixed information can be inserted into a part of the identification information. This figure shows one embodiment of the complementary unit identification information source. The state of the switches SW1 and SW2, that is, whether they are short-circuited or disconnected, is determined on a photomask for an aluminum wiring layer used for manufacturing a CCD solid-state imaging device. Determined by the corresponding figure. For example, when the switch SW1 is short-circuited, the potential of the output Va is always higher than that of Vb, so that the corresponding identification information is always fixed to either defined '1' or '0'. For example, fixed information such as a production lot can be inserted.

  FIG. 9D shows the load resistance in FIG. 9A changed to a constant current source. Since the reference current source including the NMOS transistor Q1 and the resistor R1 is common to the plurality of unit identification information sources 1010, the area can be reduced.

  FIG. 9E shows an embodiment in which outputs of two unit identification information sources are output from one terminal Va. This is a combination of the resistor R1 and the voltage Va in which two of FIG. 9A are connected in parallel. When the potential of the voltage VF1 is increased and the potential of the voltage VF2 is decreased, the voltage Va is lower than the voltage VF1 by the sum of the threshold voltages of the NMOS transistors Q11 and Q12. When the voltage VF1 is lowered and the voltage VF2 is raised, the voltage Va is lower than the voltage VF2 by the sum of the threshold voltages of the NMOS transistors Q51 and Q52. Thereby, the amount of identification information can be easily increased by adding the NMOS transistors Q51 and Q52 and the voltage VF2.

  FIG. 10 shows a schematic configuration diagram of an embodiment of a CCD solid-state imaging device using a unit identification information source that forms two voltages Va and Vb. The unit identification information source in this embodiment is a complementary unit identification information source 3011. The voltage outputs Va and Vb formed by the complementary unit identification information source 3011 exhibit opposite changes such that when one rises or falls, the other falls or rises. Furthermore, since the absolute value of the change amount of the voltage Va is gm · R times the difference between the threshold voltages Vth of the left and right transistors Q1 and Q3, the difference between the threshold voltages Vth of the left and right transistors Q1 and Q3 appears more clearly. Therefore, it is possible to generate the identification information more reliably by transmitting the charge amount corresponding to the potentials of the voltages Va and Vb to the vertical CCD 101 and the horizontal CCD 102, converting the charge amount into the charge voltage, and comparing it. It is. The same applies to the unit identification information sources provided in the solid-state imaging device of this embodiment as shown in FIGS. 8C, 8E, 8F, 9B, and 9C.

  FIG. 11 shows a schematic configuration diagram of another embodiment of a CCD solid-state imaging device using a unit identification information source that forms two voltages Va and Vb. The stored charges corresponding to the voltages Va and Vb of the complementary unit identification information source 3011 are affected by various noises during transmission through the vertical CCD 101. Therefore, by transferring the charges in parallel using a plurality of vertical CCDs 101, fluctuations in the charge amount due to the influence of noise can be suppressed. For example, in the figure, two voltage values of the output terminal VOUT corresponding to the voltages Va and Vb are obtained, respectively, and the average can be regarded as the potential of Va or Vb.

  FIG. 12 shows a configuration diagram of another embodiment in which the information of the unit identification information sources arranged in the vertical direction is parallelized. The solid-state imaging device of this embodiment is provided with a dummy vertical CCD as shown in FIG. 7, and transfers charges corresponding to the voltage Va formed by the unit identification information source 301 to two adjacent dummy vertical CCD stages, The output unit averages it and obtains identification information from the difference between adjacent unit identification information sources 301.

  FIG. 13 shows a configuration diagram of still another embodiment in which the information of the unit identification information sources arranged in the vertical direction is parallelized. In this embodiment, the voltages Va and Vb of the complementary unit identification information source 3011 are output by the dummy vertical CCD similar to that shown in FIG. In this example, as described above, the complementary unit identification information source 3011 forms voltages Va and Vb in a form in which the difference in process variation of the threshold voltage Vth of the NMOS transistor is amplified, and the same dummy vertical CCD is used. Therefore, identification information unique to the solid-state imaging device can be obtained by signal processing such as simple voltage comparison of the output signal VOUT.

  As described above, the inventor has devised a method suitable for a CCD type solid-state imaging device with respect to a technique for providing identification information to a semiconductor device. Furthermore, the inventor devised a method suitable for a CMOS solid-state imaging device in a study on a technique for providing identification information using a characteristic variation of an element to a semiconductor device.

  A CCD solid-state image sensor is specialized for the purpose of taking an image, and is composed of a photodiode, a CCD, and a few NMOS transistors, and is a semiconductor device that is different from a general LSI. Then it is a special existence. On the other hand, the CMOS type solid-state imaging device is based on a general CMOS semiconductor manufacturing / design technology, and is not significantly different from a general LSI except for a photoelectric conversion unit using only a photodiode.

  The inventor researched and researched solid-state image sensors, and the existence of CMOS-type solid-state image sensor fixed pattern noise and the fixed pattern noise were caused by threshold MOS transistor variation in the photoelectric conversion unit of the CMOS-type solid-state image sensor. I realized that the threshold variation can be used as an identification information source.

  FIG. 14 and FIG. 15 show a configuration diagram of an embodiment of a CMOS type solid-state imaging device according to the present invention. A detailed description of the operating principle of the CMOS type solid-state imaging device will be left to a technical book, but is roughly as follows. First, the accumulated charge at the cathode electrode end Nk of the photodiode PD is initialized by the high voltage of the reset signal RR from the vertical scanning circuit 1201 and the NMOS transistor MR, and then the photoelectric conversion of the irradiated light and the photodiode PD is performed. Electric charges are accumulated at the cathode electrode end Nk, and light is converted into an electrical physical quantity. Thereafter, the output of the amplification MOS transistor MA is transmitted to the column signal line CD via the switch NMOS transistor MS which is turned on with a high voltage on the horizontal selection line, and passes through a circuit 1202 and a column selection switch 1304 which will be described later in the horizontal scanning circuit 1203. Are output to the common signal line CB.

  The amplification MOS transistor MA is a source follower type, and a voltage lower than the gate voltage of the amplification MOS transistor MA by the threshold voltage Vtm is present at the end of the constant current source 1303 if the resistance of the column signal line CD is ignored. appear. Eventually, the threshold value Vtm of the amplification MOS transistor MA influences when the amount of light is extracted as electric charge and voltage value. The threshold voltage Vtm varies in the manufacturing process, and the magnitude of the variation is not negligible compared to the size of the original video signal obtained by the photoelectric conversion. Therefore, a CMOS type solid-state imaging device always includes a fixed pattern noise suppression circuit 1302 (generally referred to as CDS) for canceling the threshold voltage by various methods. In other words, the CMOS type solid-state imaging device cannot avoid the influence of the variation of the threshold voltage Vtm of the amplification MOS transistor MA, and at the same time, the variation can be used as an identification information source.

  The identification information source 1204 is a dedicated identification information generation source that generates a threshold variation that is a source of identification information based on the image sensor 1025 of a CMOS solid-state image sensor, and is adjacent to the regular image sensor 1205. Be placed. The identification information generation circuit 1202 is a circuit that generates identification information from a signal generated by the identification information generation source 1204.

  FIG. 16 shows a circuit diagram of one embodiment of the identification information source 1204 and the identification information detection circuit 1202. The identification information source 1204 basically has the same configuration as that of the original imaging circuit 1205 of the imaging device, but in order to eliminate the influence of the reset MOS transistor MR and the photodiode PD, the drain and source of the amplification MOS transistor MA are short-circuited. It is different in letting it be done.

  When a specific row selection line RS becomes a high voltage, the switch MOS transistor MS of the corresponding two identification information sources 1204 is turned on, and the two inputs of the comparator 1402 in the identification information generation circuit 1202 have the above two identifications. A voltage lower than the power supply voltage is generated by the threshold voltage Vth of each amplification MOS transistor MA in the information source 1204. The threshold voltage Vth of the two amplification MOS transistors MA has random variations as described above. When the threshold voltage Vth of the amplification MOS transistor MA in the identification information source 1204 on the “+” input side of the comparator 1402 is larger than that on the “−” side, the voltage of the column signal line CDa becomes lower than the voltage of CDb. The output CPP 1402 is a low voltage. A state where the voltage of the CPP is low is defined as identification information “0”. Further, when the magnitude relation of the input voltage is reversed, the output CPP of the comparator 1402 is a high voltage. The high voltage state is defined as identification information “1”.

  FIG. 17 shows a circuit diagram of an embodiment of an identification information source for inserting arbitrary fixed information into a part of the identification information. In FIG. 17A, identification information “1” is always obtained, and the switch MOS transistor MS on the “−” input side of the comparator 1402 is opened (not connected) from the column signal line CDb. Conversely, FIG. 17B always obtains identification information “0”, and the switch MOS transistor MS on the “+” input side of the comparator 1402 is opened from the column signal line CDa (not connected). .

  FIG. 18 shows a circuit diagram of an embodiment of an identification information source for inserting arbitrary fixed information into a part of identification information in a photodiode + FD pixel. 18A always obtains identification information “1”, and FIG. 18B always obtains identification information “0”. Also in this example, the switch MOS transistor MS is opened from the column signal line CDb or the column signal line CDa as in FIG. The photodiode + FD type pixel in the figure is naturally applied to a regular image sensor 1025.

  FIG. 19 shows a block diagram of another embodiment for giving identification information to a CMOS type solid-state imaging device. This embodiment is a serial identification information generation method. The identification information source 1204 is adjacent to the regular image sensor 1205 and arranged in only one column. The identification information is generated based on the difference between the threshold voltages Vth of the amplification MOS transistors MA in the two adjacent identification information sources 1204. That is, the identification information detection circuit 1601 uses the first and second identification information sources 1204, the third and fourth identification information sources 1204, the fifth and sixth identification information sources 1204, and thereafter the Nth and N + 1th identification information. Each bit is generated from the source 1204 to 1 bit. The identification information source 1204 may use a dummy element disposed on the outer periphery of a regular imaging element.

  FIG. 20 shows a circuit diagram of an embodiment of an identification information detection circuit 1601 suitable for the serial identification information generation method. This embodiment circuit receives the column selection line CDx and obtains identification information at the output CPS of the latch 1701 by signals T, W, and L.

  FIG. 21 is a waveform diagram for explaining the operation of the identification information detection circuit 1601 of FIG. The figure shows an example in which identification information is generated from two identification information sources 1204 selected by RS0 and RS1. The amplification MOS of the identification information source 1204 selected by RS0 with reference to the logic threshold voltage formed by short-circuiting the inputs and outputs of the amplifier circuits AMP1 and AMP2 formed of inverter circuits by the high levels of the signals W and T A voltage (Vdd−Vth0) corresponding to the threshold voltage Vth of the transistor MA is held in the capacitor C1. The signal W is set to the low level, and the voltage (Vdd−Vth1) corresponding to the threshold voltage Vth of the amplification MOS transistor MA of the identification information source 1204 selected by RS1 by the high level of T is input to the capacitor C1.

  If (Vdd−Vth0)> (Vdd−Vth1), the voltage transmitted through the capacitor C1 becomes lower than the logic threshold voltage, and is amplified by the two-stage amplifier circuits AMP1 and AMP2 to be output at a low level. A signal is formed. On the other hand, if (Vdd−Vth0) <(Vdd−Vth1), the voltage transmitted through the capacitor C1 becomes higher than the logical threshold voltage, and is amplified by the two-stage amplifier circuits AMP1 and AMP2 to output a high level output signal. Is formed. These high level / low level amplified signals are held in the latch 1701 by the signal L. The capacitor C2 performs offset cancellation while holding the difference between the logic threshold values of the amplifier circuits AMP1 and AMP2.

  FIG. 22 is a block diagram showing an embodiment in which identification information unique to the image sensor is extracted from the frame buffer type CMOS image sensor. In the frame buffer system, the fixed pattern noise is removed by external signal processing. Detailed operation explanation is left to a technical book, but it is roughly as follows. That is, the variation in the threshold voltage Vth of the amplification MOS transistor MA in the image sensor that is the cause of the fixed pattern noise is once taken into the frame buffer 1903 in a state where light is blocked, and is subtracted from the signal obtained by normal imaging. Is. That is, the frame buffer 1903 is information on the variation of the threshold voltage of the amplification MOS transistor MA in the image sensor, and is extracted by the identification information extraction circuit 1905 or the signal processing software.

  FIG. 23 shows a schematic block diagram of an embodiment of a CCD solid-state imaging device having a function of giving unique identification information according to the present invention. When a CCD solid-state imaging device is used, the CCD solid-state imaging device is provided with a timing / control IC and a video signal processing IC in addition to the CCD imaging device as the main body. In the figure, VF, RD, VG, IN, and ID of the timing / control IC are signal terminals added to extract identification information from the CCD solid-state imaging device. When the identification information request signal RD is activated, VF changes to a high voltage. VF is the power supply voltage of the unit identification information source shown in FIGS. 2, 8, and 9, for example.

  When the identification information is not requested, the power supply voltage VF is cut off or set to a low voltage to avoid electrical stress on the NMOS transistor in the unit identification information source and to prevent a current from flowing constantly. . Subsequently, VG, V.phi.1, V.phi.2, V.phi.3, V.phi.4, RG, etc. operate as shown in FIG. 4, and output an analog quantity serving as a basis of identification information from the video signal output Vout. The timing / control IC receives the analog quantity from the video signal output Vout and converts the video signal into identification information in the IC according to a signal processing method as shown in FIG. The obtained identification information is output as a digital signal from the terminal ID. The identification information conversion may be performed by a video signal processing IC.

  By applying identification information to each solid-state imaging device, various applications and effects can be expected. For example, in a manufacturing factory, it can be used to improve product yield and quality. Furthermore, it is possible to trace the history of individual shipments, and it is possible to quickly respond when a product accident occurs. In addition, the solid-state imaging device may need to be corrected or may include defective pixels within an allowable range because the color adjustment slightly changes depending on the lot or wafer at the time of manufacture. In such a case, an appropriate color correction method and defect interpolation processing can be performed based on the history information obtained from the identification information.

  FIG. 24 shows an explanatory diagram of an embodiment of application of the identification information related to the CCD solid-state imaging device and the CMOS solid-state imaging device according to the present invention to the digital signature technology. The signature information with the identification information 2102 as the prime of the normally captured image information 2101 is synthesized 2103 using, for example, a watermark technique. As a result, it becomes possible to know which imaging element the image itself was taken and to detect fraud such as tampering. In recent years, so-called copyright crimes such as illegal duplication, imitation, and falsification of video information have become a major social problem. In order to prevent such illegal acts, various encryption and security technologies have been put into practical use. Among them, there is a so-called digital signature technique, which is used for signature information based on the identification information 2102.

  FIG. 25 is a block diagram showing still another embodiment in which identification information unique to a CMOS type solid-state imaging device is given. In FIG. 14 and FIG. 19, a dedicated identification information source 1204 is added as the basis of unique identification information. However, in this embodiment, a normal imaging circuit 1205 is used as it is. That is, in FIG. 25, the imaging circuit 1205 used as the identification information source is on the column signal line CD0, and the variation of the threshold voltage Vth of the NMOS amplification transistor MA in the circuit is the basis of the identification information.

  FIG. 26 shows an operation waveform diagram when the identification information is extracted from the identification information source in the configuration of FIG. When the control signal AS is activated, a transition is made to an operation state in which identification information is extracted from the imaging circuit. That is, all the reset signals RR0 to RRi-1 of the row scanning line circuit 2201 are at a high potential, and the cathode end of the photodiode of the imaging circuit 1205, that is, the potential of the gate Nk of the amplification NMOS transistor MA is set to the same potential as the power supply Vdd. Fix it. Subsequently, the row selection signal SR is sequentially changed to a higher potential to turn on the selection switch NMOS transistor MS. As a result, a voltage (Vdd−Vth) that is lower than the potential of the power source Vdd by the threshold voltage Vth of the amplification NMOS transistor MA of the imaging circuit 1205 that is the identification information source is applied to CD0 at the input terminal of the serial identification information generation circuit 2202. Occurs.

  FIG. 27 shows a circuit diagram of an embodiment of the serial identification information generation circuit 2202. This circuit is substantially the same as the column type identification information generation circuit 1601 shown in FIG. 20, but does not include the constant current source Io. The serial identification information generation circuit 2202 extracts identification information from the CD0 and outputs it from the CPT. Although not shown in particular, the serial identification information generation circuit 2202 operates only when the control signal AS is activated.

  FIG. 28 is a block diagram showing still another embodiment in which identification information unique to a CMOS type solid-state imaging device is given. As described above, the CMOS solid-state imaging device has a fixed pattern noise in principle, and this noise is due to the influence of the variation of the threshold voltage of the amplification NMOS transistor in the imaging circuit. To remove the influence of the variation. The CMOS type solid-state imaging device is equipped with various technique removal mechanisms represented by a CDS circuit. On the other hand, if the removal mechanism is invalidated, the variation in the threshold voltage of the amplification NMOS transistor can be extracted from the output DB and used.

  FIG. 29 shows a circuit diagram of an embodiment of the column selection circuit 2502 of FIG. In the figure, in addition to the normal column signal path CB passing through the CDS circuit, a path DB for bypassing the CDS circuit 2703 and directly extracting the voltage of the column signal line is added. By setting the bypass signal AS to a high voltage, the column signals CD0 to CDn-1 selected by the column selection signals CS0 to CSn-1 are output from the common signal line DB. The detour path does not need to be provided for all of the column signals CD0 to CDn-1, but only the number necessary for the identification capability.

  FIG. 30 shows an operation waveform diagram when the identification information is extracted from the identification information source in the configuration of FIG. When the control signal AS is activated, a transition is made to an operation state in which identification information is extracted from the imaging circuit. That is, all the reset signals RR0 to RRi-1 of the row scanning line circuit 2501 become high potential, and the cathode end of the photodiode of the imaging circuit 1205, that is, the potential of the amplification NMOS transistor MA gate Nk is fixed to the same potential as the power supply Vdd. To do. Further, in the column selection circuit 2502, the NMOS transistor 2701 is turned on. Subsequently, the row selection signals SR0 to SRi-1 are sequentially changed to a higher potential to turn on the selection switch NMOS transistor MS. As a result, a voltage that is lower than the potential of the power supply Vdd by the threshold voltage Vth of the amplification NMOS transistor MA of the imaging circuit 1205 that is the identification information source is applied to the input terminals CD0 to CDn-1 of the serial identification information generation circuit 2502. appear. Finally, the signals of the column signal lines CD0 to CDn-1 selected by the column selection signals CS0 to CSn-1 bypass the CDS circuit 2703 and appear on the common signal line DB.

  FIG. 31 shows a block diagram of an embodiment of a method for extracting identification information corresponding to the embodiment shown in FIG. The analog signal output of the CMOS type solid-state imaging device 2801 shown in FIG. 28 is digitized by an analog-digital conversion circuit 2802, and the image analog signal CB and the identification information analog signal DB are output from FCB and FDB, respectively. The CB and DB may be shared by the same signal line. Similarly, the image digital signal FCB and the identification information digital signal FDB may be shared by the same signal line. The image digital signal FCB is processed into image information by the image processing circuit 2803. Identification information is extracted from the identification information digital signal FDB by the control circuit 2804. A method for extracting the identification information from the identification information digital signal FDB reflecting the variation in the threshold voltage of the amplification NMOS transistor is shown in FIG. 5, for example. Each of the above 2802, 2803 and 2804 may be independently a semiconductor device, but may be a combination of functions.

  FIG. 32 shows a block diagram of an embodiment of the present invention in a so-called system on chip. This is a circuit provided with, for example, an image compression function and an identification / authentication function for advanced information processing after the video processing circuit 2903. Since identification information can be easily given to such a large-scale system-on-chip, it contributes to improvement in yield and reliability of the device.

  FIG. 33 shows a schematic configuration diagram of an embodiment of a solid-state imaging device using the identification information generating circuit according to the present invention. The original purpose of giving identification information to a solid-state image sensor is to give a unique number to each solid-state image sensor. As the most common method of numbering, there is a method using a laser fuse, a flash (FLASH) memory, or the like, but a special process or a program step is required as described above.

  In this embodiment, an identification information source generated by the identification information source of the present application in a wafer state is read by a tester and registered in association with various data at a workstation. After each solid-state image sensor becomes a product and is mounted on an electronic device such as a mobile phone or a digital camera, identification information is read from the solid-state image sensor. At that time, even if the identification information read out is the same solid-state imaging device, the operating environment and conditions may be different from those at the time of registration, and there is no guarantee that they will completely match. However, it can be estimated from the degree of discrepancy of the identification information that it is the same or not the same. Specifically, the degree of discrepancy can be quantified by the “Hamming distance” between the identification information read out at the time of registration and later.

  FIG. 34 and FIG. 35 each show a configuration diagram of an embodiment of a collation algorithm in the solid-state imaging device identification system according to the present invention. FIG. 34 shows a registration method.

(1) The size comparison result information of the difference between those sequentially output based on the analog value from the identification information source is read to generate, for example, 256 bits of identification information.
(2) Register it in the identification information management ledger and provide a management number to associate it with a database that stores information such as measurement data.
(3) Increase the number of registrations by one. Here, it is assumed that the newly registered identification information does not always overlap with the registered information, but the procedure for confirming the overlap with the registered information at the time of new registration and issuing some warning It is also effective to add

FIG. 35 shows a collation method. This system is characterized by allowing variation in identification information due to differences in environment and conditions during registration and verification.
(1) Read 256-bit identification information from the identification information generation circuit in the same manner as described above. This is called identification information.
(2) Retrieve registration identification information sequentially from the management ledger.
(3) Find the Hamming distance between the registered identification information and the identified information.
(4) A candidate having a small Hamming distance between the registered identification information and the identified information is used as a match candidate. By repeating the above (2) to (4), the smallest difference among all the registered identification information finally becomes the same most likely candidate.

  FIG. 36 shows a simplified diagram of an embodiment of a trace management system for a solid-state imaging device using the identification information generating circuit according to the present invention. The system intends to realize by associating individual solid-state image pickup devices arranged on a wafer with the same chip in a packaged state by adding a minimum amount of resources. In other words, it is possible to consistently manage the history from the manufacture of the solid-state imaging device to the final use stage. For example, when a final product such as a camera is assembled, a defective pixel address or color correction information may be programmed in 2803 of FIG. 31 based on the identification information.

  In this embodiment, a general semiconductor manufacturing process, that is, a pre-process, several electrical tests (probe test) in a wafer state, and a sorting test in a post-process are shown. (1) In the previous process, various device data, process conditions, process management information and the like in the manufacturing process are managed by the previous process data collection / analysis system. (2) In the probe test, the test results in the wafer state are accumulated in the probe test data collection system, and information is exchanged with the previous process data collection / analysis system. For example, the previous process is compared with the history to improve the yield. ing. Depending on the form of the semiconductor manufacturing factory, the pre-process data collection / analysis system and the probe test data collection system are integrated. (3) The screening test in the post-process is the same as the probe test.

  In a production method that spans a semiconductor manufacturing factory or a plurality of companies that have already introduced such a general production management system, a new semiconductor product trace management system that uses the identification information generation circuit according to the present invention is introduced. An important issue is how to achieve it quickly by adding a minimum amount of resources. The problems to be solved by the production history system illustrated in the figure and the means for solving them will become apparent from the following description.

  Needless to say, the process from the start to the end of semiconductor manufacturing proceeds in one direction. Therefore, on the premise of production management, data is sequentially collected in a management system in the order of processes. The trace history management system collects probe test identification information from the probe test data collection system. The probe test identification information includes at least the identification information according to the present invention, a product name for distinguishing products, a manufacturing lot number, a wafer number, position information on the wafer, and the like. When collecting the probe test identification information, for example, the validity of information such as chip duplication or abnormality of identification information generated from the identification information generation circuit according to the present invention is checked.

  Next, the production history system collects screening test identification information from the screening test data collection system. The screening test identification information includes at least identification information obtained from the identification information generation circuit according to the present invention. At the time of collecting the screening test identification information, for example, the validity of information such as chip duplication or abnormality of identification information generated from the identification information generation circuit according to the present invention is checked.

  When the above-mentioned probe test identification information and sorting test identification information can be collected, the production history system associates the individual chips arranged on the wafer with the same chip in the packaged state. Is possible. The association can be performed by the identification information obtained from the identification information generating circuit according to the present invention, which is included in each of the probe test identification information and the screening test identification information.

  The basic concept of the identification information generation circuit using the variation in the voltage between the gate and the source of the plurality of MOSFETs formed in the same form in the same manufacturing process has already been proposed by the inventor of the present application. More detailed configurations for the CMOS circuit are described in Japanese Patent Application Laid-Open Nos. 2002-143582, 2002-537646, 2003-332552, and 2005-005432, and the collation algorithm and the like in the identification system are described. Are described in detail in these publications.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the solid-state imaging device can be similarly applied to a line sensor in addition to the area sensor as in the above embodiment. The present invention can be widely used in an identification information source for providing unique identification information to a solid-state imaging device and an identification information providing method using the identification information source.

It is a schematic block diagram which shows one Example of the solid-state image sensor which concerns on this invention. It is a circuit diagram which shows one Example of the unit identification information source 301 of FIG. It is explanatory drawing of an example of the charge transfer mechanism concerning the vertical CCD of FIG. It is explanatory drawing of another example of the charge transfer mechanism concerning the vertical CCD of FIG. It is explanatory drawing which shows one Example of the identification information provision method concerning this invention. It is a schematic block diagram which shows another Example of the solid-state image sensor which concerns on this invention. It is a schematic block diagram which shows another one Example of the solid-state image sensor which concerns on this invention. It is a circuit diagram which shows another Example of the unit identification information source based on this invention. It is a circuit diagram which shows another Example of the unit identification information source based on this invention. It is a schematic block diagram which shows one Example of the CCD solid-state image sensor using the unit identification information source which forms two voltage Va and Vb. It is a schematic block diagram which shows another Example of the CCD solid-state image sensor using the unit identification information source which forms two voltage Va and Vb. It is a schematic block diagram which shows the other Example which parallelizes the information of the said unit identification information source arrange | positioned to the perpendicular direction. It is a schematic block diagram which shows the further another Example which parallelizes the information of the said unit identification information source arrange | positioned at the orthogonal | vertical direction. It is a block diagram which shows one Example of the CMOS type solid-state image sensor concerning this invention. It is a block diagram which shows one Example of the CMOS type solid-state image sensor concerning this invention. FIG. 11 is a circuit diagram showing an embodiment of an identification information source 1204 and an identification information detection circuit 1202. It is a circuit diagram which shows one Example of the identification information source for inserting arbitrary fixed information in a part of identification information. It is a circuit diagram which shows one Example of the identification information source for inserting arbitrary fixed information in a part of identification information in the pixel of a photodiode + FD system. It is a block diagram which shows the other Example which provides identification information to a CMOS type solid-state image sensor. It is a circuit diagram which shows one Example of the identification information detection circuit 1601 suitable for a serial identification information generation system. FIG. 21 is a waveform diagram for explaining the operation of the identification information detection circuit 1601 of FIG. 20. It is a block diagram which shows one Example which extracts the identification information intrinsic | native to the image pick-up element from a frame buffer type CMOS image pick-up element. It is a schematic block diagram which shows one Example of the CCD type solid-state imaging device provided with the function to provide the specific identification information based on this invention. It is explanatory drawing which shows one Example toward the application to the digital signature technique of the identification information concerning the CCD type solid-state image sensor and CMOS type solid-state image sensor concerning this invention. It is a block diagram which shows another one Example which provides the specific identification information to a CMOS type solid-state image sensor. FIG. 26 is an operation waveform diagram when extracting identification information from the identification information source of FIG. 25. FIG. 10 is a circuit diagram showing one embodiment of a serial identification information generation circuit 2202. It is a block diagram which shows another one Example which provides the specific identification information to a CMOS type solid-state image sensor. FIG. 29 is a circuit diagram showing one embodiment of the column selection circuit 2502 of FIG. 28. FIG. 29 is an operation waveform diagram when extracting identification information from an identification information source in the configuration of FIG. 28. It is a block diagram which shows one Example of the extraction method of the identification information corresponding to the Example shown by FIG. FIG. 2 is a block diagram illustrating one embodiment of the present invention directed to a system on chip. It is a schematic block diagram which shows one Example of the solid-state image sensor using the identification information generation circuit which concerns on this invention. It is a block diagram which shows one Example of the collation algorithm in the identification system of the solid-state image sensor concerning this invention. It is a block diagram which shows one Example of the collation algorithm in the identification system of the solid-state image sensor concerning this invention. 1 is a simplified diagram showing an embodiment of a trace management system for a solid-state imaging device using an identification information generating circuit according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Photodiode, 101 ... Vertical CCD, 102 ... Horizontal CCD, 103 ... Amplifier, 301 ... Identification information source, 1011 ... Dummy vertical CCD, 3011 ... Complementary unit identification information source, 1201 ... Vertical scanning circuit, 1202 ... Identification information Generating circuit, 1204... Identification information generation source, 1205... Regular image sensor, 1304... Column selection switch, 1303... Constant current source, 1302 ... noise suppression circuit, 1402 ... comparator, 1601 ... identification information detection circuit, 1701. 1903... Frame buffer, 2201... Row scanning line circuit, 2202.

Claims (12)

A plurality of photodiodes;
A signal transmission circuit that sequentially transmits a signal corresponding to a photoelectric conversion signal by the plurality of photodiodes according to a timing signal;
A first circuit that takes out a gate-source voltage of a plurality of MOSFETs formed in the same form in the same manufacturing process as a first voltage;
A solid-state image pickup device comprising: a second circuit that sequentially outputs the plurality of first voltages. In claim 1,
The second circuit includes a circuit that transmits a signal corresponding to the plurality of first voltages to the signal transmission circuit,
The solid-state imaging device, wherein the signals sequentially transmitted through the signal transmission circuit are output through an output circuit. In claim 2,
The solid-state imaging device according to claim 1, wherein the output signal of the output circuit corresponding to the first voltage is a binary signal composed of a result of comparing the magnitude levels of temporally adjacent signals. In claim 3,
The photodiodes are arranged in the vertical and horizontal directions,
The signal transmission path includes a plurality of vertical CDDs provided corresponding to the photodiodes and a horizontal CCD provided corresponding to the output side of the plurality of vertical CCDs.
A solid-state imaging device, wherein the MOSFET is an N-channel MOSFET. In claim 4,
The solid-state imaging device, wherein the first circuit and the second circuit are provided on a first stage side of the vertical CCD transfer path. In claim 4,
The solid-state imaging device, wherein the first circuit and the second circuit are provided at positions facing the vertical CCD of the horizontal CCD. In claim 4,
The solid-state imaging device, wherein the first circuit and the second circuit are provided corresponding to one vertical CCD disposed at a horizontal end of the plurality of vertical CCDs. In claim 1,
The photodiode is provided with a horizontal selection switch MOSFET and an amplification MOSFET for amplifying a photoelectric conversion signal of the photodiode to constitute a pixel cell, and the pixel cell is arranged in the horizontal and vertical directions,
The pixel cells arranged in the horizontal direction are connected to a horizontal selection line,
The pixel cells arranged in the vertical direction are connected to a column selection line,
The signal transmission path is composed of a combination of a column selection circuit that senses a signal of the column selection line and the column selection line,
The first circuit includes a dummy pixel cell connected to the horizontal selection line and corresponding to the pixel cell,
The solid-state imaging device, wherein the second circuit includes a dummy column selection line provided in the dummy pixel cell. In claim 8,
The first circuit includes two dummy pixel cells provided on one horizontal selection line,
The solid-state imaging device, wherein the second circuit includes a voltage comparison circuit provided corresponding to two dummy column selection lines. In claim 1,
The photodiode is provided with a horizontal selection switch MOSFET and an amplification MOSFET for amplifying the photoelectric conversion signal of the photodiode to constitute a pixel cell, and a plurality of the pixel cells are arranged in the horizontal and vertical directions, respectively. And
The pixel cells arranged in the horizontal direction are connected to a horizontal selection line,
The pixel cells arranged in the vertical direction are connected to a column selection line,
The signal transmission path is composed of a combination of a column selection circuit that senses a signal of the column selection line and the column selection line,
The first circuit is connected to a specific column selection line and used in combination with the pixel cell.
The solid-state imaging device, wherein the second circuit includes a column selection line provided in the pixel cell. A plurality of photodiodes;
A method for providing identification information of a solid-state imaging device including a signal transmission circuit that sequentially transmits a signal corresponding to a photoelectric conversion signal by the plurality of photodiodes according to a timing signal,
A first circuit that takes out a gate-source voltage of a plurality of MOSFETs formed in the same form in the same manufacturing process as a first voltage;
A second circuit for sequentially outputting signals corresponding to the plurality of first voltages,
An identification information providing method for a solid-state imaging device, wherein a result of comparing the levels of signals output from the second circuit is used as identification information for the solid-state imaging device. In claim 11,
The signal transmission path consists of a CCD,
The second circuit is a circuit that transmits the first voltage to the CCD.
The method for providing identification information of a solid-state imaging device, wherein the signal to be compared in level is a signal output through the CCD.

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