JP7201156B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic device.

A complementary metal oxide semiconductor (CMOS) image sensor has been put into practical use as a solid-state imaging device (image sensor) using a photoelectric conversion element that detects light and generates an electric charge.
CMOS image sensors are widely used as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones. there is

As described above, the market scale of CMOS image sensors used for optical imaging in various fields is large, and it is expected that the demand will continue to grow due to the increase in on-board applications such as in-vehicle cameras.

In recent years, IoT (Internet of Things), which connects all things around us to the Internet, has attracted a great deal of attention. Data obtained by IoT is collected by a computer on the cloud side through the Internet, and the analyzed results can be transmitted to the IoT side again as information.
For example, in-vehicle sensors for achieving fully automated driving can also be regarded as IoT, and falsification of acquired data may cause serious damage such as accidents.

In this way, it is important to improve the security of IoT sensors, which are gateways for information in the IoT age. As a requirement to improve the security of IoT sensors, it is necessary to first ensure that unauthorized sensors are not connected, and as the next step, a means to confirm that the data acquired by the sensors has not been tampered with.
Conventional encryption technology protects the digitized signal after the microcomputer chip, but does not necessarily protect the signal immediately after coming out of the sensor chip. The reason for this is that low cost is required for a single sensor as a component, and security technology, which is an extra circuit, has not spread.

On the other hand, as an LSI security technology, a technology called PUF (Physically Unclonable Function) has attracted attention in recent years. PUF is a technology that extracts variations in semiconductors as physical feature quantities and obtains device-specific outputs.
In addition, a PUF in a semiconductor device is a circuit that extracts minute deviations in performance caused by variations in threshold values of transistors that occur during manufacturing, and outputs them as unique IDs.
By using the unique ID generated by this PUF to authenticate the device, and by adding a message authentication code (MAC) to ensure the authenticity of the obtained data, falsification of information can be prevented.

Under these circumstances, the CMOS image sensor PUF (CMOS image sensor PUF ( CIS-PUF) has been proposed.

For example, Non-Patent Document 1 proposes a CMOS image sensor PUF (CIS-PUF) that generates a unique ID for a PUF from pixel variation information in a CMOS image sensor as a measure to prevent sensor device authentication and image data falsification. It is

The CIS-PUF extracts at least one of pixel variation information of a CMOS image sensor and readout unit variation information and applies it to the PUF.
Originally, most of the pixel variation is removed by a correlated double sampling (CDS) circuit that takes the difference between the reset level and the luminance level for each pixel, but the CIS-PUF operates the CDS circuit to shoot. It has a normal imaging mode (normal operation mode) and a security mode (PUF mode or response generation mode MDR) for imaging without operating the CDS circuit.

In the PUF mode (security mode), by extracting only the reset level with reduced noise, a unique pixel variation pattern for each chip that does not depend on the ambient luminance is output as a response (unique ID).

In Non-Patent Document 1, in the PUF mode, a potential obtained from a clip circuit that exists for each column is used as a reference potential, and the difference between the reset potential of each pixel and the difference is taken to extract variations for each pixel.

In such a CIS-PUF, when generating a PUF response, a multi-bit digital value related to differential data corresponding to variations in pixel transistors is output, and 1/0 is obtained based on the magnitude relationship of the threshold voltages of adjacent transistors. get a response.
If there is a large difference between the values of the pixel transistors compared in magnitude, even if environmental conditions such as noise, temperature, and voltage fluctuate, the magnitude relationship of the threshold voltage does not reverse, so it can be determined that the bit is stable. .

More specifically, the PUF response generation using the pixel variation of the CIS-PUF is the output value (LSB value) of two source follower transistors SF-Tr that are adjacent in the vertical direction (up and down), which is the reading direction of the pixel signal. are compared to generate 1/0 data.
For example, when comparing the upper and lower output values, if the upper output value is greater than the lower output value (top > bottom), "1", and if the upper output value is less than the lower output value (top < bottom) ) shall be “0”.

International Image Sensor Workshop, 2017, pp. 66-69

As described above, in order to derive a highly reliable response (device unique ID) in CIS-PUF, signal processing to remove random noise and FPN is necessary. used.

In this case, in order to minimize the cost of the overall system, no processing should be done on the controller side (system) side. If the processing is done inside the CIS, a lot of memory is required, circuit overhead is another concern, and thus the chip cost is high, so a region processing topology inside the CIS is strongly desired. will be
Ideally, for interface (I/F) data sorting, it is preferable to process pixel data in one or two line memories, or even several line memories, which are usually equipped in CIS.

INDUSTRIAL APPLICABILITY The present invention is a solid-state imaging device capable of realizing signal processing that removes random noise and FPN with a small storage unit, and thus capable of preventing an increase in device cost due to a processing circuit, and a solid-state imaging device. An object of the present invention is to provide a driving method and an electronic device.

A solid-state imaging device according to a first aspect of the present invention comprises: a pixel section in which a plurality of pixels having a photoelectric conversion function are arranged in a matrix; a reading section for reading out pixel signals from the pixel section; a signal processing circuit including a response data generation unit that generates response data in association with at least one of the pixel variation information and the readout unit variation information in a security mode different from the normal operation mode; In the security mode, the readout unit obtains a difference between a clip signal as a reference level in the readout direction and a pixel reset signal as a reset level of each pixel from a plurality of pixels in a pixel signal readout direction. The signal processing circuit sequentially acquires difference data, and includes an arithmetic unit and at least two first and second storage units, and in the security mode, the first storage unit and the second storage unit. selectively storing the first difference data of each pixel acquired by the reading unit in at least one of the second storage units, selectively storing the calculation result of the calculation unit, and performing the calculation; unit performs averaging processing between the first difference data of two pixels of the plurality of pixels in the readout direction of the pixel signal, and stores the result of the averaging processing in the first storage unit and the second storage unit; stored in at least one of

A second aspect of the present invention is a driving method for a solid-state imaging device including a pixel section in which a plurality of pixels having a photoelectric conversion function are arranged in a matrix, and a reading section for reading out pixel signals from the pixel section. In a security mode different from a normal operation mode for generating a normal image, a clip signal as a reference level in the readout direction and a pixel reset signal as a reset level of each pixel are obtained from a plurality of pixels in the readout direction of pixel signals. a readout step of sequentially acquiring first difference data obtained by taking the difference between the second and second differential data; and a signal processing step including a data generating step, wherein in the signal processing step, the data acquired by the reading step is stored in at least one of a first storage unit and a second storage unit during the security mode. selectively storing the first difference data of each pixel and selectively storing the calculation result of the calculating step, wherein the calculating step comprises the steps of: Averaging processing is performed between the first difference data of pixels, and the result of the averaging processing is stored in at least one of the first storage section and the second storage section.

An electronic device according to a third aspect of the present invention includes a solid-state imaging device and an optical system for forming an object image on the solid-state imaging device, wherein the solid-state imaging device comprises a plurality of pixels having a photoelectric conversion function. are arranged in a matrix, a reading unit for reading pixel signals from the pixel unit, and a security mode different from a normal operation mode for generating a normal image, the pixel variation information and the reading unit variation. a signal processing circuit including a response data generation unit that generates response data in association with at least one of the information; First difference data obtained by taking a difference between a clip signal as a reference level in the readout direction and a pixel reset signal as a reset level of each pixel is sequentially obtained, and the signal processing circuit includes an arithmetic unit and at least two a first storage unit and a second storage unit, and each pixel acquired by the reading unit is stored in at least one of the first storage unit and the second storage unit during the security mode. selectively storing the first difference data of the two pixels of the plurality of pixels in the reading direction of the pixel signal, and selectively storing the operation result of the operation unit. Averaging processing is performed between the difference data, and the result of the averaging processing is stored in at least one of the first storage section and the second storage section.

According to the present invention, it is possible to realize signal processing that removes random noise and FPN with a small storage unit (memory), thereby preventing an increase in device cost due to the processing circuit.

1 is a block diagram showing a configuration example of a solid-state imaging device according to an embodiment of the present invention; FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining an overview of a challenge and response authentication (Challenge & Response (CR authentication)) system; FIG. 4 is a diagram for explaining device authentication in this embodiment; FIG. 4 is a diagram for explaining data consistency authentication in this embodiment; FIG. 1 is a first diagram for explaining data encryption processing in this embodiment; FIG. 2 is a second diagram for explaining data encryption processing in this embodiment; 3 is a circuit diagram showing an example of a pixel according to this embodiment; FIG. FIG. 3 is a diagram for explaining a configuration example of a column output readout system of a pixel unit of the solid-state imaging device according to the embodiment of the present invention; FIG. 3 is a block diagram showing an overall overview of a response generation unit, which is an encryption processing system according to the embodiment; FIG. 10 is a diagram schematically showing processing for creating response data, which is the encryption processing system of FIG. 9; FIG. 10 is a diagram showing operation waveforms of main parts in a normal operation mode and a response creation mode when threshold value variation information of a source follower transistor is employed as pixel variation information; An overview of a pixel unit and a column readout circuit arranged for each column according to the present embodiment, including an information acquisition unit suitable for acquiring variation information that forms the main part of a CMOS image sensor PUF (CIS-PUF). FIG. 10 shows. FIG. 13 is a diagram showing how a PUF response is generated using the pixel variation of the CIS-PUF of FIG. 12; FIG. 3 is a diagram showing a first configuration example of a response data creation unit of a signal processing circuit that executes averaging processing and determination processing according to the present embodiment; 15 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 14; FIG. 10 is a diagram showing a second configuration example of the response data creation unit of the signal processing circuit that executes the averaging process and the determination process of the embodiment; 17 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 16; FIG. 10 is a diagram showing a third configuration example of a response data creation unit of a signal processing circuit that executes averaging processing and determination processing according to the present embodiment; 19 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 18; FIG. 11 is a diagram showing a fourth configuration example of a response data creation unit of a signal processing circuit that executes averaging processing and determination processing according to the present embodiment; 21 is a diagram showing an example of a port configuration of the dual port memory of FIG. 20 and an operation waveform at each port; FIG. 21 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 20; FIG. 11 is a diagram showing a fifth configuration example of a response data creation unit of a signal processing circuit that executes averaging processing and determination processing according to the present embodiment; 24 is a diagram showing an example of a port configuration of the two-port memory of FIG. 23 and an operation waveform at each port; FIG. 24 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 23; FIG. FIG. 11 is a diagram showing a sixth configuration example of a response data creation unit of a signal processing circuit that executes averaging processing and determination processing according to the present embodiment; FIG. 27 is a diagram showing an example of the port configuration of the FIFO in FIG. 26 and operation waveforms at each port; 27 is a timing chart for explaining averaging processing and determination processing of the circuit of FIG. 26; FIG. 14 is a diagram showing reproducibility and uniqueness as PUF performance obtained by the response generation method as shown in FIGS. 12 and 13; FIG. 4 is a diagram showing FPR and FNR determined from uniqueness and reproducibility. FIG. 4 is a diagram showing an example of Lehmer code; FIG. 4 is a diagram showing a correspondence table between binary codes and Gray codes; FIG. 4 is a diagram for explaining a processing procedure when the Lehmer-Gray method (LG method) is applied to CIS-PUF; FIG. 10 is a diagram showing the appearance rate of responses when the Lehmer-Gray method is applied to CIS-PUF. FIG. 10 is a diagram showing distributions of uniqueness and reproducibility of five prepared chips when N=2, 4, 8, 16, 32, and 64; FIG. 11 shows a table summarizing the mean and standard deviation of reproducibility and uniqueness HD. FIG. 4 is a diagram showing FNR and FPR obtained from reproducibility and uniqueness; FIG. 4 is a table showing thresholds at which FNR and FPR are 0.001 ppm or less; FIG. 4 is a table showing lengths of responses generated from N outputs; FIG. 10 is a diagram showing a table summarizing the information amount I of a 128-bit ID and the number of identifiable individuals calculated from the obtained threshold. FIG. 10 is a table showing a trial calculation of the number of CR authentications that can be performed for N=2 to 64 when a 128-bit response is consumed for one authentication; It is a figure showing an example of composition of electronic equipment with which a solid imaging device concerning an embodiment of the present invention is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device according to an embodiment of the present invention.
In this embodiment, the solid-state imaging device 10 is composed of, for example, a CMOS image sensor.

As shown in FIG. 1, the solid-state imaging device 10 includes a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, a timing control circuit 60, and a signal processing circuit 70 as main components.
Among these components, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal reading section 90, for example.

The solid-state imaging device 10 according to the present embodiment is a CMOS image sensor PUF (CIS-PUF) that generates a unique ID of the PUF from pixel variations in the CMOS image sensor as a countermeasure for device authentication of the sensor and prevention of falsification of image data. formed.
When the solid-state imaging device 10 generates a PUF response (hereinafter sometimes referred to as a PUF response) in the CIS-PUF, the solid-state imaging device 10 associates with at least one of pixel variation information and reading unit variation information a unique It is configured to be able to generate response data containing the key.

The CIS-PUF according to the present embodiment extracts at least one of pixel variation information and reading unit variation information of a CMOS image sensor and applies it to the PUF.
Originally, most of the pixel variations are removed by the CDS circuit, but the CIS-PUF according to this embodiment can be used in a normal imaging mode (normal operation mode) in which the CDS circuit is operated to perform imaging, and in a normal imaging mode in which the CDS circuit is not operated. It has a security mode for shooting (PUF mode or response creation mode MDR).

As will be described in detail later, the solid-state imaging device 10 according to the present embodiment generates the variation information of the pixels and the readout unit 90, which is the PUF response, as an example, when generating the variation information of the pixel transistor. A multi-bit digital value (LSB value) relating to the difference data is output, and 1/0 response data is acquired from the magnitude relationship between the threshold voltages of the adjacent transistors.
In the solid-state imaging device 10, when the digital value difference between the pixel transistors compared in magnitude is large, even if environmental conditions such as noise, temperature, and voltage fluctuate, the magnitude relationship with the threshold voltage VTH is not reversed. It can be determined that the bits are stable.

In the solid-state imaging device 10 of the present embodiment, as will be described in detail later, in the security mode, the reading unit 90 reads a plurality of pixels (this embodiment In the embodiment, the first difference data SDF1 obtained by taking the difference between the clip signal as the reference level (reference potential) in the readout direction and the pixel reset signal as the reset level of each pixel is sequentially obtained from four pixel units as an example. get.
The signal processing circuit 70 basically includes an arithmetic unit and at least two storage units, a first memory and a second memory. It selectively stores the first difference data SDF1 of each pixel acquired by the unit 90, and selectively stores the computation result of the computation unit.

The calculation unit averages first difference data of two pixels of a plurality of pixels in the readout direction of the pixel signal, and stores the averaged result data in at least one of the first memory and the second memory. Remember.
The calculation unit acquires second difference data SDF2 obtained by taking a difference between two pixels for the data subjected to the averaging process, and stores the acquired second difference data SDF2 in the first memory and the second memory. Store at least one.
The signal processing circuit 70 performs binarization by determining the size between two adjacent pixels based on the obtained second difference data SDF2.

In the solid-state imaging device 10 according to the present embodiment, the signal processing circuit 70 includes a response data generation unit 80 (800), and generates response data in a security mode different from the normal operation mode MDU for generating normal images. Information security signal processing including generation processing of is configured to be possible.
The signal processing circuit 70 of this embodiment has a video interface (I/F) 710 capable of communicating with a microcomputer (hereinafter referred to as a microcomputer) as a control device regarding authentication processing and the like.
The signal processing circuit 70 performs information security signal processing so as to prevent a reduction in the image data frame rate due to the processing time of signal processing for information security and to prevent an increase in device cost due to the processing circuit. , signal processing during a blanking period of image signal processing or signal processing for each row (line).

In this embodiment, the information security signal processing performed by the signal processing circuit 70 is at least one of response data generation processing, device authentication, data consistency authentication, and data encryption.
The information security signal processing includes authentication processing in which a pixel address is used as a challenge and response data generated by a predetermined procedure is used as a response.

In addition, the signal processing circuit 70 of the present embodiment can increase the number of challenge and response authentication (CR authentication) while securing authentication accuracy without requiring complicated effort. It includes a bit-multiplexing unit 720 having a function of bit-multiplexing the variation information, which is the PUF response read for response data generation.
In the signal processing circuit 70, the bit-multiplexing unit 720 extracts a plurality of outputs of the variation information as one block, encodes them with Lehmer code, and converts the Lehmer-coded information into grayscale. The LG (Lehmer-Gray) method, which converts to a code (Gray code), is adopted.
The multi-bit processing by the LG method will be described in detail later.

As will be described in detail later, the authentication accuracy to be ensured when performing authentication is the probability FPR( False Positive Rate) and the probability FNR (False Negative Rate) of recognizing a genuine article as a counterfeit are obtained, and evaluation (determination, selection) is possible by the probability FPR and the probability FNR.

A CIS-PUF is a PUF in which a pixel address is used as a challenge and 1/0 data generated by a predetermined procedure is used as a response.
Here, an outline of challenge and response authentication (Challenge & Response (CR authentication)) as an application of PUF that uses device-specific variations for security will be described.
After that, the processing of device authentication, data consistency authentication, and data encryption, which are one of the features of this embodiment, will be described.

(Overview of response authentication system)
FIG. 2 is a diagram for explaining an overview of a challenge and response authentication (Challenge & Response (CR authentication)) system.

The CR authentication system 100 of FIG. 2 includes a CIS-PUF chip 200 on which the solid-state imaging device 10 according to the present embodiment is mounted, and a microcomputer (hereinafter referred to as microcomputer) 300 .
The CIS-PUF chip 200 has a video interface (Video I/F) 210 as the video interface 710 in FIG. 1, and the microcomputer 300 has a control interface (Control I/F) 310.

The CR authentication system 100 using CIS-PUF has a pre-registration mode and an authentication mode, and information of the CIS-PUF chip 200 must be registered in the microcomputer 300 before authentication.
In the pre-registration mode, IDs of all pixels are generated from the PUF mode side and stored in a safe area of the microcomputer 300 .

In the CR authentication system 100 using this CIS-PUF, in the authentication mode, the authentication-side microcomputer 300 first transmits a PUF mode command to the CIS-PUF chip 200 (step ST1).
In response to this, the CIS-PUF chip 200 performs imaging in PUF mode to obtain a PUF mode image.
Next, the microcomputer 300 uses a random number generator (RNG) 301 to determine which pixels are to be used to generate an ID, and transmits the address designation to the CIS-PUF chip 200 as challenge information (step ST2). .
The CIS-PUF chip 200 crops the PUF mode image according to the received addressing and generates 1/0 data. The CIS-PUF chip 200 transmits this ID to the microcomputer 300 as a response to the challenge (step ST3).
The microcomputer 300 cuts out the ID of the designated address from the 1/0 data registered in advance and compares it with the ID received from the CIS-PUF chip 200 . If the IDs match, the authentication is successful (step ST4).

Based on the communication processing of this CR authentication system 100, device authentication, data integrity authentication, and Each processing of data encryption will be described.

(device authentication)
FIGS. 3A and 3B are diagrams for explaining device authentication in this embodiment.

In device authentication, the signal processing circuit 70, which is a part of the CIS-PUF chip 200, receives a pixel address XY challenge from the microcomputer 300 as a control device during pixel readout, and registers in the CIS-PUF chip 200. writes the received address to
Next, in security mode (PUF mode), pixels are accessed according to the Y address received during the vertical blanking interval PVB.
Pixel signals are processed during the vertical blanking interval PVB to obtain a device ID with improved reproducibility and uniqueness.
Then, the device ID obtained during the vertical blanking period PVB or during the next pixel readout period is transmitted to the microcomputer 300 as a response to the challenge.
Microcomputer 300 checks the device ID for authentication.
Authentication is performed for a period of either one frame, one second, one minute, one hour, or one day, for example for streaming video data.

(data integrity authentication)
FIGS. 4A and 4B are diagrams for explaining data consistency authentication in this embodiment.

In data integrity authentication, the signal processing circuit 70, which is part of the CIS-PUF chip 200, sets the pixel address to obtain the device ID.
A device ID is obtained from the variation information of the pixels addressed during the vertical blanking period PVB.
Then, it reads the row (line) pixel signal and generates a data tag using the device ID as a unique key and the line pixel signal as a message by a message authentication code (MAC) function.
Next, during the horizontal blanking period PHB via the video I/F 210 or the control I/F 310 or during the vertical blanking period PVB via the video I/F 210 or the control I/F 310, the pixel address, the line pixel signal, and The data tag is transferred to the microcomputer 300, which is a control device that performs consistency authentication.
The microcomputer 300 on the receiver side executes MAC processing using the same key generated together with the pixel address and pixel data for consistency verification.
Note that the pixel address can be arbitrarily changed at any time.

(data encryption)
FIGS. 5A and 5B are first diagrams for explaining data encryption processing in this embodiment.
FIGS. 6A to 6C are second diagrams for explaining the data encryption processing in this embodiment.

In the data encryption process, the signal processing circuit 70, which is part of the CIS-PUF chip 200, sets the pixel address for obtaining the device ID.
A device ID is obtained from the variation information of the pixels addressed during the vertical blanking interval PVB.
The pixel signals of the first row (Line 1) are read out from the pixel section 20 and stored in the internal line memory.
While the pixel signals of the second row (Line 2) are being read out from the pixel unit 20, the pixel signals of the first row (Line 1) are encrypted with the device ID key.
While reading the pixel signals of the third row (Line 3) from the pixel unit 20, the encrypted pixel signals and pixel addresses of the first row (Line 1) are decrypted by the control device side ISP (Image Signal Processor). is transferred to the microcomputer 300 of
The microcomputer 300 decrypts the encrypted pixel values of the first row (Line1) with the same key.

Note that encryption can be applied to only a portion of the line pixels and need not be applied to the entire pixel array of the pixel portion.
Background encryption processing takes more time, but need not occur during the reading of a row.
A CMOS image sensor (CIS) is usually equipped with several lines of memory, and by reusing this line memory, line-by-line encryption also realizes negligible circuit cost.

As described above, in the present embodiment, information security signal processing such as device authentication, data integrity authentication, and data encryption is performed as signal processing during the blanking period of image signal processing or as signal processing for each row (line). Since it is executed, it is possible to prevent the image data frame rate from being lowered due to the processing time of signal processing for information security, and to prevent the device cost from increasing due to the processing circuit.

The processing of the authentication system has been described above.
An outline of the configuration and function of each section of the solid-state imaging device 10, in particular, the configuration and function of the pixel section 20 will be described below.
After that, regarding the characteristic configuration and functions of the solid-state imaging device 10 of the present embodiment, a so-called encryption process of generating a unique key and integrating identification data including the unique key and image data to create response data. , a response data creation process that makes it possible to realize signal processing that removes random noise and FPN with a small amount of memory, a function to convert the variation information, which is the PUF response read for response data generation, into multiple bits, The explanation will focus on the evaluation of certification.

(Basic Configuration of Pixel and Pixel Unit 20)
In the pixel section 20, a plurality of pixels including photodiodes (photoelectric conversion elements) and in-pixel amplifiers are arranged in a two-dimensional matrix of n rows×m columns.

FIG. 7 is a circuit diagram showing an example of a pixel according to this embodiment.

This pixel PXL has a photodiode (PD), which is a photoelectric conversion element, for example.
For this photodiode PD, one transfer transistor TG-Tr, one reset transistor RST-Tr, one source follower transistor SF-Tr, and one selection transistor SEL-Tr are provided.

The photodiode PD generates and accumulates signal charges (here, electrons) corresponding to the amount of incident light.
In the following description, the signal charges are electrons and each transistor is an n-type transistor. However, the signal charges may be holes or each transistor may be a p-type transistor.
Further, as will be exemplified later, the present embodiment is applicable when the reset transistor RST-Tr, the source follower transistor SF-Tr, and the select transistor SEL-Tr are shared among a plurality of photodiodes. is also effective, and it is also effective when employing a 3-transistor (3Tr) pixel that does not have a selection transistor.

The transfer transistor TG-Tr is connected between a photodiode PD and a floating diffusion FD (Floating Diffusion) and controlled by a control signal TG.
The transfer transistor TG-Tr is selected during a high level (H) period of the control signal TG and becomes conductive, and transfers electrons photoelectrically converted by the photodiode PD to the floating diffusion FD.

The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion FD and controlled by the control signal RST.
The reset transistor RST-Tr may be connected between the power supply line VDD and the floating diffusion FD and controlled by the control signal RST.
The reset transistor RST-Tr is selected and rendered conductive while the control signal RST is at H level, and resets the floating diffusion FD to the potential of the power supply line VRst (or VDD).

The source follower transistor SF-Tr and the select transistor SEL-Tr are connected in series between the power supply line VDD and the vertical signal line LSGN.
A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the select transistor SEL-Tr is controlled through a control signal SEL.
The selection transistor SEL-Tr is selected and becomes conductive during the period in which the control signal SEL is H. As a result, the source follower transistor SF-Tr outputs the column output analog signal VSL corresponding to the potential of the floating diffusion FD to the vertical signal line LSGN.
Since the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the select transistor SEL-Tr are connected in row units, these operations are performed simultaneously and in parallel for each pixel in one row. will be

Since pixels PXL are arranged in n rows×m columns in the pixel section 20, there are n control lines for each of the control signals SEL, RST, and TG, and m vertical signal lines LSGN.
In FIG. 1, control lines for the respective control signals SEL, RST, and TG are represented as one row scanning control line.

The vertical scanning circuit 30 drives the pixels in the shutter row and the readout row through row scanning control lines under the control of the timing control circuit 60 .
In addition, the vertical scanning circuit 30 outputs row selection signals of row addresses of read rows for reading out signals and shutter rows for resetting charges accumulated in the photodiodes PD according to the address signals.

The readout circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and is configured to enable column parallel processing with the plurality of column signal processing circuits. may be

The readout circuit 40 can be configured to include a CDS circuit, an ADC (analog-to-digital converter; AD converter), an amplifier (AMP), a sample-and-hold (S/H) circuit, and the like.

In this manner, the readout circuit 40 may include an ADC 41 that converts each column output analog signal VSL of the pixel section 20 into a digital signal, as shown in FIG. 8A, for example.
Alternatively, the readout circuit 40 may include an amplifier (AMP) 42 for amplifying each column output analog signal VSL of the pixel section 20, as shown in FIG. 8B, for example.
Further, the readout circuit 40 may include a sample-and-hold (S/H) circuit 43 for sampling and holding each column output analog signal VSL of the pixel section 20, as shown in FIG. 8C, for example.
Further, the readout circuit 40 may be provided with an SRAM as a column memory for storing pixel signals output from each column of the pixel section 20 and subjected to predetermined processing.

The horizontal scanning circuit 50 scans signals processed by a plurality of column signal processing circuits such as ADCs of the readout circuit 40 , horizontally transfers the signals, and outputs the signals to the signal processing circuit 70 .

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

In the normal readout mode MDU, the signal processing circuit 70 generates two-dimensional image data by performing predetermined signal processing on readout signals read by the readout circuit 40 and subjected to predetermined processing.

As described above, in a solid-state imaging device (CMOS image sensor), electrons generated by photoelectric conversion with a small amount of light are converted into a voltage with a minute capacitance, and a source follower transistor SF-Tr with a minute area is used to output the voltage. are doing. Therefore, it is necessary to remove minute noise such as noise generated when resetting the capacitor and variations in transistor elements. ing.
Thus, in the CMOS image sensor, by outputting the difference between the reset level and the luminance level for each pixel, it is possible to eliminate the reset noise and threshold variation and detect a signal of several electrons. The operation of detecting this difference is called CDS (correlated double sampling) as described above, and is a widely used technique. One frame of normal two-dimensional image data is output.

The solid-state imaging device 10 of the present embodiment is configured such that the operation for generating the normal two-dimensional image data can be performed in the normal operation mode MDU.

However, in the signal processing circuit 70 of the present embodiment, in order to prevent unauthorized use, falsification, or forgery of an image, the inherent variation information of the solid-state imaging device 10 (variation of pixels, readout circuits, etc.) information), generates identification data by combining the unique key and acquired data obtained from the solid-state imaging device 10, integrates the identification data with image data, outputs response data RPD, and outputs the response data RPD. It is configured so that identification data cannot be created correctly if the information is not recognized.

The solid-state imaging device 10 of the present embodiment is configured to be operable in the response generation mode MDR (PUF mode, security mode) for the operation related to generation of this unique key.

In the response generation mode MDR of the present embodiment, a pixel variation pattern (variation information) unique to each chip, which does not depend on the ambient luminance, is output as a unique ID.
In this embodiment, a clip circuit for limiting the pixel output voltage amplitude and reading the clip signal is arranged at the end of the pixel array. The difference between the clip signal as the reference level (reference potential) in the reading direction and the pixel reset signal as the reset level of each pixel is obtained from a plurality of pixels (in this embodiment, a unit of four pixels as an example) in the wiring direction). The first differential data SDF1 are obtained sequentially.
Thus, in the response creation mode MDR of this embodiment, only the variation pattern for each pixel is output. Since the luminance level is not output, it is possible to output a pattern image that does not depend on the exposure conditions of the image sensor. In addition, although the output of each pixel contains FPN and thermal noise that fluctuates randomly for each frame, the FPN in the response creation mode MDR is ten times larger than the thermal noise, so a stable fixed variation pattern can be used as a response. It can be output as data RPD.

In the response generation mode MDR of the present embodiment, upon generation of the unique key, response data including the unique key is generated in association with at least one of the pixel variation information and the reading unit variation information.

The outline of the configuration and function of each section of the solid-state imaging device 10, particularly the basic configuration and function of the pixel section 20 have been described above.
Hereinafter, the characteristic configuration and functions of the solid-state imaging device 10 of the present embodiment will be described in a so-called encryption process of generating a unique key and integrating identification data including the unique key and image data to create response data. , a response data creation process that makes it possible to realize signal processing that removes random noise and FPN with a small amount of memory, a function to convert the variation information, which is the PUF response read for response data generation, into multiple bits, The explanation focuses on the evaluation of certification.

FIG. 9 is a block diagram showing an overall overview of response data creation, which is an encryption processing system according to this embodiment.
FIG. 10 is a diagram schematically showing processing for creating response data, which is the encryption processing system of FIG.

The response data creation unit 80, which is the encryption processing system in FIG. have as
Although the information acquisition unit 81 and the key generation unit 82 are configured as separate functional blocks in the example of FIG. 9, it is also possible to configure the information acquisition unit 81 and the key generation unit 82 as one functional block. .

The information acquisition unit 81 acquires at least one of the variation information PFLC of the pixel PXL and the variation information CFLC of the circuits constituting the readout circuit 40 , and supplies the acquired variation information to the key generation unit 82 .

Here, as an example, the outline of the variation information PFLC of the pixel PXL will be described.

(Threshold of source follower transistor SF)
The information acquisition unit 81 can employ variation information of the threshold value VTH of the source follower transistor SF as the pixel variation information.

FIGS. 11A to 11E are diagrams showing operation waveforms and the like of main parts in the normal operation mode and the response creation mode when the variation information of the threshold value VTH of the source follower transistor SF is adopted as the pixel variation information. is.
11(A) is a circuit diagram of the readout system of the pixel PXL, FIG. 11(B) shows operation waveforms in the normal operation mode MDU, FIG. 11(C) shows operation waveforms in the response creation mode MDR, and FIG. D) shows a key pattern image obtained by binarizing the variation information, and FIG. 11E shows the relationship between the output signal, the number of pixels, and the threshold value VTH.
In the readout system of the pixel PXL in FIG. 11A, the CDS circuit 44 is connected to the vertical signal line LSGN via one terminal of the switch SW0. The other terminal of the switch SW0 is connected to the supply line of the reference voltage Vref.

In the normal operation mode MDU, as shown in FIG. 11B, the difference signal is used as the output signal of the pixel, thereby eliminating variation in the threshold value of the source follower transistor SF included in each pixel PXL.

In the response creation mode MDR, as shown in FIG. 11C, the latter circuit takes in the reference voltage level (Vref) at time t1, and the reset voltage level of the pixel at time t2.
By reading the difference between these signals, variations in the reset voltage of each pixel PXL can be extracted.
In this example, this variation distribution is used as a key.
Since the variation is about 100 mV, it may be amplified by an amplifier or the like.

The key generation unit 82 (FIGS. 9 and 10) generates a unique key using at least one of the pixel variation information and the readout circuit 40 variation information acquired and supplied by the information acquisition unit 81 .
The key generator 82 supplies the generated unique key KY to the identification data generator 84 .
The key generation unit 82 generates the unique key KY during a period (for example, a blanking period) other than when the effective pixels of the pixel unit 20 are read, for example.

The image data generator 83 in FIGS. 9 and 10 generates a two-dimensional image, for example, as shown in FIG. Generate data IMG.
The image data generation unit 83 supplies the generated image data IMG to the integration unit 85 .

The image data generator 83 supplies the acquired data AQD acquired from the solid-state imaging device 10 to the identification data generator 84 .
Here, the acquired data AQD is at least one of data relating to pixels, date, temperature, and GPS (Global Positioning System).

The identification data generator 84 combines the unique key KY generated by the key generator 82 and the obtained data AQD obtained by the solid-state imaging device 10 to generate identification data DSCD.
The identification data generator 84 supplies the generated identification data DSCD to the integration unit 85 .

As shown in FIG. 10, the integration unit 85 integrates the identification data DSCD generated by the identification data generation unit 84 and the image data IMG based on the readout data by the image data generation unit 83 to obtain the final response of the sensor chip. Output as data RPD.
For example, as shown in FIG. 10, the integration unit 85 integrates the integrated data such that the header HD, the identification data DSCD, and the image data IMG are arranged in this order.

As described above, the solid-state imaging device 10 according to the present embodiment uses a CMOS image sensor PUF ( CIS-PUF).
Next, when generating a PUF response (hereinafter sometimes referred to as a PUF response), response data including a unique key in association with pixel variation information (and at least one of reading unit variation information) A preferred configuration example of the CIS-PUF capable of generating is described.
After that, regarding the characteristic configuration and functions of the solid-state imaging device 10 of the present embodiment, a so-called encryption process of generating a unique key and integrating identification data including the unique key and image data to create response data. , a response data creation process that makes it possible to realize signal processing that removes random noise and FPN with a small amount of memory, a function to convert the variation information, which is the PUF response read for response data generation, into multiple bits, The explanation will focus on the evaluation of certification.

FIG. 12 shows a pixel unit according to the present embodiment, including an information acquisition unit suitable for acquiring variation information that forms the main part of a CMOS image sensor PUF (CIS-PUF), and a column readout arranged for each column. It is a figure which shows the outline|summary of a circuit.

The pixel unit 20A and the column readout circuit 40, which constitute a part of the readout unit 90 of FIG. It is configured such that it is possible to perform magnitude determination (subtraction or the like) between two pixels of and perform binarization.

The pixel section 20A of FIG. 12 includes one floating diffusion FD, one source follower transistor SF-Tr as a source follower element, one reset transistor RST-Tr as a reset element, and one selection transistor SEL as a selection element. -Tr is shared by a plurality (two in this example) of photodiodes PD1 and PD22 as photoelectric conversion elements and transfer transistors TG-Tr1 and TG-Tr2 as transfer elements.

That is, the pixel PXLA of the CMOS image sensor in FIG. 12 is driven by photodiodes PD1 and PD2, transfer transistors TG-Tr1 and TG-Tr2 driven by control signals TG1 and TG2 that are transfer clocks, and control signal RST that is a reset clock. A reset transistor RST-Tr, a source follower (SF) transistor SF-Tr, and a selection transistor SEL-Tr driven by a control signal SEL, which is a selection clock.
Here, two photodiodes PD1 and PD2 share a reset transistor RST-Tr, a source follower (SF) transistor SF-Tr, and a select transistor SEL-Tr.
This is a method that is widely used for fine pixels in recent years, and by sharing each transistor between PDs, the area of the PDs is increased relative to a predetermined elementary size, and the area capable of photoelectric conversion is widened. This increases the detection sensitivity for incident light.

In a pixel in which the selection transistor SEL-Tr is turned on, the power supply line VDD of the power supply voltage Vdd, the source follower (SF) transistor SF-Tr, and the current source Id are connected in series to form a source follower circuit.
By this source follower circuit, the voltage of the floating diffusion FD is input to the ADC 41 via the AMP 42 of the readout circuit 40 and converted into a digital value.
A clip circuit 44 is arranged at the end of the pixel array, and a clip gate CG and a diode-connected transistor M0 driven by a control signal CLIP, which is a clip clock, are arranged at the end of the pixel array to limit the pixel output voltage amplitude. Used for stable operation.

(Overview of CIS-PUF in Figure 12)
Here, an overview of the CIS-PUF in FIG. 12 will be described.
The CIS-PUF utilizes the characteristic variation of each pixel of the CMOS image sensor to generate a unique PUF response (pixel variation information) for each device. As described above, characteristic variations include fixed pattern noise (FPN) occurring at fixed positions and random noise occurring at random regardless of pixel positions.
In the normal operation mode MDU, the CMOS image sensor uses CDS (Correlated Double Sampling), which takes the difference between the reset potential (VRST) and the signal potential (VSIG) for each pixel, in order to remove these characteristic variations. It is carried out.

On the other hand, the CIS-PUF has a response creation mode (PUF mode) MDR, which is a signal readout mode that does not operate the CDS, in order to obtain variation information for the purpose of generating a PUF response. This PUF mode makes it possible to obtain an output in which pixel variation is dominant.

A solid-state imaging device (CMOS image sensor) 10A as a CIS-PUF in FIG. 12 has an array structure with 1,920×1,080 (full HD) pixels.
In this solid-state imaging device (CMOS image sensor) 10A, two pixels adjacent in the vertical direction (top and bottom in the drawing) share a source follower transistor SF-Tr, and the number of source follower transistors SF-Tr is 1,920×540. be.

In the PUF mode, the potential obtained from the clip circuit 44 that exists for each column is used as a reference potential, and the difference between the reset potential of each pixel and the difference is taken to extract variations for each pixel.
In the PUF mode, first, the clip circuits 44 arranged for each column are selected. At this time, the gate voltage of the diode-connected transistor M0 is VDD, and the voltage shifted from the power supply voltage by the offset voltage through the amplifier 42 is held in the ADC41. Next, a target pixel is selected, and the reset transistor RST-Tr and the transfer transistor TG-Tr are turned on at the same time to discharge the charge accumulated in the photodiode PD. At this time, the potential of the floating diffusion FD, which is a very small capacitance, becomes VDD, and similarly, the ADC 41 holds a voltage dropped from the power supply voltage by the offset voltage.
The ADC 41 obtains the difference between these voltages and acquires the first difference data SDF1, so that the offset variation between the source follower transistor SF-Tr of the pixel and the transistor CG of the clip circuit 44 is fixed pattern noise with high reproducibility. A unique ID is generated using the first difference data SDF1, which is, for example, 12-bit digital data.

(Generation of PUF response in CIS-PUF in FIG. 12)
Next, an outline of generating a PUF response in the CIS-PUF of FIG. 12 will be described.
FIG. 13 is a diagram showing how a PUF response is generated using the pixel variation of the CIS-PUF of FIG.

PUF response generation using CIS-PUF pixel variations compares the second difference data SDF2 related to the output values (LSB values) of two source follower transistors SF-Tr adjacent in the vertical direction (up and down). , to generate 1/0 data.
In the example of FIG. 13, the upper and lower output values are compared in size, and if the upper output value is greater than the lower output value (up>lower) "1", if the upper output value is smaller than the lower output value (Top < bottom) is set to "0".

In this example, as described above, the source follower transistor SF-Tr is shared by two upper and lower pixels. Therefore, by averaging the vertically adjacent outputs, one output value is taken for each source follower transistor SF-Tr, and a map of 540×1,920 outputs is obtained.
Furthermore, the vertically adjacent outputs are compared in size to generate 270×1,920 1/0 data.
In this way, the CIS-PUF is a PUF that uses the pixel address as a challenge and the 1/0 data generated by the above procedure as a response.

As described above, the pixel section 20A and the column readout circuit 40 of FIG. 12 are arranged to increase the reproducibility of the variation signal and to improve the uniqueness of the variation pattern. is configured to enable binarization by performing magnitude determination (subtraction, etc.).
Then, the ADC 41 in FIG. 12 obtains the difference between these voltages and obtains the first difference data SDF1, thereby reducing the offset variation between the source follower transistor SF-Tr of the pixel and the transistor CG of the clip circuit 44 with reproducibility. It is a high fixed pattern noise, and the signal processing circuit 70 uses this to generate a unique ID.
The first difference data SDF1, which is the output data of the ADC 41, is supplied to, for example, the response data creating section 800 (80) of the signal processing circuit 70, and undergoes the following processing.

In the response data generation unit 800, two vertical pixels of the key generation data KYGD are averaged in order to improve the reproducibility of the variation signal. Judgment processing for binarization is performed by judging the magnitude (subtraction, etc.) between the two values.
Note that it is also possible to perform a data compression process for compressing data after the determination process.

The above signal processing can be realized with a small circuit scale by sequentially processing, for example, every four rows without holding data of all pixel arrays.

The response data generation unit 800 of the signal processing circuit 70 of the present embodiment can realize signal processing that removes random noise and FPN with a small amount of memory (storage unit), thereby preventing an increase in device cost due to the processing circuit. In order to make this possible, the averaging process and the determination process are basically implemented by one calculation unit and at least two storage units, a first memory and a second memory.
In the security mode, the signal processing circuit 70 selectively stores the first difference data SDF1 of each pixel acquired by the reading unit 90 in at least one of the two memories, and selects the operation result of the operation unit. memorize.

The calculation unit averages first difference data of two pixels of a plurality of pixels in the readout direction of the pixel signal, and stores the averaged result data in at least one of the first memory and the second memory. Remember.
The calculation unit acquires second difference data SDF2 obtained by taking a difference between two pixels for the data subjected to the averaging process, and stores the acquired second difference data SDF2 in the first memory and the second memory. Store at least one.
The signal processing circuit 70 performs binarization by determining the size between two adjacent pixels based on the obtained second difference data SDF2.

A specific configuration of the response data generating section of the signal processing circuit 70 that executes the averaging process and the determination process will be described below. Six configuration examples from the first to the sixth will be described below with reference to the drawings.
Here, reference numeral 800 denotes a response data generating section of the signal processing circuit 70 that executes the averaging process and the determination process.
In the circuit of FIG. 12, the plurality of pixels in the pixel signal reading direction are the first pixel PXLj, the second pixel PXLj+1, the third pixel PXLj+2, and the third pixel PXLj+2 over four rows in the same column. It is a 4-pixel unit of 4 pixels PXLj+3.

(First configuration example of a signal processing circuit that executes averaging processing and determination processing)
FIG. 14 is a diagram showing a first configuration example of the response data creating section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.

The response data creation section 800 in FIG. 14 includes an arithmetic section (arithmetic unit, AU) 810 and first to sixth line memories 811 to 816 .
The first line memory 811 to the sixth line memory 816 are composed of SRAMs, for example.

The response data creation unit 800 in FIG. 14 uses six line memories 811 to 816 to store the first difference data SDF1 for four pixels, and then the calculation unit 810 performs calculations ( addition, subtraction, etc.).
The response data generation unit 800 in FIG. 14 stores the first difference data SDF1 for four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), and then stores the six lines, which is the minimum required to store the calculation data. It is configured including memory.
In this example, the first line memory (SRAM 1) 811 and the fifth line memory (SRAM 5) 815 has a master-slave relationship and is a second line memory (SRAM 2) 812 to fourth line memory (SRAM 4) Sequential writes (stores) to 814 are performed.

FIGS. 15A to 15H are timing charts for explaining averaging processing and determination processing of the circuit of FIG.
15A shows the horizontal synchronizing signal HD, FIG. 15B shows the 12-bit first difference data SDF1 from the ADC 41 of FIG. ) is the first line memory (SRAM 1) The data storage state of 811 is shown in FIG. 15D in the second line memory (SRAM 2) The data storage state of 812 is shown in FIG. 3) The data storage state of 813 is shown in FIG. 15F in the fourth line memory (SRAM 4) The data storage state of 814 is shown in FIG. 15(G) in the fifth line memory (SRAM 5) The data storage state of 815 is shown in FIG. 15(H) in the sixth line memory (SRAM 6) 816 data storage states, respectively.
Note that OS in FIG. 15 indicates an offset value. Although this offset value OS is actually taken into consideration, the following description will be made assuming that there is no offset value OS.

The response data creation unit 800 of the signal processing circuit 70 stores, for example, the first difference data Dj of the first pixel PXLj in the first line memory (SRAM) in the response creation mode MDR which is the security mode. 1) store in 811;
Next, the first difference data Dj+1 of the second pixel PXLj+1 is stored in the second line memory (SRAM). 2) 812 and the first line memory (SRAM 1) The first differential data Dj of the first pixel PXLj stored in 811 is transferred to the fifth line memory (SRAM 5) store in 815;
The first difference data Dj+2 of the third pixel PXLj+2 is stored in the third line memory (SRAM). 3) store in 813;
Next, the first difference data Dj+3 of the fourth pixel PXLj+3 is stored in the fourth line memory (SRAM). 4) store in 814;

Then, the calculation unit 810 is used as a fifth line memory (SRAM 5) The first differential data Dj of the first pixel PXLj stored in 815 and the second line memory (SRAM 2) A first averaging process between the first difference data Dj+1 of the second pixel PXLj+1 stored in 812 is performed. As a result, the first averaging result data {(Dj+Dj+1)/2)} is obtained.
Similarly, the calculation unit 810 is a third line memory (SRAM 3) The first difference data Dj+2 of the third pixel PXLj+2 stored in 813 and the fourth line memory (SRAM 4) Perform a second averaging process between the first difference data Dj+3 of the fourth pixel PXLj+3 stored in 814; As a result, the second average processing result data {(Dj+2+Dj+3)/2)} is obtained.
Next, the calculation unit 810 computes the difference between the first average processing result data {(Dj+Dj+1)/2)} and the second average processing result data {(Dj+2+Dj+3)/2)}. Second differential data SDF2 (Qj=({(Dj+Dj+1)/2)}-{(Dj+2+Dj+3)/2)}) is obtained.
The calculation unit 810 stores the obtained second difference data Qj in a sixth line memory (SRAM 6) store in 816;

Then, the signal processing circuit 70 performs binarization by judging the size between two adjacent pixels based on the obtained second difference data Qj.

As described above, according to the first configuration example, after storing the first difference data SDF1 for four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), the minimum required data for storing the operation data is stored. Since it is composed of a maximum of six line memories, it is possible to realize signal processing that removes random noise and FPN with a small amount of memory (storage unit). can be prevented.

(Second configuration example of signal processing circuit that executes averaging processing and determination processing)
FIG. 16 is a diagram showing a second configuration example of the response data creation section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.

The response data creation section 800A in FIG. 16 includes a computing section (computing unit) 810A and two first line memories 811A and a second line memory 812A.
The first line memory 811A and the second line memory 812A are composed of 13-bit SRAMs, for example.

16 uses two line memories 811A and 812A to store first difference data SDF1 related to four pixels (for example, pixels PXLj to PXLj+3 in FIG. 12), A calculation (addition/subtraction, etc.) necessary for the averaging process and the determination process is performed, and the calculation result is selectively stored in two line memories 811A and 812A as appropriate.
The response data generation unit 800A in FIG. 16 stores the first difference data SDF1 regarding four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), and the calculation unit 810A performs calculations necessary for averaging processing and determination processing. (addition/subtraction, etc.) and selectively storing the calculation result in the two line memories 811A and 812A.
In this example, the first line memory (SRAM 1) 811A and second line memory (SRAM 2) selective and sequential writes (stores) to 812A;

FIGS. 17A to 17D are timing charts for explaining averaging processing and determination processing of the circuit of FIG.
17A shows the horizontal synchronizing signal HD, FIG. 17B shows the 12-bit first difference data SDF1 from the ADC 41 of FIG. ) is the first line memory (SRAM 1) The data storage state of 811A is shown in FIG. 2) Shows the storage state of data in 812A, respectively.

The response data creation unit 800A of the signal processing circuit 70 stores, for example, the first difference data Dj of the first pixel PXLj in the first line memory (SRAM) in the response creation mode MDR which is the security mode. 1) Store in 811A.
Next, the calculation unit 810A stores the first line memory (SRAM 1) Add the first difference data Dj of the first pixel PXLj and the first difference data Dj+1 of the second pixel PXLj+1 stored in 811A, and obtain the added data (Dj+Dj+1). to the second line memory (SRAM 2) store in 812A;
Next, the calculation unit 810A stores the second line memory (SRAM 2) Addition data (Dj+Dj+1) of the first difference data Dj of the first pixel PXLj and the first difference data Dj+1 of the second pixel PXLj+1 stored in 812A to the third pixel The addition/subtraction data (Dj+Dj+1-Dj+2) obtained by subtracting the first difference data Dj+2 of PXLj+2 is stored in the first line memory (SRAM 1) Store in 811A.

Next, the calculation unit 810A stores the first line memory (SRAM 1) A second difference obtained by taking the difference between the addition/subtraction data (Dj+Dj+1-Dj+2) stored in 811A and the first difference data Dj+3 of the fourth pixel PXLj+3 and dividing the difference by 2. Obtain data SDF2(Qj=({(Dj+Dj+1)/2)}-{(Dj+2+Dj+3)/2)}).
The calculation unit 810A stores the obtained second difference data Qj in a second line memory (SRAM 2) store in 812A;

Then, the signal processing circuit 70 performs binarization by judging the size between two adjacent pixels based on the obtained second difference data Qj.

As described above, according to the second configuration example, the minimum number of pixels required to store the calculation data while storing the first differential data SDF1 for four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12) is stored. Since it is configured including two line memories, it is possible to realize signal processing that removes random noise and FPN with less memory (storage unit) than the first configuration, and by extension, the processing circuit It is possible to prevent an increase in device cost due to

(Third configuration example of signal processing circuit that executes averaging processing and determination processing)
FIG. 18 is a diagram showing a third configuration example of the response data creation section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.

The response data creation section 800B in FIG. 18 includes a computing section (computing unit) 810B, and two first line memories 811B and a second line memory 812B.
The first line memory 811B and the second line memory 812B are composed of 12-bit SRAMs, for example.

The response data creation unit 800B in FIG. 18 uses two line memories 811B and 812B to store calculation data for the first difference data SDF1 regarding four pixels (for example, pixels PXLj to PXLj+3 in FIG. 12), and calculates A section 810B performs calculations (addition/subtraction, etc.) necessary for the averaging process and the determination process, and selectively stores the calculation results in two line memories 811B and 812B as appropriate.
The response data generation unit 800B in FIG. 18 stores the calculation data for the first difference data SDF1 regarding the four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), and the calculation unit 810B performs the averaging process and the determination process. It is composed of a minimum number of two line memories for performing necessary calculations (addition and subtraction, etc.) and selectively storing the calculation results in the two line memories 811B and 812B.
In this example, the first line memory (SRAM 1) 811B and second line memory (SRAM 2) selective and sequential writes (stores) to 812B;

FIGS. 19A to 19D are timing charts for explaining averaging processing and determination processing of the circuit of FIG.
19(A) shows the horizontal synchronizing signal HD, FIG. 19(B) shows the 12-bit first difference data SDF1 by the ADC 41 of FIG. ) is the first line memory (SRAM 1) The data storage state of 811B is shown in FIG. 2) Each shows the storage state of the data of 812B.

The response data generation unit 800B of the signal processing circuit 70 divides the first differential data Dj of the first pixel PXLj by 2, for example, to generate first division data (Dj/2) in the response generation mode MDR which is the security mode. to the first line memory (SRAM 1) Store in 811B.
Next, the calculation unit 810B stores the first line memory (SRAM 1) Second division data (Dj+1/ 2) is added, and this added data {(Dj/2)+(Dj+1/2)} is used as the first difference data Dj of the first pixel PXLj and the first difference data Dj of the second pixel PXLj+1. Second line memory (SRAM 2) store in 812B;
Arithmetic unit 810B is a second line memory (SRAM 2) The first difference data Dj+2 of the third pixel PXLj+2 is divided by 2 from the first average processing result data {(Dj+Dj+1)/2} stored in 812B to obtain the third The addition/subtraction data {(Dj+Dj+1-Dj+2)/2} obtained by subtracting the division data (Dj+2/2) is stored in the first line memory (SRAM 1) Store in 811B.

Next, the calculation unit 810B stores the first line memory (SRAM 1) The difference between the addition/subtraction data {(Dj+Dj+1-Dj+2)/2} stored in 811B and the data obtained by dividing the first difference data Dj+3 of the fourth pixel PXLj+3 by 2 Second differential data SDF2 (Qj=({(Dj+Dj+1)/2)}-{(Dj+2+Dj+3)/2)}) is obtained.
The calculation unit 810B stores the obtained second difference data Qj in a second line memory (SRAM 2) store in 812B;

Then, the signal processing circuit 70 performs binarization by judging the size between two adjacent pixels based on the obtained second difference data Qj.

As described above, according to the third configuration example, while storing the calculation data for the first difference data SDF1 regarding four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), the averaging process and the determination process are performed. Since the configuration includes two line memories, which are the minimum necessary for storing the intermediate calculation data and the final calculation data, the random It is possible to implement signal processing that removes noise and FPN, thereby preventing an increase in device cost due to the processing circuit.

(Fourth configuration example of signal processing circuit that executes averaging processing and determination processing)
FIG. 20 is a diagram showing a fourth configuration example of the response data creating section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.

The difference between the response data creation unit 800C of FIG. 20 and the response data creation unit 800B of the third configuration example of FIG. 18 is as follows.
In the response data creation unit 800C of FIG. 20, the first memory (storage unit) and the second memory (storage unit) are shared, and the access system to the shared memory (storage unit) is the first access system. There are two access systems A and a second access system B, and these two access systems include a dual port memory 820 in which addresses for data input and data output are individually controlled.

21A to 21K are diagrams showing an example of the port configuration of the dual port memory of FIG. 20 and the operation waveforms at each port.
21A shows the port configuration of the dual port memory 820, FIG. 21B shows the clock signal CLK (A, B), and FIG. 12 shows first differential data SDF1 of 12 bits by the ADC 41 of FIG. 12 to be input.
FIG. 21(D) shows the first write enable signal WE of the first access system A. A, and FIG. 21(E) is the address signal ADDR of the first access system A. A, and FIG. 21(F) is the input data DATA of the first access system A A, and FIG. 21(G) is the output data Q of the first access system A A, respectively.
FIG. 21(H) shows the second write enable signal WE of the second access system B. B, and FIG. 21(I) is the address signal ADDR of the second access system B. B, and FIG. 21(J) is the input data DATA of the second access system B B, and FIG. 21(K) is the output data Q of the second access system B B, respectively.

In the dual port memory 820 shown in FIG. 21A, in the first access system A, the first write enable signal WE A input port P1A, address signal ADDR Input port P2A of A, input data DATA A input port P3A, data Q A output port P4A, and clock CLK A input port P5A.
In the dual port memory 820 shown in FIG. 21A, in the second access system B, the first write enable signal WE B input port P1B, address signal ADDR B input port P2B, input data DATA B input port P3B, data Q B output port P4B, and clock CLK B input port P5B.

The response data creation unit 800C in FIG. 20 uses one dual port memory 820 to store calculation data for the first difference data SDF1 regarding four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), and the calculation unit In 810C, calculations (addition/subtraction, etc.) necessary for averaging processing and determination processing are performed, and the calculation results are selectively stored in the shared memory area of one dual port memory 820 as appropriate.
The response data creation unit 800C in FIG. 20 stores the calculation data for the first difference data SDF1 regarding four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), and the calculation unit 810C performs the averaging process and the determination process. It is composed of one dual port memory 820 which performs necessary calculations (addition and subtraction, etc.) and selectively stores the calculation results in one dual port memory 820 as appropriate.

FIGS. 22A to 22C are timing charts for explaining averaging processing and determination processing of the circuit of FIG.
22(A) shows the horizontal synchronizing signal HD, FIG. 22(B) shows the 12-bit first difference data SDF1 by the ADC 41 of FIG. ) indicate the storage state of the dual port memory (DPSRAM) 820, respectively.

The response data creation unit 800C of the signal processing circuit 70 divides the first differential data Dj of the first pixel PXLj by 2, for example, into first division data (Dj/2) in the response creation mode MDR which is the security mode. to the first write enable signal WE A is stored in the dual port memory (DPSRA) 820 as a shared storage section by the first access system A whose level is high.
Next, the calculation unit 810C outputs the second write enable signal WE The first difference between the first division data (Dj/2) stored in the dual port memory (DPSRAM) 820 and the second pixel PXLj+1, which is read by the second access system B in which B is low level. The second divided data (Dj+1/2) obtained by dividing the data Dj+1 by 2 is added, and this added data {(Dj/2)+(Dj+1/2)} is the first pixel PXLj. and the first differential data Dj+1 of the second pixel PXLj+1, the first access system A is stored in dual port memory (DPSRAM) 820 by .
Similarly, the calculation unit 810C outputs the second write enable signal WE The third pixel PXLj+ is obtained from the first average processing result data {(Dj+Dj+1)/2} stored in the dual port memory (DPSRAM) 820 read out by the second access system B with B being low level. The addition/subtraction data {(Dj+Dj+1-Dj+2)/2} obtained by subtracting the third division data (Dj+2/2) obtained by dividing the first difference data Dj+2 of 2 by 2 is first written. Enable signal WE The data is stored in the dual port memory (DPSRAM) 820 by the first access system A whose level A is high.

Next, the calculation unit 810C outputs the second write enable signal WE The fourth pixel PXLj+ is obtained from the addition/subtraction data {(Dj+Dj+1-Dj+2)/2} stored in the dual port memory (DPSRAM) 820, which is read by the second access system B in which B is low level. The fourth division data (Dj+3/2) obtained by dividing the first difference data Dj+3 of 3 by 2 is subtracted to obtain the second difference data SDF2 (Qj=({(Dj+Dj+1)/2 )}-{(Dj+2+Dj+3)/2)}).
The calculation unit 810C converts the acquired second difference data Qj into the first write enable signal WE The data is stored in the dual port memory (DPSRAM) 820 by the first access system A whose level A is high.

Then, the signal processing circuit 70 performs binarization by judging the size between two adjacent pixels based on the obtained second difference data Qj.

As described above, according to the fourth configuration example, while storing calculation data for the first difference data SDF1 regarding four pixels (for example, pixels PXLj to PXLj+3 in FIG. 12), averaging processing and determination processing are performed. Since it is configured to include a minimum of one dual port memory required to store the intermediate calculation data and the final calculation data, the memory (storage unit ), it is possible to realize signal processing that removes random noise and FPN, thereby preventing an increase in device cost due to the processing circuit.

In addition, in the fourth configuration example, the processing method in which division is performed from the beginning adopted in the third configuration example has been described. It is also possible to adopt the method.

(Fifth configuration example of a signal processing circuit that executes averaging processing and determination processing)
FIG. 23 is a diagram showing a fifth configuration example of the response data creating section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.
FIGS. 24A to 24I are diagrams showing an example of the port configuration of the two-port memory of FIG. 23 and operation waveforms at each port.
FIGS. 25A to 25C are timing charts for explaining the averaging process and determination process of the circuit of FIG.

The difference between the response data creation unit 800D of FIG. 23 and the response data creation unit 800C of the fourth configuration example of FIG. 20 is as follows.
The response data generator 800D of FIG. 23 employs a two-port memory (TPSRAM) 830 instead of a dual-port memory.
In the 2-port memory 830, the read enable signal RE is adopted instead of the second write enable signal, the first access system A side has no data output port, and the second access system B has a data output port. No input port.
Basically, in the fifth configuration example, the same processing as in the above-described fourth configuration example is performed, so detailed description thereof will be omitted.

As described above, according to the fifth configuration example, while storing the calculation data for the first difference data SDF1 regarding four pixels (for example, the pixels PXLj to PXLj+3 in FIG. 12), the averaging process and the determination process are performed. Since it is configured to include a minimum of one 2-port memory necessary to store the intermediate calculation data and the final calculation data, the memory (storage unit ), it is possible to realize signal processing that removes random noise and FPN, thereby preventing an increase in device cost due to the processing circuit.

Also in this fifth configuration example, the processing method in which division is performed from the beginning adopted in the third configuration example has been described. It is also possible to adopt the method.

(Sixth configuration example of signal processing circuit that executes averaging processing and determination processing)
FIG. 26 is a diagram showing a sixth configuration example of the response data creation section of the signal processing circuit that executes the averaging process and the determination process of this embodiment.
27A to 27G are diagrams showing an example of the port configuration of the FIFO in FIG. 26 and the operation waveforms at each port.
FIGS. 28A to 28C are timing charts for explaining averaging processing and determination processing of the circuit of FIG.

The difference between the response data creation unit 800E in FIG. 26 and the response data creation unit 800D in the fifth configuration example in FIG. 23 is as follows.
The response data creation unit 800E of FIG. 26 employs the FIFO 840 instead of the two-port memory.
The FIFO 840 monitors a full (FULL) signal and an empty (EMPTY) signal to control writing and reading of data (DATA) by the write enable signal WE and the read enable signal RE.
Since basically the same processing as in the above-described fourth configuration example is performed also in the sixth configuration example, detailed description thereof will be omitted.

As described above, according to the sixth configuration example, while storing calculation data for the first difference data SDF1 regarding four pixels (for example, pixels PXLj to PXLj+3 in FIG. 12), averaging processing and determination processing are performed. Since it is configured including one FIFO, which is the minimum necessary for storing the intermediate calculation data and the final calculation data, it requires less memory (storage unit) than the first to third configurations. , it is possible to implement signal processing that removes random noise and FPN, thereby preventing an increase in device cost due to the processing circuit.

Also in this sixth configuration example, the processing method in which division is performed from the beginning adopted in the third configuration example has been described. It is also possible to adopt the method.

(Evaluation of uniqueness and reproducibility)
Next, the evaluation results of uniqueness and reproducibility will be described.
FIG. 29 is a diagram showing reproducibility and uniqueness as PUF performance obtained by the response generation method shown in FIGS. 12 and 13. FIG.

Uniqueness and reproducibility were evaluated as performance evaluations of CIS-PUF.
Uniqueness is an index that indicates how different the IDs of two chips are when compared. For uniqueness, create 3,840 blocks of 128-bit length IDs from images obtained by averaging 100 images on each chip, calculate the HD (Hamming stance) between IDs generated by two different chips, and find the average value. obtained by
When the ID length is L, the ideal values for the uniqueness HD distribution are L/2 for the average and √L/2 for the standard deviation.

Reproducibility is an index that indicates how stable an ID generated by a certain chip is. 3,840 blocks of 128-bit length IDs are created from images obtained by averaging 100 images in each chip. is used as a reference, the HDs of the reference ID and the ID created from each of the 100 images are calculated, and the average value is obtained.
When using the output of the PUF for authentication, it is required that the ID is stably output. Therefore, it is ideal that reproducible HD is mostly distributed near zero.

FIG. 29 shows the distribution of uniqueness and reproducibility when evaluating the five prepared chips with an ID length of 128 bits.
The unique HD has an average value μ=63.9 and a standard deviation σ=5.66, which are almost ideal values (μ=64, σ=5.66). The reproducibility HD has an average value μ=1.49 and a standard deviation σ=1.21, indicating that the ID generated by CIS-PUF has high reproducibility.

(Accreditation by FPR and FNR)
Next, the results of certification evaluation by FPR and FNR will be described.

As described above, in CR authentication using a PUF, authentication is performed by verifying whether an ID registered in advance in the microcomputer 300 matches an ID generated by the PUF.
However, as can be seen from the reproducibility evaluation results described above, the PUF does not output exactly the same ID every time, and some bit inversion occurs. Therefore, it is necessary to allow a certain amount of error in authentication.

Here, in order to evaluate how much authentication accuracy can be achieved with CR authentication using CIS-PUF, and how many bits of error should be allowed, False Positive Two indices, Rate (FPR) and False Negative Rate (FNR), were derived and evaluated.
FPR represents the probability of recognizing a fake as real, and FNR represents the probability of recognizing real as fake. Let L be the ID length used for authentication, Pu(M) be the probability that the uniqueness HD is M bits, and Ps(M) be the probability that the reproducibility HD be M bits. is set to T, FNR and FPR can be derived from equations (1) and (2).

FIG. 30 is a diagram showing FPR and FNR determined from uniqueness and reproducibility.
In FIG. 30, the horizontal axis represents the threshold value, and the vertical axis represents the FPR and FNR values at that time.

The authentication accuracy that should be secured when performing authentication was determined with reference to the authentication accuracy of biometric authentication. The biometric authentication system currently in operation has an authentication accuracy of 0.1 ppm or less. The targets of biometric authentication are humans, and the total number is about 7.5 billion. On the other hand, CR authentication using CIS-PUF targets sensors, and the total number of sensors is estimated to be approximately 1 trillion.
Therefore, in consideration of the difference in the number of objects, both the FPR and FNR are set to 0.001 ppm or less as a standard. From FIG. 30, it can be seen that the error rate can be reduced to 0.001 ppm or less by setting the number of bits for which errors are allowed between 9 and 29 bits.

(CIS-PUF response multi-bit)
Next, the multi-bit conversion of the CIS-PUF response will be described in detail.

In CR authentication using CIS-PUF, the same CR pair cannot be reused to prevent replay attacks.
In addition, since the CIS-PUF has a narrow CR space like other memory-type PUFs, the number of times CR authentication is possible is small. For example, if one authentication consumes a 128-bit response, there is a risk that IDs will be exhausted after 3,840 authentications. Depending on how it is used, for example, if authentication is performed four times a day, there is a risk that the IDs will be used up within three years.
Therefore, it is necessary to increase the number of CR pairs of CIS-PUFs, and a proposal has been made to use similar characteristic variations of CMOS image sensors as PUFs to further expand the CR pair space. However, this method requires calculations to rearrange the output pairs, and when comparing pixels at distant positions, it is affected by unique components for each column and variations that occur widely during manufacturing. There is a problem.
Therefore, in this embodiment, the Lehmer-Gray method (LG method) that realizes multi-bit is adopted in order to increase the number of CR pairs while removing these effects.

(Lehmer-Gray method (LG method))
The LG method for increasing the number of CR pairs will be described in detail below as a method for increasing the number of bits.
The LG method is a response generation method that combines Lehmer code and Gray code.
In the Lehmer code, when there are n numbers, the sequence order is n! It is a code that focuses on points that exist in the same direction. For example, when there are three values A, B, and C, there are the following 6 (=3!) arrangements, and this arrangement order is treated as a code.

(A, B, C) (A, C, B) (B, A, C)
(B, C, A) (C, A, B) (C, B, A)

As a simple Lehmer code encoding method, there is a method of encoding by counting the number of numbers to the right (or left) that are larger (or smaller) than a certain number.

FIG. 31 is a diagram showing an example of Lehmer code.
FIG. 32 is a diagram showing a correspondence table between binary codes and Gray codes.

For example, as shown in FIG. 31, encoding four numerical values (1 5 2 7) results in (3 1 1).
The Gray code is a method of representing numbers using "0" and "1" which is different from the usual binary representation. A Gray code has the property that the Hamming distance of adjacent numbers is always 1. By using this, a reduction in bit errors due to noise can be expected.

(LG method in CIS-PUF)
Here, a processing procedure when the Lehmer-Gray method (LG method) is applied to CIS-PUF will be described.
FIG. 33 is a diagram for explaining the processing procedure when the Lehmer-Gray method (LG method) is applied to the CIS-PUF.

The Lehmer-Gray method encodes permutations of N cascaded outputs to generate a response.
For example, when N=4, four outputs are taken out as one block and encoded. If the extracted output is LSB=(1649, 1753, 1757, 2060) from the top, the permutation of these four outputs in Lehmer code is L=(3,2,1).
Then, when the content of the sequence represented by the Lehmer code is represented by the Gray code, G=(10,11,1).

In this example, the four outputs produce a 5-bit response, so the entire image has a 1,296,000-bit response. Since the total response of the conventional method was 518,400 bits, it can be confirmed that the number of CR pairs has increased.
Also, in the Lehmer-Gray method, N! responses are obtained by comparing N outputs. For N=4, we can confirm that each response is generated at the same rate.

FIG. 34 is a diagram showing the appearance rate of responses when the Lehmer-Gray method is applied to CIS-PUF.
In FIG. 34, 4!=24 types of responses are plotted on the horizontal axis, and the number of occurrences of each response is plotted on the vertical axis.

When 24 types of responses appear at exactly the same rate, the expected value of the number of occurrences of each response is 10,800, which is indicated by line LV in FIG. From FIG. 19, it can be confirmed that each response appears at a similar rate when N=4.

(Uniqueness and reproducibility evaluation (LG method))
Next, using the Lehmer-Gray method, the results of evaluating the reproducibility and uniqueness when a response is generated by comparing the magnitudes of N outputs in the same manner as described above will be described.
FIG. 35 is a diagram showing distributions of uniqueness and reproducibility of five prepared chips, when N=2, 4, 8, 16, 32, and 64. FIG.
Also, FIGS. 36A and 36B are diagrams showing tables summarizing the mean and standard deviation of reproducibility and unique HD.

From FIG. 35, it can be confirmed that as N increases, the reproducibility deteriorates because the influence of bit inversion increases.
Also, as N increases, the uniqueness value decreases slightly, but this is because there are codes that are not used in the Lehmer-Gray method.
Specifically, when N=4, a 5-bit response is obtained from 4 outputs, of which the 3rd and 4th bits are either (00, 01, 11), and 10 is used do not do. Therefore, the ideal value of uniqueness for N=4 when considering unused codes is μ=61.44.

(Evaluation by FNR and FPR (LG method))
The results of evaluation by FNR and FPR will be described.
FIG. 37 is a diagram showing FNR and FPR obtained from reproducibility and uniqueness.
FIG. 38 is a table showing the threshold values at which the FNR and FPR are 0.001 ppm or less.

From FIG. 38, it can be seen that the standard authentication accuracy can be secured up to N=32, and there is no threshold that satisfies the standard for N=64. Since the number of CR pairs increases as N increases, it can be seen that the best performance is obtained when N=32 and the threshold is set to 20 to 26 bits.

(Evaluation of multi-bit authentication performance)
Next, the result of evaluating the authentication performance of multi-bit is described.
Here, evaluations other than authentication accuracy are summarized as criteria for judging whether CRR authentication using CIS-PUF has achieved practical performance by increasing the number of bits in the response.

(Number of identifiable devices)
In the assumed CIS-PUF CR authentication, the number of identifiable individuals is obtained by the following formula, where I is the amount of information that one ID has, and T is the threshold value.

Due to the characteristics of the Lehmer-Gray method, some codes are not used, so the amount of information that a 128-bit ID has is less than 128 bits. When each response is generated at the same rate, the information amount H of the response generated from N outputs is obtained by the following formula.

FIG. 39 is a table showing the length LR of responses generated from N outputs.
The amount of information I that the 128-bit ID has is obtained by the following equation using the length LR and the amount of information H of the response.

FIG. 40 is a diagram showing a table summarizing the information amount I possessed by the 128-bit ID and the number of identifiable individuals calculated from the determined threshold value.
T1 in FIG. 40 is the threshold value set so that the FNR becomes the smallest within the range that satisfies the criteria, and T2 is the threshold value set so that the FPR becomes the smallest.
As already mentioned, the total number of sensors to be identified is estimated to be about 1 trillion (10 to the 12th power) at most. It can be said that it has

(Increase amount of CR pair)
As described above, the purpose of increasing the number of bits in the response is to increase the number of CR pairs. When a 128-bit response is consumed in one authentication, the number of times CR authentication is possible for N=2 to 64 is calculated and summarized in the table of FIG.

With N=2, which corresponds to the conventional method, the number of possible CR authentications is 3,840. On the other hand, when N=32, the number of CR authentication possible increases to 30,720. Therefore, it can be seen that the number of CR authentications can be increased up to 8 times by increasing the number of bits.

As described above, we investigated a CR authentication system using CIS-PUF and evaluated multi-bit responses.
So far, CIS-PUF has been shown to have excellent characteristics in both uniqueness and reproducibility. A trial calculation was made of the total number of times that CR authentication is possible assuming an operation in which authentication accuracy is ensured.
As a result, it was found that if authentication is performed four times a day, there is a risk that the CR pairs will be used up within three years. When N=32, the number of times of CR authentication can be increased eight times while ensuring the same level of authentication accuracy as the existing system.
As a result, the solid-state imaging device according to this embodiment can be mounted on an IoT device that will be used for a long period of time.

As described above, according to the present embodiment, in the solid-state imaging device 10, in the security mode, the readout unit 90 can read out pixel signals in the direction (vertical direction, vertical signal line The difference between the clip signal as the reference level (reference potential) in the readout direction and the pixel reset signal as the reset level of each pixel is obtained from a plurality of pixels (in this embodiment, a unit of four pixels as an example) in the wiring direction). The first differential data SDF1 are obtained sequentially.
The signal processing circuit 70 basically includes an arithmetic unit and at least two storage units, a first memory and a second memory. In the security mode, at least one of the two memories has It selectively stores the first difference data SDF1 of each pixel acquired by the reading unit 90, and selectively stores the calculation result of the calculation unit.
As a result, signal processing for removing random noise and FPN can be realized with a small storage unit (memory), and an increase in device cost due to the processing circuit can be prevented.

Further, according to the present embodiment, the response data generation process, at least one of device authentication, data integrity authentication, and data encryption, is generated by a predetermined procedure using a pixel address as a challenge. Information security signal processing including authentication processing using the received response data as a response is executed as signal processing during a blanking period of image signal processing or as signal processing for each row (line).
As a result, it is possible to prevent the image data frame rate from being lowered due to the processing time of signal processing for information security, and to prevent the device cost from increasing due to the processing circuit.

Further, according to the present embodiment, the signal processing circuit 70 includes a multi-bit conversion unit 720 having a function of multi-bit conversion of the variation information, which is the PUF response read for generating the response data.
Then, as the bit-multiplexing process, the bit-multiplexing unit 720 of the signal processing circuit 70 extracts a plurality of outputs of the variation information as one block, encodes them with Lehmer code, and converts them to Lehmer-encoded information. LG (Lehmer-Gray) method is adopted, which converts to Gray code.
The authentication accuracy that should be ensured when performing authentication is the FPR (False Positive Rate), the probability of recognizing a fake as a genuine article, and the recognition of a genuine article as a fake. It is possible to obtain a probability FNR (False Negative Rate) to perform an evaluation (determination, selection) based on the probability FPR and the probability FNR.
As a result, it is possible to increase the number of times of CR authentication while securing authentication accuracy without requiring complicated effort.

As described above, according to the present embodiment, it is possible to prevent a reduction in the image data frame rate due to the processing time of signal processing for information security, to prevent an increase in device cost due to the processing circuit, and to prevent complicated processing. It is possible to increase the number of times of CR authentication while ensuring authentication accuracy without requiring labor, to generate unique response data with high confidentiality, and to reliably prevent falsification and forgery of images. becomes possible.

Note that the key generation unit 82 described above generates a unique key based on the variation information of the pixels or the readout circuit 40 . It can also be configured to obtain the key.
For example, it is possible to configure as follows.

That is, the key generation unit 82 has, for example, a first function of generating a first unique key using variation information of the ADC 41, the amplifier (AMP) 42, or the S/H circuit 43 of the readout circuit 40, and a second function for generating a second unique key using the output of the SRAM of the column memory 45, the first unique key generated by the first function and the second unique key generated by the second function; It is also possible to configure so as to generate the final unique key by calculating

This configuration is similarly applicable to pixel variation information.

Note that the integration unit 85 may be configured to include a function of hierarchically masking the image portion using the key information to be integrated.
Also, the integration unit 85 may be configured to include a function of adding an electronic watermark to an image using key information to be integrated.

In addition, in this embodiment, it is possible to employ a configuration in which each component of the solid-state imaging device 10 is mounted in the same package.

A SiP (Silicon in Package), in which a solid-state imaging device (CIS) 10 and an ISP (Image Signal Processor) are sealed in the same package, completes signal processing for generating a key and identification data inside the package, and outputs it outside the package. A configuration that can generate identification data without outputting unique key data can be adopted.

In addition, in a SoC (System on Chip) equipped with an image sensor and a signal processing circuit, the signal processing for generating the key and identification data is completed within the chip, and identification is performed without outputting the unique key data outside the chip. Any configuration that can generate data can be employed.

Further, as described above, the solid-state imaging device 10 of the present embodiment can be configured to have drive timing for accumulating leakage current for a long period of time in addition to normal readout drive timing. Alternatively, the full-scale voltage of an analog amplifier, a digital amplifier, or an ADC may be reduced, and the accumulated voltage of the leak voltage may be emphasized and output. Also, random noise components may be reduced by averaging or adding data of multiple rows or multiple frames.

As for the variation information CFLC of the configuration circuit of the readout circuit 40 , the information acquiring unit 81 can employ the variation information of the ADC as the variation information CFLC of the configuration circuit of the readout circuit 40 .
Further, the information acquiring unit 81 can employ variation information of an amplifier (AMP) as the variation information CFLC of the circuits constituting the readout circuit 40 .
Further, the information acquisition unit 81 can employ variation information of the S/H circuit as the variation information CFLC of the circuits constituting the readout circuit 40 .
Further, the information acquisition unit 81 can employ the output (variation) information of the SRAM of the column memory as the variation information CFLC of the circuits constituting the readout circuit 40 .

The solid-state imaging devices 10 and 10A described above can be applied as imaging devices to electronic equipment such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

FIG. 42 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state imaging device according to the embodiment of the invention is applied.

As shown in FIG. 42, this electronic device 400 has a CMOS image sensor (IMGSNS) 410 to which the solid-state imaging device 10, 10A according to this embodiment can be applied.
Further, the electronic device 400 has an optical system (such as a lens) 420 that guides incident light to the pixel area of the CMOS image sensor 410 (forms an object image).
Electronic device 400 has a signal processing circuit (PRC) 430 that processes the output signal of CMOS image sensor 410 .

A signal processing circuit 430 performs predetermined signal processing on the output signal of the CMOS image sensor 410 .
The image signal processed by the signal processing circuit 430 can be displayed as a moving image on a monitor such as a liquid crystal display, output to a printer, or recorded directly on a recording medium such as a memory card. is possible.

As described above, by mounting the above-described solid-state imaging device 10 or 10A as the CMOS image sensor 410, it is possible to provide a high-performance, compact, and low-cost camera system.
And it is used for applications where camera installation requirements are limited to mounting size, number of connectable cables, cable length, installation height, etc. For example, electronic devices such as surveillance cameras and medical endoscope cameras can be realized.

10, 10A Solid-state imaging device 20, 20A Pixel unit 30 Vertical scanning circuit 40 Readout circuit 44 Clip circuit 50 Horizontal scanning circuit 60 . . . timing control circuit 70 . 810, 810A to 810E... operation unit, 811, 811A, 811B, 812, 812A, 812B, 813 to 816... line memory, 820... dual port memory, 830... 2 port memory, 840. FIFO, 81... Information acquisition unit, 82, 82A... Key generation unit, 83... Image data generation unit, 84... Identification data generation unit, 85... Integration unit, 86. Memory 90 Reading unit 10 CR authentication system 200 CIS-PUF chip 300 Microcomputer (microcomputer) 310 Control I/F 400 - Electronic equipment, 410... CMOS image sensor (IMGSNS), 420... Optical system, 430... Signal processing circuit (PRC).

Claims (16)

a pixel unit in which a plurality of pixels having a photoelectric conversion function are arranged in a matrix;
a reading unit that reads out pixel signals from the pixel unit;
a signal processing circuit including a response data generation unit that generates response data in association with at least one of the pixel variation information and the readout unit variation information in a security mode different from a normal operation mode that generates a normal image; has
The reading unit
In the security mode, first difference data obtained by taking a difference between a clip signal as a reference level in the readout direction and a pixel reset signal as a reset level of each pixel is sequentially obtained from a plurality of pixels in the readout direction of the pixel signal. Acquired,
The signal processing circuit is
a computing unit;
at least two first storage units and a second storage unit;
During the security mode, at least one of the first storage unit and the second storage unit selectively stores the first difference data of each pixel acquired by the reading unit, and selectively storing the calculation result of the calculation unit;
The calculation unit is
averaging processing is performed between the first difference data of two pixels of the plurality of pixels in the reading direction of the pixel signal, and the averaging processing result data is stored in at least the first storage unit and the second storage unit; A solid-state imaging device that stores data in any one of them. The arithmetic unit of the signal processing circuit,
obtaining second difference data obtained by taking a difference between two pixels of the data subjected to the averaging process, and storing the obtained second difference data in the first storage unit and the second storage unit; 2. The solid-state imaging device according to claim 1, wherein at least one is stored. The signal processing circuit is
3. The solid-state imaging device according to claim 2, wherein the obtained second difference data is used to determine the size between two adjacent pixels and perform binarization. the plurality of pixels in the readout direction of the pixel signal is a unit of four pixels of a first pixel, a second pixel, a third pixel, and a fourth pixel over four rows of the same column;
The signal processing circuit is
A first storage unit, a second storage unit, a third storage unit, a fourth storage unit, a fifth storage unit, and a sixth storage unit,
During the security mode,
storing the first difference data of the first pixel in the first storage unit;
storing the first difference data of the second pixel in the second storage unit, and storing the first difference data of the first pixel stored in the first storage unit in the fifth storage unit; stored in
storing the first difference data of the third pixel in the third storage unit;
storing the first difference data of the fourth pixel in the fourth storage unit;
The computing unit
a first difference data between the first difference data of the first pixel stored in the fifth storage unit and the first difference data of the second pixel stored in the second storage unit; While performing averaging processing, the first difference data of the third pixel stored in the third storage unit and the first difference data of the fourth pixel stored in the fourth storage unit performing a second averaging process between the difference data,
acquiring second difference data obtained by taking a difference between the first average processing result data and the second average processing result data, and storing the acquired second difference data in the sixth storage unit; 4. The solid-state imaging device according to claim 2 or 3, wherein the image is stored. the plurality of pixels in the readout direction of the pixel signal is a unit of four pixels of a first pixel, a second pixel, a third pixel, and a fourth pixel over four rows of the same column;
The signal processing circuit is
including a first storage unit and a second storage unit,
During the security mode,
storing the first difference data of the first pixel in the first storage unit;
The calculation unit adds the first difference data of the first pixel and the first difference data of the second pixel stored in the first storage unit, and stores the result in the second storage unit. remember,
The calculation unit calculates the third pixel data from the addition data of the first difference data of the first pixel and the first difference data of the second pixel stored in the second storage unit. storing the addition/subtraction data obtained by subtracting the difference data of 1 in the first storage unit;
The computing unit
subtracting the first difference data of the fourth pixel supplied from the readout unit from the addition/subtraction data stored in the first storage unit, and obtaining the first division data obtained by dividing by 2; 4. The solid-state imaging device according to claim 2, wherein said first division data obtained by dividing is stored in said second storage unit. the plurality of pixels in the readout direction of the pixel signal is a unit of four pixels of a first pixel, a second pixel, a third pixel, and a fourth pixel over four rows of the same column;
The signal processing circuit is
including a first storage unit and a second storage unit,
During the security mode,
The calculation unit stores first division data obtained by dividing the first difference data of the first pixel by 2 in the first storage unit;
The calculation unit adds the first division data stored in the first storage unit and the second division data obtained by dividing the first difference data of the second pixel by 2, and Stored in the second storage unit as first averaging processing result data between the first difference data of the first pixel and the first difference data of the second pixel;
The calculation unit subtracts third division data obtained by dividing the first difference data of the third pixel by 2 from the first average processing result data stored in the second storage unit. storing the addition/subtraction data in the first storage unit;
The computing unit
obtaining second difference data obtained by subtracting fourth division data obtained by dividing the first difference data of the fourth pixel by 2 from the addition/subtraction data stored in the first storage unit; 4. The solid-state imaging device according to claim 2, wherein said second difference data is stored in said second storage unit. the plurality of pixels in the readout direction of the pixel signal is a unit of four pixels of a first pixel, a second pixel, a third pixel, and a fourth pixel over four rows of the same column;
The signal processing circuit is
The first storage unit and the second storage unit are shared, and there are two access systems, a first access system and a second access system, to the shared storage unit, and the two access systems are including a multi-port memory with independently controlled addresses for data input and data output;
During the security mode,
the arithmetic unit stores first division data obtained by dividing the first difference data of the first pixel by 2 in the shared storage unit through the first access system;
Second division data obtained by dividing, by 2, the first difference data of the second pixel and the first division data stored in the shared storage unit read out by the second access system by the calculation unit. is added and stored in the shared memory by the first access system as first averaging processing result data between the first difference data of the first pixel and the first difference data of the second pixel stored in the department,
The calculation unit divides the first difference data of the third pixel from the first average processing result data stored in the shared storage unit read by the second access system by 2. storing the addition/subtraction data obtained by subtracting the third division data in the shared storage unit through the first access system;
The computing unit
Second data obtained by subtracting fourth division data obtained by dividing the first difference data of the fourth pixel by 2 from the addition/subtraction data stored in the shared storage unit read by the second access system 4. The solid-state imaging device according to claim 2, wherein differential data is acquired, and the acquired second differential data is stored in the shared storage section through the first access system. the plurality of pixels in the readout direction of the pixel signal is a unit of four pixels of a first pixel, a second pixel, a third pixel, and a fourth pixel over four rows of the same column;
The signal processing circuit is
a memory in which the first storage unit and the second storage unit are shared, and writing and reading of data to and from the shared storage unit are controlled by a write enable signal and a read enable signal;
During the security mode,
The arithmetic unit stores first division data obtained by dividing the first difference data of the first pixel by 2 in the shared storage unit according to the write enable signal;
The arithmetic unit adds the first division data stored in the shared storage unit read by the read enable signal and the second division data obtained by dividing the first difference data of the second pixel by 2. Then, the first difference data of the first pixel and the first difference data of the second pixel are stored in the common storage unit by the write enable signal as the first averaging process result data. ,
The calculation unit divides the first difference data of the third pixel by 2 from the first average processing result data stored in the shared storage unit read out by the read enable signal to obtain the third data. storing the addition/subtraction data obtained by subtracting the division data of from the write enable signal in the shared storage unit;
The computing unit
Second difference data obtained by subtracting fourth division data obtained by dividing the first difference data of the fourth pixel by 2 from the addition/subtraction data stored in the shared storage section read by the read enable signal. 4. The solid-state imaging device according to claim 2 or 3, wherein the obtained second difference data is stored in the shared storage unit by the write enable signal. The pixels are
a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
a transfer element capable of transferring charges accumulated in the photoelectric conversion element during a transfer period;
a floating diffusion in which charges accumulated in the photoelectric conversion element are transferred through the transfer element;
a source follower element that converts the charge of the floating diffusion into a voltage signal with a gain corresponding to the amount of charge;
9. The solid-state imaging device according to claim 1, further comprising a reset element for resetting said floating diffusion to a predetermined potential. The pixel portion is
10. The solid-state imaging device according to claim 9, having a pixel sharing structure in which one said floating diffusion, one said source follower element and one reset element are shared by a plurality of said photoelectric conversion elements and said transfer elements. 11. The solid-state imaging device according to claim 10, wherein a clip circuit for limiting pixel output voltage amplitude is arranged at the edge of the pixel array. The signal processing circuit is
Information security signal processing including response data generation processing is possible in a security mode different from the normal operation mode that generates normal images.
The solid-state imaging device according to any one of claims 1 to 11, wherein the information security signal processing is executed as signal processing during a blanking period of image signal processing or as signal processing for each row. The information security signal processing includes:
13. The solid-state imaging device according to claim 12, wherein at least one of device authentication, data integrity authentication, and data encryption. The information security signal processing includes:
including an authentication process in which a pixel address is used as a challenge and response data generated by a predetermined procedure is used as a response;
the first difference data containing the variation information is acquired as a multi-bit digital value;
The signal processing circuit is
14. The solid-state imaging device according to claim 12, further comprising a function of increasing the number of bits of the variation information read for generating the response data. The signal processing circuit is
15. The multi-bit process according to claim 14, wherein a plurality of outputs of the variation information are taken out as one block, encoded by Lehmer code, and the information encoded by Lehmer is converted into Gray code. Solid-state imaging device. The authentication accuracy that should be ensured when performing authentication is
From the uniqueness and reproducibility data of the information security signal processing, the probability FPR of recognizing a fake as a genuine article and the probability FNR of recognizing a genuine article as a fake are obtained as indicators of authentication accuracy, and the probability FPR and the probability FNR can be used for evaluation. The solid-state imaging device according to any one of claims 13 to 15.

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