JP4822071B2 - Decoding device and decoding method - Google Patents

Description

  The present invention relates to a decoding apparatus and a decoding method, and more particularly, to a decoding apparatus and a decoding method capable of reducing the circuit scale when decoding a low density parity check code (LDPC code).

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, encoding methods that exhibit performance close to the Shannon limit include, for example, so-called turbo codes such as parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC). A technique called Turbo coding has been developed. While these turbo codes have been developed, the use of low density parity check codes (hereinafter referred to as LDPC codes), which is an encoding method that has been known for a long time, is attracting attention.

  The LDPC code was first proposed in Non-Patent Document 1 by R. G. Gallager, and thereafter has been refocused in Non-Patent Document 2 and the like.

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Due to the above advantages, the error correction method with the BCH code concatenated with the LDPC code is also adopted in the DVB-S2 (Digital Video Broadcasting S2) standard standardized by the European Telecommunication Standard Institute (ETSI). The -S2 standard is a standard that combines this error correction method and multi-level modulation of 8PSK (8-Phase Shift Keying) or higher. When the receiver performance is the same, the DVB-S2 standard has a transmission capacity of 25% to 30% per band compared to the DVB-S standard, which employs a concatenated convolutional code and Reed-Solomon code. It is expected to be improved to a certain extent.

  By the way, decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which is a variable node (also called a message node) and a check node. ) And a message passing algorithm based on belief propagation on a so-called Tanner graph. Hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

  However, in probabilistic decoding, since the message passed between each node is a real value, in order to solve it analytically, it is necessary to track the probability distribution itself of messages that take consecutive values. It will require analysis with difficulty. Therefore, Gallager has proposed algorithm A or algorithm B as a decoding algorithm for LDPC codes.

The decoding of the LDPC code is generally performed according to a procedure as shown in FIG. Here, an LDPC code LDPC-encoded in frame units is a received value U ₀ , a message output from the check node is u _j, and a message output from the variable node is v _i . The message is a real value expressing the value of “0” as a so-called log likelihood ratio. Here, the log likelihood ratio of the “0” likelihood of the received value U ₀ is expressed as a received value u _0i .

First, in decoding of an LDPC code, as shown in FIG. 1, in step S11, a received value U ₀ (received value u _0i ) is received, a message u _j is initialized to “0”, and an iterative process is performed. A variable k that takes an integer as a counter of is initialized to "0". In step S12, the message v _i is obtained by performing the calculation shown in Expression (1) based on the received value u _0i , and further the calculation shown in Expression (2) is performed based on the message v _i. Asks for the message u _j .

・・・（１）

... (1)

・・・（２）

... (2)

Note that d _v and d _c in Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (row direction) and horizontal direction (column direction) of the parity check matrix H, respectively. For example, in the case of the (3, 6) code, d _v = 3 and d _c = 6.

In addition, in the calculation of the expression (1) or (2), the message input from the edge to which the message is to be output is not used as a parameter for the sum or product operation. The range of operation is 1 to d _v -1 or 1 to d _c -1. Furthermore, the calculation shown in the equation (2) actually creates a table of the function R (v ₁ , v ₂ ) shown in the equation (3) defined by one output for two inputs v ₁ and v ₂ in advance. This is done by using it continuously (recursively) as shown in equation (4).

・・・（３）

... (3)

・・・（４）

... (4)

  In step S12, the variable k is further incremented by “1”. In step S13, it is determined whether or not the variable k is equal to or greater than a predetermined iterative decoding count N. If it is determined in step S13 that the variable k is not N or more, the process returns to step S12, and the same process is repeated thereafter.

  On the other hand, if it is determined in step S13 that the variable k is greater than or equal to N, in step S14, the message v as the decoding result to be finally output is obtained by performing the calculation shown in equation (5). The LDPC code decoding process ends.

・・・（５）

... (5)

  In addition, the calculation of Formula (5) is performed using the input message from all the branches connected to the variable node, unlike the calculation of Formula (1).

For example, in the case of a (3, 6) code, such an LDPC code is decoded as shown in FIG. In FIG. 2, the calculation shown in Expression (1) is performed at the node indicated by “=” (variable node), and the calculation shown in Expression (2) is performed at the node indicated by “+” (check node). Done. In particular, in algorithm A, the message is binarized, and the exclusive OR operation of d _c −1 input messages is performed at the node indicated by “+”, and the received value at the node indicated by “=”. For R, if d _v −1 input messages all have different bit values, the sign is inverted and output.

  On the other hand, in recent years, research on implementation methods for decoding LDPC codes has also been conducted. Before describing the mounting method, first, decoding of an LDPC code will be schematically described.

  FIG. 3 is an example of a check matrix H (parity check matrix) of a (3, 6) LDPC code (coding rate 1/2, code length 12). The parity check matrix H of the LDPC code can be written using a Tanner graph as shown in FIG. In FIG. 4, “+” represents a check node, and “=” represents a variable node. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between the check node and the variable node is an edge and corresponds to “1” of the parity check matrix H. That is, when the component in the j-th row and the i-th column of the check matrix H is 1, in FIG. 4, the i-th variable node from the top ("=" node) and the j-th check node from the top ( Are connected by a branch. The branch indicates that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node. 4 is a Tanner graph of the parity check matrix H of FIG.

  An LDPC code decoding method called “Belief Propagation” or “Sum Product Algorithm” repeatedly performs variable node computation and check node computation.

In the variable node, the calculation of Expression (1) is performed as shown in FIG. That is, in FIG. 5, the message v _i corresponding to the branch to be calculated is calculated using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the reception information u _0i . Messages corresponding to other branches are similarly calculated.

  Before explaining the operation of the check node, the expression (2) is changed to the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b). And rewrite as equation (6). However, sign (x) is 1 when x ≧ 0, and −1 when x <0.

・・・（６）

... (6)

Furthermore, when x ≧ 0 and φ (x) = − ln (tanh (x / 2)), it is φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ). And can be written as equation (7).

・・・（７）

... (7)

In the check node, the calculation of Expression (7) is performed as shown in FIG. That is, in FIG. 6, the message u _j corresponding to the branch to be calculated is calculated using the messages v ₁ , v ₂ , v ₃ , v ₄ , v ₅ from the remaining branches connected to the check node. The Messages corresponding to other branches are similarly calculated.

The function φ (x) can also be expressed as φ (x) = ln ((e ^x +1) / (e ^x −1)). When x> 0, φ (x) = φ ⁻¹ ( x). When the functions φ (x) and φ ⁻¹ (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.

  When the thumb product algorithm is implemented in hardware, it is necessary to repeatedly perform the variable node operation represented by Expression (1) and the check node operation represented by Expression (7) with an appropriate circuit scale and operating frequency.

  Next, with reference to FIG. 7 to FIG. 10, as an example of a decoding device mounting method, a mounting method in the case where decoding is performed by sequentially performing each node operation one by one (full serial decoding) will be described.

  Here, for example, it is assumed that a code (coding rate 2/3, code length 108) represented by a check matrix H of 36 (rows) × 108 (columns) in FIG. 7 is decoded. The number of 1s in the parity check matrix H in FIG. 7 is 323. Therefore, in the Tanner graph, the number of branches is 323. Here, in the check matrix H in FIG. 7, 0 is expressed by “.”.

  FIG. 8 shows an example of the configuration of a decoding apparatus that sequentially performs the calculation of each node one by one.

  In the decoding device of FIG. 8, a message corresponding to one branch is calculated for each clock of the operation clock.

  That is, the decoding apparatus in FIG. 8 includes two branch memories 100 and 102, one check node calculator 101, one variable node calculator 103, one reception memory 104, and one control unit 105.

  In the decoding device of FIG. 8, message data is read one by one from the branch memory 100 or 102, and message data corresponding to a desired branch is calculated using the message data. The message data obtained by the calculation is stored in the branch memory 102 or 100 in the subsequent stage one by one. When a high error correction capability is realized by performing iterative decoding, a plurality of decoding devices of FIG. 8 that perform this one-time decoding are connected in series or by repeatedly using the decoding device of FIG. Implements iterative decoding. Here, for example, it is assumed that a plurality of decoding devices in FIG. 8 are connected.

  The branch memory 100 stores the message D100 supplied from the variable node calculator 103 of the preceding decoding device (not shown) in the order in which the subsequent check node calculator 101 reads the message D100. In the check node calculation phase, the branch memory 100 supplies the message D100 to the check node calculator 101 as the message D101 in the stored order.

  Based on the control signal D106 supplied from the control unit 105, the check node calculator 101 uses the message D101 supplied from the branch memory 100 to perform an operation according to Expression (7), and obtains the message obtained by the operation. D102 is supplied to the branch memory 102 in the subsequent stage.

  The branch memory 102 stores the message D102 supplied from the previous check node calculator 101 in the order in which the subsequent variable node calculator 103 reads the message D102. In the variable node calculation phase, the branch memory 102 supplies the message D102 to the variable node calculator 103 as the message D103 in the stored order.

  Further, the control signal D107 is supplied from the control unit 105 to the variable node calculator 103, and the reception value D104 is supplied from the reception memory 104. Based on the control signal D107, the variable node calculator 103 uses the message D103 supplied from the branch memory 100 and the received value D104 supplied from the reception memory 104, and performs an operation according to the equation (1). The message D105 obtained as a result is supplied to the branch memory 100 of the decoding device in the subsequent stage (not shown).

  The reception memory 104 receives and stores a reception value D108, which is a reception LLR (log likelihood ratio) representing the likelihood of 0 of the code bit calculated from the LDPC code received through the communication path. Note that the LDPC code is LDPC-coded in units of frames. The reception memory 104 reads the received reception value D108 and supplies it to the variable node calculator 103 as the reception value D104.

  The control unit 105 supplies a control signal D106 for controlling the variable node calculation and a control signal D107 for controlling the check node calculation to the check node calculator 101 and the variable node calculator 103, respectively. When all branch messages are stored in the branch memory 100, the control unit 105 supplies the control signal D106 to the check node calculator 101, and when all branch messages are stored in the branch memory 102, A control signal D107 is supplied to the variable node calculator 103.

  FIG. 9 shows a detailed configuration example of the check node calculator 101 of FIG.

  In FIG. 9, the check node calculator 101 is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. In FIG. 9, a check node calculation of the LDPC code represented by the check matrix H in FIG. 7 is performed. Further, a clock ck is supplied to the check node computing unit 101 in FIG. 9, and this clock ck is supplied to a necessary block. Each block performs processing in synchronization with the clock ck.

  The check node calculator 101 in FIG. 9 is supplied from the control unit 105, for example, using the message D101 read one by one from the branch memory 100 based on the 1-bit control signal D106. Therefore, calculation is performed.

That is, the check node calculator 101 reads one 6-bit message D101 (message v _i ) from the variable node corresponding to each column of the check matrix H one by one, and the absolute value D122 (| v _i |) is supplied to the LUT 121, and the sign bit D121, which is the most significant bit, is supplied to the EXOR circuit 129 and the FIFO (First In First Out) memory 133, respectively. The check node calculator 101 is supplied with a control signal D106 from the control unit 105, and the control signal D106 is supplied to the selector 124 and the selector 131.

The LUT 121 reads the 5-bit operation result D123 (φ (| v _i |)) obtained by performing the operation of φ (| v _i |) in the equation (7) with respect to the absolute value D122 (| v _i |). The adder 122 and the FIFO memory 127 are supplied.

The adder 122 adds the operation result D123 (φ (| v _i |)) and the 9-bit value D124 stored in the register 123, thereby accumulating the operation result D123, and 9 bits obtained as a result. Is stored again in the register 123. Note that when the calculation results for the absolute value D122 (| v _i |) of the message D101 from all branches over one row of the check matrix H are accumulated, the register 123 is reset.

  When the message D101 over one row of the check matrix H is read one by one and the accumulated value obtained by accumulating the operation result D123 for one row is stored in the register 123, the control signal D106 supplied from the control unit 105 is , Change from 0 to 1. For example, when the row weight is “9”, the control signal D106 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D106 is “1”, the selector 124 determines the value obtained from the value stored in the register 123, that is, the message D101 (message v _i ) from all branches over one row of the check matrix H. (| v _i |) 9-bit value that is accumulated D124 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) is selected, as a value D125, and stores and outputs to the register 125 . The register 125 supplies the stored value D125 to the selector 124 and the adder 126 as a 9-bit value D126. When the control signal D106 is “0”, the selector 124 selects the value D126 supplied from the register 125, outputs it to the register 125, and stores it again. That is, until φ (| v _i |) obtained from the message D101 (message v _i ) from all branches over one row of the check matrix H is accumulated, the register 125 accumulates φ (| v _i |) is supplied to the selector 124 and the adder 126.

On the other hand, FIFO memories 127, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D126 from the register 125 until it is output, the result calculation LUT121 has output D123 (phi (| v _i |)) is delayed and supplied to the subtractor 126 as a 5-bit value D127. The subtractor 126 subtracts the value D127 supplied from the FIFO memory 127 from the value D126 supplied from the register 125, and supplies the subtraction result to the LUT 128 as a 5-bit subtraction value D128. That is, the subtractor 126 calculates the message D101 from the branch to be obtained from the integrated value of φ (| v _i |) obtained from the message D101 (message v _i ) from all the branches over one row of the check matrix H. Φ (| v _i |) obtained from (message v _i ) is subtracted, and the subtraction value (Σφ (| v _i |) from i = 1 to i = d _c −1) is used as the subtraction value D128. Supply to LUT128.

  Since the subtractor 126 subtracts the 5-bit value D127 supplied from the FIFO memory 127 from the 9-bit value D126 supplied from the register 125, the subtraction result can be 9 bits at maximum. In contrast, a 5-bit subtraction value D128 is output. Therefore, when the subtraction result obtained by subtracting the 5-bit value D127 supplied from the FIFO memory 127 from the 9-bit value D126 supplied from the register 125 cannot be expressed in 5 bits, that is, the subtraction result is 5 bits. The subtractor 126 clips the subtraction result to the maximum value that can be represented by 5 bits and exceeds the maximum value that can be represented by 31 (11111 in binary number). Is output.

The LUT 128 calculates φ ⁻¹ (Σφ (| v _i |)) in Expression (7) with respect to the subtraction value D128 (Σφ (| v _i |) from i = 1 to i = d _c −1). A 5-bit calculation result D129 (φ ⁻¹ (Σφ (| v _i |))) is output.

  In parallel with the above processing, the EXOR circuit 129 multiplies the sign bits by calculating an exclusive OR of the 1-bit value D131 stored in the register 130 and the sign bit D121. The bit multiplication result D130 is stored again in the register 130. Note that when the sign bit D121 of the message D101 from all branches over one row of the check matrix H is multiplied, the register 130 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D130 to the sign bit D121 of the message D101 is multiplied from all of the branches across one line of the parity check matrix H is stored in the register 130, The control signal D106 supplied from the control unit 105 changes from “0” to “1”.

When the control signal D106 is “1”, the selector 131 has a value D131 obtained by multiplying the value stored in the register 130, that is, the sign bit D121 of the message D101 from all branches of one row of the check matrix H. (i = 1 from up to _{i = d c Πsign (v i} )) is selected, to store output as 1-bit value D132 to the register 132. The register 132 supplies the stored value D132 to the selector 131 and the EXOR circuit 134 as a 1-bit value D133. When the control signal D106 is “0”, the selector 131 selects the value D133 supplied from the register 132, outputs it to the register 132, and stores it again. In other words, the register 132 supplies the previously stored value to the selector 131 and the EXOR circuit 134 until the sign bits D121 of the message D101 (message v _i ) from all branches over one row of the check matrix H are multiplied. To do.

On the other hand, FIFO memories 133, between (from i = 1 i = Πsign to d _c (v _i)) a new value D133 from the register 132 until is supplied to the EXOR circuit 134 delays the sign bit D121, The 1-bit value D134 is supplied to the EXOR circuit 134. The EXOR circuit 134 calculates the exclusive OR of the value D133 supplied from the register 132 and the value D134 supplied from the FIFO memory 133, thereby dividing the value D133 by the value D134 and dividing by 1 bit. The result is output as the division value D135. That is, the EXOR circuit 134 uses the sign bit D121 (sign (| v _i |)) of the message D101 from all the branches over one row of the check matrix H as the sign bit of the message D101 from the branch to be obtained. Dividing by D121 (sign (| v _i |)), the divided value (Πsign (| v _i |) from i = 1 to i = d _c −1) is output as a divided value D135.

In the check node calculator 101, the 5-bit operation result D129 output from the LUT 128 is set to the lower 5 bits, and the total 6 bits including the 1-bit division value D135 output from the EXOR circuit 134 as the most significant bit is a message. D102 (message u _j ) is output.

As described above, the check node calculator 101 performs the calculation of Expression (7) to obtain the message u _j .

Note that since the maximum row weight of the check matrix H in FIG. 7 is 9, that is, the maximum number of messages supplied to the check node is 9, the check node calculator 101 has nine messages ( A FIFO memory 127 and a FIFO memory 133 for delaying φ (| v _i |)) are provided. When calculating a message for a row with a row weight less than 9, the amount of delay in the FIFO memory 127 and the FIFO memory 133 is reduced to the value of the row weight.

  FIG. 10 shows a detailed configuration example of the variable node calculator 103 of FIG.

  In FIG. 10, the variable node calculator 103 is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. In FIG. 10, the variable node calculation of the LDPC code represented by the check matrix H in FIG. 7 is performed. Further, the variable node computer 103 in FIG. 10 is supplied with a clock ck, and the clock ck is supplied to a necessary block. Each block performs processing in synchronization with the clock ck.

  The variable node calculator 103 in FIG. 10 is supplied from the control unit 105, for example, based on a 1-bit control signal D107, and is read from the branch memory 102 one by one and the reception memory 104. Using received value D104, calculation is performed according to equation (1).

That is, the variable node calculator 103 reads one 6-bit message D103 (message u _j ) from the check node corresponding to each row of the check matrix H, and the message D103 is added to the adder 151 and the FIFO memory 155. To be supplied. In the variable node calculator 103, the 6-bit received value D 104 is read one by one from the reception memory 104 and supplied to the adder / subtracter 156. Further, the control signal D107 is supplied from the control unit 105 to the variable node calculator 103, and the control signal D107 is supplied to the selector 153.

The adder 151 adds the message D103 (message u _j ) and the 9-bit value D151 stored in the register 152 to accumulate the message D103, and the resulting 9-bit accumulated value is stored in the register. Store again in 152. When the messages D103 from all branches over one column of the check matrix H are accumulated, the register 152 is reset.

  When the message D103 over one column of the check matrix H is read one by one and the value obtained by integrating the message D103 for one column is stored in the register 152, the control signal D107 supplied from the control unit 105 is “ It changes from “0” to “1”. For example, when the column weight is “5”, the control signal D107 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D107 is “1”, the selector 153 integrates the value stored in the register 152, that is, the message D103 (message u _j ) from all branches over one column of the check matrix H. select (? uj _j from j = 1 to d _V) value D151 of bits to be stored and outputs to the register 154. The register 154 supplies the stored value D151 to the selector 153 and the adder / subtracter 156 as a 9-bit value D152. When the control signal D107 is “0”, the selector 153 selects the value D152 supplied from the register 154, outputs it to the register 154, and stores it again. That is, until the message D103 (message u _j ) from all branches over one column of the check matrix H is accumulated, the register 154 supplies the previously accumulated value to the selector 153 and the adder / subtracter 156.

On the other hand, FIFO memories 155, between (from j = 1? Uj _j to d _V) a new value D152 from the register 154 until the output delays the message D103 from check nodes, as a 6-bit value D153 This is supplied to the adder / subtracter 156. The adder / subtracter 156 subtracts the value D153 supplied from the FIFO memory 155 from the value D152 supplied from the register 154. That is, the adder / subtracter 156 subtracts the message u _j from the branch to be obtained from the integrated value of the message D103 (message u _j ) from all branches over one column of the check matrix H, and the subtraction value (j Σu _j ) from = 1 to d _v −1. Further, the adder / subtracter 156 adds the reception value D104 supplied from the reception memory 104 to the subtraction value (Σu _j from j = 1 to d _v −1), and obtains a 6-bit obtained as a result. The value is output as message D105 (message v _i ).

As described above, the variable node calculator 103 performs the calculation of Expression (1) to obtain the message v _i .

Since the maximum weight of the column of the check matrix H in FIG. 7 is 5, that is, the maximum number of messages supplied to the variable node is 5, the variable node calculator 103 has five messages ( a FIFO memory 155 for delaying u _j ). When calculating a message for a column with a column weight less than 5, the amount of delay in the FIFO memory 155 is reduced to the value of the column weight.

  The adder / subtractor 156 subtracts the 6-bit value D153 supplied from the FIFO memory 155 from the 9-bit value D152 supplied from the register 154, and also receives the 6-bit received value supplied from the reception memory 104. Since the operation of adding D104 is performed, the operation result may be less than the minimum value that can be represented by the 6-bit message D105 or may exceed the maximum value. If the operation result is less than the minimum value that can be represented by the 6-bit message D105, the adder / subtracter 156 clips to the minimum value, and the operation result is the maximum that can be represented by the 6-bit message D105. If the value is exceeded, the maximum value is clipped.

  In the decoding apparatus of FIG. 8, a control signal is given from the control unit 105 according to the weight of the check matrix H. According to the decoding apparatus of FIG. 8, only the control signal is changed as long as the capacity of the branch memories 100 and 102 and the FIFO memories 127, 133, and 155 of the check node calculator 101 and the variable node calculator 103 are sufficient. Thus, LDPC codes of various parity check matrices H can be decoded.

  Although not shown, in the decoding device of FIG. 8, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1), and the calculation result is the final decoding. Output as a result.

  When the LDPC code is decoded by repeatedly using the decoding apparatus of FIG. 8, the check node calculation and the variable node calculation are alternately performed. That is, in the decoding device of FIG. 8, the variable node calculation is performed by the variable node calculator 103 using the check node calculation result by the check node calculator 101, and the variable node calculation result by the variable node calculator 103 is used. Thus, the check node calculator 101 performs a check node calculation.

  Therefore, one decoding using the check matrix H of FIG. 7 having 323 branches requires 323 × 2 = 646 clocks. For example, in order to perform 50 times of iterative decoding, it is necessary to operate 646 × 50 = 32300 clocks while receiving one frame of codewords consisting of 108 codes, which are code lengths, as received values. Therefore, a high-speed operation approximately 300 (≈32300 / 108) times the reception frequency is required. If the reception frequency is several tens of MHz, operation at a speed of GHz or higher is required.

  In addition, when decoding the LDPC code by connecting, for example, 50 decoding apparatuses in FIG. 8, while performing the variable node calculation of the first frame, the check node calculation of the second frame is performed, A plurality of variable node operations and check node operations can be performed simultaneously, such as performing a variable node operation of the third frame. In this case, since it is only necessary to calculate 323 branches while 108 codes are received, the decoding apparatus only needs to operate at a frequency approximately 3 (≈323 / 108) times the reception frequency. Is fully feasible. However, in this case, the circuit scale is simply 50 times that of the decoding device of FIG.

  Therefore, for example, Non-Patent Document 3 describes an implementation method for simultaneously calculating four messages in addition to the decoding device of FIG. 8. In this case, simultaneous reading from different addresses in the memory, Alternatively, it is generally not easy to avoid simultaneous writing, and there is a problem that memory access control is difficult.

  In order to solve this problem, for example, Non-Patent Document 4 and “Non-Patent Document 5” report a code and a decoding device that are highly compatible with the implementation of a partially parallel decoder rather than a random code. However, the decoding apparatus implementation methods described in Non-Patent Documents 4 and 5 correspond only to specific codes, and a single decoder decodes codes of various code lengths and coding rates. It is difficult to do.

  In addition, a P × P unit matrix, a matrix in which one or more of the unit matrices become 0 (hereinafter referred to as a quasi-unit matrix as appropriate), a unit matrix or a quasi-unit matrix is cyclic shifted. A combination of two or more (a plurality of) of unit matrices, quasi-unit matrices, or shift matrices (hereinafter referred to as a sum matrix), and a P × P 0 matrix, respectively. If the LDPC code has a parity check matrix H that can be represented by or an LDPC code that has a parity check matrix H that can be represented by a combination of these matrices by row or column replacement, the code length, coding rate A decoding apparatus has been devised that can decode even different codes.

  In this decoding apparatus, P check node calculators that perform check node operations and P variable node calculators that perform variable node operations are provided, and decoding is performed by performing P check node operations and P variable node operations in parallel. Is done.

  In addition, a method of approximating and implementing the sum product algorithm has been proposed, but this method causes performance degradation.

By the way, when the reception memory constituting the decoding device is composed of one memory for storing the reception value u _0i , the reception memory cannot read and write at the same time, and therefore stores the reception value u _0i . While one of decoding using the received value u _0i is being performed, the other cannot be performed. Therefore, the use efficiency of the reception memory is poor and the throughput is reduced.

Therefore, it is considered to provide a plurality of memories for storing the received value u _0i in the receiving memory so that reading and writing are performed simultaneously.

  FIG. 11 shows an example of the configuration of the reception memory 200 provided with two memories.

  The reception memory 200 shown in FIG. 11 includes switches 211 and 214 and reception value storage memories 212 and 213.

The switch 211 is supplied with a reception value D211 that is a reception LLR representing the likelihood of 0 of the code bit calculated from the LDPC code received through the communication path, and stores the reception value from the control unit constituting the decoding device. A control signal D210 ₁ representing selection of either one of the memories 212 and 213 is supplied. Switch 211 based on the control signal D210 _1, and supplies the received value D211, the received-value storage memory 212 as a received value D 212, or received-value storage memory 213 as a received value D213.

  The reception value storage memory 212 stores the reception value D212 from the switch 211 or supplies the reception value D212 already stored to the switch 214 as the reception value D214. Similarly to the reception value storage memory 212, the reception value storage memory 213 stores the reception value D213 from the switch 211 or supplies the reception value D215 already stored to the switch 214.

  The reception value storage memories 212 and 213 are configured by, for example, a single port RAM (Random Access Memory). Further, the amount of data stored in each of the received value storage memories 212 and 213, that is, the storage capacity required for each of the received value storage memories 212 and 213, is the code length of the LDPC code, the received value It is a multiplication value with the number of quantization bits.

The switch 214, the control unit constituting the decoding apparatus, the control signal D210 ₂ representing selection of one of the received-value storage memory 212 and 213 is supplied, the switch 214 based on the control signal D210 _2, received The reception value D214 read from the value storage memory 212 or the reception value D215 read from the reception value storage memory 213 is output to the variable node calculator as the reception value D216.

The control signal D210 ₁ represents one selection of the received value storage memories 212 and 213, and the control signal D210 ₂ represents the other selection. Therefore, while writing is being performed on one of the received value storage memories 212 and 213, reading is performed on the other.

As described above, the reception memory 200 is provided with the two reception value storage memories 212 and 213, so that while the reception value D211 input on one side is being stored, the reception value D211 is already stored on the other side. The received value D216 can be output. As a result, the reception memory 200 can continuously output the reception value D211 that is continuously input as the reception value D216.

R. G. Gallager, "Low Density Parity Check Codes", Cambridge, Massachusetts: M. I. T. Press, 1963 DJC MacKay, "Good error correcting codes based on very sparse matrices", Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999, and MG Luby, M. Mitzenmacher, MA Shokrollahi and DA Spielman, "Analysis of low density codes and improved designs using irregular graphs", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998 E. Yeo, P. Pakzad, B. Nikolic and V. Anantharam, "VLSI Architectures for iterative Decoders in Magnetic Recording Channels", IEEE Transactions on Magnetics, Vol. 37, No. 2, March 2001 T. Zhang, K. K. Parhi, “Joint (3, k) -regular LDPC Code and decoder / encoder design,” IEEE Transactions on Signal Processing, Vol. 52, No. 4, pp. 1065-1079, April 2004 M.M.Mansour, N.R.Shanbhag, “A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes,” Proceedings of IEEE Workshop on Signal Processing Systems 2003 (SIPS 2003), pp. 29-34, Aug. 2003

In the decoding apparatus that performs P check node operations and P variable node operations in parallel, each of the P variable node calculators uses the received value u _0i stored in the reception memory 200 and simultaneously performs variable processing. Since node calculation is performed, it is necessary to simultaneously read P received values u _0i from the reception memory 200. Therefore, the bit width required for each of the reception value storage memories 212 and 213 is P bits. When P is large, the bit width required for the reception value storage memories 212 and 213 is large.

  For example, when decoding an LDPC code based on the DVB-S2 standard and having a code length of 64800, when the number of quantization bits of the LDPC code is 5 bits and P is 360, the received value storage memory 212 and The bit width required for 213 is 1800 (= 360 × 5) bits, and the number of words is 180 (= 64800/360) words.

  Since the bit width of a RAM (Random Access Memory) macro or the like constituting the received value storage memories 212 and 213 is about several hundred bits, in order to secure a large bit width, the received value storage memory 212 is used. And the number of RAM macros constituting 213 increases, and the circuit scale of the reception memory 200 increases.

  The present invention has been made in view of such a situation, and makes it possible to reduce the circuit scale when decoding an LDPC code.

A decoding apparatus according to a first aspect of the present invention is a decoding apparatus that decodes an LDPC (Low Density Parity Check) code, and that temporarily stores a reception value of the LDPC code that is intermittently input. A storage means and a reception value continuously read from the first storage means or a reception value of the LDPC code input intermittently are temporarily stored, and the stored reception value is continuously stored. A second storage means for reading out the received data, a third storage means for storing the received value continuously read out by the second storage means, and reading out the stored received value for each predetermined unit; And a decoding means for decoding the received value read out for each predetermined unit by the storage means for each predetermined unit, and the bit width of the second storage means is the same as that of the third storage means. Less than bit width.

In the decoding device according to the first aspect of the present invention, the transfer time for reading the received value from the second storage means and storing the received value in the third storage means is the LDPC code. It can be made within the invalid time which is a time without a value in the received value of the codeword unit.

In the decoding device according to the first aspect of the present invention, the second storage means can read the received value in units of codewords.

In the decoding device according to the first aspect of the present invention, the first storage means can temporarily store the reception value of the intermittently input LDPC code at the transfer time.

In the decoding device according to the first aspect of the present invention, the second storage means performs a decoding requesting the end of decoding of a reception value that is a previous read target before reading the reception value in units of codewords. An end request signal is supplied to the decoding unit, and then, after a predetermined time has elapsed, the received value is read out in units of codewords, and the decoding unit is configured to read the previous read target according to the decoding end request signal. The decoding of a certain received value is terminated, and the sum of the predetermined time and the transfer time can be within the invalid time.

In the decoding device according to the first aspect of the present invention, the first storage means may temporarily store the received value of the LDPC code input intermittently at the transfer time and the predetermined time. it can.

The decoding method according to the first aspect of the present invention includes a first storage means for temporarily storing received values of LDPC codes that are input intermittently, and a continuous reading from the first storage means. Second storage means for temporarily storing the received value or the received value of the LDPC code input intermittently, and third storage means for storing the received value continuously read out by the second storage means And decoding means for decoding the LDPC code, comprising: decoding means for decoding the received value read by the third storage means for each predetermined unit for each predetermined unit; The first storage means temporarily stores the intermittently received LDPC code received value;
The second storage means having a bit width smaller than that of the third storage means temporarily receives the reception value read continuously from the first storage means or the reception value of the LDPC code input intermittently. And the second storage means continuously reads the stored reception value, and the third storage means stores the reception value continuously read by the second storage means. The third storage means reads the stored reception value for each predetermined unit, and the decoding means reads the reception value read for each predetermined unit by the third storage means. And decoding for each of the predetermined units.

A decoding apparatus according to a second aspect of the present invention is a decoding apparatus that decodes an LDPC (Low Density Parity Check) code, and that temporarily stores a reception value of the LDPC code that is input intermittently. A storage means and a reception value continuously read from the first storage means or a reception value of the LDPC code input intermittently are temporarily stored, and the stored reception value is continuously stored. A second storage means for reading out the received data, a third storage means for storing the received value continuously read out by the second storage means, and reading out the stored received value for each predetermined unit; And a decoding means for decoding the received value read out for each predetermined unit by the storage means, and the second storage means and the third storage means are connected in series. is the bit width of the second storage means, said third storage means Bit smaller than the width.

In the first aspect of the present invention, the first storage means temporarily stores the received value of the LDPC code input intermittently, and the second storage means has a bit width smaller than that of the third storage means. However, the reception value continuously read from the first storage means or the reception value of the LDPC code input intermittently is temporarily stored, and the second storage means stores the reception value stored. continuously read, the third memory means stores the received values to be read successively by the second storage means, third storage means, reading the received value stored for each predetermined unit, Decoding means decodes the received value read for each predetermined unit by the third storage means for each predetermined unit.

In the second aspect of the present invention, there is provided first storage means for temporarily storing received values of LDPC codes inputted intermittently, and reception continuously read out from the first storage means. Value or intermittently inputted LDPC code received value, second storage means for continuously reading the stored received value, and reception continuously read by the second storage means A third storage means for storing a value and reading the stored reception value for each predetermined unit, connected in series, and the reception value read for each predetermined unit by the third storage means, Decoding means for decoding for each predetermined unit is provided. The bit width of the second storage means is smaller than the bit width of the third storage means .

  As described above, according to the first and second aspects of the present invention, it is possible to reduce the circuit scale when decoding an LDPC code.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

The decoding device according to the first aspect of the present invention provides:
A decoding device (for example, the decoding device 400 in FIG. 12) that decodes an LDPC (Low Density Parity Check) code,
First storage means (for example, pre-buffer 511 in FIG. 18) for temporarily storing the received value of the LDPC code input intermittently;
Temporarily storing the received value of the first continuously read received value or the intermittent LDPC code input from the storage means, second reading the received value stored continuously Storage means (for example, the input buffer 513 in FIG. 18);
Storing the received values are continuously read out by said second storage means, third storage means for reading the received value stored in each predetermined unit (e.g., received-value storage memory 514 in FIG. 18) When,
Decoding means (for example, the calculation units 412 and 415 in FIG. 12) that decodes the received value read by the third storage means for each predetermined unit for each predetermined unit;
The bit width of the second storage means is smaller than the bit width of the third storage means.

The decoding method according to the first aspect of the present invention includes:
First storage means for temporarily storing received values of LDPC codes input intermittently; received values read continuously from the first storage means; or LDPC codes input intermittently Second storage means (for example, the input buffer 513 in FIG. 18) for temporarily storing the received value and third storage means (for example, for storing the reception value continuously read by the second storage means) , The received value storage memory 514) of FIG. 18 and a decoding means for decoding the received value read for each predetermined unit by the third storage means (for example, the calculation of FIG. 12). A decoding device (for example, the decoding device 400 of FIG. 12) for decoding the LDPC code,
The first storage means temporarily stores a reception value of the LDPC code input intermittently;
The second storage means having a bit width smaller than that of the third storage means temporarily receives the reception value read continuously from the first storage means or the reception value of the LDPC code input intermittently. (For example, step S25 in FIG. 20)
The second storage means continuously reads out the received value stored (for example, step S31 in FIG. 20),
The third storage means stores the received value continuously read out by the second storage means (for example, step S32 in FIG. 20),
The third storage means reads the stored reception value for each predetermined unit (for example, step S37 in FIG. 20),
The decoding means decodes the received value read for each predetermined unit by the third storage means for each predetermined unit (for example, step S51 in FIG. 21).
Includes steps.

The decoding device according to the second aspect of the present invention provides:
A decoding device (for example, the decoding device 400 in FIG. 12) that decodes an LDPC (Low Density Parity Check) code,
First storage means for temporarily storing the received value of the LDPC code input intermittently;
Received value continuously read from the first storage means or LD input intermittently
Second storage means (for example, the input buffer 513 in FIG. 18) for temporarily storing the received value of the PC code and continuously reading the stored received value;
The third storage means for storing the reception value continuously read out by the second storage means and reading out the stored reception value for each predetermined unit (for example, the reception value storage memory 514 in FIG. 18). When,
Decoding means (for example, the calculation units 412 and 415 in FIG. 12) that decodes the received value read by the third storage means for each predetermined unit for each predetermined unit;
The second storage means and the third storage means are connected in series ,
The bit width of the second storage means is smaller than the bit width of the third storage means .

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 12 shows a configuration example of the first embodiment of a decoding device to which the present invention is applied.

  Note that, here, an LDPC code having a parity check matrix H that can be represented by a combination of a 6 × 6 unit matrix, a quasi-unit matrix, a shift matrix, a sum matrix, and a 6 × 6 zero matrix shown in FIG. It is assumed that an LDPC code having a parity check matrix H that can be represented by a combination of these matrices is decoded by row or column replacement.

  The parity check matrix H in FIG. 13 represents the parity check matrix H shown in FIG. 7 with an interval in units of 6 × 6 matrices. In addition, the 6 × 6 unit matrix, the quasi-unit matrix, the shift matrix, the sum matrix, and the 0 matrix constituting the parity check matrix H in FIG.

12 includes a decoding intermediate result storage memory 410, a cyclic shift circuit 411, a calculation unit 412 including six calculators 412 ₁ to 412 ₆ , a decoding intermediate result storage memory 413, a cyclic shift. The circuit 414 includes a calculator 415 including _six calculators 415 ₁ to 415 ₆ , a switch 416, a reception memory 417, and a controller 418, and decodes LDPC codes six by six.

Here, the calculation performed by the calculator 412 _k (k = 1, 2,..., 6) and the calculation performed by the calculator 415 _k will be described using equations.

Specifically, the calculation unit 412 performs the first calculation according to the above-described equation (7) and the following equation (8), and decodes the decoding result u _j that is the result of the first calculation. The result is supplied to and stored in the intermediate result storage memory 410. The calculation unit 415 performs the second calculation according to the above-described equation (5), and supplies the decoding intermediate result v, which is the result of the second calculation, to the decoding intermediate result storage memory 410 for storage.

・・・（８）

... (8)

Note that u _dv in Expression (8) represents an intermediate result (in this case, the check node calculation result itself) of the check node calculation from the branch for which the i-column message of the check matrix H is to be obtained. That is, u _dv is a decoding intermediate result corresponding to the branch to be obtained.

That is, the decoding intermediate result v obtained as a result of the second calculation according to the above-described equation (5) is the check node calculation from all branches corresponding to 1 in each row of the i column of the received value u _0i and the check matrix H. because of the decoding intermediate result is obtained by adding the u _j, the values v _i used in equation (7) described above, from the equation (5) in accordance of the second operation result obtained decoding intermediate results v, test A value obtained by subtracting the decoding intermediate result u _dv of the check node operation from the branch for which a message is to be obtained from the decoding intermediate result u _j of the check node operation from the branch corresponding to 1 in each row of the i column of the matrix H. It becomes. That is, the calculation of the expression (1) for obtaining the value v _i used for the calculation of the expression (7) is a combination of the above expressions (5) and (8).

  Accordingly, in the decoding device 400, the first calculation according to the equations (7) and (8) by the calculation unit 412 and the second calculation according to the equation (5) by the calculation unit 415 are alternately performed, and the calculation is performed. The unit 415 outputs the result of the last second operation as a decoding result, so that it is possible to perform LDPC code iterative decoding.

Here, the first calculation result according to Expression (7) and Expression (8) is described as a decoding intermediate result u _j, and this decoding intermediate result u _j is the check node calculation result of Expression (7). It is equal to u _j .

Further, v in the expression (5) obtained by the second operation is obtained by adding the check node operation result u _j from the branch for which a message is to be obtained to the variable node operation result v _{i in the} expression (1). Therefore, only one is obtained for one column (one variable node) of the check matrix H.

In decoding apparatus 400, calculation unit 412 performs the first calculation using decoding intermediate result v corresponding to the column of parity check matrix H that is the result of the second calculation by calculation unit 415, and obtains the result of the calculation. Decoding intermediate result u _j of the check node operation from the branch of the message corresponding to 1 in each row (message output by each check node to each branch) of i columns of the parity check matrix H It stores in 413. Therefore, the capacity of the decoding intermediate result storage memory 413 is a value obtained by multiplying the number of 1 (the number of all branches) of the parity check matrix H and the number of quantization bits as in the case of storing the result of the check node calculation. .

On the other hand, the calculation unit 415 uses the decoding intermediate result u _j corresponding to “1” of each row and the received value u _0i of the i column of the parity check matrix H that is the result of the first calculation by the calculation unit 412 to 2 is performed, and the decoding intermediate result v corresponding to the i column obtained as a result of the calculation is stored in the decoding intermediate result storage memory 410. Therefore, the necessary capacity of the decoding intermediate result storage memory 410 is the number of columns of the parity check matrix H smaller than the number of “1” of the parity check matrix H, that is, the code length of the LDPC code and the number of quantization bits of the decoding intermediate result v It becomes the value which multiplied.

  As a result, the memory capacity of the decoding intermediate result storage memory 410 can be reduced as compared with the case where the result of the variable node calculation is stored, whereby the circuit scale of the decoding device 400 can be reduced.

  Hereinafter, the operation of each unit of the decoding device 400 of FIG. 12 will be described in detail.

The decoding intermediate result storage memory 410 is supplied with six decoding intermediate results D415 corresponding to the six columns of the check matrix H as the result of the second calculation by the calculation unit 415 from the switch 416 as the decoding intermediate result D416. The decoding intermediate result storage memory 410 stores the six decoding intermediate results D416 (v _i ) supplied from the calculation unit 415 in order from the first address.

  That is, in the decoding address storage memory 410, the decoding intermediate result D416 from the first column to the sixth column among the decoding intermediate results D416 corresponding to the columns of the check matrix H is stored. Similarly, the decryption result D416 from the seventh column to the twelfth column is stored at the second address, and the decryption result D416 from the thirteenth column to the eighteenth column is stored at the third address. Stored. Thereafter, similarly, decoding intermediate results D416 from the 103rd column to the 108th column are stored in increments of 6 from the 4th address to the 18th address, and a total of 108 decoding intermediate results D416 are stored as the decoding intermediate results. Stored in the memory 410. Therefore, the number of words in the decoding intermediate result storage memory 410 is 6, which is the number of decoding intermediate results simultaneously reading and writing 108, which is the number of columns of the check matrix H (code length of the LDPC code) in FIG. Divide by 18.

Further, the decoding intermediate result storage memory 410 sets “1” in the row of the check matrix H corresponding to the decoding intermediate result u _j to be obtained by the subsequent calculation unit 412 from the decoding intermediate result D416 already stored. Six decoding intermediate results D146 are simultaneously read and supplied to the cyclic shift circuit 411 as decoding intermediate results D410.

  Note that the decoding intermediate result storage memory 410 is composed of, for example, a single-port RAM that can simultaneously read and write six decoding intermediate results. Further, since the decoding intermediate result storage memory 410 stores the decoding intermediate result D416 corresponding to the column calculated by the second calculation of the calculation unit 415, the data stored in the decoding intermediate result storage memory 410 is stored in the decoding intermediate result storage memory 410. The amount, that is, the storage capacity required for the decoding intermediate result storage memory 410 is a product of the number of quantization bits of the decoding intermediate result D414 and the number of columns of the parity check matrix H (code length of the LDPC code). .

  The cyclic shift circuit 411 is supplied with six decoding intermediate results D410 from the decoding intermediate result storage memory 410, and the control unit 418 adds 1 of the check matrix H corresponding to the decoding intermediate result D410 to the check matrix. A control signal D420 representing information (Matrix data) indicating the number of cyclic shifts of the original unit matrix in H is supplied. The cyclic shift circuit 411 performs cyclic shift for rearranging the six decoding intermediate results D410 based on the control signal D420, and supplies the result to the calculation unit 412 as the decoding intermediate result D411.

The calculation unit 412 includes six calculators 412 _{1 to} 412 ₆ . The calculation unit 412 is supplied with six decoding intermediate results D411 (v _i ) obtained as a result of the second calculation by the calculation unit 415 from the cyclic shift circuit 411 and from the decoding intermediate result storage memory 413. The six decoding intermediate results D413 (u _j ) obtained as a result of the first calculation by the calculators 412 _{1 to} 412 ₆ are supplied last time, and the six decoding intermediate results D411 and the six decoding intermediate results D413 are These are supplied to the calculators 412 _{1 to} 412 ₆ , respectively. Further, the control unit D 418 is supplied with the control signal D 421 from the control unit 418, and the control signal D 421 is supplied to the calculators 412 _{1 to} 412 ₆ . The control signal D421 is a signal common to the _six calculators 412 _{1 to} 412 ₆ .

The calculators 412 _{1 to} 412 ₆ use the decoding intermediate result D411 and the decoding intermediate result D413, respectively, to perform the first calculation according to the equations (7) and (8), and obtain the decoding intermediate result D412 (u _j ). Ask. The calculation unit 412 supplies six decoding intermediate results D412 corresponding to six ones of the check matrix H obtained as a result of the calculation by the calculators 412 _{1 to} 412 ₆ to the decoding intermediate result storage memory 413. Details of the calculators 412 _{1 to} 412 ₆ will be described with reference to FIG.

  The decoding intermediate result storage memory 413 includes, for example, two single-port RAMs that can simultaneously read and write six decoding intermediate results. Six decoding intermediate results D412 are supplied from the calculation unit 412 to the decoding intermediate result storage memory 413, and a control signal D422 for controlling reading and writing of the decoding intermediate result storage memory 413 is supplied from the control unit 418.

  Based on the control signal D422, the decoding intermediate result storage memory 413 stores the six decoding intermediate results D412 supplied from the calculation unit 412 together, and simultaneously reads the six decoding intermediate results D412 already stored. The decoding result D413 is supplied to the calculation unit 412 and the cyclic shift circuit 414. That is, the decoding intermediate result storage memory 413 simultaneously reads the decoding intermediate result D413 supplied to the calculation unit 412 and the cyclic shift circuit 414 and writes the decoding intermediate result D412 supplied from the calculation unit 412.

  The decoding intermediate result storage memory 413 stores the decoding intermediate result D412 of the first calculation from the branch corresponding to 1 in each row of i columns of the check matrix H calculated by the first calculation of the calculation unit 412. Therefore, the amount of data stored in the decoding intermediate result storage memory 413, that is, the storage capacity required for the decoding intermediate result storage memory 413, is determined by the number of quantization bits of the decoding intermediate result D412 and the check. It is a multiplication value of the number of 1 in the matrix H. Details of the decoding intermediate result storage memory 413 will be described with reference to FIG.

The cyclic shift circuit 414 is supplied with six decoding intermediate results D413 (u _j ) from the decoding intermediate result storage memory 413, and from the control unit 418, 1 of the check matrix H corresponding to the decoding intermediate result D413. Is supplied with a control signal D423 indicating information (Matrix data) indicating how many cyclic shifts of the original unit matrix and the like in the check matrix H are performed. The cyclic shift circuit 414 performs a cyclic shift that rearranges the six decoding intermediate results D413 based on the control signal D423, and supplies the result to the calculation unit 415 as a decoding intermediate result D414.

The calculation unit 415 includes six calculators 415 _{1 to} 415 ₆ . Six decoding intermediate results D414 are supplied from the cyclic shift circuit 414 to the calculation unit 415, and the decoding intermediate results D414 are supplied to the calculators 415 _{1 to} 415 ₆ respectively. The calculation unit 415 is simultaneously supplied with six reception values D419 from the reception memory 417, and the reception values D419 are supplied to the calculators 415 _{1 to} 415 ₆ respectively. Further, a control signal D424 is supplied from the control unit 418 to the calculation unit 415, and the control signal D424 is supplied to the calculators 415 _{1 to} 415 ₆ . The control signal D424 is a signal common to the _six calculators 415 _{1 to} 415 ₆ .

Calculators 415 _{1 to} 415 ₆ use decoding intermediate result D414 and received value D419, respectively, to simultaneously perform a second calculation according to equation (5) to obtain decoding intermediate result D415. The calculation unit 415 supplies six decoding intermediate results D415 (v) obtained as a result of the second calculation of the calculators 415 _{1 to} 415 ₆ to the switch 416. Details of the calculators 415 _{1 to} 415 ₆ will be described with reference to FIG.

  As described above, the data goes around in the order of the decoding intermediate result storage memory 410, the cyclic shift circuit 411, the calculation unit 412, the decoding intermediate result storage memory 413, the cyclic shift circuit 414, and the calculation unit 415. The decoding apparatus 400 can perform one decoding.

  The switch 416 changes the output destinations of the six intermediate decoding results D415 supplied from the calculation unit 415 according to the control signal D425 supplied from the control unit 418 and representing the output of the decoding results. Specifically, when the control signal D425 is not supplied, the switch 416 supplies the six decoding intermediate results D415 to the decoding intermediate result storage memory 410 as decoding intermediate results D416. On the other hand, when the control signal D425 is supplied, the switch 416 outputs six decoding intermediate results D415 as final decoding results D417.

  The reception memory 417 receives a reception value D418, which is a reception LLR calculated from the LDPC code received through the communication path and indicating the likelihood of the code bit being zero.

  Here, for example, it is assumed that an LDPC code conforming to the DVB-S2 standard is received through the communication path. In this case, since a header is provided at the head of the actual value of each frame, and a pilot is inserted in the middle of the actual value of each frame in order to improve the synchronization performance of the demodulation process of the preceding stage of the decoding device 400, This header-pilot section is an invalid time without an actual value, and the received value D418 calculated from the received LDPC code is intermittent. Furthermore, since the operation clock of the decoding device 400 is generally faster than the operation clock of the preceding demodulation process, invalid time is generated even when the operation clock is changed, and the received value D418 becomes intermittent.

  The reception memory 417 stores the reception value D418 input intermittently. Then, the reception memory 417 reads out the reception values D418 that are already stored in the order required for variable node calculation, and supplies them to the calculation unit 415 as reception values D419. Details of the reception memory 417 will be described with reference to FIG.

  The control unit 418 controls each unit so that decoding is repeatedly performed a predetermined number of times set in advance. Specifically, the control unit 418 controls the control signal D420 by supplying the control signal D420 to the cyclic shift circuit 411 and the control signal D421 to the calculation unit 412, respectively. In addition, the control unit 418 controls the control signal D422 by supplying the control signal D422 to the decoding intermediate result storage memory 413, the control signal D423 to the cyclic shift circuit 414, and the control signal D424 to the calculation unit 415, respectively. Further, the control unit 418 supplies the control signal D425 to the switch 416 at a predetermined timing, thereby decoding the intermediate decoding result D415 obtained as the final result of the second calculation repeatedly performed a predetermined number of times. The switch 416 is controlled to output the result D417.

Figure 14 is a block diagram illustrating a detailed configuration example of a calculator 412 _first calculation portion 412 of FIG. 12.

In FIG. 14, the calculator 412 ₁ will be described, but the calculators 412 _{2 to} 412 ₆ are similarly configured.

In FIG. 14, each decoding intermediate result (u _dv ) obtained as a result of the first calculation by the previous calculation unit 412 is quantized into a total of 6 bits (bits) including the sign bit, and the calculation unit 415 performs the first calculation. as a second arithmetic operation results each decoding intermediate result obtained (v) are quantized to 9 bits represent the calculator 412 _1. Further, the calculator 412 ₁ of FIG. 14, the clock ck is supplied, the clock ck is to be supplied to the necessary blocks. Each block performs processing in synchronization with the clock ck.

Calculator 412 ₁ of FIG. 14, based on the control signal D421 supplied from the control unit 418, it is read one by one from the decoding intermediate result storage memory 413, the first operation from the previous calculation portion 412 resulting The first calculation according to the equations (7) and (8) using the decoded intermediate result D413 (u _dv ) and the decoding intermediate result D411 ( _v ) read one by one from the cyclic shift circuit 411. I do.

In other words, the calculator 412 _1, the cyclic shift circuit 411 6 9-bit decoding intermediate results supplied from D411 of (v), together with one decoding intermediate results D411 are supplied, the decoding intermediate result storage Of the six 6-bit decoding intermediate results D413 (u _j ) supplied from the previous memory 413, which is the result of the previous calculation by the calculation unit 412, is supplied, and the 9-bit decoding result D413 is supplied. The decoding intermediate result D411 (v) and the 6-bit decoding intermediate result D413 (u _dv ) are supplied to the subtractor 431. Further, the calculator 412 _1, the control signal D421 is supplied from the control unit 418, the control signal D421 is supplied to the selector 435 and the selector 442.

The subtractor 431 subtracts the 6-bit decoding intermediate result D413 (u _j ) from the 9-bit decoding intermediate result D411 (v), and outputs the 6-bit subtraction value D431. That is, the subtractor 431 performs an operation according to the equation (8), and outputs a subtraction value D431 (v _i ) that is the result of the operation.

Of the 6-bit subtraction value D431 output by the subtractor 431, the sign bit D432 (sign (v _i )) indicating the sign of the most significant bit is supplied to the EXOR circuit 440, and the absolute value D433 (| v _i |) is supplied to the LUT 432.

The LUT 432 reads out the 5-bit calculation result D434 (φ (| v _i |)) obtained by performing the calculation of φ (| v _i |) in Expression (7) with respect to the absolute value D433 (| v _i |). To the adder 433 and the FIFO memory 438.

The adder 433 adds the operation result D434 (φ (| v _i |)) and the 9-bit value D435 stored in the register 434, thereby accumulating the operation result D434, and 9 bits obtained as a result. Is stored again in the register 434. Note that when the calculation results for the absolute value D433 (| v _i |) obtained from the decoding intermediate result D411 corresponding to all 1s in one row of the check matrix H are accumulated, the register 434 is reset.

  When decoding result D411 over one row of parity check matrix H is read one by one and an integrated value obtained by integrating operation results D434 for one row is stored in register 434, a control signal supplied from control unit 418 D421 changes from 0 to 1. For example, when the row weight is “9”, the control signal D421 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D421 is “1”, the selector 435 uses the value stored in the register 434, that is, the decoding intermediate result D411 (decoding intermediate result v) corresponding to all 1s over one row of the check matrix H. obtained φ (| v _i |) 9-bit value that is accumulated D435 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) is selected, as a value D436, the output to the register 436 And store it. The register 436 supplies the stored value D436 to the selector 435 and the adder / subtracter 437 as a 9-bit value D437. When the control signal D421 is “0”, the selector 435 selects the value D437 supplied from the register 436, outputs it to the register 436, and stores it again. That is, the register 436 is accumulated last time until φ (| v _i |) obtained from the decoding intermediate result D411 (decoding intermediate result v) corresponding to all 1s in one row of the check matrix H is integrated. Φ (| v _i |) is supplied to the selector 435 and the adder / subtractor 437.

On the other hand, FIFO memories 438, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D437 from the register 436 until it is output, the result calculation LUT432 has output D434 (phi (| v _i |)) is delayed and supplied to the adder / subtracter 437 as a 5-bit value D438. The adder / subtracter 437 subtracts the value D438 supplied from the FIFO memory 438 from the value D437 supplied from the register 436, and supplies the subtraction result to the LUT 439 as a 5-bit subtraction value D439. That is, the adder / subtracter 437 determines the branch to be obtained from the integrated value of φ (| v _i |) obtained from the decoding intermediate result D411 (decoding intermediate result v) corresponding to all 1s in one row of the check matrix H. , I.e., φ (| v _i |) obtained from the decoding intermediate result D411 (decoding intermediate result v) corresponding to a predetermined 1 of the check matrix H is subtracted, and the subtraction value (i Σφ (| v _i |) from = 1 to i = d _c −1) is supplied to the LUT 439 as the subtraction value D439.

The LUT 439 calculates φ ⁻¹ (Σφ (| v _i |)) in Expression (7) for the subtraction value D439 (Σφ (| v _i |) from i = 1 to i = d _c −1). A 5-bit calculation result D440 (φ ⁻¹ (Σφ (| v _i |))) is output.

  In parallel with the above processing, the EXOR circuit 440 performs an exclusive OR operation between the 1-bit value D442 stored in the register 441 and the sign bit D432, thereby multiplying the sign bits by 1 The bit multiplication result D441 is re-stored in the register 441. When the sign bit D432 obtained from the decoding intermediate result D411 corresponding to all 1s in one row of the check matrix H is multiplied, the register 441 is reset.

(Paisign from i = 1 to d _c (v _i)) multiplication result D441 with sign bit D432 is multiplied by the obtained from the decoding intermediate result D411 corresponding to all 1 across one line of the parity check matrix H register 441 Stored in the control signal 421, the control signal D421 supplied from the control unit 418 changes from “0” to “1”.

When the control signal D421 is “1”, the selector 442 uses the value stored in the register 441, that is, the sign bit D432 obtained from the decoding intermediate result D411 corresponding to all 1s over one row of the check matrix H. There select multiplied value D442 (Πsign of i = 1 through _{i = d c (v i)} ), and stores and outputs a 1-bit value D443 to the register 443. The register 443 supplies the stored value D443 to the selector 442 and the EXOR circuit 445 as a 1-bit value D444. When the control signal D421 is “0”, the selector 442 selects the value D444 supplied from the register 443, outputs it to the register 443, and stores it again. That is, until the sign bit D432 obtained from the decoding intermediate result D411 (decoding intermediate result v) corresponding to all 1s in one row of the check matrix H is multiplied, the register 443 stores the previously stored value as a selector. 442 and the EXOR circuit 445.

On the other hand, FIFO memories 444, between (from i = 1 i = Πsign to d _c (v _i)) a new value D444 from the register 443 until is supplied to the EXOR circuit 445 delays the sign bit D432, The 1-bit value D445 is supplied to the EXOR circuit 445. The EXOR circuit 445 calculates the exclusive OR of the value D444 supplied from the register 443 and the value D445 supplied from the FIFO memory 444, thereby dividing the value D444 by the value D445 and dividing by 1 bit. The result is output as the division value D446. That is, the EXOR circuit 445 uses the multiplication value of the sign bit D432 (sign (v _i )) obtained from the decoding intermediate result D411 corresponding to all 1s over one row of the parity check matrix H as a predetermined value of the parity check matrix H. 1 is divided by the sign bit D432 (sign (v _i )) obtained from the decoding intermediate result D411 corresponding to 1, and the divided value (Πsign (v _i ) from i = 1 to i = d _c −1) is obtained. Output as division value D446.

The calculator 412 _1, an operation result D440 of 5 bits output with the lower 5 bits from LUT439, a total of 6 bits are decoded middle of the 1-bit divided value D446 outputted from the EXOR circuit 445 and the most significant bit The result is output as D412 (decoding intermediate result u _j ).

As described above, the calculator 412 _1, performs the operation of equation (7) and (8), the decoding intermediate results u _j is obtained.

Incidentally, since the maximum weight of the rows of the check matrix H of FIG. 13 is a 9, i.e., the maximum number of calculator 412 ₁ middle decoding supplied results D411 (v) decoding intermediate results to D413 (u _dv) is Therefore, the calculator 412 ₁ delays nine operation results D434 (φ (| v _i |)) obtained from nine decoding intermediate results D411, and nine code bits D432. FIFO memory 444 is provided for delaying. When calculating a message for a row with a row weight less than 9, the amount of delay in the FIFO memory 438 and FIFO memory 444 is reduced to the value of the row weight.

Figure 15 is a block diagram showing a configuration example of a calculator 415 _first calculation unit 415 of FIG. 12.

In FIG. 15, the calculator 415 ₁ will be described, but the calculators 415 _{2 to} 415 ₆ are similarly configured.

Further, in FIG. 15, as the calculation unit 412 according to the first results the decoding intermediate result obtained in operation (u _j) are quantized to six bits to suit the sign bit represents a calculator 415 ₁ ing. Further, the calculator 415 ₁ of FIG. 15, the clock ck is supplied, the clock ck is to be supplied to the necessary blocks. Each block performs processing in synchronization with the clock ck.

The calculator 415 ₁ shown in FIG. 15 receives the received value D419 (u _0i ) read one by one from the receiving memory 417 and one from the cyclic shift circuit 414 based on the control signal D424 supplied from the control unit 418. Using the decoding intermediate result D414 (u _j ) read one by one, the second calculation according to the equation (5) is performed.

That is, in the calculator 415 ₁ , the 6-bit decoding intermediate result D414 (u _j ) corresponding to 1 in each row of the check matrix H is read from the cyclic shift circuit 414 one by one, and the decoding intermediate result D414 is This is supplied to the adder 471. Further, the calculator 415 _1, the received value D419 of six bits from the receiving memory 417 are read in one by one, it is supplied to the adder 475. Further, the calculator 415 _1, the control signal D424 is supplied from the control unit 418, the control signal D424 is supplied to the selector 473.

The adder 471 adds the decoding intermediate result D414 by adding the decoding intermediate result D414 (u _j ) and the 9-bit value D471 stored in the register 472, and obtains the 9-bit integrated value obtained as a result. Is stored in the register 472 again. When the decoding intermediate results D414 corresponding to all 1s over one column of the check matrix H are accumulated, the register 472 is reset.

  When a decoding intermediate result D414 over one column of the check matrix H is read one by one and a value obtained by integrating the decoding intermediate result D414 for one column is stored in the register 472, a control signal supplied from the control unit 418 D424 changes from “0” to “1”. For example, when the column weight is “5”, the control signal D424 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D424 is “1”, the selector 473 accumulates the values stored in the register 472, that is, the decoding intermediate results D414 (u _j ) from all the branches over one column of the check matrix H. 9-bit value D471 (from j = 1? uj _j to d _V) is selected, it is stored in output register 474. The register 474 supplies the stored value D471 to the selector 473 and the adder 475 as a 9-bit value D472. When the control signal D424 is “0”, the selector 473 selects the value D472 supplied from the register 474, outputs it to the register 474, and stores it again. That is, the register 474 supplies the previous accumulated value to the selector 473 and the adder 475 until the decoding intermediate results D414 (u _j ) from all the branches over one column of the check matrix H are accumulated.

  The adder 475 adds the 9-bit value D472 and the 6-bit reception value D419 supplied from the reception memory 417, and outputs the 6-bit value obtained as a result as a decoding intermediate result D415 (v). To do.

As described above, the calculator 415 _1, performs the operation of Equation (5), the decoding intermediate results v are obtained.

Since the maximum column weight of the parity check matrix H in FIG. 7 is 5, that is, the maximum number of decoding intermediate results u _j supplied to the calculator 415 ₁ is 5, the calculator 415 ₁ A maximum of five 6-bit decoding intermediate results u _j are added. Thus, the output of the calculator 415 ₁ has a 9-bit value.

  FIG. 16 is a block diagram illustrating a configuration example of the decoding intermediate result storage memory 413 of FIG.

  The decoding intermediate result storage memory 413 includes switches 501 and 504 and decoding intermediate result storage RAMs 502 and 503 which are two single-port RAMs.

  Before describing each part of the decoding intermediate result storage memory 413 in detail, first, a method of storing data in the decoding intermediate result storage RAMs 502 and 503 will be described.

  The decoding intermediate result storage RAMs 502 and 503 store the decoding intermediate result D412 obtained as a result of the first calculation by the calculation unit 412 and supplied via the switch 501.

  Specifically, the decoding intermediate result D412 (D501) corresponding to 1 from the first row to the sixth row of the parity check matrix H in FIG. ) Are stored in a form packed in the horizontal direction (column direction) for each row (ignoring 0).

  That is, if the j-th row and the i-th column are represented as (j, i), the first address of the decoding intermediate result storage RAM 502 is the constituent matrix of the check matrix H of FIG. To (6,6) corresponding to 1 of the 6 × 6 unit matrix, the second address includes (1,25) to (6,30) which are constituent matrices of the check matrix H of FIG. Data corresponding to 1 of a shift matrix (shift matrix obtained by cyclically shifting a unit matrix of 6 × 6) by five in the right direction) is stored. Similarly, data is stored in association with the configuration matrix of the check matrix H in FIG. At the ninth address, the shift matrix (1,102) to (6,108) of the parity check matrix H (1 in the first row of the 6 × 6 unit matrix is replaced with 0 and cyclically leftward by one). Data corresponding to 1 of the shifted shift matrix) is stored. Here, in the shift matrix from (1,102) to (6,108) of the parity check matrix H in FIG. 13, since there is no 1 in the first row, no data is stored at the ninth address.

  Further, data corresponding to 1 from the 13th row to the 18th row of the check matrix H in FIG. 13 is stored in the 10th to 18th addresses of the decoding intermediate result storage RAM 502. That is, at the 10th address, data corresponding to 1 of the matrix obtained by cyclically shifting the 6 × 6 unit matrix from (13,7) to (18,12) of the check matrix H by five to the right is stored. At the eleventh address, the sum matrix of (13,13) to (18,18) of the check matrix H (6 × 6 unit matrix and 6 × 6 unit matrix only one cyclically in the right direction) The data corresponding to 1 of the shift matrix constituting the sum matrix with the shifted shift matrix) is stored. Further, data corresponding to 1 of the unit matrix constituting the sum matrix of (13,13) to (18,18) of the check matrix H is stored at the twelfth address. Hereinafter, the data corresponding to the check matrix H is also stored for the 13th to 18th addresses.

  That is, for a configuration matrix with a weight of 2 or more, the configuration matrix is a P × P unit matrix with a weight of 1, a quasi-unit matrix with one or more of its components being 0, or a unit When the matrix or the quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclic shift, the data corresponding to the position of the unit matrix, the quasi-unit matrix, or the shift matrix having a weight of 1 ( The result of decoding a message corresponding to a branch belonging to a unit matrix, a quasi-unit matrix, or a shift matrix is stored at the same address.

  Similarly, data corresponding to 1 from the 25th row to the 30th row is stored in the 19th to 27th addresses of the decoding intermediate result storage RAM 502 in association with the check matrix H in FIG. The That is, the number of words in the decoding intermediate result storage RAM 502 is 27.

  Decoding intermediate result D412 (D502) corresponding to 1 from the seventh row to the twelfth row of parity check matrix H in FIG. It is stored in a form packed in the horizontal direction (column direction) (ignoring 0).

  That is, at the first address of the decoding intermediate result storage RAM 503, the sum matrix (6 × 6 unit matrix of 2 × 6 × 6), which is the component matrix of the check matrix H, is added in the right direction. Data corresponding to 1 of the first shift matrix constituting the first shift matrix that is cyclically shifted only by 1 and the sum matrix that is the sum of the second shift matrix that is cyclically shifted by 4 in the right direction, In the second address, data corresponding to 1 of the second shift matrix constituting the sum matrix of (7,1) to (12,6), which is the constituent matrix of the check matrix H, is stored. Thereafter, data is stored in association with the configuration matrix of the check matrix H in the same manner from the third address to the ninth address.

  Similarly, the 10th to 18th addresses of the decoding intermediate result storage RAM 503 include data corresponding to 1 from the 19th line to the 24th line of the parity check matrix H in FIG. At address 27, data corresponding to 1 from the 31st row to the 36th row of the parity check matrix H is stored in association with the parity check matrix H of FIG. That is, the number of words in the decoding intermediate result storage RAM 503 is 27.

  As described above, the number of words in the decoding intermediate result storage RAMs 502 and 503 is 27. That is, the number of words is obtained by multiplying the row weight 9 of the parity check matrix H by the number 36 of the row, and the multiplication result (the number of 1s in the parity check matrix H) is simultaneously read from the decoding intermediate result D501. The value is divided by the number 6 and further divided by 2 which is the number of decoding intermediate result storage RAMs included in the decoding intermediate result storage memory 413.

  Hereinafter, the operation of each part of the decoding intermediate result storage memory 413 in FIG. 16 will be described in detail.

When the first calculation is performed by the calculation unit 412, the decoding intermediate result D 412 (u _j ) obtained as a result of the first calculation is supplied from the calculation unit 412 to the decoding intermediate result storage memory 413. The result D412 is written to a predetermined address of one of the decoding intermediate result storage RAM 502 or the decoding intermediate result storage RAM 503, and at the same time, the decoding intermediate obtained as a result of the first calculation by the previous calculation unit 412 from the other. The result D412 (u _j ) is read and output to the calculation unit 412. On the other hand, when the second calculation is performed by the calculation unit 415, the decoding intermediate result storage memory 413 does not write to the decoding intermediate result storage RAM 502 or the decoding intermediate result storage RAM 503, and the predetermined calculation of either one of the RAMs is not performed. The intermediate decoding result is read out from the address and supplied to the cyclic shift circuit 414.

Specifically, six intermediate decoding results D412 are supplied from the calculation unit 412 to the switch 501, and the decoding intermediate result storage RAM 502 or the decoding intermediate result storage RAM 503 is used as a memory for writing the decoding intermediate result D412. control signal D422 ₁ representing one of the selection is supplied from the control unit 418. The switch 501 selects _one of the decoding intermediate result storage RAM 502 or the decoding intermediate result storage RAM 503 based on the control signal D4221, and supplies six decoding intermediate results D412 to the selected one.

The decoding intermediate result storage RAM 502, 6 single decoding intermediate results D412 from the switch 501, is supplied as a decoded intermediate results D501, the control signal D422 ₂ representing the address is supplied from the control unit 418. Decoding intermediate result storage RAM502 reads the control signal D422 ₂ addresses already previous stored calculator 412 according to the first calculation result obtained six decoding intermediate results representative D501, as a decoding intermediate result D503 Supply to switch 504. Further, the decoding intermediate result storage RAM502 in the address indicated by the control signal D422 _2, stores the six decoding intermediate results D501 supplied from the switch 501.

The decoding intermediate result storage RAM 503, 6 single decoding intermediate results D412 from the switch 501, is supplied as a decoded intermediate results D502, the control signal D422 ₃ representing the address supplied from the controller 418. Decoding intermediate result storage RAM503 reads the control signal D422 ₃ represents addresses already stored first according to the previous calculation portion 412 and the calculation results obtained six decoding intermediate results D502, as a decoding intermediate result D504 Supply to switch 504. Further, the decoding intermediate result storage RAM503 in the address indicated by the control signal D422 _3, stores the six decoding intermediate results D502 supplied from the switch 501.

The switch 504 is supplied with the decoding intermediate result D503 from the decoding intermediate result storage RAM 502 or the decoding intermediate result D504 from the decoding intermediate result storage RAM 503. Further, the control unit 418, the control signal D422 ₄ that represents the selection of one of the decoding intermediate result storage RAM502 or decoding intermediate result storage RAM503 is supplied. Switch 504, the control signal D422 based on ₄ selects one of the decoding intermediate result storage RAM502 or decoding intermediate result storage RAM 503, the six decoding intermediate results supplied from one of the the selected six decoding middle The result D413 is supplied to the calculation unit 412 and the cyclic shift circuit 414.

  FIG. 17 is a timing chart for explaining the reading and writing operations of the decoding intermediate result storage RAM 502 and the decoding intermediate result storage RAM 503 of the decoding intermediate result storage memory 413.

  In FIG. 17, the horizontal axis represents time (t). In FIG. 17, reading data corresponding to 1 of the constituent matrix of the number i added to the constituent matrix so as to increase from the upper left toward the lower right is expressed as Ri, and the writing of the data is performed. Expressed as Wi.

The decoding intermediate result storage memory 413, if the calculation part 412 first operation is performed, the decoding intermediate result storage RAM 502, based on the control signal D422 _2, already stored, the previous calculation unit 412 Of decoding intermediate result D501 obtained as a result of the first calculation, decoding intermediate result D501 corresponding to 1 from the first row to the sixth row of parity check matrix H stored at the same address is set to one clock. Are read out 9 times (for 9 clocks) continuously (R0 to R8) and supplied to the calculation unit 412 via the switch 504. That is, since the row weight of the parity check matrix H in FIG. 13 is 9, there are nine decoding intermediate results corresponding to 1 in each row of the parity check matrix H, and the decoding intermediate result storage RAM 502 has the first row from the first row. Six intermediate decoding results D501 corresponding to 1 up to the sixth line are read out 9 times in units of 6 and supplied to the calculation unit 412.

Next, the decoding intermediate result storage RAM503, based on the control signal D422 _3, already stored, out of the previous calculation unit 412 according to the first resultant decoded intermediate results of computation D502, at the same address The decoding intermediate result D502 corresponding to 1 from the 7th row to the 12th row of the stored parity check matrix H is read out 9 times in units of 6 (R9 to R17), and via the switch 504 , And supplied to the calculation unit 412. Subsequently, similarly, the decoding intermediate result storage RAMs 502 and 503 alternately read the decoding intermediate result D501 or D502 nine times in units of six and supply them to the calculation unit 412.

By the way, in the calculators 412 _{1 to} 412 ₆ or 415 _{1 to} 415 ₆ that calculate nodes one by one, a delay corresponding to the node degree occurs. For example, the calculators 412 _{1 to} 412 ₆ have a delay of 9 clocks. Further, when the decoding device 400 performs a high-speed operation exceeding 100 MHz, the calculators 412 _{1 to} 412 ₆ are further delayed by about 3 clocks and need to be pipelined by about 3 clocks.

  That is, the time required for the calculation unit 412 to perform the first calculation, that is, after the decoding intermediate result D413 is read from the decoding intermediate result storage memory 413, the first calculation using the decoding intermediate result D413 is performed. The time until the decoding intermediate result D412 obtained as a result of the above is supplied to the decoding intermediate result storage memory 413 is a time T1 corresponding to 12 clocks.

In this case, after the time T1 after the first reading (R0) of the decoding intermediate result D503 from the decoding intermediate result storage RAM 502 is started, the first calculation is performed from the calculation unit 412 to the decoding intermediate result storage memory 413. Supply of six intermediate decoding results D412 corresponding to 1 from the first row to the sixth row of the check matrix H obtained as a result is started. The decoded intermediate results D413 are supplied to the decoding intermediate result storage RAM502 as decoded intermediate results D501 via the switch 501, the decoding intermediate result storage RAM502 is the decoded intermediate results D501, based on the control signal D422 _2, It is stored nine times continuously at the address where the already decoded intermediate result D503 has been stored (W0 to W8).

  In other words, after the decoding intermediate result D503 is read nine times (R0 to R8) by the decoding intermediate result storage RAM 502, the decoding intermediate result D501 is stored nine times (W0 to W8) by the decoding intermediate result storage RAM 502. Is started for a period of time Tw (= T1-9) for three clocks.

  As a result, nine times of reading (R9 to R17) from the decoding intermediate result storage RAM 503 is completed, and nine times of storage (W0 to W8) to the decoding intermediate result storage RAM 502 is completed after the time Tw has elapsed. To do. Accordingly, the time Tw from the end of nine readings (R9 to R17) to the decoding intermediate result storage RAM 503 to the start of nine readings (R18 to R26) from the decoding intermediate result storage RAM 502 is completed. Waiting time is required.

  FIG. 18 shows a detailed configuration example of the reception memory 417 in FIG.

  The reception memory 417 in FIG. 18 includes a pre-buffer 511, a switch 512, an input buffer 513, and a reception value storage memory 514. The reception value D418 is intermittently input to the reception memory 417, and the reception value D418 is supplied to the prebuffer 511 and the terminal 512A of the switch 512.

  A control signal D515 indicating selection of the prebuffer 511 is supplied from the input buffer 513 to the prebuffer 511. The pre-buffer 511 temporarily stores the received value D418 according to the control signal D515. Note that the storage capacity of the pre-buffer 511 is the maximum number M of received values D418 that can be received within the time required to transfer the received value D513 for one frame from the input buffer 513 to the received value storage memory 514. , The multiplication value with the number of quantization bits.

  On the other hand, as will be described later, the storage capacity of the input buffer 513 and the reception value storage memory 514 is the data amount of the reception value for one frame, that is, the product of the code length and the number of quantization bits. The storage capacity of the pre-buffer 511 is sufficiently smaller than the storage capacity of the input buffer 513 and the received value storage memory 514.

  Further, the pre-buffer 511 continuously reads the stored received value D418 as the received value D511 and supplies it to the input buffer 513 via the switch 512. Further, the pre-buffer 511 deletes the received reception value D418 that has been read. The pre-buffer 511 supplies a control signal D514 indicating selection of the terminal 512A to the switch 512 when there is no stored reception value D418.

  The switch 512 has three terminals 512A to 512C. The received value D418 is input to the terminal 512A, the pre-buffer 511 is connected to the terminal 512B, and the input buffer 513 is connected to the terminal 512C. The switch 512 connects the terminal 512A and the terminal 512C according to the control signal D514 supplied from the pre-buffer 511, and inputs the reception value D418 input to the terminal 512A to the input buffer 513 as the reception value D512. The switch 512 connects the terminal 512B and the terminal 512C according to the control signal D515 supplied from the input buffer 513, and the received value D511 read from the prebuffer 511 is input to the input buffer 513 as the received value D512. input.

  The storage capacity of the input buffer 513 is, for example, a multiplication value of the code length and the number of quantization bits, and the input buffer 513 temporarily stores the received value D512 input by the switch 512 for one frame. Here, the bit width of the input buffer 513 is 1 / N (N is an integer of 2 or more) times the bit width of the received value storage memory 514, and the number of words is the number of words in the received value storage memory 514. Although the bit width of the input buffer 513 is smaller than the bit width of the received value storage memory 514, it is not necessary to be 1 / N times.

  The input buffer 513 inputs the control signal D515 to the prebuffer 511 and the switch 512 when the writing of the reception value D512 for one frame is completed, for example, when the free capacity of the input buffer 513 becomes zero. Then, the input buffer 513 continuously reads the stored received value D512 for one frame as the received value D513, and transfers it to the received value storage memory 514. That is, the input buffer 513 continuously reads the received value D512 in units of one frame, that is, in codeword units, and transfers the received value D512 to the received value storage memory 514.

  The reception value storage memory 514 is connected in series to the input buffer 513, and the storage capacity of the reception value storage memory 514 is a product of the code length and the number of quantization bits. The reception value storage memory 514 stores the reception value D513 for one frame transferred from the input buffer 513 in order from the first address.

As described above, since the six calculators 415 _{1 to} 415 ₆ perform the second calculation at the same time, the received value storage memory 514 simultaneously outputs the six received values D419 to the calculators 415 _{1 to} 415 ₆ . Each needs to be supplied. Accordingly, the reception value storage memory 514 is configured by, for example, a single port RAM that can simultaneously read six reception values D419, and the bit width of the reception value storage memory 514 is 6 times the number of quantization bits. Yes, the number of words is a value obtained by dividing 6 from the code length (108 in this case) (18 in this case).

  Specifically, among the reception values D513 corresponding to the columns of the check matrix H, the reception values D513 in the first to sixth columns are stored in the first address of the reception value storage memory 514. Similarly, received values D513 in the seventh column to the twelfth column are stored in the second address, and received values D513 in the thirteenth column to the eighteenth column are stored in the third address. The Thereafter, similarly, received values D513 from the 103rd column to the 108th column are stored in increments of 6 from the 4th address to the 18th address, and a total of 108 received values D513 are stored in the received value storage memory 514. Stored.

  The received value storage memory 514 reads the received values D513 for one frame stored in units of words in units of six words, and the calculated six received values D513 as six received values D419 are calculated by a calculation unit 415 (FIG. 12). ).

  As described above, in the reception memory 417, the input buffer 513 and the reception value storage memory 514 are connected in series, and output of the reception value D419 to the calculation unit 415 is performed by one reception value storage memory 514. Therefore, the input buffer 513 does not need to read the six received values D419 at the same time, and the bit width of the input buffer 513 can be made smaller than six times the number of quantization bits. As a result, the reception memory 417 is configured as compared with the conventional reception memory 104 (FIG. 11) configured by the two reception value storage memories 212 and 213 having a bit width 6 times the number of quantization bits. By reducing the number of RAM macros, the circuit scale of the reception memory 417 can be reduced.

  Next, timing in the reception memory 417 in FIG. 18 will be described with reference to FIG.

As shown in FIG. 19A, when intermittent input of the reception value D418 of frame #i, which is the i-th frame from the beginning, is started to the reception memory 417 at time t _A as shown in FIG. 19B. The pre-buffer 511 starts writing the received value D418 in response to the control signal D515 from the input buffer 513, and receives the received value of the received value D513 of the frame # i-1 immediately before the frame #i described later. During the time A up to the time t _B when the transfer to the storage memory 514 ends, only the reception value D418 is written (W _{i in the} figure). Since the header is added before the actual value at the beginning of the reception value D418 of the frame #i as described above, the prebuffer 511 starts from the time t _A ′ when the actual value is received. Start writing.

Further, from time t _A ′ to time t _B , as shown in FIG. 19D, the switch 512 selects the pre-buffer 511 in accordance with the control signal D515 from the input buffer 513, as shown in FIG. 19B. As described above, the pre-buffer 511 does not perform reading. Accordingly, nothing is supplied from the pre-buffer 511 to the switch 512 as shown in FIG. 19C, and nothing is supplied from the switch 512 to the input buffer 513 as shown in FIG. 19E.

On the other hand, as shown in FIG. 19F, at time t _A , the input buffer 513 reads the received value D512 of the frame # i−1 that has already been stored, and stores the received value D512 in the received value storage memory 514. It starts the transfer (in the figure, R _i-1), thereby, as shown in FIG. 19G, the received-value storage memory 514, frame # i-1 of the received value D512 is supplied as a received value D513 The Then, as shown in FIG. 19H, the reception value storage memory 514 starts writing the reception value D513 of the frame # i−1 supplied from the input buffer 513 (W _{i−1 in the} figure).

At time t _B after the time A from the time t _A, as shown in FIG. 19F to FIG. 19H, the transfer of the frame # i-1 received value D513 from the input buffer 513 to the received-value storage memory 514 is completed, As shown in FIG. 19B, the pre-buffer 511 starts both writing of the reception value D418 of the frame #i supplied intermittently and continuous reading of the reception value D418 of the frame #i already written. (W _i & R _{i in the} figure). Accordingly, as shown in FIG. 19C, the received value D418 of frame #i is input from the pre-buffer 511 to the switch 512 as the received value D511 with the invalid time reduced.

At this time, as shown in FIG. 19D, the switch 512 keeps selecting the pre-buffer 511, and the received value D511 of the frame #i read from the pre-buffer 511 is changed to the received value as shown in FIG. This is supplied to the input buffer 513 as D512. Also, as shown in FIG. 19F, at time t _B , the input buffer 513 finishes reading the received value D513 of frame # i−1 and writes the received value D512 of frame #i supplied from the switch 512. Is started (W _{i in the} figure). Accordingly, as shown in FIG. 19G, the received value D513 is not input to the received value storage memory 514. At this time, as shown in FIG. 19H, the received value storage memory 514 reads the received value D513 of frame # i−1 written at time A as received values D419 in units of six, and supplies them to the calculation unit 415. As a result, iterative decoding of frame # i-1 is performed (iterative decoding # i-1).

  By the way, the reception value D418 is intermittently supplied to the pre-buffer 511, but the reception value D418 is continuously read from the pre-buffer 511. Therefore, if both the writing and reading of the reception value D418 are performed, a predetermined time is obtained. After the elapse, the prebuffer 511 is emptied. In the example of FIG. 19, this predetermined time is assumed to be time B.

Accordingly, as shown in FIG. 19B, the pre-buffer 511 finishes writing and reading the received value D418 (NO in the figure) at time t _C after time _B from time t _B , thereby causing FIG. As shown, the supply of the received value D511 from the prebuffer 511 to the switch 512 is terminated. At this time, the pre-buffer 511 supplies the control signal D514 to the switch 512, and the switch 512 selects the terminal 512A according to the control signal D514 as shown in FIG. 19D. As a result, as shown in FIG. 19E, the reception value D418 of the frame #i that is intermittently input is input as it is to the input buffer 513 as the reception value D512.

Also, as shown in FIG. 19F, at time t _C , the input buffer 513 continues to write the received value D512 of frame #i input from the switch 512, and at time t _D , the received value of frame #i. When all writing of D512 is completed, the writing ends. That is, the input buffer 513 writes the reception value D511 continuously input from the pre-buffer 511 as the reception value D512 during the time _B from time t _B to time t _C , and from time t _C to time t _D. During time C, all received values D418 of frame #i are written by writing received values D418 that are directly input intermittently without passing through the pre-buffer 511 as received values D512.

As described above, since the input buffer 513 performs writing and does not perform reading during the time B and C, the reception from the input buffer 513 is also performed between the time t _C and the time C as shown in FIG. 19G. The received value D513 is not supplied to the value storage memory 514. Therefore, iterative decoding of frame # i-1 continues to be performed between time t _C and time C. When the predetermined number of times of decoding of frame # i-1 is completed at time t _D after time _C from time t _C , the decoding ends.

Next, as shown in FIG. 19A, at time t _D, for receiving memory 417, the intermittent input received value D418 of the next frame # i + 1 of the frame #i is started, time from time t _A Processing is performed in the same manner as the times A to C until t _D.

That is, during time A from time t _D to time t _E , as shown in FIGS. 19F to 19H, the received value of frame #i written to the input buffer 513 from time t _B to time t _D is shown. The D512 is read and the received value D512 is transferred to the received value storage memory 514 (R _{i in the} figure), and the six received values D419 from the received value storage memory 514 are written. (W _{i in the} figure). Further, as shown in FIG. 19B, between the time t _D 'the actual value of the frame # i + 1 is received until time t _E, the pre-buffer 511, only performs writing received values D418 of frame # i + 1 ( In the figure, W _{i + 1} ), as shown in FIG. 19D, the switch 512 selects the pre-buffer 511 in accordance with the control signal D515 from the input buffer 513. Therefore, as shown in FIGS. 19C and 19E, Nothing is supplied from the pre-buffer 511 to the input buffer 513.

Then, as shown in FIGS. 19B to 19F, the frame # written in the prebuffer 511 from the time t _D during the time B from the time t _E to the time t _F and the time C from the time t _F to the time t _G. The received value D418 of i + 1 and the received value D418 of frame # i + 1 supplied directly without being written to the prebuffer 511 are written to the input buffer 513 (W _{i + 1 in the} figure), and during this time, the decoding of frame #i is performed. It is repeated a predetermined number of times (in the figure, iterative decoding #i).

  As described above, since the reception value D418 is intermittently supplied, the invalid time of the reception value D418 of each frame received between the times A and B continuously read from the prebuffer 511 is used. If it is within the invalid time, the received value D513 can be transferred from the input buffer 513 to the received value storage memory 514. Therefore, in the reception memory 417, the input buffer 513 and the reception value storage memory 514 can be connected in series, and as a result, the circuit scale can be reduced as described above.

  It is easy to design the time A for transferring the reception value D513 to be sufficiently shorter than the times B and C. With this design, it is possible to suppress degradation of decoding due to the long time A.

  Next, reception value processing in the reception memory 417 of FIG. 18 will be described with reference to FIG. This reception value processing is started, for example, when the reception value D418 of each frame is intermittently input to the reception memory 417.

  In step S21, the pre-buffer 511 starts writing the reception value D418 that is input intermittently. In step S22, the switch 512 determines whether or not the control signal D515 is input from the input buffer 513 in the process of step S31 for the previous frame.

  If it is determined in step S22 that the control signal D515 has not been input, that is, if the reception value D512 of the previous frame has not been written to the input buffer 513, the switch 512 receives the control signal D515. Wait until On the other hand, if it is determined in step S22 that the control signal D515 has been input, that is, if writing of the received value D512 of the previous frame to the input buffer 513 is completed, in step S23, the switch 512 controls the control signal D515. The pre-buffer 511 and the input buffer 513 are connected according to D515.

  In step S24, the pre-buffer 511 starts continuous reading of the reception value D418 already written as the reception value D511 in response to the control signal D515. That is, the pre-buffer 511 writes the received value D418 and reads the received value D511. The received value D511 read from the pre-buffer 511 is supplied to the switch 512, and is supplied to the input buffer 513 as the received value D512.

  In step S25, the input buffer 513 starts writing the received value D512 supplied from the prebuffer 511 via the switch 512. In step S26, the pre-buffer 511 determines whether or not the pre-buffer 511 is empty, that is, whether or not all the reception values D418 written to the pre-buffer 511 have been read, and the pre-buffer 511 is empty. If not, wait until it is empty.

  On the other hand, if it is determined in step S26 that the prebuffer 511 is empty, in step S27, the prebuffer 511 ends writing and reading of the received value D418. In step S <b> 28, the prebuffer 511 outputs the control signal D514 to the switch 512. In step S29, the switch 512 connects the terminal 512A and the input buffer 513 according to the control signal D514 supplied from the prebuffer 511.

  In step S30, the input buffer 513 determines whether or not the received value D512 for one frame has been written, that is, whether or not the free capacity of the input buffer 513 has become zero. If it is determined in step S30 that the reception value D512 for one frame has not yet been written, the process waits until all the reception values D512 for one frame are written.

  On the other hand, if it is determined in step S30 that the received value D512 for one frame has been written, the input buffer 513 outputs the control signal D515 to the prebuffer 511 and the switch 512 in step S31. It is determined whether or not this control signal D515 has been input to the switch 512 in the process of step S22 for the frame next to the frame corresponding to the received value D512 written in the input buffer 513.

  In step S32, the input buffer 513 reads the received value D512 for one frame written as the received value D513, and starts transferring the received value D513 to the received value storage memory 514.

  In step S <b> 33, the reception value storage memory 514 starts writing the reception value D <b> 513 transferred from the input buffer 513. In step S34, the input buffer 513 determines whether or not the transfer of the reception value D513 for one frame has been completed, that is, whether or not all of the written reception values D513 have been transferred. If it is determined that the transfer of D513 is not yet completed, the process waits until the transfer is completed.

  On the other hand, if it is determined in step S34 that the transfer of the received value D513 for one frame has been completed, the input buffer 513 ends the transfer of the received value D513 in step S35. In step S36, the received value storage memory 514 finishes writing the received value D513 transferred from the input buffer 513.

  In step S <b> 37, the received value storage memory 514 reads out the written received values D513 in units of 6 words, and outputs the received values D419 to the calculator 415 as received values D419. Then, the process ends.

  Next, with reference to FIG. 21, the decoding process in the decoding device 400 of FIG. 12 will be described. This decoding process is started, for example, when the reception value D419 of each frame is read from the reception memory 417 in units of six.

In step S49, the control unit 418 selects any one of the decoding intermediate result storage RAMs 502 and 503 (FIG. 16) as a read memory, and supplies a control signal D422 ₄ indicating the selection to the switch 504. Switch 504, based on the control signal D422 _4, and select the decoded intermediate result storage RAM502 or 503, the decoding intermediate result D503 or D504 supplied from the decoding intermediate result storage RAM502 or 503 the selected six units The result is supplied to the cyclic shift circuit 414 and the calculation unit 412 as a decoding intermediate result D413.

After the processing of step S49, the process proceeds to step S50, where the cyclic shift circuit 414 cyclically shifts the six decoding intermediate results D413 (u _j ) supplied from the switch 504 of the decoding intermediate result storage memory 413 to calculate To the unit 415.

  Specifically, the cyclic intermediate circuit D414 is supplied with the decoding intermediate result D413 in units of six from the decoding intermediate result storage memory 413, and from the control unit 418, the Matrix data corresponding to the decoding intermediate result D413. Is supplied with a control signal D423. The cyclic shift circuit 414 cyclically shifts the six decoding intermediate results D413 based on the control signal D423, and supplies the result to the calculation unit 415 as a decoding intermediate result D414.

  In step S51, the calculation unit 415 performs the second calculation, and supplies the decoding intermediate result D415, which is the result of the calculation, to the switch 416.

Specifically, the decoding unit 415 is supplied with six intermediate decoding results D414 from the cyclic shift circuit 414 in step S50, and is also supplied with six reception values D419 from the reception memory 417, and the intermediate decoding result D414. The received value D419 is supplied to each of the calculators 415 _{1 to} 415 ₆ of the calculation unit 415. Further, a control signal D424 is supplied from the control unit 418 to the calculation unit 415, and the control signal D424 is supplied to the calculators 415 _{1 to} 415 ₆ .

Calculators 415 _{1 to} 415 ₆ use decoding intermediate result D414 and received value D419, respectively, to perform a second calculation according to equation (5) based on control signal D424, and the result of the second calculation The decoding intermediate result D415 (v) corresponding to the column of the check matrix H obtained is supplied to the switch 416.

When the first calculation has not yet been performed on the reception value D419 supplied from the reception memory 417, and the decoding intermediate result D412 is not stored in the decoding intermediate result storage memory 413, the calculation unit In step S415, the decoding intermediate result u _j is set to an initial value, and the second calculation is performed.

  In step S52, the control unit 418 determines whether decoding has been performed a predetermined number of times, that is, whether the first calculation and the second calculation have been performed a predetermined number of times. To do. If it is determined in step S52 that decoding has not been performed a predetermined number of times, the switch 416 stores the six decoding intermediate results D415 (v) supplied from the calculation unit 415 in step S53. Supply to the memory 410.

  In step S54, the decoding intermediate result storage memory 410 stores the six decoding intermediate results D415 (v) supplied from the switch 416 at the same address.

  In step S55, the control unit 418 determines whether all the decoding intermediate results D415 corresponding to the columns of the check matrix H have been calculated by the calculation unit 415, and determines that all the decoding intermediate results D415 have not been calculated. If so, the process returns to step S49 and the above-described processing is repeated.

  On the other hand, in step S55, when the control unit 418 determines that all the decoding intermediate results D415 corresponding to the columns of the check matrix H are calculated by the calculation unit 415, in step S56, the cyclic shift circuit 411 Based on the control signal D420 supplied from the unit 418, the six decoding intermediate results D410 (v) supplied from the decoding intermediate result storage memory 410 are cyclically shifted, and the results are decoded in units of six D411. Is supplied to the calculation unit 412.

  In step S57, the calculation unit 412 performs the first calculation, and supplies the decoding intermediate result D412 that is the result of the first calculation to the decoding intermediate result storage memory 413.

Specifically, the calculation unit 412 is supplied with six decoding intermediate results D411 (v) from the cyclic shift circuit 411 in step S56, and is also stored in the previous calculation unit 412 already stored in step S59 described later. Six decoding intermediate results D413 (u _j ) obtained as a result of the first calculation are supplied, and the decoding intermediate results D411 and D413 are supplied to each of the calculators 412 _{1 to} 412 ₆ of the calculation unit 412. Is done. Further, the calculation unit 412 is supplied with the control signal D421 from the control unit 418, and the control signal D421 is supplied to the calculators 412 _{1 to} 412 ₆ .

The calculators 412 _{1 to} 412 ₆ respectively perform first calculations according to the equations (7) and (8) based on the control signal D421 using the decoding intermediate results D411 and D413, respectively. The decoding intermediate result D412 (u _j ) obtained as a result of the above operation is supplied to the decoding intermediate result storage memory 413.

When the first calculation has not yet been performed on the reception value D419 supplied from the reception memory 417, and the decoding intermediate result D412 is not stored in the decoding intermediate result storage memory 413, the calculation unit In 412, the decoding result u _dv is set to 0. Specifically, for example, before decoding the received value D419, the decoding intermediate result storage memory 413 is initialized to 0, or the calculation unit 412 sets the input from the decoding intermediate result storage memory 413 to 0. To mask.

In step S58, the control unit 418 selects a storage memory any one of the decoding intermediate result storage RAM502 and 503, and supplies a control signal D422 ₁ representing the selection switch 501 (FIG. 16). Switch 501 based on the control signal D422 _1, six decoding intermediate results select the decoding intermediate result storage RAM502 or 503 for storing the D412, decoding intermediate result storage RAM502 or 503 the selected, decoded intermediate results D412 Is supplied as a decoding intermediate result D501 or D502.

In step S59, the decoding intermediate result storage RAM 502 or 503 stores the six decoding intermediate results D501 or D502 (u _j ) supplied from the switch 501 in step S58 at the same address.

  In step S60, the control unit 418 determines whether or not the decoding intermediate result D412 corresponding to all 1s of the check matrix H has been calculated by the calculation unit 412 and determines that all the decoding intermediate results D412 have not been calculated. If so, the process returns to step S56, and the above-described process is repeated.

  On the other hand, if it is determined in step S60 that the calculation unit 412 has calculated the intermediate decoding results D412 corresponding to all 1, the process returns to step S49 and the above-described process is repeated.

  If it is determined in step S52 that decoding has been performed a predetermined number of times, the control unit 418 outputs a control signal D425 to the switch 416 in step S61. In step S62, the switch 416 outputs the decoding intermediate result D415 obtained in the immediately preceding step S51 as the final decoding result D417.

  FIG. 22 shows a configuration example of the second embodiment of the decoding device to which the present invention is applied.

22 includes a decoding intermediate result storage memory 410, a cyclic shift circuit 411, a calculation unit 412 including six calculators 412 ₁ to 412 ₆ , a decoding intermediate result storage memory 413, a cyclic shift. The circuit 414 includes a calculator 415 including _six calculators 415 ₁ to 415 ₆ , a switch 416, a reception memory 611, and a control unit 612. The control unit 612 is supplied from the reception memory 611. A control signal D425 is supplied to the switch 416 in response to a decoding end request signal D601 requesting the end of decoding. In addition, the same code | symbol is attached | subjected to the same thing as FIG. 12, and since description is repeated, it abbreviate | omits.

  Similarly to the reception memory 417 of FIG. 12, the reception value 418 is input to the reception memory 611, and the reception memory 611 stores the reception value D418. Then, the reception memory 611 reads out the reception values D418 that are already stored in the order required for variable node calculation, and supplies them to the calculation unit 415 as reception values D419. Further, the reception memory 611 supplies the decoding end request signal D601 to the control unit 612 when the reception value D418 of the next frame to be decoded is ready to be read. Details of the reception memory 611 will be described with reference to FIG.

  The control unit 612 controls each unit so that decoding is repeatedly performed until the decoding end request signal D601 is supplied from the reception memory 611. Specifically, the control unit 612 controls the control signal D420 by supplying the control signal D420 to the cyclic shift circuit 411 and the control signal D421 to the calculation unit 412, respectively. Further, the control unit 612 controls the control signal D422 by supplying the control signal D422 to the decoding intermediate result storage memory 413, the control signal D423 to the cyclic shift circuit 414, and the control signal D424 to the calculation unit 415, respectively. Furthermore, the control unit 612 supplies the control signal D425 to the switch 416 in response to the decoding end request signal D601, thereby repeatedly performing the last operation until the decoding end request signal D601 is supplied. The switch 416 is controlled so that the decoding intermediate result D415 obtained as a result of the above is output as the decoding result D417.

  FIG. 23 shows a detailed configuration example of the reception memory 611 of FIG.

  The reception memory 611 in FIG. 23 includes a pre-buffer 511, a switch 512, a reception value storage memory 514, and an input buffer 621. In FIG. 23, the same components as those in FIG. 18 are denoted by the same reference numerals, and the description thereof will be omitted to avoid repetition.

  The storage capacity of the input buffer 621 is, for example, a multiplication value of the code length and the number of quantization bits, as in the input buffer 513 in FIG. 18. The input buffer 621 temporarily stores the received value D512 input by the switch 512. One frame is stored. Note that the bit width of the input buffer 621 is 1 / N times the bit width of the received value storage memory 514, and the number of words is N times that of the received value storage memory 514, similar to the input buffer 513. And

  When the input buffer 621 has completed the writing of the reception value D512 for one frame, the input buffer 621 controls the decoding end request signal D601 of the frame immediately before that frame in order to set the frame corresponding to the reception value D512 as the decoding target. Supplied to the unit 612. Thereafter, when a predetermined time has elapsed, the input buffer 621 determines that the decoding of the frame preceding the frame that has just been written has been completed, inputs the control signal D515 to the prebuffer 511 and the switch 512, and stores it. The received value D512 for one frame is read as the received value D513 and transferred to the received value storage memory 514. As a result, the frame to be decoded is changed.

  Next, timing in the reception memory 611 in FIG. 23 will be described with reference to FIG.

  Note that FIGS. 24A to 24E are the same as FIGS. 19A to 19E, and a description thereof will be omitted as appropriate.

As shown in FIG. 24A, at time t _A , intermittent input of the received value D418 of frame #i to the receiving memory 611 is started, that is, writing of the frame # i−1 to the input buffer 621 is started. When completed, as shown in FIG. 24H, the input buffer 621 supplies the decoding end request signal D601 of the frame # i-2 before the frame # i-1 to the control unit 612, and the input as shown in FIG. 24F. The buffer 621 waits until a predetermined time D elapses.

Then, at time t _H when the predetermined time D has elapsed, as shown in FIG. 24F, the input buffer 621 reads the received value D512 of frame # i−1 for which writing has been completed, and receives the received value D512. To the received value storage memory 514 (R _{i-1 in} the figure), and as shown in FIG. 24G, the received value storage memory 514 stores the received value of frame # i−1. D512 is supplied as the received value D513. Then, as shown in FIG. 24I, the received value storage memory 514 starts writing the received value D513 of the frame # i−1 supplied from the input buffer 621 (W _{i−1 in the} figure).

Incidentally, from the time t _B after the time A from the time t _A, the process between the time B and C up to time t _D is the same as the case shown in FIG. 19A through FIG. 19H, description will be omitted.

Next, as shown in FIG. 24A, at time t _D, for receiving memory 611, the intermittent input received value D418 frame # i + 1 is started, from the time t _A to time t _D Time A Processing is performed in the same manner as in C.

That is, at time t _D , as shown in FIG. 24H, the input buffer 621 uses the control unit to transmit the decoding end request signal D601 of frame # i−1 before frame #i written from time t _B to time t _D. The input buffer 621 waits until a predetermined time D elapses, as shown in FIG. 24F.

Then, at time t _J when the predetermined time D has elapsed, the input buffer 621 reads the received value D512 of frame #i written between time t _B and time t _D and receives the received value D 512. The transfer to the value storage memory 514 is started (R _{i in} the figure). As shown in FIG. 24I, the reception value storage memory 514 receives the received value D513 of the frame #i supplied from the input buffer 621. Start writing (W _{i in the} figure). Note that the decoding of frame # i-1 is ended after the decoding end request signal D601 is output, as shown in FIG. 24I. In the example of FIG. 24, the decoding is completed at time t _J when a predetermined time D has elapsed after the decoding end request signal D601 is output.

  As described above, since the reception value D418 is intermittently supplied, the invalid time of the reception value D418 of each frame received between the times A and B continuously read from the prebuffer 511 is used. If it is within the invalid time, the decoding end request signal D601 is output and a predetermined time is awaited, and then the received value D513 can be transferred from the input buffer 621 to the received value storage memory 514.

  In addition, the reception memory 611 supplies the decoding end request signal D601 to the control unit 612, and the control unit 612 controls each unit to repeatedly perform decoding until the decoding end request signal D601 is supplied. Decoding can be performed as many times as possible. As a result, the decoding performance can be further improved as compared with the case where the decoding is repeatedly performed a predetermined number of times. Further, it is possible to save the trouble of setting the number of times of decoding in advance.

  Next, received value processing in the reception memory 611 in FIG. 23 will be described with reference to FIG. This reception value processing is started, for example, when the reception value D418 of each frame is intermittently input to the reception memory 611.

  The processing in steps S111 to S121 is the same as the processing in steps S21 to S31 in FIG.

  In step S122, the input buffer 621 outputs the decoding end request signal D601 to the control unit 612. In step S123, the input buffer 621 determines whether or not a predetermined time has elapsed since the decoding end request signal D601 was output in step S122. If it is determined that the predetermined time has not elapsed, Wait until time has passed.

  In step S123, when it is determined that a predetermined time has elapsed since the decoding end request signal D601 was output in step S122, the input buffer 621 in step S124 is similar to the process in step S32 of FIG. The written reception value D512 for one frame is read as the reception value D513, and transfer of the reception value D513 to the reception value storage memory 514 is started.

  The processing in steps S124 to S129 is the same as the processing in steps S32 to S37 in FIG.

  Next, with reference to FIG. 26, the decoding process in the decoding device 600 of FIG. 22 will be described. This decoding process is started, for example, when the reception value D419 of each frame is read in units of six from the reception memory 611.

  The processing in steps S149 through S151 is the same as the processing in steps S49 through S51 in FIG.

  In step S152, the control unit 612 determines whether or not the decoding end request signal is supplied from the input buffer 621 of the reception memory 611. If it is determined that the decoding end request signal is not supplied, in step S153, the switch Step 416 supplies the six decoding intermediate results D415 (v) supplied from the calculation unit 415 to the decoding intermediate result storage memory 410 as in the process of step S53 of FIG. The processing in steps S154 to S160 is the same as the processing in steps S54 to S60 in FIG.

  On the other hand, when it is determined in step S152 that the decoding end request signal has been supplied from the input buffer 621, in step S161, the control unit 612 outputs the control signal D425 as in the process of step S61 in FIG. In step S162, the switch 416 outputs the decoding intermediate result D415 obtained in the immediately preceding step S51 as the final decoding result D417, similarly to the processing in step S62 of FIG.

  Note that in the decoding device 400 in FIG. 12 and the decoding device 600 in FIG. 22, decoding is performed by repeatedly performing the first calculation and the second calculation, but decoding is performed by repeatedly performing the check node calculation and the variable node calculation. It is also possible to perform.

  Further, in the above case, for the sake of simplicity of explanation, the case where P is 6, that is, the case where the number of rows and the number of columns of the constituent matrix constituting the parity check matrix H is given as an example, The number of rows and the number of columns P of the matrix do not necessarily have to be 6, and may take different values depending on the check matrix H. For example, P may be 360 or 392.

  For example, when P is 360, when an LDPC code having a quantization length of 5 bits and a code length of 64800 conforming to the DVB-S2 standard is decoded, the reception memory 417 in FIG. In the reception memory 611, the bit width of the reception value storage memory 514 is 1800 (= 360 × 5) bits, and the number of words is 180 (= 64800/360) words. That is, the received value storage memory 514 is a multi-bit small word memory having a bit width to word number ratio of 10: 1. Here, if N is 10, for example, the bit width of the input buffers 513 and 621 is 180 (= 1800/10) bits, and the number of words is 1800 (= 180 × 10) words. That is, the input buffer 513 is a small-bit multi-word memory having a bit width to word ratio of 1:10.

  On the other hand, in the conventional reception memory 200 of FIG. 11, as described above, the bit widths of both the reception value storage memories 212 and 213 are 1800 (= 360 × 5) bits, and the number of words is 180. (= 5 × 1800/360) words. That is, both the received value storage memories 212 and 213 are multi-bit small word memories having a bit width to word number ratio of 10: 1.

  As described above, in the reception memory 417 in FIG. 18 and the reception memory 611 in FIG. 23, if the reception value storage memory 514 for multi-bit small words and the input buffer 513 for small bits and multi-words are provided one by one. Therefore, the number of macros constituting the reception memory 417 (611) is reduced as compared with the reception memory 200 in which both the reception values storage memories 212 and 213 for multi-bit small words shown in FIG. can do. As a result, the circuit scale of the reception memory 417 (611) can be reduced.

  Further, the reception memory 417 in FIG. 18 and the reception memory 611 in FIG. 23 can also be applied to a decoding device in a case where decoding is performed by simultaneously performing operations on all nodes (full parallel decoding).

  An implementation method of this decoding apparatus is described in, for example, C. Howland and A. Blanksby, “Parallel Decoding Architectures for Low Density Parity Check Codes”, Symposium on Circuits and Systems, 2001.

  FIG. 27 shows a configuration example of a third embodiment of a decoding device to which the present invention is applied that performs computations on all nodes simultaneously.

  In this case as well, it is assumed that the code (coding rate 2/3, code length 108) represented by parity check matrix H in FIG. 13 is decoded.

  In the decoding device 1100 of FIG. 27, all message data corresponding to 323 branches are simultaneously read from the branch memory 1202 or 1206, and new message data corresponding to 323 branches are calculated using the message data. To do. Further, all new message data obtained as a result of the calculation are simultaneously stored in the branch memory 1206 or 1202 at the subsequent stage. Then, iterative decoding is realized by repeatedly using the decoding device 1100 of FIG.

In FIG. 27, the decoding device 1100 includes one reception memory 1205, two branch switching devices 1200 and 1203, two branch memories 1202 and 1206, ₃₆ check node calculators 1201 _{1 to} 1201 ₃₆ , and 108 pieces. It consists of variable node calculators 1204 _{1 to} 1204 ₁₀₈ . Hereinafter, each part will be described in detail.

Branch memory 1206 stores all the messages D1206 ₁ D1206 ₁₀₈ from the preceding variable node calculator 1204 ₁ to 1204 ₁₀₈ At the same time, the next time (the timing of the next clock), a message D1206 ₁ D1206 ₁₀₈ The messages are read as messages D1207 _{1 to} D1207 _{108 and} supplied as messages D1200 (D1200 _{1 to} D1200 ₁₀₈ ) to the branch switching device 1200 at the next stage. Branch swapping device 1200, the order of the supplied message D1200 ₁ D1200 ₁₀₈ from the branch memory 1206, reordering according to the check matrix H of FIG. 13, the check node calculator 1201 ₁ to 1201 _36, message D1201 ₁ Supplied as D1201 ₃₆ .

Check node calculator 1201 ₁ to 1201 _36, branch replacement by using the messages D1201 ₁ D1201 ₃₆ supplied from the apparatus 1200 performs arithmetic according to equation (7), the message D1202 ₁ D1202 ₃₆ obtained as a result of the calculation Is supplied to the branch memory 1202.

The branch memory 1202 stores all the messages D1202 _{1 to} D1202 ₃₆ supplied from the previous check node calculators 1201 _{1 to} 1201 ₃₆ at the same time, and at the next time, all the messages D1202 _{1 to} D1202 ₃₆ are D1203 _{1 to} D1203 ₃₆ are supplied to the next-stage branch replacement device 1203.

Branch swapping device 1203, reordering according to the check matrix H of FIG. 13 the order of the supplied message D1203 ₁ D1203 ₃₆ from the branch memory 1202, a variable node calculator 1204 ₁ to 1204 _108, messages D1204 ₁ D1204 Supply as ₁₀₈ .

The variable node calculators 1204 _{1 to} 1204 ₁₀₈ use the messages D1204 _{1 to} D1204 ₁₀₈ supplied from the branch switching device 1203 and the received values D1205 _{1 to} D1205 ₁₀₈ supplied from the reception memory 1205 to formula (1). Therefore, an operation is performed, and messages D1206 _{1 to} D1206 ₁₀₈ obtained as a result of the operation are supplied to the branch memory 1206 at the next stage.

  The reception memory 1205 is configured in the same manner as the reception memory 417 in FIG. 18 or the reception memory 611 in FIG. That is, although not shown, the reception memory 1205 includes a pre-buffer, a switch, an input buffer, and a reception value storage memory. The bit width of the reception value storage memory is 108, which is the number of variable nodes. This is a multiplication value of the number of quantization bits, and the bit width of the input buffer is 1 / N times the multiplication value.

The reception memory 1205 is input with received values D1205 _{1 to} D1205 _{108 that} are reception LLRs indicating the likelihood of 0 of the code bits calculated from the LDPC code received through the communication path. Receiving memory 1205 stores the received value 1205 ₁ to D1205 _108. Then, the reception memory 1205 simultaneously reads all the ₁₀₈ reception values D1205 _{1 to} D1205 ₁₀₈ already stored, and supplies them to the variable node calculators 1204 _{1 to} 1204 ₁₀₈ as reception values D1205 _{1 to} D1205 ₁₀₈ . When reception memory 1205 is configured in the same manner as reception memory 611 in FIG. 23, a decoding end request signal is output to a control unit (not shown) that controls each unit.

FIG. 28 shows a configuration example of the check node calculator 1201 _m (m = 1, 2,..., 36) of FIG.

In the check node calculator 1201 _{m of} FIG. 28, the check node calculation of Expression (7) is performed in the same manner as the check node calculator 101 of FIG. 9, and the check node calculation is simultaneously performed for all branches. .

That is, in the check node calculator 1201 _{m of} FIG. 28, all the messages D12221 _{1 to} D1221 ₉ (v _i ) from the variable nodes corresponding to the columns of the check matrix H of FIG. The absolute values D1222 to D1222 ₉ (| v _i |), which are the lower 5 bits of each, are supplied to the LUTs 1221 _{1 to} 1221 ₉ respectively. The message D1221 ₁ D1221 ₉ (v _i) of the 1-bit is the most significant bit sign bit D1223 ₁ D1223 ₉ is, while being supplied to the EXOR circuit 1226 ₁ to 1226 _9, is supplied to the EXOR circuit 1225 The

The LUTs 1221 _{1 to} 1221 ₉ are 5-bit calculation results D1224 _{1 to} D1224 ₉ obtained by performing the calculation of φ (| v _i |) in Expression (7) on the absolute values D1222 to D1222 ₉ (| v _i |). _{(φ (| v i |)} ) read respectively, and supplies each to a subtractor 1223 ₁ to 1223 _9. Further, LUT1221 ₁ to 1221 _9, the operation result D1224 ₁ to D1224 ₉ supplied to the adder 1222 a _{(φ (|) | v i} ).

The adder 1222 calculates the sum of the values of the calculation results D1224 _{1 to} D1224 ₉ (φ (| v _i |)) (sum of the calculation results for one row), and calculates the 9-bit calculation result D1225 (from i = 1) 9 Σφ (| v _i |)) is supplied to the subtracters 1223 _{1 to} 1223 ₉ . The subtracters 1223 _{1 to} 1223 ₉ subtract the calculation results D1224 _{1 to} D1224 ₉ (φ (| v _i |)) from the calculation result D1225, respectively, and subtract the 5-bit subtraction values D1227 _{1 to} D1227 ₉ to the LUT 1224 _{1 to} 1224 is supplied to the _9. That is, the subtracters 1223 _{1 to} 1223 ₉ obtain φ (|) obtained from the message v _i from the branch to be obtained from the integrated value of φ (| v _i |) obtained from the message v _i from all the branches. v _i |) is subtracted, the subtraction value D1227 ₁ D1227 ₉ (from i = 1 to 8 Σφ (| v _i |) respectively supply) LUT1224 to ₁ to 1224 _9. LUT1224 ₁ to 1224 _9, to the subtraction value D1227 ₁ to ^{_{D1227 9, φ -1 (Σφ (}} | v i |)) in Equation (7) computes the 5-bit operation result D1228 ₁ to Been of D1228 ₉ Is read and output.

On the other hand, EXOR circuit 1225, by calculating all the exclusive OR of the sign bit D1223 ₁ to D1223 _9, multiplies the sign bits D1223 ₁ to D1223 _9, 1 bit multiplier D1226 (for one row It supplies each multiplication value of the sign bit of the (Paisign of i = 1 to 9 (v _i))) to the EXOR circuit 1226 ₁ to 1226 _9. EXOR circuits 1226 ₁ to 1226 _9, by calculating an exclusive OR of the multiplication value D1226 and the sign bit D1223 ₁ D1223 ₉ respectively, 1-bit multiplication value D1226, divided by the sign bit D1223 ₁ D1223 ₉ respectively The division values D1229 _{1 to} D1229 ₉ (i sign (v _i ) from 1 to 8) are obtained and output.

In the check node calculator 1201 _m , the 5-bit calculation results D1228 _{1 to} D1228 ₉ output from the LUTs 1224 _{1 to} 1224 ₉ are set to the lower 5 bits, and the division value D1229 output from the EXOR circuits 1226 _{1 to} 1226 _{9 1} to D1229 ₉ total 6 bits of the most significant bit, respectively, is output as a message D1230 ₁ D1230 ₉ obtained as a result of the check node operation.

As described above, in the check node calculator 1201 _m , the calculation of Expression (7) is performed and the message u _j is obtained.

In FIG. 28, the check node calculator 1201 _m is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. The circuit in FIG. 28 corresponds to one check node. Since the check matrix H in FIG. 13 to be processed here has 36 check nodes, which is the number of the check matrix H, the decoding device 1100 in FIG. 27 uses the check node calculator as shown in FIG. There are 36 1201 _m .

In addition, the check node calculator 1201 _m in FIG. 28 can simultaneously calculate nine messages. The weights of the check matrix H in FIG. 13 to be processed here are 8 for the first row and 9 for the second to 36th rows, that is, the message supplied to the check node. Since there are one case of 8 and 29 cases of 9, the check node calculator 12011 ₁ has a circuit configuration that can simultaneously calculate eight messages similar to the circuit of FIG. The remaining check node calculators 1201 _{2 to} 1201 ₃₆ have the same configuration as the circuit of FIG.

FIG. 29 shows a configuration example of the variable node calculator 1204 _p (p = 1, 2,..., 108) of FIG.

In the variable node calculator 1204 _{p of} FIG. 29, the variable node calculation of Expression (1) is performed in the same manner as the variable node calculator 103 of FIG. 10, but the variable node calculation is simultaneously performed for all branches. .

That is, in the variable node calculator 1204 _{p of} FIG. 29, all of the 6-bit messages D1251 _{1 to} D1251 ₅ (message u _j ) supplied from the branch replacement device 1203 from the check nodes corresponding to each row of the check matrix H read simultaneously, it is supplied to the subtracter 1252 ₁ to 1252 ₅ respectively, are supplied to the adder 1251. Further, the variable node calculator 1204 _p, the reception value D1271 supplied from the receiving memory 1205, the received value D1271 is supplied to the subtracter 1252 ₁ to 1252 _5.

The adder 1251 accumulates all the messages D1251 _{1 to} D1251 ₅ (message u _j ), and adds a 9-bit accumulated value D1252 (total value of messages for one column (Σu _j from 1 to 5)). This is supplied to the adders / subtracters 1252 _{1 to} 1252 ₅ . The adders / subtracters 1252 _{1 to} 1252 ₅ subtract the messages D12511 _{1 to} D1251 ₅ (message u _j ) from the integrated value D1252, respectively. That is, the adders / subtracters 1252 _{1 to} 1252 ₅ subtract the messages D1251 _{1 to} D1251 ₅ (message u _j ) from the branches to be obtained from the integrated values D1252 of the messages u _j from all branches, respectively, and the subtracted values. (Σu _j from j = 1 to 4) is obtained.

Further, the adder / subtracters 1252 _{1 to} 1252 ₅ add the received value D1271 (u _0i ) to the subtraction value (Σu _j from j = 1 to 4), and the 6-bit addition values D1253 _{1 to} D1253 ₅ are obtained. Output as a result of variable node operation.

As described above, the variable node calculator 1204 _p performs the calculation of Expression (1) to obtain the message v _i .

In FIG. 29, the variable node calculator 1204 _p is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. The circuit in FIG. 29 corresponds to one variable node. Since there are 108 variable nodes as the number of columns for the check matrix H in FIG. 13 to be processed here, the decoding apparatus 1100 in FIG. 27 has 108 circuits as shown in FIG. Have.

In addition, the variable node calculator 1204 _p in FIG. 29 can simultaneously calculate five messages. In the parity check matrix H of FIG. 13 to be processed here, there are 18 columns, 54 columns, 35 columns, and 1 column of weights 5, 3, 2, and 1, respectively. 18 of 1204 _{1 to} 1204 _{108 have} the same configuration as the circuit of FIG. 29, and the remaining 54, 35, and 1 are 3, 2, and 1 messages similar to the circuit of FIG. It is a circuit configuration that can calculate each of them simultaneously.

  Although not shown, in the decoding device 1100 of FIG. 27, as in the case of FIG. 8, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1). The operation result is output as the final decoding result.

  According to the decoding device 1100 of FIG. 27, all messages corresponding to 323 branches can be calculated simultaneously in one clock.

  In the case of decoding by repeatedly using the decoding device 1100 of FIG. 27, check node calculation and variable node calculation can be alternately performed, and one decoding can be performed in two clocks. Therefore, for example, in order to perform decoding 50 times, it is only necessary to operate 2 × 50 = 100 clocks while receiving a code word for one frame composed of 108 codes having a code length as a reception value. In other words, the operating frequency that is substantially the same as the reception frequency is sufficient. In general, since the LDPC code has a code length as large as several thousand to several tens of thousands, if the decoding apparatus 1100 in FIG. 27 is used, the number of decoding can be extremely increased, and improvement in error correction performance is expected. Can do.

  However, since the decoding apparatus 1100 of FIG. 27 performs computation of messages corresponding to all branches of the Tanner graph in parallel, the circuit scale increases in proportion to the code length. In addition, when the decoding apparatus 1100 in FIG. 27 is configured as an apparatus that decodes an LDPC code having a certain code length, a certain coding rate, and a certain parity check matrix H, the decoding apparatus 1100 may have other code lengths or It becomes difficult to decode LDPC codes having other coding rates and other check matrices H.

  In this embodiment, an LDPC code having a code length of 108 and an encoding rate of 2/3 is used, but the LDPC code may have any value for the code length and the encoding rate.

  If the parity check matrix H is not a multiple of the number of rows and the number of columns P of the constituent matrix, apply all the components of 0 (all 0) outside the fraction of the parity check matrix H as a multiple of P. May be possible.

  In general, since the LDPC code has a code length as large as several thousand to several tens of thousands, a code having a P value of several hundreds is used. In that case, the effect of using the decoding device according to the present invention is further increased.

  Note that the decoding device that decodes the LDPC code described above can be applied to, for example, a tuner that receives a (digital) satellite broadcast.

It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure explaining the flow of a message. It is a figure which shows the example of the check matrix H of a LDPC code. 6 is a diagram illustrating a Tanner graph of a check matrix H. FIG. It is a figure which shows a variable node. It is a figure which shows a check node. It is a figure which shows the example of the check matrix H of a LDPC code. It is a block diagram which shows an example of a structure of the decoding apparatus of the LDPC code which performs node calculation one by one. It is a block diagram which shows the detailed structural example of the check node calculator of FIG. It is a block diagram which shows the detailed structural example of the variable node calculator of FIG. It is a block diagram which shows an example of a structure of the memory for reception provided with two memories. It is a block diagram which shows the structural example of 1st Embodiment of the decoding apparatus to which this invention is applied. It is a figure which shows the example of the test matrix H divided | segmented into 6x6 units. It is a block diagram which shows the detailed structural example of the calculator of FIG. It is a block diagram which shows the detailed structural example of the calculator of FIG. It is a block diagram which shows the structural example of the memory for decoding result storage of FIG. 13 is a timing chart for explaining the operation of the decoding intermediate result storage RAM of FIG. 12; 13 illustrates a detailed configuration example of the reception memory in FIG. 12. FIG. 19 is a timing chart illustrating timings in the reception memory of FIG. 18. FIG. FIG. 19 is a flowchart for describing reception value processing in the reception memory of FIG. 18. FIG. Fig. 13 is a flowchart for describing decoding processing in the decoding device of Fig. 12. It is a block diagram which shows the structural example of 2nd Embodiment of the decoding apparatus to which this invention is applied. It is a block diagram which shows the detailed structural example of the memory for reception of FIG. 24 is a timing chart for describing timing in the reception memory of FIG. It is a flowchart explaining the received value process in the memory for reception of FIG. It is a flowchart explaining the decoding process in the decoding apparatus of FIG. It is a block diagram which shows the structural example of 3rd Embodiment of the decoding apparatus to which this invention is applied. It is a block diagram which shows the structural example of the check node calculator of FIG. It is a block diagram which shows the structural example of the variable node calculator of FIG.

Explanation of symbols

  400 decoding device, 412, 415 calculation unit, 417 reception memory, 511 pre-buffer, 513 input buffer, 514 received value storage memory, 600 decoding device, 611 reception memory, 621 input buffer, 1100 decoding device, 1205 reception Memory, 1201 check node calculator, 1204 variable node calculator

Claims (8)

A decoding device for decoding LDPC (Low Density Parity Check) code,
First storage means for temporarily storing the received value of the LDPC code input intermittently;
A second value that temporarily stores the reception value continuously read from the first storage means or the reception value of the LDPC code that is intermittently input, and that continuously reads the stored reception value; Storage means,
Storing a reception value continuously read out by the second storage unit, and reading out the stored reception value for each predetermined unit;
Decoding means for decoding the received value read for each predetermined unit by the third storage means for each predetermined unit;
The bit width of the second storage means is smaller than the bit width of the third storage means. The transfer time when the received value is read from the second storage means and the received value is stored in the third storage means is a time when there is no value in the received value of the code word unit of the LDPC code. The decoding device according to claim 1, which is within a certain invalid time. The decoding device according to claim 2, wherein the second storage unit reads the received value in units of the codeword. The decoding device according to claim 3, wherein the first storage means temporarily stores the reception value of the LDPC code input intermittently at the transfer time. The second storage means supplies the decoding means with a decoding end request signal for requesting the end of decoding of the reception value that is the previous reading target before reading the reception value in units of codewords, and then After a predetermined time elapses, the received value is read in the codeword unit,
In response to the decoding end request signal, the decoding means ends decoding of the received value that is the previous reading target,
The decoding device according to claim 3, wherein a sum of the predetermined time and the transfer time is within the invalid time. The decoding device according to claim 5, wherein the first storage means temporarily stores the reception value of the intermittently input LDPC code at the transfer time and the predetermined time. First storage means for temporarily storing received values of LDPC codes input intermittently; received values read continuously from the first storage means; or LDPC codes input intermittently A second storage means for temporarily storing the received value, a third storage means for storing the received value continuously read by the second storage means, and a predetermined unit by the third storage means A decoding means for decoding the LDPC code, comprising: a decoding means for decoding the received value read for each predetermined unit;
The first storage means temporarily stores a reception value of the LDPC code input intermittently;
The second storage means having a bit width smaller than that of the third storage means temporarily receives the reception value read continuously from the first storage means or the reception value of the LDPC code input intermittently. Memorize,
The second storage means continuously reads out the received value stored therein,
The third storage means stores received values continuously read out by the second storage means;
The third storage means reads the stored received value for each predetermined unit,
A decoding method, comprising: a step in which the decoding means decodes the received value read out for each predetermined unit by the third storage means for each predetermined unit. A decoding device for decoding LDPC (Low Density Parity Check) code,
First storage means for temporarily storing the received value of the LDPC code input intermittently;
A second value that temporarily stores the reception value continuously read from the first storage means or the reception value of the LDPC code that is intermittently input, and that continuously reads the stored reception value; Storage means,
Storing a reception value continuously read out by the second storage unit, and reading out the stored reception value for each predetermined unit;
Decoding means for decoding the received value read for each predetermined unit by the third storage means for each predetermined unit;
The second storage means and the third storage means are connected in series ,
A decoding device in which the bit width of the second storage means is smaller than the bit width of the third storage means .

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