JP2007036776A - Decoding apparatus and decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the throughput of a decoding apparatus. <P>SOLUTION: A receiving part 811 simultaneously stores two receiving data D416 in each operation and simultaneously supplies six already stored receiving data D811 to a calculation part 415 in each operation. The calculation part 415 executes second operation, by using the receiving data D811 and a decoding halfway result D414, obtained as a result of first operation and a calculation part 412 executes the first operation by using a decoding halfway result D411, obtained as a result of the second operation and a decoding halfway result D413, obtained as a result of the preceding first operation. A decoding halfway result D415, obtained as a result of the final second operation is supplied to an output part 812, which stores the decoding halfway result D415. The output part 812 simultaneously reads out two already stored halfway results D415 as decoded results in each operation and outputs the read decoded results. This invention can be applied to tuners that receive satellite broadcasting, for instance. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a decoding device and a decoding method, and more particularly, to a decoding device and a decoding method for decoding a code that has been encoded by a low density parity check code (LDPC code).

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, encoding methods that exhibit performance close to the Shannon limit include, for example, so-called turbo codes such as parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC). A technique called Turbo coding has been developed. While these turbo codes are being developed, low density parity check codes (hereinafter referred to as LDPC codes), which is an encoding method that has been known for a long time, are attracting attention.

  The LDPC code was first proposed in "RG Gallager," Low Density Parity Check Codes ", Cambridge, Massachusetts: MIT Press, 1963 by RG Gallager, and then" DJC MacKay, "Good error correcting codes based on very sparse matrices ", IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999" and "MG Luby, M. Mitzenmacher, MA Shokrollahi and DA Spielman," Analysis of low density codes and improved designs using irregular graphs ", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998".

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

  The LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse. Here, the sparse matrix is configured so that the number of “1” of the matrix components is very small. If the sparse check matrix is represented by H, such a check matrix H is as follows: For example, as shown in FIG. 1, the hamming weight (number of “1” s) (weight) of each column is “3”, and the hamming weight of each row is “6”.

  Thus, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is not constant is referred to as an irregular LDPC code.

Such encoding into an LDPC code is realized by generating a generator matrix G based on the parity check matrix H and generating a codeword by multiplying the binary information message by the generator matrix G. The Specifically, the encoding device which performs encoding by LDPC codes, first, between the transposed matrix H ^T of the parity check matrix H, calculates a generator matrix G which formula GH ^T = 0 is established. Here, when the generation matrix G is a k × n matrix (a matrix of k rows and n columns), the check matrix H is a matrix of nk rows and n columns.

  For example, when an n-bit codeword c is a systematic code that matches a bit string in which nk-bit parity bits are arranged following the k-bit information message u, in a check matrix H of nk rows and n columns The portion of nk rows and k columns corresponding to the k-bit information message u in the n-bit code word c is referred to as the information portion, and the portion of the nk rows and nk columns corresponding to the nk bit parity bits is referred to as the parity portion. Then, if the parity part is a lower triangular matrix or an upper triangular matrix, encoding of the information message u into an LDPC code can be performed using the check matrix H.

  That is, for example, as shown in FIG. 2, if the parity check matrix H is composed of an information part and a parity part of a lower triangular matrix, and the elements of the lower triangular part of the parity part are all 1, The first bit of the parity bit of the word c calculates the EXOR (exclusive OR) of the bit corresponding to the element which is 1 in the first row of the information part of the check matrix H of the information message u It becomes the value.

  The second bit of the parity bit of the code word c is the bit corresponding to the element that is 1 in the second row of the information part of the check matrix H of the information message u and the first of the parity bits. This is the value obtained by calculating the EXOR of the bits.

  Further, the third bit of the parity bit of the codeword c is the bit corresponding to the element that is 1 in the third row of the information part of the check matrix H of the information message u and the first of the parity bits. And the value obtained by calculating EXOR of the second bit.

  In the same manner, the i-th bit of the parity bit of the codeword c is the same as the bit corresponding to the element corresponding to the element that is 1 in the i-th row of the information part of the parity check matrix H of the information message u, and the parity. This is a value obtained by calculating the EXOR of the 1st to i-1th bits.

  As described above, n-k parity bits are obtained and arranged after the k-bit information message u, whereby an n-bit code word c can be obtained.

  On the other hand, decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which is a variable node (also called a message node) and a check node (check node). ) And a message passing algorithm based on belief propagation on a so-called Tanner graph. Here, hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

  However, in probabilistic decoding, since the message passed between each node is a real value, in order to solve it analytically, it is necessary to track the probability distribution itself of messages that take consecutive values. It will require analysis with difficulty. Therefore, Gallager has proposed algorithm A or algorithm B as a decoding algorithm for LDPC codes.

The decoding of the LDPC code is generally performed according to a procedure as shown in FIG. Here, the received value is U ₀ , the message output from the check node is u _j, and the message output from the variable node is v _i . Further, here, the message is a real value expressing the value of “0” as a so-called log likelihood ratio. Further, the log likelihood ratio of “0” likelihood of the received value U ₀ is represented as received data u _0i .

First, in decoding of an LDPC code, as shown in FIG. 3, in step S11, a received value U ₀ (received data u _0i ) is received, a message u _j is initialized to “0”, and an iterative process is performed. The variable k, which takes an integer as a counter, is initialized to “0”, and the process proceeds to step S12. In step S12, based on the received value U ₀ (received data u _0i ), the message v _i is obtained by performing the calculation shown in the equation (1). Further, based on this message v _i , the equation (2) The message u _j is obtained by performing the calculation shown in FIG.

・・・（１）

... (1)

・・・（２）

... (2)

Here, d _v and d _c in equations (1) and (2) are arbitrarily selected to indicate the number of “1” s in the vertical direction (row direction) and horizontal direction (column direction) of the parity check matrix H, respectively. For example, in the case of a (3, 6) code, d _v = 3 and d _c = 6.

Note that in the calculation of the expression (1) or (2), the message input from the edge to which the message is to be output is not used as a parameter for the sum or product operation. The range of operation is 1 to d _v -1 or 1 to d _c -1. In addition, the calculation shown in equation (2) actually creates a table of function R (v ₁ , v ₂ ) shown in equation (3) defined by one output for two inputs v ₁ and v ₂ in advance. This is done by using it continuously (recursively) as shown in equation (4).

・・・（３）

... (3)

・・・（４）

... (4)

  In step S12, the variable k is further incremented by “1”, and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is equal to or greater than a predetermined iterative decoding count N. If it is determined in step S13 that the variable k is not equal to or greater than N, the process returns to step S12, and the same processing is repeated thereafter.

  If it is determined in step S13 that the variable k is greater than or equal to N, the process proceeds to step S14, and the message v as the decoding result that is finally output is obtained by performing the calculation shown in equation (5). The LDPC code decoding process ends.

・・・（５）

... (5)

  Here, unlike the operation of equation (1), the operation of equation (5) is performed using input messages from all branches connected to the variable node.

For example, in the case of a (3, 6) code, such an LDPC code is decoded as shown in FIG. In FIG. 4, the node indicated by “=” (variable node) performs the calculation shown in Expression (1), and the node indicated by “+” (check node) performs the calculation shown in Expression (2). Done. In particular, in algorithm A, the message is binarized, and the exclusive OR operation of d _c −1 input messages is performed at the node indicated by “+”, and the received value is obtained at the node indicated by “=”. For R, if d _v −1 input messages all have different bit values, the sign is inverted and output.

  On the other hand, in recent years, research on an implementation method for decoding an LDPC code is also being conducted. Before describing the mounting method, first, decoding of an LDPC code will be schematically described.

  FIG. 5 is an example of a parity check matrix (3, 6) LDPC code (coding rate 1/2, code length 12). The parity check matrix H of the LDPC code can be written using a Tanner graph as shown in FIG. Here, in FIG. 6, “+” represents a check node, and “=” represents a variable node. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between the check node and the variable node is an edge and corresponds to “1” of the parity check matrix H. That is, when the component in the j-th row and the i-th column of the check matrix H is 1, in FIG. 6, the i-th variable node from the top ("=" node) and the j-th check node from the top ( Are connected by a branch. The branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node. 6 is a Tanner graph of the parity check matrix H in FIG.

  The Sum Product Algorithm, which is an LDPC code decoding method, repeatedly performs a variable node operation and a check node operation.

In the variable node, the calculation of Expression (1) is performed as shown in FIG. That is, in FIG. 7, the message v _i corresponding to the branch to be calculated is calculated using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the received data u _0i . Messages corresponding to other branches are similarly calculated.

  Before explaining the operation of the check node, the expression (2) is changed to the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b). And rewrite as equation (6). However, sign (x) is 1 when x ≧ 0, and −1 when x <0.

・・・（６）

... (6)

Furthermore, when x ≧ 0 and φ (x) = ln (tanh (x / 2)) is defined, φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ), so equation (6) is It can be written as equation (7).

・・・（７）

... (7)

In the check node, the calculation of Expression (7) is performed as shown in FIG. That is, in FIG. 8, the message u _j corresponding to the branch to be calculated is calculated using the messages v ₁ , v ₂ , v ₃ , v ₄ , v ₅ from the remaining branches connected to the check node. The Messages corresponding to other branches are similarly calculated.

The function φ (x) can also be expressed as φ (x) = ln ((e ^x +1) / (e ^x −1)). When x> 0, φ (x) = φ ⁻¹ ( x). When the functions φ (x) and φ ⁻¹ (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.

  When the thumb product algorithm is implemented in hardware, it is necessary to repeatedly perform the variable node calculation represented by Expression (1) and the check node calculation represented by Expression (7) with an appropriate circuit scale and operating frequency. is there.

  As an example of the implementation of a decoding device, a decoding device that performs LDPC code decoding (full serial decoding) by sequentially performing each node operation one by one, a certain number of operations that are not one or all of each node A decoding device (Patent Document 1) that performs node operations simultaneously (partly parallel decoding) and a decoding device that performs decoding by performing operations on all nodes simultaneously (non-patent document 1) have been proposed. .

  Hereinafter, an implementation method in the case where decoding is performed by sequentially performing a plurality of operations at each node (partly parallel decoding) will be described.

  Here, for example, a code (coding rate 2/3, code length 108) represented by a check matrix H of 36 (rows) × 108 (columns) in FIG. 9 is decoded. The number of 1s in the parity check matrix H in FIG. 9 is 323. Therefore, in the Tanner graph, the number of branches is 323. Here, in the parity check matrix H in FIG. 9, 0 is represented by “.”. Also, the parity check matrix H in FIG. 9 is expressed with an interval in units of 6 × 6 matrices.

  In FIG. 9, a check matrix H is a 6 × 6 unit matrix, a matrix in which one or more of the unit matrices are 0 (hereinafter referred to as a quasi-unit matrix as appropriate), a unit matrix or a quasi-unit matrix. A cyclic shift matrix (hereinafter referred to as a shift matrix as appropriate), a unit matrix, a quasi-unit matrix, or a sum of two or more of a shift matrix (hereinafter referred to as a sum matrix as appropriate), It is represented by a combination of 6 × 6 zero matrices.

  Note that the 6 × 6 unit matrix, quasi-unit matrix, shift matrix, sum matrix, and zero matrix constituting the parity check matrix H in FIG.

  With reference to FIG. 10, a decoding apparatus for decoding an LDPC code represented by parity check matrix H in FIG. 9 will be described.

  FIG. 10 is a block diagram illustrating an exemplary configuration of decoding apparatus 400 that decodes the LDPC code represented by parity check matrix H in FIG.

The decoding device 400 includes a decoding intermediate result storage memory 410, a cyclic shift circuit 411, a calculation unit 412 including six calculators 412 ₁ to 412 ₆ , a decoding intermediate result storage memory 413, a cyclic shift circuit 414, The calculation unit 415 includes _six calculators 415 ₁ to 415 ₆ , a reception memory 416, and a control unit 417.

Here, the calculation performed by the calculator 412 _k (k = 1, 2,..., 6) and the calculation performed by the calculator 415 _k will be described using equations.

The calculation unit 412 performs the first calculation according to the above-described equation (7) and the following equation (8), and stores the decoding intermediate result u _j that is the result of the first calculation for the decoding intermediate result. The data is supplied to the memory 413 and stored. The calculation unit 415 performs the second calculation according to the above-described equation (5), and supplies the decoding intermediate result v, which is the result of the second calculation, to the decoding intermediate result storage memory 410 for storage.

・・・（８）

... (8)

Note that u _dv in Expression (8) represents an intermediate result of a check node calculation from a branch for which a message of i columns of the check matrix H is to be obtained (in this case, the check node message itself). That is, u _dv is a decoding intermediate result corresponding to the branch to be obtained.

The decoding intermediate result v obtained as a result of the second operation according to the above equation (5) is the decoding of the check node operation from all branches corresponding to 1 in each row of the i columns of the received data u _0i and the check matrix H. Since the intermediate result u _j is added, the value v _i used in the above equation (7) is obtained from the decoding intermediate result v obtained as a result of the second operation according to the equation (5) from the check matrix H. In the decoding intermediate result u _j of the check node operation from the branch corresponding to 1 of each row in the i column, the value obtained by subtracting the decoding intermediate result u _dv of the check node operation from the branch for which a message is to be obtained is obtained. . That is, the calculation of the expression (1) for obtaining the value v _i used for the calculation of the expression (7) is a combination of the above expressions (5) and (8).

  Accordingly, in the decoding device 400, the first calculation according to the equations (7) and (8) by the calculation unit 412 and the second calculation according to the equation (5) by the calculation unit 415 are alternately performed, and the calculation is performed. The unit 415 outputs the result of the last second operation as a decoding result, so that it is possible to perform LDPC code iterative decoding.

Here, the first calculation result according to Expression (7) and Expression (8) is described as a decoding intermediate result u _j, and this decoding intermediate result u _j is the message of the check node in Expression (7). It is equal to u _j .

In addition, v in Expression (5) obtained by the second operation is obtained by adding the message u _j of the check node from the branch for which a message is to be obtained to the variable node calculation result v _{i in} Expression (1). Therefore, only one is obtained for one column (one variable node) of the check matrix H.

In decoding apparatus 400, calculation unit 412 performs the first calculation using decoding intermediate result v corresponding to the column of parity check matrix H that is the result of the second calculation by calculation unit 415, and obtains the result of the calculation. Decoding intermediate result u _j of the check node operation from the branch of the message corresponding to 1 in each row (message output by each check node to each branch) of i columns of the parity check matrix H It stores in 413. Therefore, the capacity of the decoding intermediate result storage memory 413 is a value obtained by multiplying the number of 1 (the number of all branches) of the parity check matrix H and the number of quantization bits as in the case of storing the result of the check node calculation. .

On the other hand, the calculation unit 415 uses the decoding intermediate result u _j corresponding to “1” of each row of the i matrix of the parity check matrix H, which is the result of the first calculation by the calculation unit 412, and the received data u _0i . 2 is performed, and the decoding intermediate result v corresponding to the i column obtained as a result of the calculation is stored in the decoding intermediate result storage memory 410. Therefore, the necessary capacity of the decoding intermediate result storage memory 410 is the number of columns of the parity check matrix H smaller than the number of “1” of the parity check matrix H, that is, the code length of the LCPC code and the number of quantization bits of the decoding intermediate result v It becomes the value which multiplied.

  As a result, the memory capacity of the decoding intermediate result storage memory 410 can be reduced as compared with the case where the result of the variable node calculation is stored, whereby the circuit scale of the decoding device 400 can be reduced.

  Hereinafter, the operation of each unit of the decoding device 400 of FIG. 10 will be described in detail.

  The decoding intermediate result storage memory 410 is supplied with six decoding intermediate results D415 corresponding to the six columns of the check matrix H, which is the result of the second calculation by the calculation unit 415, from the calculation unit 415. The storage memory 410 stores (stores) the six decoding intermediate results D415 supplied from the calculation unit 415 in order from the first address.

  That is, the first address of the decoding intermediate result storage memory 410 stores the decoding intermediate results v from the first column to the sixth column among the decoding intermediate results corresponding to the columns of the check matrix H. Similarly, the second address stores the decoding intermediate result v of the seventh column to the twelfth column, and the third address stores the decoding intermediate result of the thirteenth column to the eighteenth column. Is done. Thereafter, in the same manner, decoding intermediate results v from the 103rd column to the 108th column are stored in increments of 6 from the 4th address to the 18th address, and a total of 108 decoding intermediate results v are stored during the decoding. Stored in the memory 410. Therefore, the number of words in the decoding intermediate result storage memory 410 is 6 which is the number of decoding intermediate results simultaneously reading and writing 108, which is the number of columns of the check matrix H (code length of the LDPC code) in FIG. Divide by 18.

Further, the decoding intermediate result storage memory 410 sets “1” in the row of the check matrix H corresponding to the decoding intermediate result u _j to be obtained by the calculation unit 412 at the subsequent stage from the already stored decoding intermediate result D415. Six decoding intermediate results v are simultaneously read and supplied to the cyclic shift circuit 411 as decoding intermediate results D410.

  Note that the decoding intermediate result storage memory 410 is composed of, for example, a single-port RAM that can simultaneously read and write six decoding intermediate results v. Further, since the decoding intermediate result D415 corresponding to the column calculated by the second calculation of the calculation unit 415 is stored in the decoding intermediate result storage memory 410, the data stored in the decoding intermediate result storage memory 410 is stored in the decoding intermediate result storage memory 410. The storage capacity required for the amount, that is, the decoding result storage memory 410 is a product of the number of quantization bits of the decoding result D415 and the number of columns of the check matrix H (code length of the LDPC code). .

The cyclic shift circuit 411 is supplied with the six decoding intermediate results D410 from the decoding intermediate result storage memory 410, and the control unit 417 adds 1 of the check matrix H corresponding to the decoding intermediate result D410 to the check matrix. A control signal D418 representing information (Matrix data) indicating the number of cyclic shifts of the original unit matrix and the like in H is supplied. The cyclic shift circuit 611 performs cyclic shift for rearranging the six decoding intermediate results D410 based on the control signal D418, and supplies the result to the calculating unit 412 as decoding intermediate results D411 (D411 _{1 to} D411 ₆ ). To do.

The calculation unit 412 includes six calculators 412 _{1 to} 412 ₆ . The calculation unit 412 is supplied with six decoding intermediate results D411 (v) obtained as a result of the second calculation by the calculation unit 415 from the cyclic shift circuit 411, and from the decoding intermediate result storage memory 413, Six decoding intermediate results D413 (D413 _{1 to} D413 ₆ ) (u _j ) obtained as a result of the first calculation by the calculators 412 _{1 to} 412 ₆ are supplied last time, and the six decoding intermediate results D411 and six The decoding intermediate result D413 is supplied to the calculators 412 _{1 to} 412 ₆ , respectively. Further, the calculation unit 412 is supplied with the control signal D419 from the control unit 417, and the control signal D419 is supplied to the calculators 412 _{1 to} 412 ₆ . The control signal D419 is a signal common to the _six calculators 412 _{1 to} 412 ₆ .

The calculators 412 _{1 to} 412 ₆ perform the first calculation according to the equations (7) and (8) using the decoding intermediate result D411 and the decoding intermediate result D413, respectively, and perform decoding intermediate results D412 (D412 _{1 to} D412). ₆ ) Find (u _j ). The calculation unit 412 supplies six decoding intermediate results D412 corresponding to six ones of the check matrix H obtained as a result of the calculation by the calculators 412 _{1 to} 412 ₆ to the decoding intermediate result storage memory 413.

The decoding intermediate result storage memory 413 includes, for example, two single-port RAMs that can simultaneously read and write six decoding intermediate results D412. Six decoding intermediate results D412 are supplied from the calculation unit 412 to the decoding intermediate result storage memory 413, and a control signal D420 (D420 _{1 to} D420 ₄ ) for controlling reading / writing of the decoding intermediate result 413 from the control unit 417. Supplied.

  Based on the control signal D420, the decoding intermediate result storage memory 413 stores the six decoding intermediate results D412 supplied from the calculation unit 412 together, and simultaneously reads the six decoding intermediate results D412 already stored. The decoding result D413 is supplied to the calculation unit 412 and the cyclic shift circuit 414. That is, the decoding intermediate result storage memory 413 simultaneously reads the decoding intermediate result D413 supplied to the calculation unit 412 and the cyclic shift circuit 414 and writes the decoding intermediate result D412 supplied from the calculation unit 412.

  The decoding intermediate result storage memory 413 stores the decoding intermediate result D412 of the first calculation from the branch corresponding to 1 in each row of i columns of the check matrix H calculated by the first calculation of the calculation unit 412. Therefore, the amount of data stored in the decoding intermediate result storage memory 413, that is, the storage capacity required for the decoding intermediate result storage memory 413, is determined by the number of quantization bits of the decoding intermediate result D412 and the check. This is a multiplication value of the number of 1s in the matrix H.

The cyclic shift circuit 414 is supplied with six decoding intermediate results D413 (decoding intermediate results u _j ) from the decoding intermediate result storage memory 413, and from the control unit 417, a check matrix corresponding to the decoding intermediate result D413. A control signal D421 representing information (Matrix data) indicating how many 1s of H are cyclic shifts of the original unit matrix in the check matrix H is supplied. The cyclic shift circuit 414 performs a cyclic shift to rearrange the six decoding intermediate results D413 based on the control signal D421, and supplies the result to the calculation unit 415 as a decoding intermediate result D414.

The calculation unit 415 includes six calculators 415 _{1 to} 415 ₆ . Six decoding intermediate results D414 (D414 _{1 to} D414 ₆ ) are supplied from the cyclic shift circuit 414 to the calculation unit 415, and the decoding intermediate results D414 are supplied to the calculators 415 _{1 to} 415 ₆ respectively. The calculation unit 415 is supplied with _six reception data D416 stored in the reception memory 417 as reception data D417 (LDPC code) (D417 _{1 to} D417 ₆ ), and the reception data D417 is calculated by the calculator. 415 _{1 to} 415 ₆ are supplied. Further, a control signal D422 is supplied from the control unit 417 to the calculation unit 417, and the control signal D422 is supplied to the calculators 415 _{1 to} 415 ₆ . The control signal D422 is a signal common to the _six calculators 417 _{1 to} 417 ₆ .

The calculators 415 _{1 to} 415 ₆ use the decoding intermediate result D414 and the received data D417, respectively, to perform the second calculation according to the equation (5), respectively, and obtain the decoding intermediate result D415 (D415 _{1 to} D415 ₆ ). Ask. The calculation unit 415 supplies six decoding intermediate results D415 (v) obtained as a result of the second calculation of the calculators 415 _{1 to} 415 ₆ to the decoding intermediate result storage memory 410. Further, when the operation to be performed is the last second operation, the calculation unit 415 outputs six decoding intermediate results D415 obtained as a result of the operation as final decoding results.

Receiving memory 416, the data (received data) received values received through a communication path (sign bit) received LLR is zero likelihood value of a bit of code calculated from U ₀ (log likelihood ratio) D416 (u _0i ) is stored one by one.

  That is, among the reception data D416 corresponding to the column of the check matrix H, the reception data D416 corresponding to the first to sixth columns of the check matrix H is stored in the first address of the reception memory 416. Is done. Then, received data D416 corresponding to the seventh column to the twelfth column of the parity check matrix H is stored at the second address, and the thirteenth column to the eighteenth column of the parity check matrix H are stored at the third address. The reception data D416 corresponding to the columns are stored. Thereafter, similarly, received data D416 corresponding to the 19th column to the 108th column of the check matrix H is stored 6 by 6 from the 4th address to the 18th address.

The receiving memory 616, already by that reception data D416 to store, read by six in the order required for a variable node calculation, and supplies the calculation unit 415 as reception data D417 ₁ to D417 _6.

  Note that the reception memory 416 is composed of, for example, a single-port RAM that can simultaneously read and write six reception data D416. The amount of data stored in the reception memory 416, that is, the storage capacity required for the reception memory 315 is a product of the code length of the LDPC code and the number of quantization bits of the reception data D416. Further, the number of words in the reception memory 416 is a value obtained by dividing the code length of the LDPC code, that is, the number of columns of the check matrix H, by 6, which is the number of received data D417 (D416) to be read simultaneously. 18 of.

  The control unit 417 controls the control signal D418 by supplying the control signal D418 to the cyclic shift circuit 411 and the control signal D419 to the calculation unit 412. In addition, the control unit 417 controls the control signal D420 by supplying the control signal D420 to the decoding intermediate result storage memory 413, the control signal D421 to the cyclic shift circuit 414, and the control signal D422 to the calculation unit 415, respectively.

  The decoding apparatus 400 performs a round of data in the order of the decoding intermediate result storage memory 410, the cyclic shift circuit 411, the calculation unit 412, the decoding intermediate result storage memory 413, the cyclic shift circuit 414, and the calculation unit 415. One decoding can be performed. In the decoding device 400, after decoding is repeated a predetermined number of times, decoding intermediate results D415, which are the results of the second calculation by the calculation unit 415, are output one by one as the final decoding result.

  Also, a method of approximating and implementing the sum product algorithm has been proposed, but this method causes performance degradation.

JP 2004-364233 A C. Howland and A. Blanksby, "Parallel Decoding Architectures for Low Density Parity Check Codes", Symposium on Circuits and Systems, 2001

  However, in the decoding apparatus 400 of FIG. 10, it has not been proposed to improve the throughput by inputting the reception data D416 or outputting the decoding results at the same time.

  The present invention has been made in view of such circumstances, and is intended to improve the throughput of a decoding device.

  A decoding apparatus according to an aspect of the present invention is a decoding apparatus that decodes an LDPC (Low Density Parity Check) code, and one or more of P × P unit matrices and 1 that are components of the unit matrix are 0. A quasi-unit matrix that is a matrix, a shift matrix that is a cyclic shift of the unit matrix or quasi-unit matrix, the unit matrix, a quasi-unit matrix, or a sum matrix that is a sum of a plurality of shift matrices, Alternatively, when the P × P 0 matrix is used as a constituent matrix, the LDPC code parity check matrix is represented by a combination of a plurality of the constituent matrices, or the LDPC code parity check matrix is a plurality of rows or columns replaced. A code storage unit that stores the LDPC code, a decoding unit that decodes the LDPC code stored in the code storage unit, and a decoding unit that decodes the LDPC code. Decoding result storage means for storing the decoding result obtained as a result, and reading out the already stored decoding result, wherein the code storage means stores the LDPC code at the same time by a plurality of P or less, The decoding result storage means reads the decoding result at the same time by a plurality of P or less, or the code storage means stores the LDPC code at a time by a plurality of the P or less at the same time, and stores the decoding result The means reads the decoding result at the same time by a plurality of P or less.

  The code storage means stores the LDPC code by several divisors of the P simultaneously, the decoding result storage means reads the decoding results by divisors of the P simultaneously, or the code storage means The LDPC code can be stored at the same time for each of about several Ps, and the decoding result storage means can simultaneously read out the about several Ps for the decoding results.

  The code storage means is configured by a memory capable of simultaneously reading and writing about a few of the LDPC codes of the P, and the decoding result storage means is configured by a memory capable of simultaneously reading and writing the plurality of the decoding results of the P. Can be configured.

  Compared to the operation clock of the first external device that inputs the LDPC code to the code storage means and the second external device that outputs the decoding result read from the decoding result storage means, the decoding device, The operation can be performed with a high-speed operation clock.

  The code storage means may store the LDPC codes corresponding to the P columns of the parity check matrix after the row or column replacement in an order that can be read simultaneously.

  The code storage means is a RAM (Random Access Memory), and the LDPC code corresponding to the P columns of the parity check matrix after replacement of the row or column is stored in each address of the RAM. it can.

  The decoding apparatus further includes order control means for controlling the order of at least one of the LDPC code before being stored in the code storage means or the decoding result after being read from the decoding result storage means. Can do.

  The order control means may include order code storage means for storing the LDPC code and selection means for selecting and outputting the LDPC code stored in the order code storage means.

  The order control means may include order decoding result storage means for storing the decoding result and selection means for selecting and outputting the decoding result stored in the order decoding result storage means.

  A decoding method according to an aspect of the present invention is a decoding method of a decoding apparatus that decodes an LDPC (Low Density Parity Check) code, and includes a P × P unit matrix and one of 1 that is a component of the unit matrix. The above is a quasi-unit matrix that is a matrix of zero, a shift matrix that is a cyclic shift of the unit matrix or quasi-unit matrix, the unit matrix, a quasi-unit matrix, or a sum of a plurality of shift matrices. When the parity check matrix of the LDPC code is represented by a combination of a plurality of the configuration matrices, where the sum matrix or the P × P 0 matrix is the configuration matrix, or the LDPC code check matrix is a row or column replacement Accordingly, in the case where the combination matrix is represented by a combination of a plurality of the configuration matrices, a code storage step for storing the LDPC code and a decoding step for decoding the LDPC code stored by the processing of the code storage step And a decoding result storing step for storing a decoding result obtained as a result of decoding by the processing of the decoding step and reading out a decoding result that has already been stored, and the processing of the code storing step includes the LDPC code Are stored at the same time, or the decoding result storing step is to simultaneously read the decoding results at the P number or less, or the code storing step is the LDPC A plurality of P or less codes are simultaneously stored, and the decoding result storing step reads the decoding results simultaneously by the P or less.

  In one aspect of the present invention, a plurality of P or less LDPC codes are simultaneously stored, a plurality of P or less decoded results are read simultaneously, or a plurality of P or less LDPC codes are read. The decoding results are simultaneously stored, and the decoding results are simultaneously read out in increments of P or less.

  As described above, according to one aspect of the present invention, the throughput of the decoding device can be improved.

  Embodiments of the present invention will be described below. Correspondences between the configuration requirements of the present invention and the embodiments described in the detailed description of the present invention are exemplified as follows. This description is to confirm that the embodiments supporting the present invention are described in the detailed description of the invention. Accordingly, although there are embodiments that are described in the detailed description of the invention but are not described here as embodiments corresponding to the constituent elements of the present invention, It does not mean that the embodiment does not correspond to the configuration requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

A decoding device according to one aspect of the present invention provides:
A decoding device (for example, the decoding device 800 in FIG. 15) for decoding an LDPC (Low Density Parity Check) code,
A P × P unit matrix, a quasi-unit matrix that is a matrix in which one or more of 1s that are components of the unit matrix are 0, and a shift matrix that is a cyclic shift of the unit matrix or the quasi-unit matrix , A unit matrix, a quasi-unit matrix, or a sum matrix that is a sum of a plurality of shift matrices, or a P × P 0 matrix, and a parity check matrix of the LDPC code is a combination of a plurality of the constituent matrices Or when the parity check matrix of the LDPC code is represented by a combination of a plurality of the constituent matrices by row or column replacement,
Code storage means for storing the LDPC code (for example, reception memory 834 in FIG. 16);
Decoding means for decoding the LDPC code stored in the code storage means (for example, the calculation units 412 and 415 in FIG. 15);
A decoding result storage means (for example, a decoding result memory 901 in FIG. 24) that stores a decoding result obtained as a result of decoding by the decoding means and reads out a decoding result that has already been stored;
The code storage means stores the LDPC codes at the same time in a plurality of P or less, or the decoding result storage means reads out the decoding results at a time in a plurality of P or less, or the code storage The means stores the LDPC code at the P number or less at the same time, and the decoding result storage means reads the decoding result at the P number or less at the same time (for example, the process of step S35 in FIG. 29). , Processing of step S71 of FIG. 31).

The decoding device outputs a decoding result read from the first external device (for example, the interleaver 831 and the selector 832 in FIG. 16) that inputs the LDPC code to the code storage unit, and the decoding result storage unit. second external device (e.g., deinterleaver 903 and the selector 904 in FIG. 24) operation clock (e.g., low-speed clock CK ₁ or CK ₃₎ compared to the high-speed operation clock (e.g., high-speed clock CK ₂₎ Do the operation with.

Order control means for controlling the order of at least one of the LDPC code before being stored in the code storage means or the decoding result after being read from the decoding result storage means (for example, the interleaver 831 in FIG. 16). )
Is further provided.

The order control means (for example, the interleaver 831 in FIG. 17)
Order code storage means for storing the LDPC code (for example, the registers 851-1 to 851-5 and 852-1 to 852-5 in FIG. 17);
Selection means (for example, selector 853 in FIG. 17) for selecting and outputting the LDPC code stored in the order code storage means is provided.

The order control means (for example, the deinterleaver 903 in FIG. 26)
Order decoding result storage means for storing the decoding results (for example, registers 921-1 to 921-5 and 922-1 to 922-5);
Selection means (for example, a selector 923 in FIG. 26) for selecting and outputting the decoding result stored in the order decoding result storage means is provided.

A decoding method according to one aspect of the present invention includes:
A decoding method of a decoding device (for example, the decoding device 800 in FIG. 15) for decoding an LDPC (Low Density Parity Check) code,
A P × P unit matrix, a quasi-unit matrix that is a matrix in which one or more of 1s that are components of the unit matrix are 0, and a shift matrix that is a cyclic shift of the unit matrix or the quasi-unit matrix , A unit matrix, a quasi-unit matrix, or a sum matrix that is a sum of a plurality of shift matrices, or a P × P 0 matrix, and a parity check matrix of the LDPC code is a combination of a plurality of the constituent matrices Or when the parity check matrix of the LDPC code is represented by a combination of a plurality of the constituent matrices by row or column replacement,
A code storing step (for example, step S35 in FIG. 29) for storing the LDPC code;
A decoding step (for example, the decoding process of FIG. 30) for decoding the LDPC code stored by the process of the code storing step;
A decoding result storage step (for example, step S71 in FIG. 31) that stores a decoding result obtained as a result of decoding by the processing of the decoding step and reads out a decoding result that has already been stored;
Whether the code storing step stores the LDPC code at the P number or less simultaneously, or the decoding result storing step reads the decoding result at the P number or less simultaneously. Alternatively, the process of the code storage step stores the LDPC code at the P number or less at the same time, and the process of the decoding result storage step simultaneously reads the decoding result at the P number or less at a time ( For example, step S35 in FIG. 29, step S71 in FIG. 31).

  FIG. 11 shows an example of parity check matrix H used for decoding the LDPC code.

  The parity check matrix H in FIG. 11 is a parity check matrix H for obtaining a codeword c (coding rate 2/3, code length 108) of n = 108, k = 72, and is 36 (rows) × 108 (columns). Is a matrix. In the parity check matrix H of FIG. 11 (the same applies to the matrices of FIGS. 12 to 14 described later), 0 is represented by “.”. In addition, the parity check matrix H in FIG. 11 is expressed with an interval in units of 6 × 6 matrices.

  That is, the parity check matrix H is composed of an information part of 36 (= n−k) rows 72 (= k) columns and a parity part of 36 (= n−k) rows 36 (= n−k) columns.

  In the parity check matrix H in FIG. 11, each row of the information part corresponding to the information word i of the LDPC code is composed of seven “1” s and 101 “0s”. The parity part is a matrix having a lower triangular structure (lower triangular matrix). That is, the parity part of the parity check matrix H in FIG. 11 is a matrix in which the upper right corner of the diagonal of the matrix is all “0”, and has a lower triangular structure.

  12 and 13 show a parity check matrix H ′ after row replacement or column replacement of the parity check matrix H of FIG.

  In the parity check matrix H ′ in FIG. 12, the information part is a unit matrix of P × P (P = 6 in the example of FIG. 12), and a quasi-unit matrix in which at least one of the unit matrices is 0. , A shift matrix obtained by cyclically shifting a unit matrix or quasi-unit matrix, a unit matrix, a quasi-unit matrix, a sum matrix that is the sum of two or more of the shift matrices, and a combination of P × P 0 matrices be able to. That is, the parity check matrix H ′ in FIG. 12 can be represented by a combination of 6 × 6 configuration matrices.

The parity check matrix H ′ in FIG. 13 represents the parity check matrix H ′ shown in FIG. 12 with an interval in the unit of a 6 × 6 configuration matrix. If the number of lateral configuration matrix constituting the check matrix H'the _zero n, the number of lateral configuration matrixes constituting the information of the check matrix H'to _zero k, n ₀ (= n / P = 108/6) is 18, and k ₀ (= k / P = 72/6) is 12.

That is, in the parity check matrix H ′ in FIG. 12 and FIG. 13, 6 (= n ₀ -k ₀ = 18−12) constituent matrices in the vertical direction and n ₀ (= 18) constituent matrices in the horizontal direction. Are lined up.

Further, the left-most column of the parity part of the check matrix H of FIG. 11 (first column) and 0 column, (n ₀ -k ₀₎ of the parity part of the check matrix H × v + w (0 ≦ v ≦ P −1,0 ≦ w ≦ n ₀ −k ₀ −1) The column of the column is the P × w + v column in the parity part of the parity check matrix H ′ in FIGS. 12 and 13.

As described above, since the parity check matrix H ′ in FIG. 12 and FIG. 13 is configured with a configuration matrix, when the LDPC code is decoded using the parity check matrix H ′, the first matrix necessary for decoding the LDPC code is used. Reading the decoding intermediate result u _j obtained as a result of the operation in the order used for the second operation, and reading the decoding intermediate result v obtained as the result of the second operation in the order used for the first operation This can be done by cyclically shifting the decoding intermediate results u _j and v in units of six. Moreover, by cyclically shifting the decoding intermediate results u _j six units, the product of the row of the check matrix H'decoding intermediate result u _j in the second operation, it is possible to calculate six simultaneously.

  14A to 14B show the parity part of the parity check matrix H in FIG. 11 and the parity check matrix H ′ in FIGS. 12 and 13.

  As shown in FIG. 14A, the parity part of the parity check matrix H in FIG. 11 is a matrix in which the upper right corner of the diagonal of the matrix is all “0”, and has a lower triangular structure. In the parity part, the diagonal component of the lower triangular matrix and the component immediately below the component are 1, and the other components are 0.

As shown in FIG. 14B, in the parity part of the parity check matrix H ′ in FIGS. 12 and 13, the 6 × 6 unit matrix is diagonal so that the diagonal component is the diagonal component of the 6 × 6 unit matrix. A 6 × 6 unit matrix is also arranged immediately below the unit matrix. Further, in the parity part, a matrix obtained by cyclically shifting the matrix in which 1 in the uppermost row of the 6 × 6 unit matrix is 0 to the left by 1 is arranged on the upper right. In addition to the above, a 6 × 6 zero matrix is arranged. In the parity part of FIG. 14B, the row of the (n ₀ −k ₀ ) × v + w column of the parity part of FIG. 14A is the column of the P × w + v column.

  FIG. 15 shows a configuration example of a decoding apparatus 800 that decodes an LDPC code according to an embodiment of the present invention. In the figure, portions corresponding to those of the decoding device 400 in FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

15 includes a decoding intermediate result storage memory 410, a cyclic shift circuit 411, a calculation unit 412 including six calculators 412 ₁ to 412 ₆ , a decoding intermediate result storage memory 413, a cyclic shift. Although common to the decoding device 400 in FIG. 10 in that a circuit 414, a calculation unit 415 including six calculators 415 ₁ to 415 ₆ and a control unit 417 are provided, the reception unit 416 is replaced with the reception memory 416. 10 is different from the decoding device 400 of FIG. 10 in that a receiving unit 811 is provided and an output unit 812 is newly provided.

  Here, in decoding apparatus 800 in FIG. 15, for example, it is assumed that LDPC code (coding rate 2/3, code length 108) represented by parity check matrix H shown in FIG. 11 is decoded.

  In decoding apparatus 800 in FIG. 15, received data D416 is rearranged in the order corresponding to parity check matrix H ′, and using received data D811 after the rearrangement, calculation unit 415 performs second processing corresponding to parity check matrix H ′. Six calculations are performed, and the calculation unit 412 performs six first calculations corresponding to the check matrix H ′, and the first calculation and the second calculation are alternately performed. Then, the LDPC code is decoded by rearranging the decoding intermediate result D415 obtained as a result of the last second calculation in the order corresponding to the check matrix H.

That is, the reception unit 811 receives the reception value U _{0 of the} LDPC code represented by the check matrix H, and receives and stores the reception data D416 (u _0i ). Then, the receiving unit 811, the already stored to have received data D416, reads the second six received data D416 in the order required for operation corresponding to the check matrix H ', the received data D811 ₁ to D811 ₆ (D811 ) To the calculation unit 415. In other words, the reception unit 811 rearranges the reception data D416 supplied in the order corresponding to the check matrix H and supplies the received data D416 to the calculation unit 415 as reception data D811 in the order corresponding to the check matrix H ′.

  Then, calculation section 415 performs a second operation corresponding to parity check matrix H ′ for decoding the LDPC code.

That is, the decoding intermediate result storage memory 413 stores decoding intermediate results D412 _{1 to} D412 ₆ (D412) (u _j ) as a result of the first calculation by the calculation unit 412 described later. The storage memory 413 supplies the six decoding intermediate results D412 among the decoding intermediate results D412 already stored to the cyclic shift circuit 414 and the calculation unit 412 as decoding intermediate results D413 _{1 to} D413 ₆ (D413). To do.

The cyclic shift circuit 414 cyclically shifts the decoding intermediate result D413 based on the control signal D421 from the control unit 417, and supplies the result to the calculating unit 415 as decoding intermediate results D414 _{1 to} D414 ₆ (D414). Further, a control signal D422 is supplied from the control unit 417 to the calculation unit 415, and six reception data D811 are supplied from the reception unit 811.

The calculator 415 includes calculators 415 _{1 to} 415 ₆ . Based on the control signal D422, each calculator 415 _k receives the decoding intermediate result D414 _k (u _j ) supplied from the cyclic shift circuit 414 and the received data D811 _k (u _0i ) supplied from the receiving unit 811. And the second calculation is performed according to equation (5). Then, each calculator 415 _k supplies the decoding intermediate result D415 _k (v) obtained as a result of the second calculation to the decoding intermediate result storage memory 410.

The decoding intermediate result storage memory 410 stores decoding intermediate results D415 _{1 to} D415 ₆ (D415) (v), which are the results of the six second operations, supplied from the calculation unit 415. Then, the decoding intermediate result storage memory 410 reads six decoding intermediate results D415 as the decoding intermediate results D410 from the already stored decoding intermediate results D415, and supplies them to the cyclic shift circuit 411. The cyclic shift circuit 411 cyclically shifts the six decoding intermediate results D410 based on the control signal D418 supplied from the control unit 417, and the calculation unit 412 uses the results as decoding intermediate results D411 _{1 to} D411 ₆ (D411). To supply.

  The calculation unit 412 performs a first operation corresponding to the parity check matrix H ′ for decoding the LDPC code.

That is, the calculation unit 412 includes calculators 412 _{1 to} 412 ₆ . Each calculator 412 _k is based on the control signal D419 supplied from the control unit 417, and the previous decoding result D411 _k supplied from the cyclic shift circuit 411 and the previous decoding result storage memory 413 are supplied. Using the decoding intermediate result D413 _k obtained as a result of the first calculation by the calculation unit 412, the first calculation is performed according to the equations (7) and (8), and the first calculation is performed. Six decoding intermediate results D412 _k (u _j ) are supplied to the decoding intermediate result storage memory 413.

The decoding intermediate result storage memory 413 stores the decoding intermediate results D412 _{1 to} D412 ₆ supplied from the calculation unit 412. Then, the decoding intermediate result D412 stored in the decoding intermediate result storage memory 413 is read as decoding intermediate results D413 _{1 to} D413 ₆ as described above, and supplied to the cyclic shift circuit 414 and the calculation unit 412.

  As described above, after the first calculation and the second calculation are alternately repeated a predetermined number of times, the decoding intermediate result D415 obtained as a result of the second calculation by the calculation unit 415 is output to the output unit 812. Supplied.

  The output unit 812 stores the decoding intermediate result D415 obtained from the second calculation corresponding to the check matrix H ′ supplied from the calculation unit 415. Then, the output unit 812 reads the decoding intermediate result D415 already stored in the order corresponding to the check matrix H, and outputs it as a decoding result. That is, the output unit 812 rearranges the decoding intermediate results D415 supplied in the order corresponding to the check matrix H ′ in the order corresponding to the check matrix H, and outputs the result as a decoding result. Thereby, it is possible to output the result of iterative decoding of the LDPC code represented by the check matrix H.

  FIG. 16 is a block diagram illustrating a detailed configuration example of the reception unit 811 in FIG. 15.

  The reception unit 811 in FIG. 16 includes an interleaver 831, a selector 832, a bit width adjustment circuit 833, a reception memory 834, and a control unit 835.

In FIG. 16, the interleaver 831 and the selector 832 operate with the low-speed clock CK ₁ , and the bit width adjustment circuit 833, the reception memory 834, and the control unit 835 operate with the high-speed clock CK ₂ (CK ₂ > CK ₁ ). Operate.

Further, the reception unit 811 is assumed to receive data D416 generated from the received value U ₀ is supplied by two. That is, the reception unit 811 is supplied with two pieces of reception data D416 in the order corresponding to the check matrix H, and the reception data D416 is supplied to the interleaver 831 and the selector 832.

Interleaver 831, in synchronization with the low-speed clock CK _1, based on the control signal D834 from the control unit 835 controls the order of the two reception data D416. Specifically, the component corresponding to the information message u of the reception value U _{0 in} the reception data D 416, that is, the component corresponding to the information part of the check matrix H (hereinafter referred to as information component) is supplied to the interleaver 831. In this case, when the control signal D834 is “0” and a component corresponding to the parity bit, that is, a component corresponding to the parity part of the check matrix H (hereinafter referred to as a parity component) is supplied to the interleaver 831, the control signal D834 is “1”.

  When the control signal D834 is “0”, the interleaver 831 supplies the two received data D416 as they are to the selector 832 as the received data D831. On the other hand, when the control signal D834 is “1”, the interleaver 831 rearranges the two reception data D416 in the order corresponding to the check matrix H ′, and supplies the two reception data D831 after the rearrangement to the selector 832. To do. That is, the interleaver 831 controls the order of the parity components of the two received data D416.

The selector 832, in synchronization with the low-speed clock CK _1, based on the control signal D835 from the control unit 835, selects one of two received data D831 from two received data D416 or interleaver 831, the The two selected reception data D416 or D831 are supplied in parallel to the bit width adjustment circuit 833 as two reception data D832.

Specifically, when the speed of the high-speed clock CK ₂ is smaller than 2 times the speed of the low-speed clock CK _1, the control signal D835 is "0", and more than twice the rate of the high-speed clock rate of the low-speed clock At this time, the control signal D835 becomes “1”. When the control signal D835 is “0”, the selector 832 selects the two received data D831 from the interleaver 831. When the control signal D835 is “1”, the selector 832 receives the two received data D416. select.

Bit width adjusting circuit 833, in synchronization with the high-speed clock CK _2, based on the control signal D835 from the control unit 835 to adjust the bit width of the received data D832 from the selector 832. Specifically, when the control signal D835 is “0”, the bit width adjustment circuit 833 converts, for example, two received data D832 supplied in parallel in synchronization with one clock of the low-speed clock CK ₁ into the high-speed clock CK. _In synchronization with one clock of _2, the data is supplied in parallel to the reception memory 834 as two reception data D833.

On the other hand, when the control signal D835 is "1", the bit width adjustment circuit 833 adjusts the two-bit width of the received data D832 supplied in parallel in synchronization with one clock of the low-speed clock CK _1, the high-speed clock in synchronization with one clock CK _2, one by one, and supplies the reception memory 834 as received data D833 serially. That is, the bit width adjustment circuit 833, between two clocks of the high-speed clock CK _2, and supplies the reception memory 834 two reception data D833 serially.

The reception memory 834 is composed of, for example, a RAM (Random Access Memory), and can simultaneously write two reception data D833 and read six reception data D811 simultaneously. The number of bits of the reception memory 834 is a value obtained by multiplying P (= 6) by the number of quantization bits of the reception data D833, and the number of words is n / P (= n ₀ = 18). Reception memory 834, in synchronism with the high-speed clock CK _2, based on the control signal D834 from the control unit 835, the reception data D833 supplied from the bit width adjustment circuit 833, corresponding to the six columns of the check matrix H' Are written in the bit direction (vertical direction) (FIG. 18 described later) or the word direction (horizontal direction) in the order in which they can be read simultaneously.

  Specifically, when the control signal D834 is “0”, the reception memory 834 writes the reception data D833 in the bit direction. On the other hand, when the control signal D834 is “1”, the reception memory 834 writes the reception data D833 in the word direction. That is, the reception data D833 corresponding to the information component is written in the bit direction, and the reception data D833 corresponding to the parity component is written in the word direction.

Reception memory 834, in synchronism with the high-speed clock CK _2, already reading the received data D833 which is stored in the bit direction six units, and supplies the calculation unit 415 as reception data D811.

Control unit 835, in synchronization with the low-speed clock CK _1, supplies a control signal D834 is supplied to the interleaver 831, in synchronization with the high-speed clock CK _2, a control signal D834 to the reception memory 834. The control unit 835, in synchronization with the low-speed clock CK _1, supplies a control signal D835 to the selector 832.

  FIG. 17 is a diagram illustrating a detailed configuration example of the interleaver 831 in FIG. 16.

  The interleaver 831 in FIG. 17 is supplied from five registers 851-1 to 851-5, five registers 852-1 to 852-5, and a selector 853.

  Two pieces of received data D416 are supplied to the interleaver 831, one of which is sequentially stored in the registers 851-1 to 851-5 as received data D851. The other one is sequentially stored in the registers 852-1 to 852-5 as received data D852. The registers 851-1 to 851-5 and the registers 852-1 to 852-5 supply the received data D851 or D852 stored therein to the selector 853, respectively. The two reception data D416 are directly supplied to the selector 853 as reception data D851 or D852, respectively.

  The selector 853 is one of five received data D851 or D852 supplied from each of the registers 851-1 to 851-5 and the registers 852-1 to 852-5 and directly received data D851 or D852. Two received data D851 or D852 are selected and output as received data D853 and D854. The received data D853 and D854 are combined and supplied to the selector 832 as two received data D831.

  As described above, in the interleaver 831, the registers 851-1 to 851-5 and the registers 852-1 to 852-5 store the input reception data D416 (reception data D851 or D852), and the selector 853 The received data D416 stored in the registers 851-1 to 851-5 and the registers 852-1 to 852-5 is selected and output as received data D831 (received data D853 and D854). The order of reception data D416 and output reception data D831 is switched.

  Next, reception data D833 stored in reception memory 834 in FIG. 16 will be described with reference to FIGS.

  As shown in FIG. 18, the word direction of the reception memory 834 used in the following description is the horizontal direction in the figure, and is referred to as address 0, address 1, address 2,. The bit direction of the reception memory 834 is the vertical direction in the figure, and is referred to as the 0th bit, the 1st bit, the 2nd bit,.

In the following, the information component of the received data D833 corresponding to the m-th column of the information part of the check matrix H, represents also a received data I _m, of the received data D833 corresponding to the m-th column of the parity part of the check matrix H parity components, also denoted received data D _m.

  The reception memory 834 will be described with reference to FIG. In FIG. 19, for convenience of explanation, the bit of the reception memory 834 is described on the assumption that the quantization bit of the reception data D833 is 1 bit.

  As shown in FIG. 19, the number of bits of the reception memory 834 is a value obtained by multiplying P (= 6) by the number of quantization bits of the reception data D833, and the number of words is n / p (= 18).

First, the reception memory 834, based on the control signal D834 supplied from the control unit 835, two received data I ₀ and I ₁ supplied from the bit width adjustment circuit 833, the zeroth bit of the zeroth address Are stored in the first bit.

Next, the reception memory 834 stores the two reception data I ₂ and I ₃ from the bit width adjustment circuit 833 in the second and third bits of the 0th address, respectively, based on the control signal D834.

Then, the same processing is repeated, and the received data I _{0 to} I ₅ are stored in the bit direction in the 0th to 5th bits of the 0th address of the reception memory 834, respectively, and the 0th to 0th of the 1st address of the reception memory 834 are stored. In the fifth bit, received data I _{6 to} I ₁₁ are stored in the bit direction, respectively. Similarly, the received data I _{12 to} I ₇₁ are stored at addresses 2 to 11 (= k ₀ −1) in the reception memory 834.

Next, the reception memory 834, based on the control signal D834 supplied from the control unit 835, the received data D ₀ to be supplied from the bit width adjustment circuit 833 is stored in the zeroth bit of the 12th address. The reception memory 834 stores the reception data D ₁ from the bit width adjustment circuit 833 in the 0th bit of the 13th address based on the control signal D834.

The same processing is repeated, and the received data D _{0 to} D ₅ are stored in the word direction in the 0th bit of the 12th to 17th (= n ₀ −1) addresses of the reception memory 834, respectively. the first bit of the 12 to 17th address, the received data D ₆ to D ₁₁ are respectively stored in the word direction. Following the similar manner in the subsequent stages, the second to sixth bit of the received memory 834, received data D ₁₂ to D ₃₅ are stored.

Here, the order of the 12th to 17th addresses in the word direction is (n ₀ -k ₀ ) × x + y (x = 0, 1,..., 5, y = 0, 1,... 5) The order of the received data _Dm in the bit direction is P × y + xth. The order in the bit direction is such that the fifth bit after each number address is the 0th bit of the address on the right (the address of the next number). The order in the word direction is such that the next address of the 5th address of each bit is the 0th address of the immediately lower bit (next bit). For example, the received data D833 order is the sixth in the bit direction, the received data D _1, and the order in the word direction is 6 th received data D833 becomes the received data D _6.

As described above, (n ₀ -k ₀₎ of the parity part of the check matrix H of FIG. 11 × v + w-th column, in the parity part of the check matrix H'in FIG 12, P × w + v-th column of It becomes a column. That is, the P × w + v column of the parity part of the parity check matrix H ′ is the (n ₀ −k ₀ ) × v + w column of the parity part of the parity check matrix H. Therefore, the received data D _m corresponding to the 0th column of the parity part of the parity check matrix H stored in the word direction of the reception memory 834 in order from the 0th column of the parity matrix is 0 in the parity part of the parity check matrix H ′. Corresponding reception data _Dm is obtained from the column.

  That is, since the decoding apparatus 800 performs the second calculation using the reception data D811 corresponding to the column of the parity check matrix H ′, the order of the reception data D416 supplied in the order corresponding to the column of the parity check matrix H is checked. It is necessary to replace them in the order corresponding to the columns of the matrix H ′. As described above, the order of the columns of the check matrix H and the check matrix H ′ is the same in the information part, but is different in the parity part. Accordingly, the reception memory 834 stores the parity component of the reception data D831 in the word direction and reads it in the bit direction, thereby allowing the calculation unit 415 that performs the second calculation to receive the six columns of the check matrix H ′. Data D811 can be supplied simultaneously.

  As described above, the addresses of the reception memory 834 in FIG. 19 correspond to the six columns of the check matrix H ′, and the reception memory 834 reads the received data D831 at the same address in the bit direction, thereby The reception data D811 corresponding to the six columns of the matrix H ′ can be read out.

Next, with reference to FIGS. 20 and 21, an input parity component of the received data D416 to the reception unit 811 of FIG. 16, the writing of received data D _m to the receiving memory 834 will be described. 20 and 21, the horizontal axis represents time.

In the following, a parity component of the received data D416 corresponding to m columns of the check matrix H, also referred to as received data A _m.

Figure 20 is a timing chart speed of the high speed clock CK ₂ is described in the case where more than twice the speed of the low-speed clock CK _1, the input of the reception data A _m, and writes the received data D _m.

As shown in FIG. 20, the reception unit 811, receives the data A _m is two by two inputs. For example, received data A ₀ and A ₁ , received data A ₂ and A ₃ , received data A ₄ and A ₅ , received data A ₆ and A ₇ .

In FIG. 20, since the speed of the high-speed clock CK ₂ is twice or more the speed of the low-speed clock CK ₁ , that is, the control signal D835 is “1”, the selector 832 receives the two receptions input to the reception unit 811. the data a _m, and supplies the bit width adjustment circuit 833.

As shown in FIG. 20, the bit width adjustment circuit 833, two received data A _m inputted from the selector 832 in parallel in synchronization with one clock of the low-speed clock CK _1, synchronized to one clock of the high-speed clock CK ₂ to, one by one, and supplies the serial to the reception memory 834 as received data D _m, to write.

For example, when the reception data A ₀ and A ₁ are input in parallel to the reception unit 811 in synchronization with the low-speed clock CK ₁ , the reception memory 834 receives the reception data D in synchronization with one clock of the high-speed clock CK _{2. 0} after writing the 0 bit of the 12th address, in synchronization with the next one clock writes the received data D ₁ to 0 bit of 13th address.

As described above, in FIG. 20, the reception memory 834 operates with the high-speed clock CK ₂ that is twice or more the low-speed clock CK ₁ that is the operation clock of the interleaver 831 and the selector 832 other than the reception memory 834. during one clock of the low-speed clock CK _1, it can be written two received data D _m to a different address.

As a result, enter at the same time by two received data A _m to the decoding device 800, it is possible to improve the throughput.

Figure 21 is a timing chart speed of the high speed clock CK ₂ is described when it is less than twice the rate of the slow clock CK _1, the input of the reception data A _m, and writes the received data D _m.

As shown in FIG. 21, the receiving unit 811 has received data A ₀ and A ₁ , received data A ₂ and A ₃ , received data A ₄ and A ₅ , received data A ₆ and A _{7, as in FIG.} Are inputted in parallel in order.

In FIG. 21, since the speed of the high-speed clock CK ₂ is less than twice the speed of the low-speed clock CK ₁ , that is, the control signal D835 is “0”, the selector 832 receives the received data D831 supplied from the interleaver 831. Is supplied to the reception memory 834 via the bit width adjustment circuit 833.

That is, the interleaver 831 (FIG. 17) receives received data A ₀ and A ₁ , received data A ₂ and A ₃ , received data A ₄ and A ₅ , received data A ₆ and A _7. is input, the register 851-1 to 851-5, one of the two received data a _m entered in parallel (e.g., received data _{a 0, a 2, a 4} , a 6, ···) and stored as received data D851, the register 851-2 to 852-5, on the other hand (e.g., the received data _{a 1, a 3, a 5} , a 7, ···) stores as received data D852. Then, the register 851-1 to 851-5 and 852-1 to 852-5 and supplies the received data A _m (reception data D851 or D852), each selector 853. The two received data A _m, respectively, as received data D851 or D852, supplied directly to the selector 853.

The selector 853 first selects the reception data A ₀ and A ₆ and outputs them as reception data D853 and D854, respectively. Next, the selector 853 selects the reception data A ₁ and A ₇ and outputs them as reception data D853 and D854, respectively. Thereafter, the selector 853 selects and outputs the received data A ₂ and A ₈ , the received data A ₃ and A ₉ .

In other words, the two received data A _m that is inputted in parallel to the interleaver _{831, 6 (= n 0 -k} 0) one unit (three parallel input units) sequence alternately # 1 or say sequence # 2 The selector 853 selects the sequence # 1 (for example, received data A _{0 to} A ₅ ) and the sequence # 2 (for example, received data A _{6 to} A ₁₁ ) in the order of input from the received data A ₀ and A _6. Select and output one by one. That is, the selector 853, the received data A _m corresponding to the received data D _m to be written in the bit direction of the reception memory 834, and outputs two by two select.

Two received data A _m output by the selector 853 of the interleaver 831 via the selector 832 and the bit width adjustment circuit 833, is supplied to the reception memory 834 as two of the received data D _m. The reception memory 834 is synchronized to one clock of the high-speed clock CK _2, written in parallel to the two receiving data A _m to the same address.

More specifically, as shown in FIG. 21, the reception memory 834, received data D ₀ and D _6, received data D ₁ and D _7, the received data D ₂ and D _8, the received data D ₃ and D ₉ · .. are supplied in parallel in order. The reception memory 834 first writes the two reception data D ₀ and D ₆ in parallel with the 0th bit and the 1st bit of the 12th address in synchronization with one clock of the high-speed clock CK ₂ . Similarly, the reception memory 834 stores the reception data D ₁ and D ₇ , the reception data D ₂ and D ₈ , the reception data D ₃ and D ₉ ..., The 13th address, the 14th address, the 15th address. ..Write in parallel to the 0th and 1st bits.

As described above, the interleaver 831, the received data A _m corresponding to the received data D _m to be written in the bit direction of the reception memory 834, since the output two by two by selecting, receiving memory 834, two receiving data can be written D _m in parallel. Thus, the high-speed clock CK ₂ is, when it is less than twice the low-speed clock CK ₁ also during one clock of the low-speed clock CK _1, it is possible to write two received data D _m.

As a result, the throughput of the decoding device 800 can be improved without increasing the speed of the high-speed clock CK ₂ to more than twice the speed of the low-speed clock CK ₁ .

FIG. 22 is a block diagram illustrating a configuration example of the calculator 412 _k of the calculation unit 412 in FIG.

In FIG. 22, each decoding intermediate result D412 _k (D413 _k ) (u _dv ) obtained as a result of the first calculation by the previous calculation unit 412 is quantized to a total of 6 bits (bits) including the sign bit, The calculator 412 _k is represented on the assumption that each decoding intermediate result D415 (D411 _k ) (v) obtained as a result of the second calculation by the unit 415 is quantized to 9 bits. Further, a high-speed clock CK ₂ is supplied to the calculator 412 _k in FIG. 22, and this high-speed clock CK ₂ is supplied to a necessary block. Each block performs a synchronization and processing the high-speed clock CK _2.

The calculator 412 _{k in} FIG. 22 obtains the result of the first calculation by the previous calculation unit 412 that is read one by one from the decoding intermediate result storage memory 413 based on the control signal D419 supplied from the control unit 417. and it was decoded intermediate results D413 _k (u _dv), by using the cyclic shift circuit 411 one by one from the decoding intermediate results to be read D411 _k (v), first according to equation (8) and equation (7) Perform the operation.

That is, the calculator 412 _k is supplied with one decoding intermediate result D411 _k among the _six 9-bit decoding intermediate results D411 _{1 to} D411 ₆ (v) supplied from the cyclic shift circuit 411. The previous calculation unit 412 out of the six 6-bit decoding intermediate results D413 _{1 to} D413 ₆ (u _j ), which are supplied from the decoding intermediate result storage memory 413 and are the result of the calculation by the previous calculation unit 412. one decoding intermediate results D413 _k is the calculated result is supplied by its 9-bit decoding intermediate results D411 _k (v) and 6-bit decoding intermediate results D413 _k (u _dv) is supplied to the subtracter 431 The Further, the control signal D419 is supplied from the control unit 417 to the calculator 412 _k , and the control signal D419 is supplied to the selector 435 and the selector 442.

Subtractor 431, 9-bit decoding intermediate results D411 _k (v) from 6-bit decoding intermediate results subtracted D413 _k (u _j), and outputs the 6-bit subtraction value D431 (v _i). That is, the subtractor 431 performs an operation according to the equation (8), and outputs a subtraction value D431 that is the result of the operation.

Of the 6-bit subtraction value D431 output by the subtractor 431, the sign bit D432 (sign (v _i )) indicating the sign of the most significant bit is supplied to the EXOR circuit 440, and the absolute value D433 (| v _i |) is supplied to the LUT 432.

The LUT 432 reads out the 5-bit calculation result D434 (φ (| v _i |)) obtained by performing the calculation of φ (| v _i |) in Expression (7) with respect to the absolute value D433 (| v _i |). To the adder 433 and the FIFO memory 438.

The adder 433 adds the operation result D434 (φ (| v _i |)) and the 9-bit value D435 stored in the register 434, thereby accumulating the operation result D434, and 9 bits obtained as a result. Is stored again in the register 434. Note that when the operation result D434 for the absolute value D433 (| v _i |) obtained from the decoding intermediate result D411 _k corresponding to all 1s in one row of the check matrix H ′ is accumulated, the register 434 is reset. The

When the decoding intermediate result D411 _k for one row of the check matrix H ′ is read one by one and the accumulated value obtained by accumulating the operation result D434 for one row is stored in the register 434, it is supplied from the control unit 417. The control signal D419 changes from 0 to 1. For example, when the row weight is “9”, the control signal D419 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D419 is “1”, the selector 435 obtains the value stored in the register 434, that is, the decoding intermediate result D411 _k (v) corresponding to all 1s over one row of the check matrix H ′. It was φ (| v _i |) 9-bit value that is accumulated D435 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) is selected, as a value D436, and outputs this to the register 436 To store. The register 436 supplies the stored value D436 to the selector 435 and the adder 437 as a 9-bit value D437. When the control signal D419 is “0”, the selector 435 selects the value D437 supplied from the register 436, outputs it to the register 436, and stores it again. That is, until the φ (| v _i |) obtained from the decoding intermediate result D411 _k (v) corresponding to all 1s over one row of the check matrix H ′ is accumulated, the register 436 is accumulated last time. φ (| v _i |) is supplied to the selector 435 and the adder 437.

On the other hand, FIFO memories 438, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D437 from the register 436 until it is output, the result calculation LUT432 has output D434 (phi (| v _i |)) is delayed and supplied to the subtractor 437 as a 5-bit value D438. The subtracter 437 subtracts the value D438 supplied from the FIFO memory 438 from the value D437 supplied from the register 436, and supplies the subtraction result to the LUT 439 as a 5-bit subtraction value D439. In other words, the subtracter 437 determines the branch to be obtained from the integrated value of φ (| v _i |) obtained from the decoding intermediate result D411 _k (v) corresponding to all 1s over one row of the check matrix H ′. The corresponding decoding intermediate result, that is, φ (| v _i |) obtained from the decoding intermediate result D411 _k (v) corresponding to the predetermined 1 of the check matrix H ′ is subtracted, and the subtraction value (i = 1). Σφ (| v _i |) from i to d _c −1) is supplied to the LUT 439 as the subtraction value D439.

The LUT 439 calculates φ ⁻¹ (Σφ (| v _i |)) in Expression (7) for the subtraction value D439 (Σφ (| v _i |) from i = 1 to i = d _c −1). A 5-bit calculation result D440 (φ ⁻¹ (Σφ (| v _i |))) is output.

In parallel with the above processing, the EXOR circuit 440 performs an exclusive OR operation between the 1-bit value D442 stored in the register 441 and the sign bit D432, thereby multiplying the sign bits by 1 The bit multiplication result D441 is re-stored in the register 441. Incidentally, when the sign bits D432 obtained from the decoding intermediate results D411 _k corresponding to all 1 across one line of the parity check matrix H'have been multiplied, the register 441 is reset.

(Paisign from i = 1 to d _c (v _i)) decoding intermediate results multiplied result sign bit D432 obtained is multiplied from D411 D441 corresponding to all 1 across one line of the parity check matrix H'registers When stored in 441, the control signal D419 supplied from the control unit 417 changes from “0” to “1”.

When the control signal D419 is “1”, the selector 442 uses the value stored in the register 441, that is, the code obtained from the decoding intermediate result D411 _k corresponding to all 1s over one row of the check matrix H ′. select (Πsign (v _i) from i = 1 to i = d _c) bit D432 is multiplied value D442, to store and output as 1-bit value D443 to the register 443. The register 443 supplies the stored value D443 to the selector 442 and the EXOR circuit 445 as a 1-bit value D444. When the control signal D419 is “0”, the selector 442 selects the value D444 supplied from the register 443, outputs it to the register 443, and stores it again. That is, until the sign bit D432 obtained from the decoding intermediate result D411 _k (v) corresponding to all 1s in one row of the check matrix H ′ is multiplied, the register 443 stores the previously stored value in the selector 442. And supplied to the EXOR circuit 445.

On the other hand, FIFO memories 444, between (from i = 1 i = Πsign to d _c (v _i)) a new value D444 from the register 443 until is supplied to the EXOR circuit 445 delays the sign bit D432, The 1-bit value D445 is supplied to the EXOR circuit 445. The EXOR circuit 445 calculates the exclusive OR of the value D444 supplied from the register 443 and the value D445 supplied from the FIFO memory 444, thereby dividing the value D444 by the value D445 and dividing by 1 bit. The result is output as the division value D446. That is, the EXOR circuit 445 uses the multiplication value of the sign bit D432 (sign (v _i )) obtained from the decoding intermediate result D411 _k corresponding to all 1s over one row of the check matrix H ′ as the check matrix H ′. Is divided by the sign bit D432 (sign (v _i )) obtained from the decoding intermediate result D411 _k corresponding to predetermined one of Πsign (v from i = 1 to i = d _c −1. _i )) is output as the division value D446.

In the calculator 412 _k , the 5-bit calculation result D440 output from the LUT 439 is set to the lower 5 bits, and a total of 6 bits including the 1-bit division value D446 output from the EXOR circuit 445 as the most significant bit is being decoded. The result is output as D412 _k (u _j ).

As described above, the calculator 412 _k performs the calculations of Expressions (7) and (8), and obtains a decoding intermediate result u _j .

Incidentally, since the maximum weight of the rows of the check matrix H'in FIG. 12 is a 9, i.e., the calculator 412 _k decoding intermediate results supplied to D411 _k (v) decoding intermediate results D413 _k of (u _dv) Since the maximum number is 9, the calculator 412 _k includes nine FIFO memories 438 that delay nine calculation results D434 (φ (| v _i |)) obtained from the nine decoding intermediate results D411 _k , and nine FIFO memory 444 is provided for delaying the sign bit D432. When calculating a message for a row with a row weight less than 9, the amount of delay in the FIFO memory 438 and FIFO memory 444 is reduced to the value of the row weight.

FIG. 23 is a block diagram illustrating a configuration example of the calculator 415 _k of the calculation unit 415 of FIG.

In FIG. 23, it is assumed that each decoding intermediate result D412 _k (D414 _k ) (u _j ) obtained as a result of the first calculation by the calculation unit 412 is quantized into a total of 6 bits including the sign bit, Represents the calculator 415 _k . Further, a high-speed clock CK ₂ is supplied to the calculator 415 _k of FIG. 23, and this high-speed clock CK ₂ is supplied to a necessary block. Each block performs a synchronization and processing the high-speed clock CK _2.

The calculator 415 _{k in} FIG. 23 receives received data D811 _k (u _0i ) read from the receiving memory 416 one by one based on the control signal D422 supplied from the control unit 417 and the cyclic shift circuit 414 to 1 A second calculation according to the equation (5) is performed using the decoding intermediate result D414 _k (u _j ) read one by one.

That is, in the calculator 415 _k , a 6-bit decoding intermediate result D414 _k (u _j ) corresponding to 1 of each row of the check matrix H ′ is read from the cyclic shift circuit 414 one by one, and the decoding intermediate result D414 is read. Is supplied to the adder 471. The calculator 415 _k reads 6-bit reception data D811 _k one by one from the reception memory 416 and supplies the read data D811 _k to the adder 475. Further, the control signal D422 is supplied from the control unit 417 to the calculator 415 _k , and the control signal D422 is supplied to the selector 473.

The adder 471 by adding the decoded intermediate results D414 _k (u _j) a register 472 to store has been has 9-bit value D471, the decoding intermediate result by integrating D414 _k, of 9 bits obtained as a result The integrated value is stored again in the register 472. Incidentally, if the decoding intermediate results D414 _k corresponding to all 1 across one row of the check matrix H'is integrated, the register 472 is reset.

If read in one by one the decoding intermediate results D414 _k across one row of the check matrix H ', the value of the decoding intermediate results D414 _k for one column is accumulated in the register 472 is stored, supplied from the control unit 417 The control signal D422 changes from “0” to “1”. For example, when the column weight is “5”, the control signal D422 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D422 is “1”, the selector 473 accumulates the values stored in the register 472, that is, the decoding intermediate results D414 _k (u _j ) from all the branches over one column of the check matrix H ′. (from j = 1? uj _j to d _V) 9-bit value D471 which is selected and is stored in the output to the register 474. The register 474 supplies the stored value D471 to the selector 473 and the adder 475 as a 9-bit value D472. When the control signal D422 is “0”, the selector 473 selects the value D472 supplied from the register 474, outputs it to the register 474, and stores it again. That is, the register 474 supplies the previously accumulated values to the selector 473 and the adder 475 until the decoding intermediate results D414 _k (u _j ) from all the branches over one column of the check matrix H ′ are accumulated. To do.

The adder 475 adds the 9-bit value D472 and the 6-bit reception data D811 _k supplied from the reception memory 416, and decodes the 6-bit value obtained as a result D415 _k (v) Output as.

As described above, the calculator 415 _k performs the calculation of Expression (5) and obtains a decoding intermediate result v.

Since the maximum weight of the column of the parity check matrix H ′ in FIG. 12 is 5, that is, the maximum number of decoding intermediate results u _j supplied to the calculator 415 _k is 5, the calculator 415 _k is , A maximum of five 6-bit decoding intermediate results u _j are added. Therefore, the output of the calculator 415 _k is a 9-bit value.

  FIG. 24 shows a detailed configuration example of the output unit 812 of FIG.

  The output unit 812 in FIG. 24 includes a decoding result memory 901, a bit width adjustment circuit 902, a deinterleaver 903, a selector 904, and a control unit 905.

In FIG. 24, the decoding result memory 901, the bit width adjustment circuit 902, and the control unit 905 operate with the high-speed clock CK ₂ (CK ₂ > CK ₃ ), and the deinterleaver 903 and the selector 904 operate with the low-speed clock CK _3. Works with. Note that the low-speed clock CK ₁ in FIG. 16 and the low-speed clock CK _{3 in} FIG. 24 may be the same or different.

  Six decoding intermediate results D415 are supplied from the calculation unit 415 (FIG. 23) to the output unit 812 in the order corresponding to the check matrix H ′, and are supplied to the decoding result memory 901.

The decoding result memory 901 is constituted by, for example, a RAM, and can simultaneously write six decoding intermediate results D415 and simultaneously read two decoding results D901. The number of bits in the decoding result memory 901 is a value obtained by multiplying P (= 6) by the number of quantization bits of the decoding intermediate result D415, and the number of words is n / P (= 18). Decoding result memory 901, in synchronism with the high-speed clock CK _2, and writes the decoded intermediate results D415 in the bit direction.

Moreover, the decoding result memory 901, in synchronism with the high-speed clock CK _2, already decoded intermediate results D415 which is stored, based on the control signal D906 supplied from the control unit 905 reads in the bit direction or the word direction, The decoded result D901 is supplied to the bit width adjustment circuit 902.

  Specifically, when the decoding intermediate result D415 obtained using the information component of the reception data D416 is supplied to the decoding result memory 901, the control signal D906 becomes “0” and is obtained using the parity component. When the decoding intermediate result D415 is supplied to the decoding result memory 901, the control signal D906 becomes “1”.

  When the control signal D906 is “0”, the decoding result memory 901 reads the decoding intermediate result D415 in the bit direction. On the other hand, when the control signal D906 is “1”, the decoding result memory 901 reads the decoding intermediate result D415 in the word direction. That is, the decoding intermediate result D415 obtained using the information component is read in the bit direction, and the decoding intermediate result D415 obtained using the parity component is read in the word direction.

When the speed of the high-speed clock CK ₂ is twice or more than the speed of the low-speed clock CK ₃ , the decoding result memory 901 serializes one decoding result D901 in synchronization with, for example, one clock of the high-speed clock CK _2. If the speed of the high-speed clock CK ₂ is less than twice the speed of the low-speed clock CK ₃ , the decoding result memory 901 synchronizes two decoding results D901 in parallel with one clock of the high-speed clock CK _2. Output.

Bit width adjusting circuit 902, in synchronization with the high-speed clock CK _2, based on the control signal D905 from the control unit 905 to adjust the bit width of the decoding result D901 from the decoding result memory 901. Specifically, when the speed of the high-speed clock CK ₂ is less than twice the speed of the low-speed clock CK ₃ , the control signal D905 becomes “0”, and the speed of the high-speed clock CK ₂ is _{2 that is} the speed of the low-speed clock CK _3. When the number is twice or more, the control signal D905 becomes “1”.

When the control signal D905 is "0", the bit width adjustment circuit 902, for example, a high-speed clock CK ₂ for one clock synchronized with the two decoding result supplied in parallel to D901, one clock of the low-speed clock CK ₃ Synchronously, two decoding results D902 are supplied in parallel to the deinterleaver 903 and the selector 904.

On the other hand, when the control signal D905 is "1", the bit width adjustment circuit 902, in synchronization with one clock of the high-speed clock CK ₂ to adjust the bit width of one decoding result D901 supplied to the serial low-speed clock In synchronization with one clock of CK ₃ , two decoding results D901 are supplied to the deinterleaver 903 and the selector 904 in parallel as decoding results D902. That is, the bit width adjustment circuit 902 supplies two decoding results D901 supplied between two clocks of the high-speed clock CK _{2 to} the deinterleaver 903 and the selector 904 in parallel.

Deinterleaver 903, in synchronization with the low-speed clock CK _3, based on the control signal D906 from the control unit 905 controls the order of the two decoding results D902 supplied from the bit width adjustment circuit 902.

  Specifically, when the control signal D906 is “0”, the deinterleaver 903 supplies the two decoding results D902 as they are to the selector 904 as the decoding results D903. On the other hand, when the control signal D906 is “1”, the deinterleaver 903 rearranges the two decoded results D902 in the order corresponding to the check matrix H, and supplies the two decoded results D903 to the selector 904. To do. That is, the deinterleaver 903 controls the order of the decoding results D902 corresponding to the two decoding intermediate results D415 obtained using the parity component of the reception data D416.

The selector 904, in synchronization with the low-speed clock CK _3, based on the control signal D905 from the control unit 905 selects either of the two decoding results D903 from two decoding results D902 or deinterleaver 903 The selected two decoding results D902 or D903 are output as a decoding result D812.

  Specifically, when the control signal D905 is “0”, the selector 904 selects two decoding results D903 from the deinterleaver 903, and when the control signal D905 is “1”, the selector 904 Two decryption results D902 are selected.

Control unit 905, in synchronization with the low-speed clock CK _3, and supplies a control signal D905 to the selector 904. The control unit 905 supplies in synchronism with the high-speed clock CK _2, and supplies the decoding result memory 901 a control signal D906, in synchronization with the low-speed clock CK _3, the control signal D906 to the deinterleaver 903.

  Next, the decoding result memory 901 in FIG. 24 will be described with reference to FIG.

  In FIG. 25, for convenience of explanation, the bit of the decoding result memory 901 will be described on the assumption that the quantization bit of the decoding intermediate result D415 is 1 bit.

In the following, corresponding to the m-th column of the information part of the check matrix H', the decoding intermediate results D415 obtained by using the information component of the received data D416, also represents a decoding intermediate result B _m, the check matrix H' of corresponding to the m-th column of the parity part, a decoding intermediate result D415 to the parity component obtained by using the received data D416, also denoted decoding intermediate result C _m.

  As shown in FIG. 25, the number of bits of the decoding result memory 901 is a value obtained by multiplying P (= 6) by the number of quantization bits of the decoding result D415, and the number of words is n / p (= 18). .

First, the decoding result memory 901 stores the six decoding results B _{0 to} B ₅ supplied from the calculation unit 415 in the bit direction at the 0th to 5th bits of the 0th address, respectively. Next, the decoding result memory 901 stores the six decoding results B _{6 to} B ₁₁ from the calculation unit 415 in the bit direction at the 0th to 5th bits of the first address, respectively.

Thereafter, similarly, the decoding results B _{12 to} B ₇₁ are stored in the 0th to 5th bits of the addresses 2 to 11 (= k ₀ −1) in the decoding result memory 901.

Next, the decoding result memory 901 stores the six decoding results C _{0 to} C ₅ supplied from the calculation unit 415 in the bit direction at the 0th to 5th bits of the 12th address, respectively. Also, the decoding result memory 901 stores the six decoding results C _{6 to} C ₁₁ from the calculation unit 415 in the bit direction at the 0th to 5th bits of the 13th address, respectively. The same processing is repeated, and the decoding results C _{12 to} C ₃₅ are stored in the 0th to 5th bits of the 14th address to the 17th address of the decoding result memory 901.

Here, the decoding result C _m of the 12th to 17th addresses in the order of P × y + x in the bit direction has the order of (n ₀ −k ₀ ) × x + y in the word direction.

As described above, the P × w + v column of the parity part of the parity check matrix H ′ in FIG. 12 is the (n ₀ −k ₀ ) × v + w column of the parity part of the parity check matrix H in FIG. It is. Therefore, the decoding results C _m stored in the bit direction of the decoding result memory 901 corresponding to the 0th column of the parity part of the parity check matrix H ′ in order from the 0th column in the parity matrix are as follows. Corresponding decoding results C _m are obtained in order from the 0th column.

That is, since the decoding apparatus 800 performs the first and second operations using the check matrix H ′, the order of the decoding intermediate results D415 obtained in the order corresponding to the check matrix H ′ is changed to the order corresponding to the check matrix H. Need to be output as a decoding result D812. As described above, the order of the columns of the check matrix H and the check matrix H ′ is the same in the information part, but is different in the parity part. Therefore, the decoding result memory 901 can output the decoding result C _m corresponding to the check matrix H by storing the decoding result C _m in the bit direction and reading it in the word direction.

  FIG. 26 is a diagram illustrating a detailed configuration example of the deinterleaver 903 in FIG.

  The deinterleaver 903 of FIG. 26 is supplied from five registers 921-1 to 921-5, five registers 922-1 to 922-5, and a selector 923.

  The deinterleaver 903 is supplied with two decoding results D902 from the bit width adjustment circuit 902, one of which is stored in the registers 921-1 to 921-5 in turn as a decoding result D921. The other one is sequentially stored in the registers 922-1 to 922-5 as the decoding result D922. The registers 921-1 to 921-5 and the registers 922-1 to 922-5 supply the stored decoding results D921 or D922 to the selector 923, respectively. The two decoding results D902 from the bit width adjustment circuit 902 are directly supplied to the selector 923 as the decoding results D921 or D922, respectively.

  The selector 923 includes five decoding results D921 or D922 supplied from each of the registers 921-1 to 921-5 and the registers 922-1 to 922-5, and a decoding result D921 supplied directly from the bit width adjustment circuit 902 or Any two decoding results D921 or D922 are selected from D922 and output as decoding results D923 and D924. The decoding results D923 and D924 are combined and supplied to the selector 904 as two decoding results D903.

  As described above, in the deinterleaver 903, the registers 921-1 to 921-5 and the registers 922-1 to 922-5 store the input decoding result D902 (decoding result D921 or D922), and the selector 923 The decoding results D902 stored in the registers 921-1 to 921-5 and the registers 922-1 to 922-5 are selected and output as decoding results D903 (decoding results D923 and D924). The order of the decoded result D902 and the output decoded result D903 are switched.

Next, reading of the decoding result C _m from the decoding result memory 901 in FIG. 24 and output of the decoding result D 812 from the output unit 812 will be described with reference to FIGS. 27 and 28. 27 and 28, the horizontal axis represents time.

In the following, the decoding results D812 corresponding to m columns of the parity part of the check matrix H, the decoding result also referred to as E _m.

Figure 27 is a timing chart speed of the high speed clock CK ₂ is described in the case where more than twice the speed of the low-speed clock CK _3, and an output of the read and decoded result E _m of decoding result C _m.

As shown in FIG. 27, the decoding result memory 901, the decoding result C _m which are already stored, in synchronization with one clock of the high-speed clock CK _2, in order from the zeroth bit of the 12th address, one by one word Read in direction. For example, the decoding result memory 901 reads the decoding results C ₀ , C ₆ , C ₁₂ , C ₁₈ , C ₂₄ , C ₃₀ , C ₁ , C ₇ .

Then, the bit width adjustment circuit 902, the two decoding result C _m read sequentially from the decoding result memory 901, in synchronism with one clock of the low-speed clock CK _3, as two decoding results D902, in parallel The deinterleaver 903 and the selector 904 are supplied.

In FIG. 27, since the speed of the high-speed clock CK ₂ is twice or more the speed of the low-speed clock CK ₃ , that is, the control signal D905 supplied from the control unit 905 is 1, the selector 904 includes the bit width adjustment circuit 902. two decoding result D902 from the decoding result E _m, is output as it is.

That is, as shown in FIG. 27, the selector 904 of the output unit 812 sequentially outputs the decoding results E ₀ and E ₆ , E ₁₂ and E ₁₈ , E ₂₄ and E ₃₀ , E ₁ and E _7. Output. Here, as described above, the P × w + v-th column of the parity part of the parity check matrix H ′ in FIG. 12 is (n ₀ −k ₀ ) × v + w in the parity part of the parity check matrix H in FIG. The decoding results E ₀ and E ₆ , E ₁₂ and E ₁₈ , E ₂₄ and E ₃₀ , E ₁ and E ₇ ... Output by the output unit 812 are the parity of the parity check matrix H. It becomes the decoding result D812 corresponding to the 0th column to the 35th column. That is, the output unit 812 includes, in order from the 0th column of the check matrix H, and outputs two by two decoding results E _m for each column of the check matrix H.

As described above, the decoding device 800 outputs simultaneously received data E _m two by two, it is possible to improve the throughput.

FIG. 28 shows the reading of the decoding result C _m from the decoding result memory 901 and the decoding result E _m from the output unit 812 when the speed of the high-speed clock CK ₂ is less than twice the speed of the low-speed clock CK ₃ . It is a timing chart explaining an output.

As shown in FIG. 28, the decoding result memory 901, the decoding result C _m which are already stored, in synchronization with one clock of the high-speed clock CK _2, in order from the 0th bit and the first bit of the 12th address, Read serially in the word direction two by two. For example, the decoding result memory 901 reads the decoding results C ₀ and C ₁ , C ₆ and C ₇ , C ₁₂ and C ₁₃ , C ₁₈ and C ₁₉ .

The decoding result C _m output from the decoding result memory 901 is supplied to the deinterleaver 903 and the selector 904 via the bit width adjustment circuit 902.

In FIG. 28, since the speed of the high-speed clock CK ₂ is less than twice the speed of the low-speed clock CK ₃ , that is, the control signal D905 is “0”, the selector 904 outputs the decoding result supplied from the deinterleaver 903. D903 is output as the decoding result D812.

That is, the decoding result memory 901, to read the decoded results C _m different addresses, that is, decoding a word direction in parallel results can not be read out C _m, the decoding device 800, the deinterleaver 903, the decoding result memory 901 two decoding results read in parallel to control the order of C _m in the bit direction from, via the selector 904, the decoding result corresponding to the two decoding result C _m in parallel in order to be stored in the word direction D812 Is output.

Specifically, the deinterleaver 903 (FIG. 26) includes decoding results C ₀ and C ₁ , decoding results C ₆ and C ₇ , decoding results C ₁₂ and C ₁₃ , decoding results C ₁₈ and C _19. There are input in sequence as a decoding result D902 in parallel, the register 921-1 to 921-5, one of the two decoding result C _m which is input to the parallel as a decoding result D902 (e.g., decoding result C _0, C ₆ , C ₁₂ , C ₁₈ ) are stored as a decoding result D921, and the registers 922-1 to 922-5 store the other (eg, decoding results C ₁ , C ₇ , C ₁₃ , C ₁₉ ) as a decoding result D922. To do. Then, the registers 921-1 to 921-5 and 922-1 to 922-5 supply the decoding result C _m (decoding result D921 or D922) to the selector 923, respectively. The two decoding results D902 are directly supplied to the selector 923 as the decoding results D921 or D922, respectively.

The selector 923 first selects the decoding results C ₀ and C ₆ and outputs them as received data D853 and D854, respectively. Next, the selector 923 selects the decoding results C ₁₂ and C ₁₈ and outputs them as received data D853 and D854, respectively. Thereafter, the selector 923 selects and outputs the decoding results C ₂₄ and C ₃₀ , the decoding results C ₁ and C ₇ .

That is, when one of the two decoding results C _m input in parallel to the deinterleaver 903 is referred to as a sequence # 1 ′ and the other is a sequence # 2 ′, the selector 923 alternately performs in units of 6 parallel inputs. sequence # 1 '(e.g., decoding result _{C 0, C 6, C 12} , C 18, C 24, C 30) and line # 2' (e.g., the decoding result _{C 1, C 7, C 13} , C 19, C ₂₅ , C ₃₁ ), and select and output them in the order of input. That is, the selector 923 selects the received data C _m to be written in the word direction of the decoding result memory 901 two by two and supplies them to the selector 904.

The two decoding results C _m output by the selector 923 of the deinterleaver 903 are output in parallel as two received data E _m via the selector 904.

Specifically, as shown in FIG. 28, the selector 904, in synchronization with the low-speed clock CK _3, the decoded result E ₀ and E _6, E ₁₂ and E _18, E ₂₄ and E _30, E ₁ and E ₇ Are sequentially output in parallel.

As described above, the deinterleaver 903, the decoding result C _m read out to the bit direction from the decoded result memory 901, in the order in which they are stored in the word direction, the output two by two in parallel, the output section 812 , can output the decoded result E _m corresponding to the check matrix H by two in parallel. Thus, the high-speed clock CK ₂ is, when it is less than twice the low-speed clock CK ₃ also, during one clock of the low-speed clock CK _3, it is possible to output two decoded result E _m. As a result, the decoding device 800 can improve the throughput of the decoding device 800 without increasing the speed of the high-speed clock CK ₂ to more than twice the speed of the low-speed clock CK ₃ .

  Next, with reference to FIG. 29, a reception data output process in which the reception unit 811 in FIG. This reception data output processing is started when, for example, two pieces of reception data D416 are supplied to the interleaver 831 and the selector 832 of the reception unit 811.

  In step S31, the interleaver 831 controls the order of the two reception data D416, supplies the two reception data D831 obtained as a result to the selector 832, and proceeds to step S32.

  In step S32, the selector 832 selects either the two reception data D416 or the two reception data D831 supplied in step S31 based on the control signal D835 from the control unit 835, and sets the two reception data D832. The bit width adjustment circuit 833 is supplied.

  After the processing in step S32, the process proceeds to step S33, and the bit width adjustment circuit 833 adjusts the bit widths of the two reception data D832 supplied in step S32 based on the control signal D835 from the control unit 835, The reception data D833 obtained as a result is supplied to the reception memory 834.

  After the process of step S33, the process proceeds to step S34, and the reception memory 834 stores the reception data D833 supplied in step S33 in the bit direction or the word direction based on the control signal D834 from the control unit 835, and performs the process. finish.

  In addition, after all the reception data D833 corresponding to the LDPC code is stored by the process of step S34, the reception memory 834 reads the reception data D833 that has already been stored in the bit direction in units of 6, and as reception data D811 It supplies to the calculation part 415.

  FIG. 30 is a flowchart for explaining the decoding process of the decoding device 800 of FIG. This process is started, for example, when the reception data D811 is supplied to the calculation unit 415.

In step S50, the cyclic shift circuit 414 cyclically shifts six decoding intermediate results D413 (u _j ) stored in step S56 described later supplied from the decoding intermediate result storage memory 413, and calculates the calculation unit 415. To supply.

Specifically, the cyclic shift circuit 414 is supplied with _six decoding intermediate results D413 _{1 to} D413 ₆ from the decoding intermediate result storage memory 413, and corresponds to the decoding intermediate result D413 from the control unit 417. A control signal D421 is supplied that represents information (Matrix data) indicating how many 1s of the parity check matrix H ′ are cyclic shifts of the original unit matrix in the parity check matrix H ′. The cyclic shift circuit 414 cyclically shifts (rearranges) the _six decoding intermediate results D413 _{1 to} D413 ₆ based on the control signal D421, and the calculation results are used as decoding intermediate results D414 _{1 to} D414 ₆ as a calculation unit 415. To supply.

If the first calculation has not yet been performed on the reception data D811 supplied from the reception unit 811 and the decoding intermediate result D412 is not stored in the decoding intermediate result storage memory 413, the calculation unit 415 Sets the decoding intermediate result u _j to an initial value (for example, received data D811).

After the processing of step S50, the process proceeds to step S51, where the calculation unit 415 performs the second calculation and supplies the decoding intermediate results D415 _{1 to} D415 ₆ which are the results of the calculation to the decoding intermediate result storage memory 410.

More specifically, the calculation unit 415, together with the six decoding intermediate results D414 ₁ to D414 ₆ from the cyclic shift circuit 414 is supplied at step S50, from the receiving unit 811 six received data D811 ₁ to D811 ₆ The decoding intermediate results D415 _{1 to} D415 ₆ and received data D811 _{1 to} D811 ₆ are supplied to the calculators 415 _{1 to} 415 ₆ of the calculation unit 415 one by one. Further, a control signal D422 is supplied to the calculation unit 415 from the control unit 417, and the control signal D422 is supplied to the calculators 415 _{1 to} 415 ₆ .

Each calculator 415 _k performs a second calculation according to the equation (5) based on the control signal D422 using the decoding intermediate result D414 _k and the received data D811 _k, and a check matrix H obtained as a result of the calculation. The decoding intermediate result D415 _k (v) corresponding to the column 'is supplied to the decoding intermediate result storage memory 410.

After the process of step S51, the process proceeds to step S52, and the decoding intermediate result storage memory 410 stores the six decoding intermediate results D415 _{1 to} D415 ₆ supplied from the calculation unit 415 in step S51 at the same address. Proceed to S53.

  In step S53, the control unit 417 determines whether all decoding intermediate results D415 corresponding to the columns of the check matrix H ′ have been calculated by the calculation unit 415, and all decoding intermediate results D415 have not been calculated. When it determines, it returns to step S50 and repeats the process mentioned above.

  On the other hand, in step S53, when the control unit 417 determines that all the decoding intermediate results D415 corresponding to the columns of the check matrix H ′ have been calculated by the calculation unit 415, the control unit 417 proceeds to step S54, and the cyclic shift circuit 411 The decoding intermediate result D410 (v) supplied from the decoding intermediate result storage memory 410 is cyclically shifted.

Specifically, the cyclic shift circuit 411 is supplied with six decoding intermediate results D410 from the decoding intermediate result storage memory 410, and from the control unit 417, a check matrix H ′ corresponding to the decoding intermediate result D410. Is supplied with a control signal D418 representing information (Matrix data) indicating how many 1's are cyclically shifted from the original unit matrix in the check matrix H '. The cyclic shift circuit 411 cyclically shifts (rearranges) the six decoding intermediate results D410 based on the control signal D418, and supplies the results as decoding intermediate results D411 _{1 to} D411 ₆ to the calculation unit 412.

After the process of step S54, the process proceeds to step S55, and the calculation unit 412 simultaneously performs the six first calculations as described above with reference to FIG. 22, and the decoding intermediate results D412 _{1 to} D412 that are the calculation results. ₆ is supplied to the decoding result storage memory 413.

After the process of step S55, the process proceeds to step S56, and the decoding intermediate result storage memory 413 stores the six decoding intermediate results D412 _{1 to} D412 ₆ supplied from the calculation unit 412 in step S55 at the same address, Proceed to step S57.

  In step S57, the control unit 417 determines whether or not the decoding intermediate results D412 corresponding to all 1s of the check matrix H ′ have been calculated by the calculation unit 412 and all the decoding intermediate results D412 have not been calculated. When it determines, it returns to step S54 and repeats the process mentioned above.

  On the other hand, when the control unit 417 determines in step S57 that the calculation unit 412 has calculated the intermediate decoding results D412 corresponding to all 1, the processing ends.

  Note that the decoding device 800 repeatedly performs the decoding process of FIG. 30 a predetermined number of times of decoding. Then, the calculation unit 415 supplies the decoding intermediate result D415 obtained as a result of the last second calculation to the output unit 812.

  Note that the decoding apparatus 400 does not repeatedly perform the decoding process of FIG. 30 a predetermined number of times of decoding, but performs a syndrome calculation of the hard decision value of the decoding intermediate result D415, and whether the syndrome obtained as a result is 0, Alternatively, the decoding process may be repeated until the number of decoding times reaches a predetermined number.

  Next, a decoding result output process in which the output unit 812 in FIG. 24 outputs the decoding result D812 will be described with reference to FIG. This decoding result output process is started, for example, when the decoding intermediate result D415 is supplied from the calculation unit 415 to the decoding result memory 901 of the output unit 812.

  In step S71, the decoding result memory 901 stores the decoding intermediate result D415 from the calculation unit 415. Then, based on the control signal D906 from the control unit 905, the decoding result memory 901 reads the decoding intermediate result D415 that is already stored, and supplies it to the bit width adjustment circuit 902 as the decoding result D901.

  After the processing in step S71, the process proceeds to step S72, and the bit width adjustment circuit 902 adjusts the bit width of the decoding result D901 supplied in step S71 based on the control signal D905 from the control unit 905, and obtains the result. The decoded intermediate result D902 is supplied to the deinterleaver 903 and the selector 904.

  After the processing of step S72, the process proceeds to step S73, and the deinterleaver 903 controls the order of the decoding result D902 supplied in step S72 based on the control signal D906 from the control unit 905, and the decoding obtained as a result The result D903 is supplied to the selector 904.

  After the processing in step S73, the process proceeds to step S74, and the selector 904 selects either the decoding result D902 supplied in step S72 or the decoding result D903 supplied in step S73 based on the control signal D905 from the control unit 905. Is selected and output as the decoding result D812, and the process is terminated.

  As described above, the decoding device 800 in FIG. 15 repeatedly decodes the received data D416 input two by two, and outputs two decoding results D812 obtained as a result.

  Note that both input and output to the decoding device 800 are not performed two by two, but only one of them may be performed two by two.

  In the above case, in order to simplify the explanation, the case where P is 6, that is, the case where the number of rows and the number of columns of the constituent matrix constituting the parity check matrix H is given as an example, The number of rows and the number of columns P do not necessarily have to be 6, and may take different values depending on the check matrix H. For example, P may be 360 or 392.

Further, in the decoding device 800 of FIG. 15, the reception data D416 input simultaneously to the reception unit 811 and the decoding result D812 output simultaneously from the output unit 812 are two, but output simultaneously with the reception data D416 input simultaneously. The number N _p of the decoding results D812 to be performed is not limited to this, and can be P or less (for example, a divisor of P). In this case, the speed of the high-speed clock CK _2, based on whether a low-speed clock CK ₁ or CK ₃ speed N _p times, the control signal D835 and D905 are determined.

  Further, although the decoding apparatus 800 in FIG. 15 uses the LDPC code having the code length 108 and the coding rate 2/3, the code length and the coding rate of the LDPC code may be any values. For example, when the number of rows and the number of columns P of the configuration matrix is 6, if the total number of branches is 6 or less, the LDPC code of any code length and coding rate can be used to change the decoding device 800 by simply changing the control signal. And can be decrypted.

  Further, the number of bits and the number of words in the reception memory 834 and the decoding result memory 901 are not limited to the numbers described above.

Furthermore, the present invention can be applied not to the decoding device 800 that alternately performs the first operation and the second operation, but also to a decoding device that alternately performs the check node operation and the variable node operation. In this case, the check node calculator that performs the check node calculation is configured by deleting the subtracter 431 of the calculator 412 _{k in} FIG. 22, and the variable node calculator that performs the variable node calculation is the calculator 415 in FIG. It is constructed by adding a subtracter 431 to the end of _k .

  As described above, in the decoding device 800 of FIG. 15, the reception memory 834 stores the reception data D833 two at a time, and the decoding result memory 901 reads out two decoding results D901 at the same time. Can be improved.

  Further, since the decoding apparatus 800 according to the present invention faithfully implements the thumb product algorithm, no decoding loss other than message quantization occurs.

  Note that the decoding apparatus that decodes the LDPC code described above can be applied to, for example, a tuner that receives (digital) satellite broadcasts.

  Further, in the present specification, the steps describing the processing are not only processing performed in time series in the described order, but also processing executed in parallel or individually even if processing is not necessarily performed in time series. Is also included.

  Furthermore, the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

It is a figure explaining the check matrix H of an LDPC code. It is a figure which shows the check matrix H whose parity part is a lower triangular matrix. It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure explaining the flow of a message. It is a figure which shows the example of the check matrix H of a LDPC code. 6 is a diagram illustrating a Tanner graph of a check matrix H. FIG. It is a figure which shows a variable node. It is a figure which shows a check node. It is a figure which shows the example of the check matrix H of a LDPC code. It is a block diagram which shows the structural example of the decoding apparatus which performs six node calculations simultaneously. It is a figure which shows the example of the test matrix H used for a LDPC code. FIG. 12 is a diagram illustrating a parity check matrix H ′ after row replacement or column replacement of the parity check matrix H in FIG. 11. FIG. 12 is a diagram illustrating a parity check matrix H ′ after row replacement or column replacement of the parity check matrix H in FIG. 11. It is a figure which shows the parity part of the matrix H of FIG. 11, and the check matrix H 'of FIG. It is a figure which shows the structural example of the decoding apparatus which decodes an LDPC code of one embodiment of this invention. FIG. 16 is a block diagram illustrating a detailed configuration example of a receiving unit in FIG. 15. It is a block diagram which shows the detailed structural example of the interleaver of FIG. It is a figure explaining the bit direction and word direction of RAM. It is a figure explaining the reception data memorize | stored in the reception memory of FIG. It is a timing chart explaining the input to the receiving part of FIG. 16, and the writing to a receiving memory. It is a timing chart explaining the input to the receiving part of FIG. 16, and the writing to a receiving memory. It is a block diagram which shows the structural example of the calculator of FIG. It is a block diagram which shows the structural example of the calculator of FIG. It is a block diagram which shows the detailed structural example of the output part of FIG. It is a figure explaining the decoding result memory of FIG. It is a block diagram which shows the detailed structural example of the deinterleaver of FIG. FIG. 25 is a timing chart illustrating reading from the decoding result memory of FIG. 24 and output from the output unit. FIG. 25 is a timing chart illustrating reading from the decoding result memory of FIG. 24 and output from the output unit. It is a flowchart explaining a reception data output process. It is a flowchart explaining a decoding process. It is a flowchart explaining a decoding result output process.

Explanation of symbols

  410 Decoding intermediate result storage memory, 411 cyclic shift circuit, 412 calculation unit, 413 Decoding intermediate result storage memory, 414 cyclic shift circuit, 415 calculation unit, 417 control unit, 800 decoding device, 811 receiving unit, 812 output Unit, 831 interleaver, 832 selector, 833 bit width adjustment circuit, 834 reception memory, 835 control unit, 901 decoding result memory, 902 bit width adjustment circuit, 903 deinterleaver, 904 selector, 905 control unit

Claims (10)

A decoding device for decoding LDPC (Low Density Parity Check) code,
A P × P unit matrix, a quasi-unit matrix that is a matrix in which one or more of 1s that are components of the unit matrix are 0, and a shift matrix that is a cyclic shift of the unit matrix or the quasi-unit matrix , A unit matrix, a quasi-unit matrix, or a sum matrix that is a sum of a plurality of shift matrices, or a P × P 0 matrix, and a parity check matrix of the LDPC code is a combination of a plurality of the constituent matrices Or when the parity check matrix of the LDPC code is represented by a combination of a plurality of the constituent matrices by row or column replacement,
Code storage means for storing the LDPC code;
Decoding means for decoding the LDPC code stored in the code storage means;
A decoding result storage unit that stores a decoding result obtained as a result of decoding by the decoding unit and reads out a decoding result that has already been stored;
The code storage means stores the LDPC code at the same time in a plurality of P pieces or less, or the decoding result storage means reads out the decoding result at a time in a plurality of P pieces or less, or the code storage A means stores the LDPC code at the P number or less at the same time, and the decoding result storage means reads out the decoding result at the P number or less at the same time. The code storage means stores the LDPC code by several divisors of the P simultaneously, the decoding result storage means reads the decoding results by divisors of the P simultaneously, or the code storage means 2. The decoding device according to claim 1, wherein the LDPC code is simultaneously stored in approximately several pieces of the P, and the decoding result storage unit reads out the decoding results in several pieces of the P simultaneously. The code storage means is composed of a memory that can simultaneously read and write about several LDPC codes of the P,
The decoding device according to claim 2, wherein the decoding result storage unit is configured by a memory capable of simultaneously reading and writing the approximately several P decoding results. Compared to the operation clock of the first external device that inputs the LDPC code to the code storage means and the second external device that outputs the decoding result read from the decoding result storage means, the decoding device, The decoding device according to claim 3, wherein the operation is performed with a high-speed operation clock. The decoding apparatus according to claim 4, wherein the code storage unit stores the LDPC codes corresponding to the P columns of the parity check matrix after the row or column replacement in an order that can be read simultaneously. The code storage means is a RAM (Random Access Memory), and stores the LDPC code corresponding to the P columns of the parity check matrix after replacement of the row or column at each address of the RAM. 5. The decoding device according to 5. The order control means for controlling the order of at least one of the LDPC code before being stored in the code storage means or the decoding result after being read out from the decoding result storage means. Decoding device. The order control means includes
Order code storage means for storing the LDPC code;
The decoding apparatus according to claim 7, further comprising selection means for selecting and outputting the LDPC code stored in the order code storage means. The order control means includes
Ordered decoding result storage means for storing the decoding result;
The decoding device according to claim 7, further comprising selection means for selecting and outputting the decoding result stored in the ordered decoding result storage means. A decoding method of a decoding device for decoding LDPC (Low Density Parity Check) code,
A P × P unit matrix, a quasi-unit matrix that is a matrix in which one or more of 1s that are components of the unit matrix are 0, and a shift matrix that is a cyclic shift of the unit matrix or the quasi-unit matrix , A unit matrix, a quasi-unit matrix, or a sum matrix that is a sum of a plurality of shift matrices, or a P × P 0 matrix, and a parity check matrix of the LDPC code is a combination of a plurality of the constituent matrices Or when the parity check matrix of the LDPC code is represented by a combination of a plurality of the constituent matrices by row or column replacement,
A code storage step for storing the LDPC code;
A decoding step of decoding the LDPC code stored by the processing of the code storage step;
A decoding result storage step of storing a decoding result obtained as a result of decoding by the processing of the decoding step and reading out a decoding result that has already been stored;
Whether the code storing step stores the LDPC code at the P number or less simultaneously, or the decoding result storing step reads the decoding result at the P number or less simultaneously. Alternatively, the processing of the code storage step stores the LDPC code at the P number or less at the same time, and the processing of the decoding result storage step reads the decoding result at the time of the P or less at the same time. Method.

Images