JP4780027B2 - Decoding device, control method, and program - Google Patents

Description

  The present invention relates to a decoding device, a control method, and a program, and more particularly, for example, a decoding device, a control method, and a program that can reduce the scale of a decoding device that decodes an LDPC (Low Density Parity Check) code. About.

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, encoding methods that exhibit performance close to the Shannon limit include, for example, so-called turbo codes such as parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC). A technique called Turbo coding has been developed. While these turbo codes are being developed, low density parity check codes (hereinafter referred to as LDPC codes), which is an encoding method that has been known for a long time, are attracting attention.

  The LDPC code was first proposed in RG Gallager's "RG Gallager," Low Density Parity Check Codes ", Cambridge, Massachusetts: MIT Press, 1963" and then "DJC MacKay," Good error correcting codes based on very sparse matrices ", Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999" and "MG Luby, M. Mitzenmacher, MA Shokrollahi and DA Spielman," Analysis of low density codes and improved designs using irregular graphs ", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998".

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

  The LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse. Here, the sparse matrix is configured so that the number of “1” of the matrix components is very small. If the sparse check matrix is represented by H, such a check matrix H is as follows: For example, as shown in FIG. 1, the hamming weight (number of “1” s) (weight) of each column is “3”, and the hamming weight of each row is “6”.

  Thus, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is not constant is referred to as an irregular LDPC code.

Such an LDPC code encoding is realized by generating a generator matrix G based on the check matrix H and generating a codeword by multiplying the binary information message by the generator matrix G. . Specifically, the encoding device which performs encoding by LDPC codes, first, between the transposed matrix H ^T of the parity check matrix H, calculates a generator matrix G which formula GH ^T = 0 is established. Here, when the generator matrix G is a k × n matrix, the encoding device multiplies the generator matrix G by an information message (vector u) consisting of k bits, and a codeword c consisting of n bits. (= UG) is generated. The codeword generated by this encoding device is transmitted after being mapped such that the sign bit having a value of “0” is “+1”, the sign bit having a value of “1” is “−1”, and the like. The signal is received on the receiving side via a predetermined communication path.

  On the other hand, decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which is a variable node (also called a message node) and a check node (check node). ) And a message passing algorithm based on belief propagation on a so-called Tanner graph. Here, hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

  However, in probabilistic decoding, since the message passed between each node is a real value, in order to solve it analytically, it is necessary to track the probability distribution of the message that takes consecutive values. This requires analysis with difficulty. Therefore, Gallager has proposed algorithm A or algorithm B as a decoding algorithm for LDPC codes.

The decoding of the LDPC code is performed, for example, according to a procedure as shown in FIG. Note that here, the i-th received data of the LDPC code having a code length is U ₀ (u _0i ), and the j-th message output from the check node (the j-th branch connected to the check node) U _j ) and the i-th message output from the variable node (message output from the i-th branch connected to the variable node) as v _i . Further, here, the message is a real value representing a so-called log likelihood ratio or the like representing the value of “0” of the value.

First, in decoding of an LDPC code, as shown in FIG. 2, in step S11, received data U ₀ (u _0i ) is received, a message u _j is initialized to “0”, and a counter for repetition processing is performed. The variable k taking an integer is initialized to “0”, and the process proceeds to step S12. In step S12, using the received data U ₀ (u _0i ), a message v _i is obtained by performing a variable node calculation shown in equation (1), and further using this message v _i , equation (2) The message u _j is obtained by performing the check node calculation shown in FIG.

・・・（１）

... (1)

・・・（２）

... (2)

Here, d _v and d _c in Equation (1) and Equation (2) are the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, that is, the column weight ( This is a parameter that can be arbitrarily selected indicating the Hamming weight) and the row weight. For example, in the case of the (3, 6) code, d _v = 3 and d _c = 6.

Note that in the calculation of the expression (1) or (2), the message input from the edge to which the message is to be output is not used as the target of the sum or product operation. The range of operation is 1 to d _v -1 or 1 to d _c -1. In addition, in the calculation shown in the equation (2), a table of the function R (v ₁ , v ₂ ) shown in the equation (3) in which 1 is obtained for two inputs v ₁ and v ₂ is created in advance. This can be done by using it continuously (recursively) as shown in equation (4).

・・・（３）

... (3)

・・・（４）

... (4)

  In step S12, the variable k is further incremented by “1”, and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is equal to or greater than a predetermined iterative decoding count N. If it is determined in step S13 that the variable k is not equal to or greater than N, the process returns to step S12, and thereafter the same process is repeated.

  If it is determined in step S13 that the variable k is greater than or equal to N, the process proceeds to step S14, and the message v as a decoding result that is finally output by performing the calculation shown in Expression (5) is obtained. The LDPC code decoding process is completed.

・・・（５）

... (5)

Here, unlike the operation of equation (1), the operation of equation (5) is performed using messages u _j from all branches connected to the variable node.

In decoding of such an LDPC code, for example, in the case of (3, 6) code, messages are exchanged between the nodes as shown in FIG. In FIG. 3, a node indicated by “=” (equal) represents a variable node, and the variable node calculation shown in Expression (1) is performed. In FIG. 3, a node indicated by “+” (plus) represents a check node, and the calculation of the check node shown in Expression (2) is performed. In particular, in algorithm A, the message is binarized and an exclusive OR operation is performed on d _c −1 input messages (messages v _i input to the check node) at the check node indicated by “+”. , “=” In the variable node indicated by “=”, when d _v −1 input messages (message u _j input to the variable node) are all different bit values for the received data R Is inverted and output.

  In recent years, research has also been conducted on implementation methods for decoding LDPC codes. Before describing the mounting method, first, decoding of an LDPC code will be schematically described.

  FIG. 4 is an example of a parity check matrix H of an LDPC code (coding rate 1/2, code length 12) of a (3, 6) code. The parity check matrix H of the LDPC code can be written using a Tanner graph as shown in FIG. Here, in FIG. 5, “+” represents a check node, and “=” represents a variable node. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix, respectively. The connection between the check node and the variable node is an edge and corresponds to “1” of the parity check matrix H. That is, when the component in the j-th row and the i-th column of the parity check matrix is 1, the i-th variable node ("=" node) from the top and the j-th check node ("from the top) in FIG. + "Node") are connected by a branch. The branch indicates that the bit of the LDPC code (received data) corresponding to the variable node has a constraint condition corresponding to the check node. 5 is a Tanner graph of the parity check matrix H in FIG.

  The Sum Product Algorithm, which is an LDPC code decoding method, repeatedly performs a variable node operation and a check node operation.

In the variable node, as shown in FIG. 6, the variable node calculation of Expression (1) is performed. That is, in FIG. 6, the message v _i corresponding to the i-th branch among the branches connected to the variable node is received with the messages u ₁ and u ₂ from the remaining branches connected to the variable node. Calculated using data u _0i . Messages corresponding to other branches are similarly calculated.

  Before explaining the operation of the check node, the expression (2) is changed to the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b). And rewrite as equation (6). However, sign (x) is 1 (logic 0) when x ≧ 0, and -1 (logic 1) when x <0.

・・・（６）

... (6)

Furthermore, when x ≧ 0, the nonlinear function φ (x) = − ln (tanh (x / 2)) is defined, and the inverse function φ ⁻¹ (x) is expressed by the equation φ ⁻¹ (x) = 2 tanh ⁻¹ Since it is expressed by (e ^−x ), Expression (6) can be written as Expression (7).

・・・（７）

... (7)

In the check node, as shown in FIG. 7, the calculation of the check node of Expression (7) is performed. That is, in FIG. 7, the message u _j corresponding to the j-th branch among the branches connected to the check node is the messages v ₁ , v ₂ , v ₃ , from the remaining branches connected to the check node. Calculated using v ₄ and v ₅ . Messages corresponding to other branches are similarly calculated.

The function φ (x) can also be expressed as φ (x) = ln ((e ^x +1) / (e ^x −1)). When x> 0, φ (x) = φ ⁻¹ ( x), that is, the calculation result of the nonlinear function φ (x) and the calculation result of the inverse function φ ⁻¹ (x) are the same. When the functions φ (x) and φ ⁻¹ (x) are implemented in hardware, they may be implemented using a LUT (Look Up Table), but both are the same LUT.

  Further, the variable node calculation of Expression (1) can be divided into Expression (5) and the following Expression (8).

・・・（８）

... (8)

  Therefore, it is possible to repeatedly perform the calculation of the variable node of Expression (1) and the calculation of the check node of Expression (7) by repeatedly performing the calculations of Expression (5), Expression (8), and Expression (7). it can. In this case, the result of the calculation of Expression (5) among the calculations of the variable nodes of Expression (5) and Expression (8) can be used as the final decoding result as it is.

  When the thumb product algorithm is implemented in hardware and used as a decoding device, the variable node calculation (variable node calculation) and the expression (1) (or (5) and (8)) It is necessary to repeat the check node calculation (check node calculation) represented by 7) with an appropriate circuit scale and operating frequency.

  As an example of implementation of a decoding device, a method of implementing full serial decoding in which decoding is performed by simply performing operations of each node one by one will be described.

  FIG. 8 illustrates a configuration example of a decoding device that decodes an LDPC code.

  In the decoding device of FIG. 8, a message corresponding to one branch is calculated for each clock of the operation clock.

  8 includes a message calculation unit 101, a message memory 104, a reception data memory 105, and a control unit 106. The message calculation unit 101 includes a variable node calculator 102 and a check node calculator 103.

  In the decoding device of FIG. 8, messages are read one by one from the message memory 104 to the message calculation unit 101, and the message calculation unit 101 uses the messages to calculate a message corresponding to a desired branch. Then, the message obtained by the calculation is stored in the message memory 104. In the decoding apparatus of FIG. 8, the above process is repeatedly performed, so-called iterative decoding is performed.

  That is, the reception data memory 105 is supplied with reception data (LDPC code) D100, which is a log likelihood ratio representing the likelihood of 0 (or 1) of the code obtained by receiving the transmitted LDPC code, The reception data memory 105 stores (stores) the reception data D100.

  At the time of variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 106, and supplies it to the variable node calculator 102 of the message calculation unit 101 as reception data D101.

Further, at the time of variable node calculation, the message memory 104 reads the stored message (check node message u _j ) D102 according to the control signal supplied from the control unit 106, and supplies it to the variable node calculator 102. The variable node calculator 102 uses the message D102 supplied from the message memory 104 and the reception data D101 supplied from the reception data memory 105 to perform the variable node calculation of Expression (1) and obtains the result of the variable node calculation. The message (variable node message) v _i is supplied to the message memory 104 as a message D103.

  The message memory 104 stores the message D103 supplied from the variable node calculator 102 as described above.

On the other hand, at the time of a check node calculation, the message memory 104 in accordance with the control signal supplied from the control unit 106, the variable node message v _i that is stored, read as a message D104, and supplies to the check node calculator 103.

The check node calculator 103 uses the message D104 supplied from the message memory 104 to perform a check node calculation of Expression (7), and a message (check node message) u _j obtained by the check node calculation is displayed as a message. The data is supplied to the message memory 104 as D105.

  The message memory 104 stores the message D105 supplied from the check node calculator 103 as described above.

The message D105 from the check node calculator 103 stored in the message memory 104, that is, the check node message u _j is read as a message D102 and supplied to the variable node calculator 102 at the time of the next variable node calculation.

  FIG. 9 shows a configuration example of the variable node calculator 102 of FIG. 8 that performs variable node operations one by one.

  The variable node calculator 102 has two input ports P101 and P102 as input ports to which messages (data) are supplied (input) from the outside, and one output as a port to supply (output) messages to the outside. It has a port P103. Then, the variable node calculator 102 performs the variable node calculation of Expression (1) using the messages input from the input ports P101 and P102, and outputs the resulting message from the output port P103.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the message D102 (check node message u _j ) read from the message memory 104 is supplied to the input port P102.

In the variable node calculator 102, the message D102 (message u _j ) from the check node corresponding to each row of the check matrix is read one by one from the input port P102, and the message D102 is supplied to the calculator 151 and the FIFO memory 155. Is done. In the variable node calculator 102, the reception data D 101 is read from the reception data memory 105 one by one from the input port P 101 and supplied to the calculator 157.

The arithmetic unit 151 adds the message D102 (message u _j ) and the value D151 stored in the register 152 to integrate the message D102, and re-stores the obtained integrated value in the register 152. Note that when the messages D102 from all branches over one column of the check matrix are accumulated, the register 152 is reset to zero.

When the message D102 over one column of the check matrix is read one by one and the value obtained by accumulating the message D102 for one column is stored in the register 152, that is, all over the one column of the check matrix are stored in the register 152. When the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D102 (message u _j ) from the branch is stored, the selector 153 stores the value stored in the register 152, that is, select the message from all of the branches across one row of the parity check matrix D102 (message u _j) the accumulated integrated values D151 (? uj _j from j = 1 to d _v), is stored in output register 154 .

The register 154 supplies the stored value D151 as the value D152 to the selector 153 and the calculator 156. The selector 153 selects the value D152 supplied from the register 154, outputs it to the register 154, and stores it again until the value obtained by integrating the message D102 for one column is stored in the register 152. That is, until the message D102 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 154 supplies the previously accumulated value to the selector 153 and the calculator 156.

On the other hand, FIFO memories 155, between (from j = 1? Uj _j to d _v) a new value D152 from the register 154 until the output delays the message D102 from the check node, calculator 156 as a value D153 To supply. The computing unit 156 subtracts the value D153 supplied from the FIFO memory 155 from the value D152 supplied from the register 154. That is, the arithmetic unit 156 determines the message u from the branch to be obtained from the integrated value (Σu _j from j = 1 to d _v ) of the message D102 (message u _j ) from all the branches over one column of the check matrix. _j is subtracted and the subtraction value (Σu _j from j = 1 to d _v −1) is obtained and supplied to the calculator 157.

The computing unit 157 adds the reception data D101 from the input port P101 and the subtraction value (Σu _j from j = 1 to d _v −1) from the computing unit 156, and sends the resulting addition value to the message D103. (Message v _i ) is output from the output port P103.

As described above, the variable node calculator 102 performs the variable node calculation (v _i = u _oi + Σu _j ) of Expression (1), and the message (variable node message) v _i obtained as a result is output port P103. Is output from.

  FIG. 10 shows a configuration example of the check node calculator 103 in FIG. 8 that performs check node operations one by one.

  The check node calculator 103 has one input port P111 as an input port to which a message (data) is supplied (input) from the outside, and one output port P112 as a port to supply (output) a message to the outside. have. Then, the check node calculator 103 performs the check node calculation of Expression (7) using the message input from the input port P111, and outputs the resulting message from the output port P112.

That is, the message D104 (variable node message v _i ) read from the message memory 104 is supplied to the input port P111.

In the check node calculator 103, the message D104 (message v _i ) from the variable node corresponding to each column of the check matrix is read one by one from the input port P111, and the lower bits excluding the most significant bit, that is, the message D104. the absolute value of D122 (| v _i |) is supplied to a LUT 121, the most significant bit, i.e., the sign bit D121 (bit representing the sign) messages D104, EXOR circuit 129 and FIFO (First in First Out) memory 133 respectively.

The LUT 121 is an LUT that outputs the calculation result of the nonlinear function φ (x) in the check node calculation of Expression (7) using the value input thereto as an argument x, and supplies the absolute value D122 (| v _i |) On the other hand, the calculation result D123 (φ (| v _i |)) obtained by calculating the nonlinear function φ (| v _i |) is read and supplied to the calculator 122 and the FIFO memory 127.

The arithmetic unit 122 adds the calculation result D123 (φ (| v _i |)) and the value D124 stored in the register 123 to integrate the calculation result D123, and the integrated value obtained as a result is registered in the register 123. Store again. Note that when the operation result D123 (φ (| v _i |)) for the absolute value D122 (| v _i |) of the message D104 from all branches over one row of the check matrix is accumulated, the register 123 is set to 0. Reset.

When the message D104 over one row of the check matrix is read one by one and the accumulated value obtained by integrating the operation result D123 for one row is stored in the register 123, the selector 124 stores the value stored in the register 123. , i.e., phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D124 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 125 as the value D125 for storage. The register 125 supplies the stored value D125 to the selector 124 and the calculator 126 as the value D126.

The selector 124 selects the value D126 supplied from the register 125, outputs it to the register 125, and stores it again until the integrated value obtained by integrating the operation results D123 for one row is stored in the register 123. That is, until φ (| v _i |) obtained from the message D104 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 125 accumulates φ (| v _i |) is supplied to the selector 124 and the calculator 126.

On the other hand, FIFO memories 127, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D126 from the register 125 until it is output, the result calculation LUT121 has output D123 (phi (| v _i |)) is delayed and supplied to the computing unit 126 as a value D127. The arithmetic unit 126 subtracts the value D127 supplied from the FIFO memory 127 from the value D126 supplied from the register 125, and supplies the subtraction result to the LUT 128 as a subtraction value D128. That is, the arithmetic unit 126, phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) integrated value from (i = 1 to i = d _c of Σφ (| v _i |)) from, obtained from the message (message v _i of i = d _c) from a desired branch phi (| v _i |) is subtracted, the subtraction value (i = 1 Σφ (| v _i |) from i to d _c −1) is supplied to the LUT 128 as a subtraction value D128.

The LUT 128 is an LUT that outputs a calculation result of the inverse function φ ⁻¹ (x) of the nonlinear function φ (x) in the check node calculation of Expression (7) using the value input thereto as an argument x. For the supply of the subtracted value D128 from 126 (Σφ (| v _i |) from i = 1 to i = d _c −1), the inverse function φ ⁻¹ (Σφ (| v _i |)) is calculated. The operation result D129 (φ ⁻¹ (Σφ (| v _i |))) is output.

As described above, since the calculation result of the nonlinear function φ (x) and the calculation result of the inverse function φ ⁻¹ (x) for the same argument x are equal, the LUTs 121 and 128 are LUTs having the same configuration. ing.

  In parallel with the above processing, the EXOR circuit 129 calculates the exclusive OR of the value D131 stored in the register 130 and the sign bit (bit representing positive / negative) D121, thereby sign bit D121 of the message D104. The multiplication is performed, and the multiplication result D130 is stored again in the register 130. When the sign bit D121 of the message D104 from all branches over one row of the check matrix is multiplied, the register 130 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix stored in the register 130, the selector 131, Paisign the value stored in the register 130, i.e., the value D131 (i = 1 the sign bit D121 of the message D104 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 132 as the value D132 for storage. The register 132 supplies the stored value D132 to the selector 131 and the EXOR circuit 134 as the value D133.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix until just before is stored in the register 130 The selector 131 selects the value D133 supplied from the register 132, outputs it to the register 132, and stores it again. That is, the register 132 supplies the previously stored value to the selector 131 and the EXOR circuit 134 until the sign bit D121 of the message D104 (message v _i ) from all branches over one row of the check matrix is multiplied. .

On the other hand, FIFO memories 133, between (from i = 1 i = Πsign to d _c (v _i)) a new value D133 from the register 132 until is supplied to the EXOR circuit 134 delays the sign bit D121, The 1-bit value D134 is supplied to the EXOR circuit 134. The EXOR circuit 134 calculates the exclusive OR of the value D133 supplied from the register 132 and the value D134 supplied from the FIFO memory 133, thereby dividing the value D133 by the value D134 and dividing the division result. Output as value D135. That is, the EXOR circuit 134 calculates the multiplication value of the sign bit D121 (sign (v _i )) of the message D104 from all the branches over one row of the check matrix, and the sign bit D121 (sign of the message D104 from the branch to be obtained. (v _i )), and the division value (Πsign (v _i ) from i = 1 to i = d _c −1) is output as the division value D135.

Then, in the check node calculator 103, a bit string having the operation result D129 output from the LUT 128 as the lower bits and the division value D135 output from the EXOR circuit 134 as the most significant bit (sign bit) is a message D105 (message u _j ) is output from the output port P112.

As described above, the check node calculator 103 performs the calculation of Expression (7) to obtain the message (check node message) u _j .

  Although not shown, in the decoding apparatus of FIG. 8, the final stage of decoding (for example, variable node calculation performed at the last of variable node calculation and check node calculation performed for a predetermined number N of repeated decoding) In, instead of the variable node calculation of Expression (1), the calculation of Expression (5) is performed, and the calculation result is output as the final decoding result.

  8, the message memory 104 (FIG. 8), the FIFO memory 155 of the variable node calculator 102 (FIG. 9), and the FIFO memories 127 and 133 of the check node calculator 103 (FIG. 10) are sufficient. If so, LDPC codes of various parity check matrices can be decoded.

  Next, FIG. 11 is a timing chart showing message read / write timing with respect to the message memory 104 of the decoding apparatus of FIG.

In the decoding apparatus of FIG. 8, at the time of variable node calculation, a message (check node message) u _j from the check node is read from the message memory 104, and the variable node calculator 102 of the message calculation unit 101 is read from the message memory 104. A variable node operation is performed using the read message u _j , while a message (variable node message) v _i obtained as a result of the variable node operation is written in the message memory 104.

Further, during the check node calculation, a message (variable node message) v _i is read from the message memory 104, and the check node calculator 103 of the message calculation unit 101 reads the message read from the message memory 104. While performing a check node operation using v _i , a message (check node message) u _j obtained as a result of the check node operation is written to the message memory 104.

  Therefore, in the decoding apparatus of FIG. 8, the message is read from the message memory 104 and the variable node calculation or the check node calculation using the message (either the variable node calculation or the check node calculation). Hereinafter, it is necessary to simultaneously write a message obtained as a result of the above (simply referred to as a node operation).

  For this reason, the message memory 104 includes, for example, one RAM (Random Access Memory) #A as one bank (memory bank) and one other RAM #B as another bank, By accessing each of RAM # A and RAM # B, the message memory 104 can be apparently accessed at the same time.

  The timing chart of FIG. 11 represents the read / write timing for each of RAM # A and RAM # B constituting the message memory 104.

  In FIG. 11, first, it is necessary to obtain a message corresponding to a branch of a certain check node or variable node (hereinafter, collectively referred to as “node”) node # 1 from RAM #A. A message is read (R (node # 1)), and a node operation is performed using the message. Then, the message corresponding to the branch of the node node # 1 (the branch connected to the node node # 1) obtained as a result of the node calculation is written to the RAM # A at the same time as (W (node # 1)) From RAM # B, a message required to obtain a message corresponding to the branch of the next node node # 2 is read (R (node # 2)), and node calculation is performed.

  Further, a message corresponding to the branch of the node node # 2 obtained as a result of the node operation is written to the RAM # B (W (node # 2)), and at the same time, the next node node # 3 is read from the RAM # A. A message necessary to obtain a message corresponding to the branch of the node is read (R (node # 3)), and a node operation is performed. Thereafter, in the same way, reading and writing of messages to and from RAM #A and RAM #B constituting the message memory 104 are performed.

  In the decoding apparatus of FIG. 8, when decoding an LDPC code by iterative decoding in which check node calculation and variable node calculation are alternately performed, one decoding (one set of check node calculation and variable node calculation) is performed. In addition, the number of clocks is twice as many as the number of messages, and a high-speed operation is required.

  Thus, for the LDPC code of a specific parity check matrix, by providing a plurality of p message calculators 101, messages are simultaneously obtained for p nodes, and one decoding is performed in the case of the decoding apparatus of FIG. There has been proposed a decoding device that can be operated at a clock number of 1 / p, that is, a decoding device that can operate at an operation frequency that is not so high (for example, see Patent Document 1).

JP 2004-364233 A

By the way, as described above, the variable node calculator 102 (FIG. 9) constituting the message calculation unit 101 has the FIFO memory 155 that delays messages until the integration of the messages in the arithmetic unit 151 and the register 152 is completed. Is provided. Similarly, the check node calculator 103 (FIG. 10) also has a FIFO memory 127 that delays the message (value obtained from) φ (| v _i |) until the integration in the arithmetic unit 122 and the register 123 is completed. And a FIFO memory 133 that delays the message (its sign bit) until the calculation of the synergistic product of the sign bits in the EXOR circuit 129 and the register 130 is completed. As described above, a decoding device that decodes an LDPC code requires a memory for delaying a message (data) by temporarily storing a message used for variable node calculation or check node calculation.

Here, in the variable node calculator 102 (FIG. 9), as the message accumulation in the arithmetic unit 151 and the register 152, the message accumulation is performed for the number of branches connected to the variable node. FIFO memory 155 for delaying a message until the end of at least a message by the number of branches, i.e., required to have a capacity capable of storing a message number equal to the maximum value of the weight d _v column of the check matrix There is.

Further, in the check node calculator 103 (FIG. 10), as the integration in the arithmetic unit 122 and the register 123, the message (the value obtained from the number of branches) connected to the check node (value obtained from the number) φ (| v _i | ) Is performed, the FIFO memory 127 that delays the message (value obtained from it) φ (| v _i |) until the integration is completed is at least the number of messages corresponding to the number of branches, that is, the inspection. It is necessary to have a capacity capable of storing a number of messages (value obtained from) φ (| v _i |) equal to the maximum value of the matrix row weights d _c .

Further, in the check node calculator 103 (FIG. 10), as the multiplication in the EXOR circuit 129 and the register 130, the message (the sign bit) is multiplied by the number of branches connected to the check node. FIFO memory 133 for delaying the message (sign bit) to the multiplication is completed, at least, the message of the number of its branches, that is, equal to the number of messages to the maximum value of the weight d _c line of the check matrix (the code Bit)).

  As described above, a decoding device that decodes an LDPC code requires a memory for delaying a message. Furthermore, in particular, in order to operate a decoding device that decodes an LDPC code having a large number of nodes at an operation frequency that is not so high, the decoding device is required to obtain a plurality of messages for a plurality of nodes in parallel. It is necessary to provide and configure the message calculation unit 101. In this case, a memory for delaying the message is further required, and the decoding apparatus becomes large-scale.

  The present invention has been made in view of such a situation, and makes it possible to reduce the scale of a decoding apparatus that decodes an LDPC code.

A decoding device according to one aspect of the present invention is a decoding device that decodes an LDPC (Low Density Parity Check) code, and stores a variable node calculation for decoding the LDPC code or a message used for a check node calculation. Using the storage means and the message stored in the storage means, based on the parity check matrix defining the LDPC code, performs the variable node calculation or the check node calculation, and outputs a message obtained as a result of the calculation Message calculation means, and the message calculation means includes a delay memory that is delayed by temporarily storing a message used for the variable node calculation or the check node calculation, and the delay memory includes the check storing fewer messages than the maximum value of the weight of the matrix, the message calculation means output Control means for performing write control for writing a message to the storage means, and read control for reading the same message used in the calculation in the message calculation means twice from the storage means and supplying the message to the message calculation means; Selecting means for selecting one of the message delayed in the delay memory and the message read out for the second time from the storage means as a message used in the variable node calculation or the check node calculation; The selection means further includes the delay memory when the column weight of the parity check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory in the operation of the variable node. The delayed message is selected and the weight of the column is recorded in the delay memory. When it is not less than the number of memorable messages, the second message read from the storage means is selected, and in the check node calculation, the row weight of the check matrix corresponding to the check node is Select a message delayed in the delay memory when the delay memory is less than or equal to the number of messages that can be stored, and store when the weight of the row is not less than or equal to the number of messages that the delay memory can store This is a decryption device that selects a message read from the means for the second time.

In the decoding device according to one aspect, using the message stored in the storage unit that stores the message, based on the parity check matrix that defines the LDPC code, the variable node or the check node is calculated, In a delay memory that is delayed by temporarily storing a message, which is included in the message calculation means for outputting a message obtained as a result of the operation, a number of messages smaller than the maximum value of the weight of the check matrix are stored. Further, the same message used for the write control for writing the message output from the message calculation means to the storage means and the calculation in the message calculation means is read twice from the storage means and supplied to the message calculation means. Read control is performed. A message that selects one of the message delayed in the delay memory and the message read out from the storage means for the second time as a message used for the variable node calculation or the check node calculation. In the calculation of the variable node, when the weight of the column of the check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory in the calculation of the variable node, the message delayed in the delay memory Is selected and the message read out the second time from the storage means is selected when the weight of the column is not less than or equal to the number of messages that can be stored in the delay memory. In the check node calculation, when the weight of the row of the check matrix corresponding to the check node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected. When the weight of the row is not less than or equal to the number of messages that can be stored in the delay memory, the second message read from the storage means is selected.

  The control method or program according to one aspect of the present invention is a control method for controlling a decoding device that decodes an LDPC (Low Density Parity Check) code, or a program that is executed by a computer that controls the decoding device. A storage means for storing a message used for variable node computation or check node computation for decoding the LDPC code, and a test for defining the LDPC code using the message stored in the storage means A message calculation means for performing an operation of the variable node or an operation of the check node based on a matrix and outputting a message obtained as a result of the operation, wherein the message calculation means is the operation of the variable node or the check It has a delay memory that delays by temporarily storing messages used for node operations, When the delay memory stores a number of messages smaller than the maximum value of the weight of the parity check matrix, write control for writing the message output by the message calculation means to the storage means, and calculation by the message calculation means The same message used in the above is read from the storage means twice and supplied to the message calculation means, and in the variable node calculation, the column weight of the check matrix corresponding to the variable node is Selecting a message delayed in the delay memory when the delay memory is less than or equal to the number of messages that can be stored, and when the weight of the column is not less than or equal to the number of messages that the delay memory can store; Select the message read from the storage means the second time, and check the check node In the operation, when the row weight of the check matrix corresponding to the check node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected, and the row weight is selected. When the delay memory is not less than or equal to the number of messages that can be stored, the message delayed by the delay memory and 2 from the storage means so as to select the message read from the storage means for the second time. A control method including a step of controlling selection means for selecting one of the messages read out for the second time as a message used for the calculation of the variable node or the calculation of the check node, or the control process to the computer It is a program to be executed.

  In the control method or program according to one aspect, the write control for writing the message output from the message calculation unit to the storage unit and the same message used for the calculation in the message calculation unit are stored in the storage unit. Reading is performed twice, and reading control to be supplied to the message calculation means is performed. In the variable node calculation, when the weight of the column of the check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected. When the weight of the column is not less than or equal to the number of messages that can be stored in the delay memory, a message read out from the storage means for the second time is selected, and in the check node calculation, When the corresponding row weight of the check matrix is less than or equal to the number of messages that can be stored in the delay memory, a message delayed in the delay memory is selected, and the row weight is stored in the delay memory. Select to select the second message read from the storage means when not less than the number of possible messages Stage is controlled.

  According to one aspect of the present invention, the scale of a decoding device that decodes an LDPC code can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  As described above, in a decoding device that decodes an LDPC code, a message for delaying a message (for example, the FIFO memory 155 of FIG. 9) is temporarily stored by storing a message used for variable node calculation or check node calculation. (FIG. 9) and the FIFO memories 127 and 133 in FIG. 10 are required. First, a decoding apparatus that does not require such a memory will be described.

  FIG. 12 is a block diagram illustrating a configuration example of a decoding device that does not require a memory for delaying a message.

  In the figure, portions corresponding to those of the decoding device of FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the decoding device of FIG. 12 is different from the decoding device of FIG. 8 except that a message calculation unit 171 is provided instead of the message calculation unit 101 and a control unit 174 is provided instead of the control unit 106. It is constituted similarly.

  The decoding apparatus in FIG. 12 repeatedly performs full serial decoding in the same manner as the decoding apparatus in FIG.

  12 includes a message memory 104, a reception data memory 105, a message calculation unit 171, and a control unit 174. The message calculation unit 171 includes a variable node calculator 172 and a check node calculator 173.

  In the decoding device of FIG. 12, messages are read one by one from the message memory 104, and a message corresponding to a desired branch is calculated by the message calculation unit 171 using the messages. Then, the message obtained by the calculation is stored in the message memory 104. In the decoding device of FIG. 12, iterative decoding is performed by repeatedly performing the above processing.

  That is, the reception data memory 105 is supplied with reception data (LDPC code) D100, which is a log likelihood ratio representing the likelihood of 0 (or 1) of the code obtained by receiving the transmitted LDPC code, The reception data memory 105 stores (stores) the reception data D100.

  At the time of variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 174, and supplies it as reception data D101 to the variable node calculator 172 of the message calculation unit 171.

At the time of variable node calculation, the message memory 104 reads the same stored message twice according to the control signal supplied from the control unit 174 (variable node message v output from the variable node of interest). Check node message necessary to obtain _i (check node message from the check node connected to the variable node of interest) u _j is read twice, and the first read message is message D102 Is supplied to the variable node calculator 172, and the second read message is supplied as a message DD102 to the variable node calculator 172. The variable node calculator 172 uses the messages D102 and DD102 supplied from the message memory 104 and the reception data D101 supplied from the reception data memory 105 to perform the variable node calculation of Expression (1), and performs the variable node calculation. A message (variable node message) v _i obtained as a result is supplied to the message memory 104 as a message D103.

  Then, the message memory 104 stores (writes) the message D103 supplied from the variable node calculator 172 in accordance with the control signal supplied from the control unit 174.

On the other hand, during the check node calculation, the message memory 104 reads the same stored message (variable node message v _i ) twice according to the control signal supplied from the control unit 174 (from the check node of interest). Variable node message necessary to obtain the output check node message u _j (variable node message from the variable node connected to the check node of interest) v _i is read twice, first time The message read out in (1) is supplied to the check node calculator 173 as a message D104, and the message read out second time is supplied as a message DD104 to the check node calculator 173.

The check node calculator 173 performs a check node operation of Expression (7) using the messages D104 and DD104 supplied from the message memory 104, and determines a message (check node message) u _j obtained by the check node operation. The message D105 is supplied to the message memory 104.

  Then, the message memory 104 stores (writes) the message D105 supplied from the check node calculator 173 in accordance with the control signal supplied from the control unit 174.

The message D105 from the check node calculator 173 stored in the message memory 104, that is, the check node message u _j is read out as messages D102 and DD102 and supplied to the variable node calculator 172 at the next variable node calculation. .

  FIG. 13 shows a configuration example of the variable node calculator 172 of FIG.

  In the figure, portions corresponding to the variable node calculator 102 in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

  The variable node calculator 172 is configured without a memory (FIFO memory 155 provided in the variable node calculator 102 in FIG. 9) for delaying a message.

  However, the variable node calculator 172 has three input ports P101, P102, and PD102 as input ports to which a message (data) is supplied (input) from the outside.

  The reception data D101 read from the reception data memory 105 is supplied (input) to the input port P101. The input port P102 is supplied (input) with the message D102 read out the first time out of the same message D102 and DD102 read out twice from the message memory 104, and read out into the input port PD102 the second time. Message DD102 is provided.

  The check node calculator 173 performs a variable node calculation of Expression (1) based on a check matrix that defines an LDPC code to be decoded, using messages input from the input ports P101, P102, and PD102, The resulting message is output from the output port P103.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the message D102 (check node message u _j ) read from the message memory 104 is supplied to the input port P102.

In the variable node calculator 172, the message D102 from the check node corresponding to each row of the check matrix, that is, the message u _j read from the message memory 104 for the first time is input one by one from the input port P102. The message D102 is supplied to the calculator 151.

  In the variable node calculator 172, the reception data D 101 is read from the reception data memory 105 one by one from the input port P 101 and supplied to the calculator 157.

The arithmetic unit 151 adds the message D102 (message u _j ) and the value D151 stored in the register 152 to integrate the message D102, and re-stores the obtained integrated value in the register 152. Note that when the messages D102 from all branches over one column of the check matrix are accumulated, the register 152 is reset.

When the message D102 over one column of the check matrix is read one by one and the value obtained by accumulating the message D102 for one column is stored in the register 152, that is, all over the one column of the check matrix are stored in the register 152. When the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D102 (message u _j ) from the branch is stored, the selector 153 stores the value stored in the register 152, that is, select the message from all of the branches across one row of the parity check matrix D102 (message u _j) the accumulated integrated values D151 (? uj _j from j = 1 to d _v), is stored in output register 154 .

The register 154 supplies the stored value D151 as the value D152 to the selector 153 and the calculator 156. The selector 153 selects the value D152 supplied from the register 154, outputs it to the register 154, and stores it again until the value obtained by integrating the message D102 for one column is stored in the register 152. That is, until the message D102 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 154 supplies the previously accumulated value to the selector 153 and the calculator 156.

On the other hand, upon output of a new value from the register 154 D152 (? Uj _j from j = 1 to d _v) is started, namely, the integrated value message D102 is integrated for one column in the register 152 (j = 1 Immediately after storing Σu _j ) to d _v , the variable node calculator 172 stores the same message DD102 as the message D102 (message u _j ), that is, the message u read from the message memory 104 for the second time. _j are input one by one from the input port PD102, and the message DD102 is supplied to the computing unit 156.

The arithmetic unit 156 subtracts the message DD102 from the input port PD102 from the integrated value D152 supplied from the register 154. That is, the message of the calculator 156, the message D102 from all edges over one row of the parity check matrix (? Uj _j from j = 1 to d _v) integrated value D152 of (message u _j) from a desired branch The message DD102 as u _j (j = d _v u _j ) is subtracted to obtain a subtraction value (Σu _j from j = 1 to d _v −1), which is supplied to the calculator 157.

The computing unit 157 adds the reception data D101 from the input port P101 and the subtraction value (Σu _j from j = 1 to d _v −1) from the computing unit 156, and sends the resulting addition value to the message D103. (Message v _i ) is output from the output port P103.

As described above, the variable node calculator 172 performs the variable node calculation of Expression (1), and the message (variable node message) v _i obtained as a result is output from the output port P103.

  FIG. 14 shows a configuration example of the check node calculator 173 of FIG.

  In the figure, portions corresponding to the check node calculator 103 in FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The check node calculator 173 is configured without providing a memory for delaying data (FIFO memories 127 and 133 provided in the check node calculator 103 in FIG. 10).

  However, the check node calculator 173 has two input ports P111 and PD111 as input ports to which a message (data) is supplied (input) from the outside.

  The message D104 read out the first time out of the same message D104 and DD104 read out twice from the message memory 104 is supplied (input) to the input port P111, and the message DD104 read out second time is supplied to the input port PD111. Is supplied.

  The check node calculator 173 performs the check node calculation of Expression (7) based on the check matrix that defines the LDPC code to be decoded using the messages input from the input ports P111 and PD111, and obtains the result. Output message is output from the output port P112.

That is, the message D104 (variable node message u _j ) read from the message memory 104 is supplied to the input port P111.

Then, in the check node calculator 173, the message D104 (message v _i ) from the variable node corresponding to each column of the check matrix is input one by one from the input port P111, and the lower bits excluding the most significant bit, that is, The absolute value D122 (| v _i |) of the message D104 is supplied to the LUT 121, and the most significant bit, that is, the sign bit D121 of the message D104 is supplied to the EXOR circuit 129.

The LUT 121 stores the calculation result of the nonlinear function φ (x), and the calculation result D123 (φ that performs the calculation of the nonlinear function φ (| v _i |) using the absolute value D122 (| v _i |) as an argument. (| v _i |)) is read out and supplied to the computing unit 122.

The arithmetic unit 122 adds the calculation result D123 (φ (| v _i |)) and the value D124 stored in the register 123 to integrate the calculation result D123, and the integrated value obtained as a result is registered in the register 123. Store again. Note that when the calculation result D123 (φ (| v _i |)) for the absolute value D122 (| v _i |) of the message D104 from all branches over one row of the check matrix is accumulated, the register 123 is reset. The

When the message D104 over one row of the check matrix is read one by one and the accumulated value obtained by integrating the operation result D123 for one row is stored in the register 123, the selector 124 stores the value stored in the register 123. , i.e., phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D124 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 125 for storage as the integrated value D125. The register 125 supplies the stored integrated value D125 to the selector 124 and the calculator 126 as a value D126.

The selector 124 selects the value D126 supplied from the register 125, outputs it to the register 125, and stores it again until the integrated value obtained by integrating the operation results D123 for one row is stored in the register 123. That is, until φ (| v _i |) obtained from the message D104 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 125 accumulates φ (| v _i |) is supplied to the selector 124 and the calculator 126.

On the other hand, (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) a new value D126 from the register 125 when the output of the start, that is, the operation result D123 is integrated for one row in the register 125 have been (from i = 1 to _{i = d c Σφ (| v} i |)) integrated value immediately after the stored, in the check node calculator 173, messages D104 (message v _i) the same messages DD104, i.e. , The message v _i read from the message memory 104 for the second time is input one by one from the input port PD104, and the lower-order bits of the message DD104 excluding the most significant bit, that is, the absolute value of the message DD104 ( | v _i |) is supplied to the LUT 135, and the most significant bit, that is, the sign bit of the message DD 104 is supplied to the EXOR circuit 134.

The LUT 135 is the same LUT as the LUT 121, and the calculation result (φ (| v _i |)) obtained by calculating the nonlinear function φ (| v _i |) using the absolute value (| v _i |) of the message DD104 as an argument. Is supplied to the calculator 126.

The calculator 126 subtracts the calculation result (φ (| v _i |)) from the LUT 135 from the value D126 supplied from the register 125, and supplies the subtraction result to the LUT 128 as a subtraction value D128. That is, the arithmetic unit 126, phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) integrated value from (i = 1 to i = d _c Σφ (| v _i |)) of the desired branch, subtract φ (| v _i |) obtained from message DD104 as message v _i (i = d _c v _i ) from the branch to be obtained. The value (Σφ (| v _i |) from i = 1 to i = d _c −1) is supplied to the LUT 128 as the subtraction value D128.

The LUT 128 is an LUT similar to the LUT 121 or 135 that stores the calculation result of the inverse function φ ⁻¹ (x), and the subtraction value D 128 (i = 1 to i = d _c −1) from the calculator 126. of Σφ (| v _i |) a) as an argument, the inverse function _{^{φ -1 (Σφ (| v i}} |) a)) calculates the calculation result of the ^{D129 () φ -1 (Σφ (} | | v i) Output.

  In parallel with the above processing, the EXOR circuit 129 calculates the exclusive OR of the value D131 stored in the register 130 and the sign bit (bit representing positive / negative) D121, thereby multiplying the sign bits. The multiplication result D130 is stored again in the register 130. When the sign bit D121 of the message D104 from all branches over one row of the check matrix is multiplied, the register 130 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix stored in the register 130, the selector 131, Paisign the value stored in the register 130, i.e., the value D131 (i = 1 the sign bit D121 of the message D104 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 132 as the value D132 for storage. The register 132 supplies the stored value D132 to the selector 131 and the EXOR circuit 134 as the value D133.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix until just before is stored in the register 130 The selector 131 selects the value D133 supplied from the register 132, outputs it to the register 132, and stores it again. That is, the register 132 supplies the previously stored value to the selector 131 and the EXOR circuit 134 until the sign bit D121 of the message D104 (message v _i ) from all branches over one row of the check matrix is multiplied. .

On the other hand, a new value from the register 132 D133 (from i = 1 to _{i = d c Πsign (v i} )) when is supplied to the EXOR circuit 134, i.e., from all of the branches across one line to the register 130 when the sign bit D121 of the message D104 is multiplied value D131 to (Paisign of i = 1 through _{i = d c (v i)} ) are stored, as described above, the register 125, the operation of one line result D123 is integrated integrated values (from i = 1 to _{i = d c Σφ (| v} i |)) is stored.

Integration value calculation result D123 is integrated for one row in the register 125 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) When is stored, as described above, the check node calculator At 173, the same message DD104 as the message D104 (message v _i ), that is, the message v _i read from the message memory 104 for the second time is input one by one from the input port PD104, and the message DD104 The low-order bits excluding the most significant bit, that is, the absolute value (| v _i |) of the message DD104 is supplied to the LUT 135, and the most significant bit, that is, the sign bit of the message DD104 is supplied to the EXOR circuit 134. .

The EXOR circuit 134 calculates the exclusive OR of the value D133 supplied from the register 132 and the sign bit of the message DD104 from the input port PD104, thereby dividing the value D133 by the sign bit of the message DD104, The division result is output as a division value D135. That, EXOR circuit 134, branches multiplication value of the sign bit D121 of the message D104 from all of the branches across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v i)} ), to be obtained is divided by the sign bit of the message DD104 serving as the message v _i from (i = d _c of sign (v _i)), Πsign of the division value from (i = 1 to _{i = d c -1 (v i} ) ) Is output as the division value D135.

Then, in the check node calculator 173, a bit string having the operation result D129 output from the LUT 128 as the lower bit and the division value D135 output from the EXOR circuit 134 as the most significant bit (sign bit) is a message D105 (message u _j ) is output from the output port P112.

As described above, in the check node calculator 173, the calculation of Expression (7) is performed, and the message (check node message) u _j is obtained.

  Although not shown, in the decoding device of FIG. 12, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1), and the calculation result is the final decoding. Output as a result.

  Next, with reference to a flowchart of FIG. 15, a description will be given of a process of reading / writing messages (data) to / from the message memory 104 by the control unit 174 of the decoding apparatus of FIG.

  Note that, hereinafter, a message input to a node, which is used to obtain a message at a node as appropriate, is referred to as an input message, and a message obtained and output at the node using an input message is referred to as an output message. .

  In step S101, the control unit 174 outputs an input message necessary for obtaining an output message (message output from a branch connected to the target node) output from a target node (target node), that is, The message memory 104 is controlled so that the message input from the branch connected to the node of interest is read and supplied to the message calculation unit 171 (the input message is read for the first time), and step S102 is performed. Proceed to

  In step S102, the control unit 174 reads the same input message read from the message memory 104 in the immediately preceding step S101, and supplies it to the message calculation unit 171 (so that the input message is read for the second time). ), The message memory 104 is controlled, and the process proceeds to step S103.

  That is, in steps S101 and S102, the same input message used for the calculation (check node calculation or variable node calculation) in the message calculation unit 171 is read from the message memory 104 twice and supplied to the message calculation unit 171. Is done.

  In step S103, the control unit 174 writes the message memory 104 so that the message calculation unit 171 writes the output message obtained by performing the calculation using the input message read from the message memory 104 in steps S101 and S102. Control.

  That is, in step S103, write control is performed to write the output message to be output to the message memory 104 by the message calculation unit 171 performing the calculation of Expression (1) or Expression (7).

  Then, returning from step S103 to step S101, the control unit 174 sets another node as a new attention node, reads out an input message necessary to obtain an output message output from the new attention node, and calculates a message. The message memory 104 is controlled so as to be supplied to the unit 171, and the same processing is repeated thereafter.

  As described above, the message memory 104 has a two-bank configuration of RAM # A and RAM # B, and the control unit 174 is described with reference to FIG. 15 for each of the RAM # A and RAM # B. Read / write control.

  That is, FIG. 16 is a timing chart showing message read / write timing with respect to the message memory 104 of the decoding apparatus of FIG.

  The timing chart of FIG. 16 represents the read / write timing for each of the RAM # A and RAM # B constituting the message memory 104, as in the timing chart of FIG.

  In FIG. 16, first, an input message necessary for obtaining an output message from a certain node node # 1 is read from RAM # A for the first time (R1 (node # 1)). After the reading is finished, the input message necessary to obtain the output message from node node # 1 is read from RAM # A for the second time (R2 (node # 1)) and the next An input message necessary for obtaining an output message from the node node # 2 is read from the RAM # B for the first time (R1 (node # 2)).

  When the second read from the RAM #A of the input message required to obtain the output message from the node node # 1 is completed, and the message calculation unit 171 obtains the output message from the node node # 1, The output message from node node # 1 is written to RAM # A (W (node # 1)), and at the same time, the input message required to obtain the output message from node node # 2 is output from RAM # B. Is read for the second time (R2 (node # 2)).

  When the second read from the RAM #B of the input message necessary to obtain the output message from the node node # 2 is completed and the message calculation unit 171 obtains the output message from the node node # 2, The output message from that node node # 2 is written to RAM # B (W (node # 2)), and at the same time, the input message required to obtain the output message from the next node node # 3, RAM # The first reading from A is performed (R1 (node # 3)).

  When the output message from node node # 2 is written to RAM # B and the input message necessary to obtain the output message from node node # 3 is read from RAM # A for the first time, node The input message required to obtain the output message from node # 3 is read from RAM # A for the second time (R2 (node # 3)) and output from the next node node # 4 An input message necessary to obtain a message is read from RAM # B for the first time (R1 (node # 4)).

  When the second reading from the RAM #A of the input message required to obtain the output message from the node node # 3 is completed and the message calculation unit 171 obtains the output message from the node node # 3, The output message from the node node # 3 is written to the RAM # A (W (node # 3)), and at the same time, the input message required to obtain the output message from the node node # 4 is output from the RAM # B. Is read for the second time (R2 (node # 4)).

  Thereafter, in the same way, reading and writing of messages to and from RAM #A and RAM #B constituting the message memory 104 are performed.

  According to the decoding device of FIG. 12, the input message necessary for obtaining the output message in the message calculation unit 171 is read twice from the message memory 104, so that the input message is received inside the message calculation unit 171. Therefore, the message calculation unit 171 can store the memory only for delaying data (the FIFO memory 155 provided in the variable node calculator 102 in FIG. 9 and the check node calculator 103 in FIG. 10). It is possible to configure without providing the provided FIFO memories 127 and 133). As a result, the scale of the decoding device can be reduced.

  It should be noted that, without providing a memory only for delaying data (hereinafter referred to as a delay memory as appropriate), the same input message is read twice from the message memory 104. Comparing the timing (FIG. 16) with the read / write timing of the message memory 104 (FIG. 11) in the decoding apparatus of FIG. 8 that provides a delay memory and reads the input message from the message memory 104 only once. In addition, the decoding device of FIG. 12 takes about 1.5 times as long as the decoding device of FIG. 8 to read / write a message to / from the message memory 104 for obtaining an output message from a certain node. To perform iterative decoding the same number of times as It is required to operate only at a high speed amount that takes time to read and write di (requiring high-speed operation clock).

  However, in particular, for all the nodes, the output message for the decoding device that performs full parallel decoding that performs the operation for obtaining the output message simultaneously (in parallel), and for p nodes that are not all but one. When a decoding device that performs partial parallel decoding (for example, decoding described in Patent Document 1) that simultaneously performs operations for obtaining a delay memory is provided, a large number of delay memories are required. It greatly affects the scale.

  In such a decoding device, as in the decoding device of FIG. 12, by adopting a configuration that eliminates the need for a delay memory by reading the same input message twice from the message memory 104 and obtaining an output message, the decoding device However, in order to compensate for this, it is possible to obtain an extremely large reduction effect on the scale of the apparatus.

  In this specification, for the sake of simplicity, a full serial decoding device will be described. However, the configuration and processing method of the decoding device described below, including the decoding device of FIG. The present invention can be applied to a decoding device that performs decoding and a decoding device that performs partial parallel decoding. When applied to such a decoding device, a particularly large reduction effect of the device scale can be obtained.

  As described above, according to the decoding device of FIG. 12, the message calculation unit 171 reads the input message necessary (identical) for obtaining the output message twice from the message memory 104, so that the message calculation unit 171 Since it is not necessary to delay the input message internally, a delay memory (a FIFO memory 155 provided in the variable node calculator 102 in FIG. 9 and a FIFO memory 127 provided in the check node calculator 103 in FIG. 10) is used. 133) becomes unnecessary, but it takes about 1.5 times as long as that of the decoding device of FIG. 8 to read and write the message to and from the message memory 104 for obtaining the output message.

  Furthermore, in the decoding apparatus of FIG. 12 that does not require a delay memory, if the weight of the check matrix that defines the LDPC code to be decoded is small with respect to the time required for the calculation in the message calculation unit 171, the message It takes more time to read and write messages to the memory 104.

  That is, for a message (output message) output from a certain branch connected to a node, an output message will be obtained from the integrated value of messages (input messages) input from all branches connected to that node. When the weight of the check matrix is small with respect to the time required for the calculation in the message calculation unit 171, that is, for the message memory 104. When the number of messages read and written is small, for example, the input message to be subtracted from the integrated value of the input messages input from all branches connected to the node can be read from the message memory 104. However, it is necessary to wait for the input message to be read out until the integrated value is obtained. There is Rukoto. In addition, although an output message can be written to the message memory 104, it may be necessary to wait for the output message to be written until the output message is requested.

  As described above, when a time for waiting for reading / writing of a message to / from the message memory 104 occurs, as a result, it takes more time to read / write the message to / from the message memory 104.

  If it takes time to read / write messages to / from the message memory 104, the time required for one decoding also increases, and the number of times that it is possible to perform iterative decoding decreases accordingly, and the decoding performance deteriorates (the decoding result Reliability will be reduced).

  Accordingly, a decoding device that can suppress degradation in decoding performance while reducing the scale will be described.

  That is, FIG. 17 is a block diagram illustrating a configuration example of the first embodiment of the decoding device to which the present invention has been applied.

  In the figure, portions corresponding to those of the decoding device of FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the decoding apparatus of FIG. 12 is different from the decoding apparatus of FIG. 12 except that a message calculation unit 181 is provided instead of the message calculation unit 171 and a control unit 184 is provided instead of the control unit 174. It is constituted similarly.

  The decoding device in FIG. 17 repeatedly performs full serial decoding in the same manner as the decoding device in FIG.

  17 includes a message memory 104, a reception data memory 105, a message calculation unit 181 and a control unit 184. The message calculation unit 181 includes a variable node calculator 182 and a check node calculator 183.

  In the decoding device of FIG. 17, messages are read one by one from the message memory 104, and the message calculation unit 181 uses the messages to determine a desired branch based on a parity check matrix that defines an LDPC code to be decoded. A message corresponding to is calculated. Then, the message obtained by the calculation is stored in the message memory 104. In the decoding device in FIG. 17, iterative decoding is performed by repeatedly performing the above processing.

  That is, the reception data memory 105 is supplied with reception data (LDPC code) D100, which is a log likelihood ratio representing the likelihood of 0 (or 1) of the code obtained by receiving the transmitted LDPC code, The reception data memory 105 stores (stores) the reception data D100.

  At the time of variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 184, and supplies it to the variable node calculator 182 of the message calculation unit 181 as reception data D101.

Further, during the variable node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 184, and the message read first time as the message D102. Then, the message is supplied to the variable node calculator 182 and the second read message is supplied to the variable node calculator 182 as a message DD102. The variable node calculator 182 uses the message D102 read from the message memory 104 for the first time and the reception data D101 supplied from the reception data memory 105, and further read from the message memory 104 for the second time. The message DD102 is used as necessary to perform the variable node calculation of Expression (1), and the message (variable node message) v _i obtained as a result of the variable node calculation is supplied to the message memory 104 as the message D103. To do.

  The message memory 104 stores (writes) the message D103 supplied from the variable node calculator 182 in accordance with the control signal supplied from the control unit 184.

On the other hand, at the time of the check node calculation, the message memory 104 reads the same stored message (variable node message v _i ) once or twice according to the control signal supplied from the control unit 184, and the first time The read message is supplied to the check node calculator 183 as a message D104, and the second read message is supplied to the check node calculator 183 as a message DD104.

The check node calculator 183 uses the message D104 read out from the message memory 104 for the first time, and further uses the message DD104 read out from the message memory 104 for the second time as necessary, using the formula ( The check node calculation of 7) is performed, and a message (check node message) u _j obtained by the check node calculation is supplied to the message memory 104 as a message D105.

  The message memory 104 stores (writes) the message D105 supplied from the check node calculator 183 in accordance with the control signal supplied from the control unit 184.

The message D105 from the check node calculator 183 stored in the message memory 104, that is, the check node message u _j is read out as the message D102 (and further the message DD102) at the time of the next variable node calculation, and the variable node calculator 182.

  In the decoding device of FIG. 17, the control unit 184 performs read / write control similar to that of the control unit 174 of the decoding device of FIG. 12, as described in the flowchart of FIG. Control as needed.

  Further, the control unit 184 supplies the control signal C104 to the message calculation unit 181 to control the variable node calculator 182 and the check node calculator 183 constituting the message calculation unit 181.

  Here, the variable node calculator 182 performs the variable node calculation of Expression (1) by selectively using the message DD102 read from the message memory 104 for the second time in accordance with the control signal C104 from the control unit 184. . The check node calculator 183 also performs the check node calculation of Expression (7) by selectively using the message DD104 read out from the message memory 104 a second time in accordance with the control signal C104 from the control unit 184.

  FIG. 18 shows a configuration example of the variable node calculator 182 of FIG.

  In the figure, portions corresponding to those of the variable node calculator 102 of FIG. 9 or the variable node calculator 172 of FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The variable node calculator 182 includes a small FIFO memory 161 as a delay memory for delaying a message, and a selector 162.

  Similar to the FIFO memory 155 of FIG. 9, the small FIFO memory 161 is delayed by temporarily storing the message D102 read out from the message memory 104 for the first time as a message from the check node.

However, although the FIFO memory 155 of FIG. 9 has a capacity capable of storing at least a number of messages equal to the maximum value of the column weights d _v of the parity check matrix, the small FIFO memory 161 only has the capacity to store messages for fewer than the maximum value of the weight d _v column (1 or a).

  Therefore, the small FIFO memory 161 has a smaller capacity than the FIFO memory 155 and is therefore small in scale.

  The small FIFO memory 161 delays the message D102 read from the message memory 104 for the first time and supplies it to the f terminal of the selector 162.

  The selector 162 has an f terminal and an m terminal as input terminals, and the message D102 delayed by the small FIFO memory 161 is supplied to the f terminal as described above. Further, the message DD102 read from the message memory 104 for the second time is supplied to the m terminal of the selector 162.

  Furthermore, the control signal C104 is supplied to the selector 162 from the control unit 184 (FIG. 17).

  In accordance with the control signal C104 from the control unit 184, the selector 162 uses one of the message D102 delayed in the small FIFO memory 161 and the message read out from the message memory 104 for the second time as a variable node calculation. The message to be used is selected and supplied to the calculator 156 as a value D153.

  The variable node calculator 182 has an input port P104 in addition to the input ports P101, P102, PD102, and a control signal C104 from the control unit 184 is supplied to the selector 162 via the input port P104. Is done.

  In addition, when the weight of the column of the parity check matrix corresponding to the variable node to which the branch for which the message is to be obtained is connected is equal to or less than the number of messages that can be stored in the small FIFO memory 161, the control unit 184 A signal for instructing the selector 162 to select the message D102 delayed in the memory 161 is supplied to the variable node calculator 182 as the control signal C104.

  Furthermore, when the weight of the column corresponding to the variable node is not equal to or less than the number of messages that can be stored in the small FIFO memory 161, the control unit 184 selects the message DD102 read from the message memory 104 for the second time. A signal instructing the selector 162 is supplied to the variable node calculator 182 as the control signal C104.

  Here, when the control unit 184 supplies the variable node calculator 182 with the control signal C104 that instructs the selector 162 to select the message D102 delayed in the small FIFO memory 161, that is, the control signal C104 is: When it is not a signal for instructing the selector 162 to select the message DD102 read for the second time from the message memory 104, the message is read from the message memory 104 only once for reading the message from the message memory 104. Read control is performed.

  Therefore, in the case where the weight of the check matrix column corresponding to the variable node to which the branch for which the message is to be obtained is connected is not less than or equal to the number of messages that can be stored in the small FIFO memory 161, the control unit 184 The readout control for reading the same message twice from the message memory 104 described in 15 is performed, but the column weight of the parity check matrix corresponding to the variable node to which the branch for which the message is sought is connected is small FIFO. If the number of messages that can be stored in the memory 161 is less than or equal to the number of messages that can be stored, the read control for reading the same message from the message memory 104 twice is not performed, and the read control for reading only once, that is, the steps S101 and S102 in FIG. Of these, only step S101 is performed.

  The variable node calculator 182 configured as described above performs the variable node calculation of Expression (1) using the messages input from the input ports P101, P102, and PD102 as necessary, and is obtained as a result. The message is output from the output port P103.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the message D102 (check node message u _j ) read from the message memory 104 is supplied to the input port P102.

In the variable node calculator 182, the message D102 from the check node corresponding to each row of the check matrix, that is, the message u _j read out from the message memory 104 for the first time is input one by one from the input port P102. The message D102 is supplied to the calculator 151 and the small FIFO 161.

  Further, the variable node calculator 182 reads the received data D101 from the received data memory 105 one by one from the input port P101 and supplies it to the calculator 157.

The arithmetic unit 151 adds the message D102 (message u _j ) and the value D151 stored in the register 152 to integrate the message D102, and re-stores the obtained integrated value in the register 152. Note that when the messages D102 from all branches over one column of the check matrix are accumulated, the register 152 is reset.

When the message D102 over one column of the check matrix is read one by one and the value obtained by accumulating the message D102 for one column is stored in the register 152, that is, all over the one column of the check matrix are stored in the register 152. When the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D102 (message u _j ) from the branch is stored, the selector 153 stores the value stored in the register 152, that is, select the message from all of the branches across one row of the parity check matrix D102 (message u _j) the accumulated integrated values D151 (? uj _j from j = 1 to d _v), is stored in output register 154 .

The register 154 supplies the stored value D151 as the value D152 to the selector 153 and the calculator 156. The selector 153 selects the value D152 supplied from the register 154, outputs it to the register 154, and stores it again until the value obtained by integrating the message D102 for one column is stored in the register 152. That is, until the message D102 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 154 supplies the previously accumulated value to the selector 153 and the calculator 156.

On the other hand, upon output of a new value from the register 154 D152 (? Uj _j from j = 1 to d _v) is started, namely, the integrated value message D102 is integrated for one column in the register 152 (j = 1 Immediately after storing Σu _j ) to d _v , the variable node calculator 182 stores the same message DD102 as the message D102 (message u _j ), that is, the message u read from the message memory 104 for the second time. _j is input one by one from the input port PD102, and the message DD102 is supplied to the m terminal of the selector 162.

The small FIFO memory 161 is delayed for a message D102 read from the message memory 104 to first (from j = 1? Uj _j to d _v) a new value D152 from the register 154 until the output And supplied to the f terminal of the selector 162.

Here, if the number of messages that can be stored in the small FIFO memory 161 is d ₁ , the small FIFO memory 161 is smaller than the maximum value of the column weight d _v of the parity check matrix as described above. because only the capacity for storing the number of messages does not have to register 154, the parity check matrix, the integrated value of d _v number of messages D102 corresponding to a certain one column (? uj _j from j = 1 to d _v) is stored, until it is outputted from the register 154, in a small FIFO memory 161, it may not be possible to delay d _v number of messages D102 corresponding to the one row.

That is, the number d ₁ of messages that can be small FIFO memory 161 stores is the column of the check matrix corresponding to the variable nodes d _v number of message D102 that integrated value in the register 152 is stored is input weight d _In the case where it is smaller than _v , in the small FIFO memory 161, when d ₁ + _1st message is stored out of d _v messages D102 corresponding to the column, the first FIFO memory 161 Since the message is output, until the accumulated value of d _v messages D102 larger than the number d ₁ of messages that can be stored in the small FIFO memory 161 is output in the register 154, the d _v All messages D102 cannot be stored in the small FIFO memory 161.

Therefore, as described above, the control unit 184 (FIG. 17) sets the weight d _{v of} the column corresponding to the variable node to which the branch for which the message is sought is connected to the message that the small FIFO memory 161 can store. when not the number d ₁ below, a signal for instructing to select a message DD102 that is read from the message memory 104 to the second selector 162, as the control signal C 104, supplied to the variable node calculator 182.

  In the variable node calculator 182, the control signal C104 from the control unit 184 is supplied to the selector 162 via the input port P104.

  The selector 162 selects the message DD102 read from the message memory 104 for the second time supplied to the terminal m in accordance with the control signal C104, and supplies the selected message DD102 to the calculator 156 as a value D153.

The computing unit 156 subtracts the value D153 from the selector 162 (in this case, the message DD102 from the input port PD102) from the integrated value D152 supplied from the register 154. That is, the message of the calculator 156, the message D102 from all edges over one row of the parity check matrix (? Uj _j from j = 1 to d _v) integrated value D152 of (message u _j) from a desired branch The subtraction value (Σu _j from j = 1 to d _v −1) is obtained by subtracting the message D153 as u _j (j = d _v u _j ) and supplied to the computing unit 157.

On the other hand, the control unit 184 (FIG. 17) determines that the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is to be obtained is connected is the number d of messages that the small FIFO memory 161 can store. When it is ₁ or less, a signal for instructing the selector 162 to select the message D102 delayed in the small FIFO memory 161 is supplied to the variable node calculator 182 as the control signal C104.

  In the variable node calculator 182, the control signal C104 from the control unit 184 is supplied to the selector 162 via the input port P104.

  The selector 162 selects the message D102 delayed by the small FIFO memory 161 supplied to the terminal f in accordance with the control signal C104, and supplies it to the computing unit 156 as a value D153.

Here, the number d ₁ of messages that can be small FIFO memory 161 is stored in the weights of the columns of the check matrix corresponding to the variable nodes d _v number of message D102 that integrated value in the register 152 is stored is input If d _v is not smaller than, at the register 152, until d _v number of messages D102 small FIFO memory 161 is not greater than the number d ₁ of storable messages are accumulated, the d _v number of messages D102 of all, be stored in a small FIFO memory 161, that is, until d _v number of message D102 is integrated, it is possible to delay all its d _v number of messages D102, after the delay The message D102 can be output after the integration of the d _v messages D102 is completed.

Therefore, the control unit 184 (FIG. 17) is the weight d _v column of the check matrix corresponding to a variable node that branches trying to find a message is connected, the number of messages that can be stored is small FIFO memory 161 d _{When the value is 1} or less, the control signal C104 for instructing the selector 162 to select the message D102 delayed by the small FIFO memory 161 is supplied to the selector 162 of the variable node calculator 182. The message D102 delayed in the small FIFO memory 161 is selected and supplied to the calculator 156 as a value D153.

The arithmetic unit 156 subtracts the value D153 from the selector 162 (in this case, the message D102 delayed by the small FIFO memory 161) from the integrated value D152 supplied from the register 154. That is, the message of the calculator 156, the message D102 from all edges over one row of the parity check matrix (? Uj _j from j = 1 to d _v) integrated value D152 of (message u _j) from a desired branch The subtraction value (Σu _j from j = 1 to d _v −1) is obtained by subtracting the message D153 as u _j (j = d _v u _j ) and supplied to the computing unit 157.

The computing unit 157 adds the reception data D101 from the input port P101 and the subtraction value (Σu _j from j = 1 to d _v −1) from the computing unit 156, and sends the resulting addition value to the message D103. (Message v _i ) is output from the output port P103.

As described above, the variable node calculator 182 performs the variable node calculation of Expression (1), and the message (variable node message) v _i obtained as a result is output from the output port P103.

  FIG. 19 shows a configuration example of the check node calculator 183 in FIG.

  In the figure, portions corresponding to the check node calculator 103 in FIG. 10 and the check node calculator 173 in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The check node calculator 183 includes small FIFO memories 141 and 143 and selectors 142 and 144 as delay memories for delaying data.

Similar to the FIFO memory 127 in FIG. 10, the small FIFO memory 141 is a calculation result D123 (φ of the nonlinear function φ (| v _i |) obtained by the LUT 121 from the message D104 read from the message memory 104 for the first time. (| v _i |)) is delayed.

However, FIFO memory 127 of Figure 10, at least, (a non-linear function obtained from phi () calculation result of | | v _i) number messages equal to the maximum value of the weight d _c line of the parity check matrix to store had a capacity to, small FIFO memory 141, has only the capacity to store messages maximum fewer than the weight d _c line of the check matrix (1 or a).

  Therefore, the small FIFO memory 141 has a smaller capacity than the FIFO memory 127 and is therefore smaller in scale.

The small FIFO memory 141 delays the operation result D123 of the nonlinear function φ (| v _i |) obtained from the message D104 read from the message memory 104 for the first time, and supplies it to the f terminal of the selector 142.

The selector 142 has an f terminal and an m terminal as input terminals, and the f terminal has a calculation result of the nonlinear function φ (| v _i |) delayed by the small FIFO memory 141 as described above. Is supplied. The calculation result of the nonlinear function φ (| v _i |) obtained by the LUT 135 from the message DD104 read out from the message memory 104 for the second time is supplied to the m terminal of the selector 142.

  Further, the control signal C104 is supplied to the selector 142 from the control unit 184 (FIG. 17).

The selector 142 reads the operation result of the nonlinear function φ (| v _i |) obtained from the message delayed by the small FIFO memory 141 according to the control signal C104 from the control unit 184, and the second read from the message memory 104. One of the calculation results of the non-linear function φ (| v _i |) obtained from the issued message is used to calculate the non-linear function φ (| v _i |) obtained from the message (used in the check node calculation) Result) and supply it to the calculator 126 as the value D127.

  Similar to the FIFO memory 133 in FIG. 10, the small FIFO memory 143 delays the sign bit D121 of the message D104 read from the message memory 104 for the first time.

However, the FIFO memory 133 in FIG. 10, at least, had a capacity capable of storing the number of messages equal to the maximum value of the weight d _c line of the check matrix (the sign bit) of the small FIFO memories 143 has only the capacity to store messages maximum fewer than the weight d _c line of the check matrix (1 or a).

  Therefore, the small FIFO memory 143 has a smaller capacity than the FIFO memory 133 and is therefore smaller in scale.

  The small FIFO memory 143 delays the sign bit D121 of the message D104 read from the message memory 104 for the first time, and supplies it to the f terminal of the selector 144.

  The selector 144 has an f terminal and an m terminal as input terminals, and the f terminal is read from the message memory 104 for the first time, delayed by the small FIFO memory 143 as described above. The sign bit of message D104 is supplied. Further, the sign bit of the message DD104 read from the message memory 104 for the second time is supplied to the m terminal of the selector 142.

  Furthermore, the control signal C104 is supplied to the selector 144 from the control unit 184 (FIG. 17).

  In accordance with the control signal C104 from the control unit 184, the selector 144 selects one of the sign bit delayed by the small FIFO memory 143 and the sign bit of the message read from the message memory 104 for the second time as a check node. Is selected as a message (sign bit thereof) to be used for the operation of, and supplied to the EXOR circuit 134 as a value D134.

  The check node calculator 183 has an input port P114 in addition to the input ports P111 and PD111. The control signal C104 from the control unit 184 is supplied to the selectors 142 and 144 via the input port P114. Is done.

In addition, the control unit 184 determines the row weight of the parity check matrix corresponding to the check node to which the branch for which the message is to be obtained is connected from the message that can be stored in the small FIFO memory 143 (φ (| v _i |)) or less (in this case, the row weight of the parity check matrix is also less than or equal to the number of messages (sign bits) that can be stored in the small FIFO memory 143). Instructs the selector 142 to select the message D104 delayed from the FIFO memory 141 (determined from φ (| v _i |)) and selects the message (the sign bit) delayed from the small FIFO memory 143. A signal for instructing the selector 144 to do so is supplied to the check node calculator 183 as the control signal C104.

Furthermore, the control unit 184 determines that the weight of the row corresponding to the check node is not less than the number of messages that can be stored in the small FIFO memory 141 (φ (| v _i |) obtained from) (in this case, the check (Even when the row weight of the matrix is not less than or equal to the number of messages (code bits) that can be stored in the small FIFO memory 143). (φ (| v _i |)) is instructed to the selector 142, and a signal to instruct the selector 144 to select the message DD104 (the sign bit) read out from the message memory 104 for the second time. , And supplied to the check node calculator 183 as the control signal C104.

Here, the control unit 184 instructs the selector 142 to select φ (| v _i |) of the message D104 delayed by the small FIFO memory 141 (as well as the message D104 delayed by the small FIFO memory 143). When the control signal C104 (instructing the selector 144 to instruct the sign bit) is supplied to the check node calculator 183, that is, the control signal C104 is read from the message memory 104 for the second time φ If the signal is not a signal for instructing the selector 142 to select (| v _i |), the reading of the message from the message memory 104 is controlled by reading the message from the message memory 104 only once.

  Therefore, in the control unit 184, when the row weight of the check matrix corresponding to the check node to which the branch for which the message is to be obtained is connected is not less than the number of messages that can be stored in the small FIFO memory 141, The readout control for reading the same message twice from the message memory 104 described in 15 is performed, but the weight of the row of the check matrix corresponding to the check node to which the branch for which the message is requested is connected is small FIFO. When the number of messages that can be stored in the memory 141 is less than or equal to the number of messages that can be stored, the read control for reading the same message twice from the message memory 104 is not performed, and the read control for reading only once, that is, the steps S101 and S102 in FIG. Of these, only step S101 is performed.

  The check node calculator 183 configured as described above performs the check node calculation of Expression (7) using the messages input from the input ports P111 and PD111 as necessary, and obtains the message obtained as a result. And output from the output port P112.

That is, the message D104 (variable node message u _j ) read from the message memory 104 is supplied to the input port P111.

Then, in the check node calculator 183, the message D104 (message v _i ) from the variable node corresponding to each row of the check matrix is inputted one by one from the input port P111, and the lower bits excluding the most significant bit, that is, the message The absolute value D122 (| v _i |) of D104 is supplied to the LUT 121, and the most significant bit, that is, the sign bit D121 of the message D104 is supplied to the EXOR circuit 129 and the small FIFO memory 143.

The LUT 121 reads the operation result D123 (φ (| v _i |)) obtained by performing the operation of the nonlinear function φ (| v _i |) using the absolute value D122 (| v _i |) as an argument, The data is supplied to the FIFO 141.

The arithmetic unit 122 adds the calculation result D123 (φ (| v _i |)) and the value D124 stored in the register 123 to integrate the calculation result D123, and the integrated value obtained as a result is registered in the register 123. Store again. Note that when the calculation result D123 (φ (| v _i |)) for the absolute value D122 (| v _i |) of the message D104 from all branches over one row of the check matrix is accumulated, the register 123 is reset. The

When the message D104 over one row of the check matrix is read one by one and the accumulated value obtained by integrating the operation result D123 for one row is stored in the register 123, the selector 124 stores the value stored in the register 123. , i.e., phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D124 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 125 for storage as the integrated value D125. The register 125 supplies the stored integrated value D125 to the selector 124 and the calculator 126 as a value D126.

The selector 124 selects the value D126 supplied from the register 125, outputs it to the register 125, and stores it again until the integrated value obtained by integrating the operation results D123 for one row is stored in the register 123. That is, until φ (| v _i |) obtained from the message D104 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 125 accumulates φ (| v _i |) is supplied to the selector 124 and the calculator 126.

On the other hand, (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) a new value D126 from the register 125 when the output of the start, that is, the operation result D123 is integrated for one row in the register 125 have been (from i = 1 to _{i = d c Σφ (| v} i |)) integrated value immediately after the stored, in the check node calculator 183, messages D104 (message v _i) the same messages DD104, i.e. The message v _i read from the message memory 104 for the second time is input one by one from the input port PD111, and the lower-order bits of the message DD104 excluding the most significant bit, that is, the absolute value of the message DD104 ( | v _i |) is supplied to the LUT 135, and the most significant bit, that is, the sign bit of the message DD 104 is supplied to the m terminal of the selector 144.

The LUT 135 reads the operation result (φ (| v _i |)) obtained by performing the operation of the nonlinear function φ (| v _i |) using the absolute value (| v _i |) of the message DD104 as an argument, and m of the selector 142 Supply to the terminal.

The small FIFO memory 141, a new value from the register 125 D126 (from i = 1 Sigma] [phi to _{d c (| v i |)} ) until it is output, operation results of the messages D104 from LUT 121 D123 ( φ (| v _i |)) is delayed and supplied to the f terminal of the selector 142.

Here, if the number of messages (φ (| v _i |)) that can be stored in the small FIFO memory 141 is d ₂ , the small FIFO memory 141 stores the rows of the parity check matrix as described above. the weight d maximum number of messages (of φ (| v _i |)) less than the _c for only has capacity to store, in the register 125, the parity check matrix, d _c corresponding to a certain one line The accumulated value of φ (| v _i |) of each message D104 (Σφ (| v _i |) from i = 1 to d _c ) is stored and output from the register 125 until the small FIFO memory 141 is output. in, phi of d _c number of messages D104 corresponding to the one line may not be able to delay (| | v _i).

That is, the number d ₂ of messages that can be stored is small FIFO memory 141, the register 125 φ (| v _i |) corresponding to the check node d _c pieces of message D102 that integrated value is stored in is input If the weight is smaller than the row weight d _c of the parity check matrix to be checked, the small FIFO memory 141 stores φ 2 (d ₂ +1) message out of the d _c messages D104 corresponding to that row. | v _i |) is stored, φ (| v _i |) of the first message is output. Therefore, in the register 125, the number of messages d ₂ that can be stored in the small FIFO memory 141 is determined. Until φ (| v _i |) of many d _c messages D104 is accumulated, all φ (| v _i |) of the d _c messages D104 are stored in the small FIFO memory 141. I can't leave.

Therefore, the control unit 184 (FIG. 17), as described above, the weight d _c in the row corresponding to the check node branches trying to find a message is connected, a small FIFO memory 141 is possible messages stored when not the number d ₂ or less, phi obtained from the message DD104 that is read from the message memory 104 to the second (| v _i |) a signal for instructing to select a selector 142, as the control signal C 104, checks This is supplied to the node calculator 183.

  In the check node calculator 183, the control signal C104 from the control unit 184 is supplied to the selector 142 via the input port P114.

In accordance with the control signal C104, the selector 142 selects φ (| v _i |) obtained by the LUT 135 from the message DD102 read from the message memory 104 for the second time supplied to the terminal m, and calculates it as a value D127. The device 126 is supplied.

On the other hand, the control unit 184 (FIG. 17) determines that the weight d _c of the row of the check matrix corresponding to the check node to which the branch for which the message is to be obtained is connected is the number d of messages that the small FIFO memory 141 can store. When it is ₂ or less, a signal instructing the selector 142 to select φ (| v _i |) of the message D104 delayed in the small FIFO memory 141 is supplied to the check node calculator 183 as the control signal C104. .

  In the check node calculator 183, the control signal C104 from the control unit 184 is supplied to the selector 142 via the input port P114.

The selector 142 selects φ (| v _i |) of the message D104 delayed by the small FIFO memory 141 and supplied to the terminal f in accordance with the control signal C104, and supplies the selected value D127 to the calculator 156.

Here, the number d ₂ of messages that can be stored is small FIFO memory 141, the weight of the rows of the check matrix corresponding to the check nodes d _c pieces of message D104 that integrated value in the register 125 is stored is input If it is not smaller than d _c, the integrated value (i) of φ (| v _i |) of d _c messages D104 not more than the number d ₂ of messages that can be stored in the small FIFO memory 141 in the register 125. = 1 to d _c until Σφ (| v _i |)) is output, all φ (| v _i |) of the d _c messages D104 are stored in the small FIFO memory 141. That is, until φ (| v _i |) of d _c messages D104 is accumulated, all φ (| v _i |) of the d _c messages D104 can be delayed. phi messages D104 after the delay (| v _i |) a, d _c number of the messages D104 of φ (| v _i |) integrated is to be output after the completion of That.

Therefore, the control unit 184 (FIG. 17) is the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, the number of messages that can be stored is small FIFO memory 141 d _{When the value is 2} or less, the control signal C104 for instructing the selector 162 to select φ (| v _i |) of the message D104 delayed by the small FIFO memory 141 is supplied to the selector 142 of the check node calculator 183. As a result, the selector 142 selects φ (| v _i |) of the message D104 delayed by the small FIFO memory 141 and supplies it to the calculator 126 as the value D127.

The arithmetic unit 126 subtracts the value D127 (φ (| v _i |)) from the selector 142 from the value D126 supplied from the register 125, and supplies the subtraction result to the LUT 128 as the subtraction value D128. That is, the arithmetic unit 126, phi obtained from the messages D104 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) integrated value from (i = 1 to i = d _c Σφ (| v _i |)) of the desired branch, φ (| v _i |) obtained from the message v _i (i = d _c v _i ) from the branch to be obtained is subtracted, and the subtraction value (i = Σφ (| v _i |)) from 1 to i = d _c −1) is supplied to the LUT 128 as a subtraction value D128.

The LUT 128 uses the subtraction value D128 (Σφ (| v _i |) from i = 1 to i = d _c −1) as an argument to the inverse function φ ⁻¹ (Σφ (| v _i |)). The calculation result D129 (φ ⁻¹ (Σφ (| v _i |))) obtained by performing the above calculation is output.

  On the other hand, the EXOR circuit 129 calculates the exclusive OR of the value D131 stored in the register 130 and the sign bit D121, thereby multiplying the sign bits, and re-stores the multiplication result D130 in the register 130. . When the sign bit D121 of the message D104 from all branches over one row of the check matrix is multiplied, the register 130 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix stored in the register 130, the selector 131, Paisign the value stored in the register 130, i.e., the value D131 (i = 1 the sign bit D121 of the message D104 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 132 as the value D132 for storage. The register 132 supplies the stored value D132 to the selector 131 and the EXOR circuit 134 as the value D133.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D104 from all of the branches across one line of the parity check matrix until just before is stored in the register 130 The selector 131 selects the value D133 supplied from the register 132, outputs it to the register 132, and stores it again. That is, the register 132 supplies the previously stored value to the selector 131 and the EXOR circuit 134 until the sign bit D121 of the message D104 (message v _i ) from all branches over one row of the check matrix is multiplied. .

When a new value from the register 132 D133 which (Paisign of i = 1 through _{i = d c (v i)} ) is supplied to the EXOR circuit 134, i.e., messages from all of the branches across one line to the register 130 D104 when (Paisign of i = 1 through _{i = d c (v i)} ) of the sign bits D121 is multiplied value D131 is stored, as described above, the register 125, one row of the result D123 There integrating integrated values (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) is stored.

Integration value calculation result D123 is integrated for one row in the register 125 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) When is stored, as described above, the check node calculator At 183, the same message DD104 as the message D104 (message v _i ), that is, the message v _i read from the message memory 104 for the second time is input one by one from the input port PD104, and the message DD104 The low-order bits excluding the most significant bit, that is, the absolute value (| v _i |) of the message DD104 is supplied to the LUT 135, and the most significant bit, that is, the sign bit of the message DD104 is supplied to the m terminal of the selector 144. Is done.

The small FIFO memory 143, between (from i = 1 i = Πsign to d _c (v _i)) a new value D133 from the register 132 until the output is read out from the message memory 104 to the first The code bit D121 of the received message D104 is delayed and supplied to the f terminal of the selector 144.

Here, if the number of messages (the sign bits) that can be stored in the small FIFO memory 143 is d ₂ which is the same as that of the small FIFO memory 141, the small FIFO memory 143 checks as described above. Since there is only a capacity to store a smaller number of messages (sign bits of) than the maximum value of the matrix row weights d _c , the register 132 has d _c corresponding to one row of the check matrix. is stored (Πsign (v _i) from i = 1 to d _c) multiplying the result of the sign bits D121 of the messages D104, until it is outputted from the register 132, in a small FIFO memory 143, corresponding to the one line It may not be possible to delay the sign bit D121 of d _c messages D104.

That is, the number d ₂ of messages that can be small FIFO memory 143 is stored by, the sign bit D121 to the register 132 the multiplication result of the check matrix corresponding to the check node to which d _c pieces of message D102 to be stored is input If it is smaller than the weight d _c line, in a small FIFO memory 143, of the d _c number of messages D104 corresponding to that row, the sign bit D121 of d ₂ +1 th message is stored in Rutoki, because the sign bits D121 of one second message from being output, the register 132, the sign bit of the message D104 of greater d _c number than the number d ₂ messages capable of storing a small FIFO memory 143 D121 There until it is stored, the code bit D121 all of its d _c number of messages D104, can not be stored in a small FIFO memory 143.

Therefore, the control unit 184 (FIG. 17), as described above, the weight d _c in the row corresponding to the check node branches trying to find a message is connected, a small FIFO memory 143 is possible messages stored (in this case, the weights d _c rows, also when a small FIFO memory 141 is not the number d ₂ the following messages can be stored) when not the number d ₂ below is read from the message memory 104 to the second A signal for instructing the selector 144 to select the sign bit of the message DD104 is supplied to the check node calculator 183 as the control signal C104.

  In the check node calculator 183, the control signal C104 from the control unit 184 is supplied to the selector 144 via the input port P114.

  The selector 144 selects the sign bit of the message DD102 read from the message memory 104 for the second time supplied to the terminal m in accordance with the control signal C104, and supplies it to the EXOR circuit 134 as a value D134.

On the other hand, the control unit 184 (FIG. 17) is the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, the number of messages that can be stored is small FIFO memory 143 d When it is ₂ or less, a signal for instructing the selector 142 to select the sign bit of the message D104 delayed by the small FIFO memory 143 is supplied to the check node calculator 183 as the control signal C104.

  In the check node calculator 183, the control signal C104 from the control unit 184 is supplied to the selector 144 via the input port P114.

  The selector 144 selects the sign bit of the message D104, which is supplied to the terminal f and delayed by the small FIFO memory 143, according to the control signal C104, and supplies it to the EXOR circuit 134 as the value D134.

The EXOR circuit 134 calculates the exclusive OR of the value D133 supplied from the register 132 and the sign bit D134 from the selector 144, divides the value D133 by the sign bit D134, and divides the result of the division into a division value. Output as D135. That, EXOR circuit 134, (Paisign of i = 1 through _{i = d c (v i)} ) multiplied value D133 of the sign bit D121 of the message D104 from all of the branches across one line of the parity check matrix, to be obtained is divided by the sign bit of the message as the message v _i from branch D134 (i = d _c of sign (v _i)), Πsign of the division value from (i = 1 to _i = d _c -1 (v i )) Is output as the division value D135.

Then, in the check node calculator 183, the bit string having the operation result D129 output from the LUT 128 as the lower bit and the division value D135 output from the EXOR circuit 134 as the most significant bit (sign bit) is the message D105 (message u _j ) is output from the output port P112.

As described above, the check node calculator 183 performs the calculation of Expression (7) to obtain the message (check node message) u _j .

  Although not shown, in the decoding device of FIG. 17, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1), and the calculation result is the final decoding. Output as a result.

  Next, a selector control process in which the control unit 184 in FIG. 17 controls the selectors 142 and 144 (FIG. 19) and the selector 162 (FIG. 18) by the control signal C104 will be described with reference to the flowchart in FIG. .

  Here, for simplicity of explanation, the number of messages that can be stored in the small FIFO memories 141 and 143 (FIG. 19) and the small FIFO memory 161 (FIG. 18) (hereinafter referred to as the number that can be stored as appropriate). Are all the same d. However, the number of messages that can be stored in the small FIFO memories 141 and 143 (FIG. 19) and the small FIFO memory 161 (FIG. 18) may be different.

  In step S121, the control unit 184 determines the weight of the check matrix corresponding to the node (attention node) that is focused on for the message (if the attention node is a variable node, the column of the column corresponding to the variable node). If the node of interest is a check node, it is determined whether or not the weight of the row corresponding to the check node is larger than the storable number d.

If it is determined in step S121 that the weight of the parity check matrix corresponding to the node of interest is not greater than the storable number d, that is, an input used to obtain an output message corresponding to the branch connected to the node of interest. When the number of messages is less than or equal to the storable number d, the process proceeds to step S122, and the control unit 184 outputs the output of the FIFO memory, that is, for example, the small FIFO memory for the variable node calculator 182 of FIG. the message 161 is output, the check node calculator 183 of FIG. 19, phi messages output by small FIFO memory 141 (| v _i |) and, the sign bit of the message to be output is small FIFO memory 143, A control signal C104 instructing selection is output, and the process returns to step S121.

  In this case, in the variable node calculator 182 of FIG. 18, the message output from the small FIFO memory 161 is selected by the selector 162 in accordance with the control signal C104 and supplied to the calculator 156.

In the check node calculator 183 of FIG. 19, the selector 142 selects φ (| v _i |) of the message output from the small FIFO memory 141 according to the control signal C104 and supplies it to the calculator 126. In the selector 144, the sign bit of the message output from the small FIFO memory 143 is selected according to the control signal C104 and supplied to the EXOR circuit 134.

  When the number of input messages is less than or equal to the storable number d, the control unit 184 reads out the same message twice from the message memory 104 as described above (both steps S101 and S102 in FIG. 15). ) Is not performed, and readout control (step S101 in FIG. 15) for reading only once is performed.

On the other hand, when it is determined in step S121 that the weight of the check matrix corresponding to the node of interest is larger than the storable number d, that is, to obtain an output message corresponding to the branch connected to the node of interest. If the number of input messages used exceeds the storable number d, the process proceeds to step S123, and the control unit 184 reads the message (data) read out from the message memory 104 (FIG. 17) for the second time. That is, for example, the variable node calculator 182 in FIG. 18 reads the message DD102 read from the message memory 104 a second time, and the check node calculator 183 in FIG. Φ (| v _i |) obtained by the LUT 135 from the issued message DD102 and the message memory 104 , The control signal C104 instructing to select each of the sign bits of the message DD102 read for the second time is output, and the process returns to step S121.

  That is, in this case, as described above, the control unit 184 performs read control (both steps S101 and S102 in FIG. 15) for reading the same message twice from the message memory 104. Reads the same message twice.

  In this case, in the variable node calculator 182 of FIG. 18, the selector 162 selects the message DD102 read out from the message memory 104 for the second time in accordance with the control signal C104 and supplies it to the calculator 156.

Further, in the check node calculator 183 of FIG. 19, the selector 142 selects φ (| v _i |) obtained by the LUT 135 from the message DD102 read from the message memory 104 for the second time in accordance with the control signal C104. The code bit of the message DD102 read out from the message memory 104 for the second time is selected by the selector 144 in accordance with the control signal C104 and supplied to the EXOR circuit 134.

  As described above, the small FIFO memories 141 and 143 (FIG. 19) and the small FIFO memory 161 (FIG. 18) for storing a smaller number of messages than the maximum value of the check matrix weight are provided as the delay memory. Therefore, the scale of the decoding apparatus is reduced as compared with the case where the FIFO memories 127 and 133 (FIG. 10) and the FIFO memory 155 (FIG. 9) storing at least the number of messages equal to the maximum value of the check matrix weight are provided. can do.

  Furthermore, if the weight of the parity check matrix corresponding to the node of interest is less than or equal to the storable number d (if it is not greater than the storable number d), the output of the FIFO memory is selected and the node (variable node, check node) 8), the FIFO memory 127 and 133 (FIG. 10) storing at least the number of messages equal to the maximum value of the check matrix weight, and the decoding apparatus of FIG. 8 having the FIFO memory 155 (FIG. 9) are used. You can read and write messages in the time. Accordingly, since iterative decoding can be performed the same number of times as in the decoding device of FIG. 8 (the time required for one decoding is the same as that of the decoding device of FIG. 8), deterioration of decoding performance is prevented ( Suppression).

  Further, when the weight of the check matrix corresponding to the node of interest is larger than the storable number d, the same message is read twice from the message memory 104, the second read message is selected, Since it is used for the node calculation, the LDPC code can be decoded even if the weight of the parity check matrix corresponding to the node of interest is larger than the storable number d.

  From the above, according to the decoding device of FIG. 17, it is possible to suppress degradation in decoding performance while reducing the scale.

  By the way, in the decoding apparatus of FIG. 17, the message calculation unit 181 as means for obtaining the output message is configured with a variable node calculator 182 that performs variable node calculation and a check node calculator 183 that performs check node calculation. However, the means for obtaining the output message is configured by sharing a part of the circuit that performs the variable node calculation and the circuit that performs the check node calculation so that the variable node calculation and the check node calculation are selectively performed. By doing so, the scale of the decoding device can be further reduced.

  Therefore, next, a delay memory for sharing a part of the circuit for performing the variable node operation and the circuit for performing the check node operation and storing a number of messages smaller than the maximum value of the check matrix weight is provided. The decoding apparatus will be described. As a preparation for the previous stage, a part of the circuit that performs the variable node calculation and the circuit that performs the check node calculation are shared, and at least equal to the maximum weight of the check matrix A decoding apparatus provided with a delay memory for storing a number of messages will be described.

  That is, FIG. 21 is a block diagram showing an example of the configuration of such a decoding device.

  In the figure, portions corresponding to those of the decoding device of FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the decoding device of FIG. 21 is different from the decoding device of FIG. 8 except that a message calculation unit 191 is provided instead of the message calculation unit 101 and a control unit 192 is provided instead of the control unit 106. It is constituted similarly.

  The decoding device in FIG. 21 repeatedly performs full serial decoding in the same manner as the decoding device in FIG.

  In the decoding device of FIG. 21, the input message is read one by one from the message memory 104 to the message calculation unit 191, and the message calculation unit 191 calculates an output message corresponding to a desired branch using the input message. Is done. The output message obtained by the calculation is stored in the message memory 104. In the decoding device of FIG. 21, the above processing is repeatedly performed, so-called iterative decoding is performed.

  That is, the reception data memory 105 is supplied with reception data (LDPC code) D100, which is a log likelihood ratio representing the likelihood of 0 (or 1) of the code obtained by receiving the transmitted LDPC code, The reception data memory 105 stores the reception data D100.

  During the variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 192, and supplies it to the message calculation unit 191 as reception data D101.

  Further, at the time of variable node calculation, the message memory 104 reads out the stored message D201 in accordance with the control signal supplied from the control unit 192 and supplies it to the message calculation unit 191. Further, at the time of variable node calculation, the control unit 192 supplies a control signal instructing variable node calculation to the message calculation unit 191 as the control signal C203.

The message calculation unit 191 uses the input message D201 supplied from the message memory 104 and the reception data D101 supplied from the reception data memory 105, and performs variable node calculation of Expression (1) according to the control signal C203 from the control unit 192. The output message (variable node message) v _i obtained as a result of the variable node calculation is supplied to the message memory 104 as a message D202.

  The message memory 104 stores the message D202 supplied from the message calculation unit 191 as described above.

On the other hand, during the check node calculation, the message memory 104 reads the stored variable node message v _i as the input message D201 in accordance with the control signal supplied from the control unit 192, and supplies it to the message calculation unit 191.

  Further, at the time of the check node calculation, the control unit 192 supplies a control signal instructing the check node calculation to the message calculation unit 191 as the control signal C203.

The message calculation unit 191 uses the input message D201 supplied from the message memory 104, performs the check node calculation of Expression (7) according to the control signal C203 from the control unit 192, and is obtained by the check node calculation. The output message (check node message) u _j is supplied to the message memory 104 as the message D202.

  The message memory 104 stores the message D202 supplied from the message calculation unit 191 as described above.

The message D202 as the check node message u _j from the message calculation unit 191 stored in the message memory 104 is read as the message D201 and supplied to the message calculation unit 191 at the time of the next variable node calculation.

  Next, FIG. 22 shows a configuration example of the message calculation unit 191 of FIG.

  The message calculation unit 191 has two input ports P101 and P201 as input ports to which messages (data) are supplied (input) from the outside, and one output port as a port to supply (output) messages to the outside Has P202. Further, the message calculation unit 191 has one input port P203 as an input port to which a control signal is supplied (input) from the outside.

  The message calculation unit 191 uses a message input from the input port P201, and further, if necessary, a message (received data) input from the input port P101, and according to a control signal C203 input from the input port P203, Based on the check matrix that defines the LDPC code to be decoded, the variable node operation of Equation (1) or the check node operation of Equation (7) is selectively performed, and the resulting message is output from the output port P202. .

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the message D201 (check node message u _j or variable node message v _i ) read from the message memory 104 is supplied to the input port P201. Further, the control signal C203 from the control unit 192 is supplied to the input port P203.

  The reception data D101 supplied to the input port P101 is supplied to the calculator 313, and the message D201 supplied to the input port P201 is supplied to the v terminal of the selector 301. Further, the low-order bits excluding the most significant bit of the message D201 supplied to the input port P201, that is, the absolute value of the message D201 is supplied to the LUT 300 as the value D303, and the most significant bit of the message D201, that is, The sign bit of the message D201 is supplied to the EXOR circuit 306 and the FIFO memory 320 as a value D304.

  The control signal C203 supplied to the input port P203 is supplied to the selectors 301 and 316.

  The selectors 301 and 316 have a v terminal and a c terminal, select a value supplied to either the v terminal or the c terminal according to the control signal C203, and output the selected value to the subsequent stage. That is, when the control signal C203 is a control signal for instructing variable node calculation, the selectors 301 and 316 select the value supplied to the v terminal and output it to the subsequent stage, and the control signal C203 performs check node calculation. In the case of the control signal to be instructed, the value supplied to the c terminal is selected and output to the subsequent stage.

  As a result, the message calculation unit 191 substantially has the configuration shown in FIG. 23 during the variable node calculation, performs the variable node calculation, and substantially has the configuration shown in FIG. 24 during the check node calculation. , Perform a check node operation.

  That is, FIG. 23 illustrates a substantial configuration example of the message calculation unit 191 at the time of variable node calculation.

  As described above, in the variable node calculation, the selectors 301 and 316 select the v terminal. In FIG. 23, the selectors 301 and 316 in the configuration illustrated in FIG. 22 select the v terminal. A portion that does not (substantially) function at the time of variable node calculation (portion not related to variable node calculation) is not shown.

At the time of variable node calculation, the reception data D101 read from the reception data memory 105 one by one is supplied to the input port P101. In addition, the input port P201 corresponds to each row of the check node corresponding to each row of the check matrix (one column corresponding to the variable node for which the output message v _i is to be obtained) read from the message memory 104 one by one. Check node messages u _j from the check nodes) are sequentially supplied as messages D201.

  The reception data D101 supplied to the input port P101 is supplied to the calculator 313.

Further, the message D201 (message u _j ) supplied to the input port P201 is supplied to the v terminal of the selector 301. At the time of variable node calculation, the selector 301 selecting the v terminal receives a message D306 from the calculator 302. It is supplied to the FIFO memory 320.

The computing unit 302 adds up the message D306 by adding the message D306 (message u _j ) from the selector 301 and the value D307 stored in the register 303, and the integrated value obtained as a result is stored in the register 303. Store again. Note that when the messages D306 from all branches over one column of the check matrix are accumulated, the register 303 is reset.

When the message D201 over one column of the check matrix is read one by one and the value obtained by accumulating the message D306 for one column is stored in the register 303, that is, all over the one column of the check matrix are stored in the register 303. When the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D306 (message u _j ) from the branch is stored, the selector 304 stores the value stored in the register 303, that is, select the message from all of the branches across one row of the parity check matrix D306 (message u _j) the accumulated integrated values D307 (? uj _j from j = 1 to d _v), is stored in output register 305 .

The register 305 supplies the stored value D307 as the value D308 to the selector 304 and the calculator 312. The selector 304 selects the value D308 supplied from the register 305, outputs it to the register 305, and stores it again immediately before the value obtained by integrating the message D306 for one column is stored in the register 303. That is, until the message D306 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 305 supplies the previously accumulated value to the selector 304 and the calculator 312.

On the other hand, FIFO memory 320, at least, of a capacity capable of storing the maximum and same number of messages weight of the check matrix, a new value D308 (j = 1 from the register 305 to d _v? Uj Until _j ) is output, the message D306 from the check node output by the selector 301 is delayed and supplied to the computing unit 312 as a value D315. The calculator 312 subtracts the value D315 supplied from the FIFO memory 320 from the value D308 supplied from the register 305. That is, the arithmetic unit 312 determines the message from the branch to be obtained from the integrated value D308 (Σu _j from j = 1 to d _v ) of the message D306 (message u _j ) from all the branches over one column of the check matrix. D315 is subtracted (u _j), we obtain the subtraction value D316 (? uj _j from j = 1 to d _v -1), and supplies to the calculator 313.

Calculator 313 adds the reception data D101 from the input port P101, the calculator 312 subtracts value from D316 by adding the (? Uj _j from j = 1 to d _v -1), the addition value obtained as a result D317 ( The variable node message v _i ) is supplied to the v terminal of the selector 316.

The selector 316 selects the v terminal at the time of variable node calculation, and outputs the addition value D317 from the calculator 313 supplied to the v terminal from the output port P202 as a message D202 (message v _i ).

As described above, in the message calculation unit 191 in which the selectors 301 and 304 have selected the v terminal, the variable node calculation of Expression (1) is performed, and the resulting message (variable node message) v _i is output. Output from port P202.

  FIG. 24 shows a substantial configuration example of the message calculation unit 191 in FIG. 22 at the time of check node calculation.

  As described above, in the check node calculation, the selectors 301 and 316 select the c terminal, but in FIG. 24, the selectors 301 and 316 in the configuration illustrated in FIG. 22 select the c terminal. A portion that does not function (substantially) at the time of the check node calculation (portion not related to the check node calculation) is not shown.

At the time of the check node calculation, the input port P201 corresponds to the variable node corresponding to each column of the parity check matrix read from the message memory 104 (the check node for which the output message u _j is to be obtained). A variable node message v _i from a variable node corresponding to each column in a row is sequentially supplied as a message D201.

The low-order bits excluding the most significant bit of the message D201 (message u _j ) supplied to the input port P201, that is, the absolute value D303 (| v _i |) of the message D201 is supplied to the LUT 300, and the most significant bit. That is, the sign bit D304 of the message D201 is supplied to the EXOR circuit 306 and the FIFO memory 320, respectively.

The LUT 300 outputs a calculation result of the nonlinear function φ (x) in the check node calculation of Expression (7) using the value input thereto as an argument x, and a LUT that stores the calculation result of φ (x) ), And the calculation result D305 (φ (| v _i |)) obtained by performing the calculation of the nonlinear function φ (| v _i |) using the absolute value D303 (| v _i |) as an argument is read out. Supply to the terminal.

The selector 301 selects the c terminal during the check node calculation, and the calculation result D305 (φ (| v _i |)) from the LUT 300 supplied to the c terminal is used as the calculation result D306 (φ (| v _i |). )) To the computing unit 302 and the FIFO memory 320.

The computing unit 302 adds the calculation result D306 (φ (| v _i |)) and the value D307 stored in the register 303 to integrate the calculation result D306, and the integrated value obtained as a result is registered in the register 303. Store again. Note that when the operation result D306 (φ (| v _i |)) for the absolute value D303 (| v _i |) of the message D201 from all branches over one row of the check matrix is accumulated, the register 303 is reset. The

When the message D201 over one row of the check matrix is read one by one and the accumulated value obtained by accumulating the operation result D306 for one row is stored in the register 303, the selector 304 stores the value stored in the register 303. , i.e., phi obtained from the messages D201 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D307 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 305 for storage. The register 305 supplies the stored integrated value D307 as a value D308 to the selector 304 and the calculator 312.

The selector 304 selects the value D308 supplied from the register 305, outputs it to the register 305, and stores it again immediately before the integrated value obtained by integrating the operation results D306 for one row is stored in the register 303. That is, until φ (| v _i |) obtained from the message D201 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 305 accumulates φ (| v _i |) is supplied to the selector 304 and the calculator 312.

On the other hand, FIFO memories 320, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D308 from the register 305 until it is output, the result calculation LUT300 has output D306 (phi (| v _i |)) is delayed and supplied to the computing unit 312 as a value D315. The arithmetic unit 312 subtracts the value D315 supplied from the FIFO memory 320 from the value D308 supplied from the register 305, and supplies the subtraction result to the LUT 314 as a subtraction value D316. That is, the calculator 312, phi obtained from the messages D201 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) integrated value from (i = 1 to i = d _c Σφ (| v _i |)) of the desired branch is subtracted φ (| v _i |) obtained from the message D201 (message v _i ) from the branch to be obtained, and the subtraction value (i = 1 to i = d). Σφ (| v _i |) up to _c −1) is supplied to the LUT 314 as the subtraction value D316.

The LUT 314 outputs a calculation result of the inverse function φ ⁻¹ (x) of the nonlinear function φ (x) in the check node calculation of Expression (7) using the value input thereto as an argument x (φ ⁻¹ ( x) is an LUT that stores the calculation result of x), and the inverse function with the subtraction value D316 (Σφ (| v _i |) from i = 1 to i = d _c −1) from the calculator 312 as an argument _{^{φ -1 (Σφ (| v i}} |)) calculation results D318 of the operation was carried out in ^{(φ -1 (Σφ (| v} |))) outputs a.

As described above, since the calculation result of the nonlinear function φ (x) and the calculation result of the inverse function φ ⁻¹ (x) are equal, the LUTs 300 and 314 are LUTs having the same configuration.

  In parallel with the above processing, the EXOR circuit 306 calculates the exclusive OR of the value D310 stored in the register 307 and the sign bit (bit representing positive / negative) D304, thereby multiplying the sign bits. The multiplication result D309 is stored again in the register 307. When the sign bit D304 of the message D201 from all branches over one row of the check matrix is multiplied, the register 307 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D309 to the sign bit D304 is multiplied by the messages D201 from all of the branches across one line of the parity check matrix stored in the register 307, the selector 308, Paisign the value stored in the register 307, i.e., the value D310 (i = 1 the sign bit D304 of the message D201 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 309 for storage. The register 309 supplies the stored value D311 to the selector 308 and the EXOR circuit 315.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D309 to the sign bit D304 is multiplied by the messages D201 from all of the branches across one line of the parity check matrix until just before is stored in the register 307 The selector 308 selects the value D311 supplied from the register 309, outputs it to the register 309, and stores it again. That is, the register 309 supplies the previously stored value to the selector 308 and the EXOR circuit 315 until the sign bits D304 of the message D201 (message v _i ) from all branches over one row of the parity check matrix are multiplied. .

On the other hand, FIFO memories 320, between (from i = 1 i = Πsign to d _c (v _i)) a new value D311 from the register 309 until is supplied to the EXOR circuit 315, the operation result from the selector 301 D306 Along with (φ (| v _i |)), the sign bit D304 is delayed and supplied to the EXOR circuit 315 as a 1-bit value D313. The EXOR circuit 315 calculates the exclusive OR of the value D311 supplied from the register 309 and the value D313 supplied from the FIFO memory 320, thereby dividing the value D311 by the value D313 and dividing the division result. Output as the value D319. That, EXOR circuit 315, the sign bit D304 of the messages D201 from all of the branches across one line of the parity check matrix (sign (v _i)) of the multiplication value (Paisign of i = 1 through _i = d _c (v i )) Is divided by the sign bit D304 (sign (v _i )) of the message D201 from the branch to be obtained, and the divided value (Πsign (v _i ) from i = 1 to i = d _c −1) is obtained. Output as division value D319.

Then, the message calculation unit 191 sets the operation result D318 output from the LUT 314 as the lower bit and the bit string D320 (check node message u) having the division value D319 output from the EXOR circuit 315 as the most significant bit (sign bit). _j ) is supplied to the c terminal of the selector 316.

The selector 316 selects the c terminal during the check node calculation, and outputs the bit string D320 (message u _j ) supplied to the c terminal from the output port P202 as the message D202 (message v _i ).

As described above, in the message calculation unit 191 in which the selectors 301 and 304 have selected the c terminal, the check node calculation of Expression (7) is performed, and the resulting message (check node message) u _j is output. Output from port P202.

  Although not shown, in the decoding device of FIG. 21, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1), and the calculation result is the final decoding. Output as a result.

  21 can decode LDPC codes of various parity check matrices as long as the capacity of the message memory 104 and the FIFO memory 320 of the message calculation unit 191 is sufficient.

  Further, in the message calculation unit 191 (FIG. 22) of the decoding device of FIG. 21, as can be seen by comparing FIG. 23 and FIG. 24, an arithmetic unit 302 and a register 303 that perform integration of values and output an integrated value, A selector 304, a register 305, and a calculator 312 that subtract a certain value from the integrated value and output a subtracted value, and a FIFO memory 320 as a delay memory that delays the value are shared by the variable node calculation and the check node calculation. Therefore, for example, the circuit scale can be made smaller than that of the message calculation unit 101 having the independent variable node calculator 102 and the check node calculator 103 as in the decoding device of FIG.

  Next, FIG. 25 is a block diagram illustrating a configuration example of the second embodiment of the decoding device to which the present invention has been applied.

  In the figure, portions corresponding to those of the decoding device of FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. That is, the decoding device of FIG. 25 is provided with a message calculation unit 201 instead of the message calculation unit 191 and a decoding unit of FIG. 21 except that a control unit 202 is provided instead of the control unit 192. It is configured in the same way as the device.

  In the decoding device of FIG. 25, the message calculation unit 201 shares a part of a circuit that performs variable node calculation and a circuit that performs check node calculation, similar to the message calculation unit 191 of the decoding device of FIG. It has become. Further, in the decoding apparatus of FIG. 25, the message calculation unit 201 that performs variable node calculation and check node calculation is a number equal to the maximum value of the check matrix weight as in the FIFO memory 320 of the message calculation unit 191 of FIG. The delay memory stores a number of messages smaller than the maximum value of the check matrix weights.

  In the decoding device of FIG. 25, the control unit 202 performs read / write control similar to that of the control unit 174 of the decoding device of FIG. 12, as described in the flowchart of FIG. Take control.

  Further, similarly to the control unit 192 of FIG. 21, the control unit 202 supplies the control signal C203 to the message calculation unit 201, and by the control signal C203, the variable node calculation of Expression (1) or Expression (7) The message calculation unit 201 is instructed to perform the check node calculation.

  Further, as described in the flowchart of FIG. 20, the control unit 202 performs a selector control process, and supplies a control signal C204 corresponding to the control signal C104 to the message calculation unit 201. The message calculation unit 201 selectively uses the second message read from the message memory 104 in accordance with the control signal C204 from the control unit 202, and performs a variable node calculation of Expression (1) or a check node of Expression (7). Perform the operation.

  In the decoding apparatus configured as described above, the input messages are read one by one from the message memory 104 according to the control of the control unit 202, and the message calculation unit 201 uses the input messages to make a desired branch. The corresponding output message is calculated. The output message obtained by the calculation is stored in the message memory 104. In the decoding device of FIG. 25, the above processing is repeated, and full serial iterative decoding is performed.

  In other words, the reception data (LDPC code) D100 is supplied to the reception data memory 105, and the reception data memory 105 stores (stores) the reception data D100.

  At the time of variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 202, and supplies it to the message calculation unit 201 as reception data D101.

  Further, during the variable node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 202, and the message read first time as the message D201. The message read to the message calculation unit 201 and read for the second time is supplied to the message calculation unit 201 as a message DD201.

The message calculation unit 201 reads the message D201 read from the message memory 104 for the first time, the reception data D101 supplied from the reception data memory 105, and, if necessary, reads the message D201 from the message memory 104 for the second time. In accordance with the instruction of variable node calculation represented by the control signal C203 supplied from the control unit 202 and the control signal C204 supplied from the control unit 202, a check matrix that defines the LDPC code to be decoded is used. Based on the variable node calculation of Expression (1), the message (variable node message) v _i obtained as a result of the variable node calculation is supplied to the message memory 104 as a message D202.

The message memory 104 stores a message D202 (variable node message v _i ) supplied from the message calculation unit 201 in accordance with a control signal supplied from the control unit 202.

On the other hand, at the time of the check node calculation, the message memory 104 reads the same stored message (variable node message v _i ) once or twice according to the control signal supplied from the control unit 202, and the first time The read message is supplied to the message calculation unit 201 as a message D201, and the second read message is supplied to the message calculation unit 201 as a message DD201.

The message calculation unit 201 uses the message D201 read from the message memory 104 for the first time and, if necessary, the message DD201 read from the message memory 104 for the second time to control the message from the control unit 202. In accordance with the check node calculation instruction represented by the signal C203 and the control signal C204 supplied from the control unit 202, the check node calculation of Expression (7) is performed based on the check matrix that defines the LDPC code to be decoded, and the check A message (check node message) u _j obtained by the node operation is supplied to the message memory 104 as a message D202.

The message memory 104 stores a message D202 (check node message u _j ) supplied from the message calculation unit 201 in accordance with a control signal supplied from the control unit 202.

The message D202 from the message calculation unit 201 stored in the message memory 104, that is, the check node message u _j is used as the message D201, and further as the message DD201 as needed at the time of the next variable node calculation, or once or 2 It is read once and supplied to the message calculation unit 201.

  FIG. 26 shows a configuration example of the message calculation unit 201 in FIG.

  In the figure, portions corresponding to the message calculation unit 191 in FIG. 22 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In addition to the input ports P101, P201, and P203 in FIG. 22, the message calculation unit 201 is newly provided with input ports PD201 and P204, and a LUT 310 and a selector 311 are newly provided.

  Further, the message calculation unit 201 is provided with a small FIFO memory 317 instead of the FIFO memory 320 of FIG. 22, and a selector 318 is newly provided.

  The reception data D101 read from the reception data memory 105 is supplied (input) to the input port P101. The input port P201 is supplied with (inputted to) the input message D201 that is read twice from the message memory 104 and the message that is read first time (hereinafter also referred to as the first message as appropriate) D201. The port PD 201 is supplied with a message DD201 read out for the second time (hereinafter also referred to as a second message as appropriate) DD201.

  A control signal C203 is supplied from the control unit 202 (FIG. 25) to the input port P203, and a control signal C204 is supplied from the control unit 202 to the input port P204.

  The message calculation unit 201 uses the first message D201 input from the input port P201, the second message DD201 input from the input port PD201, and the message (received data) input from the input port P101. According to the control signal C203 input from P203, the variable node calculation of Expression (1) or the check node calculation of Expression (7) is performed, and the resulting message is output from the output port P202.

  That is, the received data D101 supplied to the input port P101 is supplied to the computing unit 313, and the first message D201 supplied to the input port P201 is supplied to the v terminal of the selector 301 and the small FIFO memory 317. .

  Further, the low-order bits excluding the most significant bit of the first message D201 supplied to the input port P201, that is, the absolute value of the message D201 is supplied to the LUT 300 as the value D303, and is included in the first message D201. Most significant bit, that is, the sign bit of the message D201 is supplied to the EXOR circuit 306 as a value D304.

  The second message DD201 supplied to the input port PD201 is supplied to the m terminal of the selector 318.

  Further, the control signal C203 supplied to the input port P203 is supplied to the selectors 301, 311 and 316.

  The selectors 301, 311 and 316 have a v terminal and a c terminal, select a value supplied to either the v terminal or the c terminal according to the control signal C203, and output the selected value to the subsequent stage. That is, when the control signal C203 is a control signal instructing variable node calculation, the selectors 301, 311 and 316 select the value supplied to the v terminal and output it to the subsequent stage, and the control signal C203 is checked. In the case of a control signal instructing node calculation, the value supplied to the c terminal is selected and output to the subsequent stage.

  As a result, in the message calculation unit 201 in FIG. 26, the variable node calculation is performed when the control signal C203 indicates a variable node calculation, and the check node calculation is performed when the control signal C203 indicates a check node calculation. Is done.

  The small FIFO memory 317 is a delay memory for delaying messages, and temporarily stores and delays the first message D201 from the message memory 104 in the same manner as the FIFO memory 320 in FIG.

However, the FIFO memory 320 in FIG. 22 has a capacity capable of storing at least a number of messages equal to the maximum value of the parity check matrix weight (column weight d _v and row weight d _c ). The small FIFO memory 317 has a capacity for storing a smaller number of messages (that is, 1 or more) than the maximum value of the check matrix weight.

  Therefore, the small FIFO memory 317 has a smaller capacity than the FIFO memory 320 and is therefore smaller in scale.

  As described above, the small FIFO memory 317 delays the first message D201 from the message memory 104 and supplies it to the f terminal of the selector 318.

  The selector 318 has f and m terminals as input terminals. As described above, the message D201 delayed by the small FIFO memory 317 is supplied to the f terminal, and the message is sent to the m terminal. A second message DD201 from the memory 104 is supplied.

  Further, the control signal C204 supplied from the control unit 202 (FIG. 25) to the input port P204 is supplied to the selector 318.

  The selector 318 determines whether one of the first message D201 delayed by the small FIFO memory 317 and the second message DD201 from the message memory 104 is a variable node or check according to the control signal C204 from the control unit 202. Select and output as a message for node operation.

  The message output from the selector 318, that is, the first message D201 delayed in the small FIFO memory 317 or the second message DD201 from the message memory 104 is supplied to the v terminal of the selector, and the highest one of them. The lower bits excluding the upper bits, that is, the absolute value, is supplied to the LUT 310 as the value D312. The most significant bit, that is, the sign bit, is supplied to the EXOR circuit 306 as the value D313.

  Here, in the decoding device in FIG. 25, the control unit 202 determines that the weight of the check matrix column corresponding to the variable node to which the branch for which the message is to be found is connected is the message that the small FIFO memory 317 can store. When the number is less than or equal to the number, a signal instructing the selector 318 to select the first message D201 delayed by the small FIFO memory 317 is supplied to the input port P204 of the message calculation unit 201 as the control signal C204.

  In addition, when the weight of the column corresponding to the variable node is not less than or equal to the number of messages that can be stored in the small FIFO memory 317, the control unit 202 causes the selector 318 to select the second message DD201 from the message memory 104. The instructing signal is supplied to the input port P204 of the message calculation unit 201 as the control signal C204.

  When the control unit 202 supplies the message calculation unit 201 with a control signal C204 that instructs the selector 318 to select the message D201 delayed by the small FIFO memory 317, that is, the control signal C204 is stored in the message memory. If the signal is not a signal for instructing the selector 318 to select the message DD201 read the second time from 104, the message read from the message memory 104 is read out only once. I do.

  Therefore, in the control unit 202, when the column weight of the check matrix corresponding to the variable node to which the branch for which the message is to be obtained is connected is not less than the number of messages that can be stored in the small FIFO memory 317, The readout control for reading the same message twice from the message memory 104 described in 15 is performed, but the column weight of the parity check matrix corresponding to the variable node to which the branch for which the message is sought is connected is small FIFO. When the number of messages that can be stored in the memory 317 is equal to or less than the number of messages that can be stored, the read control for reading the same message from the message memory 104 twice is not performed, and the read control for reading only once, that is, the steps S101 and S102 in FIG. Of these, only step S101 is performed.

  Next, the variable node calculation and the check node calculation performed by the message calculation unit 201 in FIG. 26 will be described with reference to FIG.

  The left side of FIG. 27 schematically illustrates a variable node that performs the variable node calculation of Expression (1) and a check node that performs the check node calculation of Expression (7).

In the variable node, the message v _i corresponding to the branch to be calculated (i-th branch among the branches connected to the variable node) is sent from the remaining branches connected to the variable node u ₁ , u ₂ ,... Are obtained by adding as shown in the equation (1).

In the check node, the message u _j corresponding to the branch to be calculated (j-th branch among the branches connected to the check node) is connected to the check node as shown in Expression (7). Are integrated with the operation results of the non-linear function φ (x) with the arguments v ₁ , v ₂ ,... As arguments x, and the inverse function φ ⁻ with the resulting integrated value as the argument x ⁻ It is obtained by calculating ¹ (x).

  Now, assuming that data input to a node (data before input) is referred to as input data and data output from the node (data before output) is referred to as output data, the variable node and check node on the left side of FIG. This calculation is equivalent to the calculation shown on the right side of FIG.

That is, on the right side of FIG. 27, the message v _i is obtained at the variable node by the same calculation as the variable node on the left side of FIG. On the right side of FIG. 27, the nonlinear function φ (x) is not calculated at the check node, but the input data (messages v ₁ , v ₂ ,... Before input) input to the check node is nonlinear. After the calculation of the function φ (x), the calculation result is input to the check node, and the calculation result of the nonlinear function φ (x) is integrated at the check node. Further, on the right side of FIG. 27, the inverse function φ ⁻¹ (x) is not calculated at the check node, but the output data output from the check node (before the inverse function φ ⁻¹ (x) is calculated). (The integrated value of the calculation result of the nonlinear function φ (x)) is subjected to the calculation of the inverse function φ ⁻¹ (x), thereby obtaining the message u _j .

In the message calculation unit 201 in FIG. 26, variable node calculation and check node calculation for obtaining the messages v _i and u _j are performed as shown on the right side of FIG.

Here, with respect to the variable node on the right side of FIG. 27, the nonlinear function φ (x) and the inverse function φ ⁻¹ (with respect to both input data input to the variable node and output data output from the variable node. The operation x) is not performed. On the other hand, for the check node, the input data is subjected to the calculation of the nonlinear function φ (x), and the output data is subjected to the calculation of the inverse function φ ⁻¹ (x).

Therefore, the message calculation unit 201 in FIG. 26 that performs both the variable node calculation and the check node calculation performs the calculation of the nonlinear function φ (x) (outputs the calculation result), and the inverse function φ ^{−. A} LUT 314 that performs ¹ (x) calculation (outputs the calculation result) is provided.

  In the variable node calculation, the message calculation unit 201 substantially bypasses the LUTs 300, 310, and 314 for input data and output data to the variable node (configuration in FIG. 28 described later). On the right side, the calculation described for the variable node is performed.

  Further, the message calculation unit 201 is configured to cause the input data input to the check node to pass through the LUT 300 or 310 and the output data output from the check node to pass through the LUT 314 at the time of the check node calculation (FIG. 29), the calculation described for the check node on the right side of FIG.

  FIG. 28 shows a substantial configuration example of the message calculation unit 201 of FIG. 26 at the time of variable node calculation shown on the right side of FIG.

  As described above, in the variable node calculation, the selectors 301, 311 and 316 select the v terminal, but in FIG. 28, the selectors 301, 311 and 316 of the configuration shown in FIG. A portion that does not function during variable node calculation by selecting a terminal (portion not related to variable node calculation) is not shown.

  The message calculation unit 201 performs a variable node calculation of Expression (1) using a message input from each of the input ports P101 and P201, and further a message input from the input port PD201 as necessary, and The resulting message D202 is output from the output port P202.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the first message D201 (check node message u _j ) is supplied to the input port P201 from the check node corresponding to each row of the check matrix read out from the message memory 104 one by one.

  The reception data D101 supplied to the input port P101 is supplied to the calculator 313.

Also, the message D201 (message u _j ) supplied to the input port P201 is supplied to the v terminal of the selector 301, and is sent to the computing unit 302 as a message D306 from the selector 301 that has selected the v terminal during variable node calculation. Supplied.

  The arithmetic unit 302, the register 303, the selector 304, and the register 305 perform the same processing as the message calculation unit 191 described with reference to FIG.

That is, the computing unit 302 adds the message D306 by adding the message D306 (message u _j ) from the selector 301 and the value D307 stored in the register 303, and the integrated value obtained as a result is stored in the register. Store again in 303.

Then, a message D306 across one row of the parity check matrix are read in one by one, to the register 303, the message D306 integrated value (message u _j) is accumulated from all of the branches across one row of the parity check matrix (j = When Σu _j ) from 1 to d _v is stored, the selector 304 receives the value stored in the register 303, that is, the message D306 (message u _j ) from all branches over one column of the check matrix. select the integrated integrated values D307 (? uj _j from j = 1 to d _v), it is stored in output register 305.

The register 305 supplies the stored value D307 as the value D308 to the selector 304 and the calculator 312. The selector 304 selects the value D308 supplied from the register 305, outputs it to the register 305, and stores it again immediately before the value obtained by integrating the message D306 for one column is stored in the register 303. That is, until the message D306 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 305 supplies the previously accumulated value to the selector 304 and the calculator 312.

On the other hand, upon output of a new value from the register 305 D308 (Σu _j from j = 1 to d _v) is started, namely, the integrated value message D201 is integrated for one column in the register 303 (j = 1 immediately after the? uj _j) to d _v is stored in the message calculation unit 201, the message D201 (message u _j) the same messages DD201, i.e., the second message u _j from the message memory 104, input The messages DD201 are input one by one from the port PD201 and supplied to the m terminal of the selector 318.

Also, the small FIFO memory 317 delays the first message D201 until a new value D308 (Σu _j from j = 1 to d _v ) is output from the register 305, and sends it to the f terminal of the selector 318. Supply.

Here, if the number of messages (storable number) that can be stored in the small FIFO memory 317 is d, the small FIFO memory 317 is smaller than the maximum weight of the parity check matrix as described above. because it does not only have capacity to store the number of messages, from the register 305, the parity check matrix, a new value d _v number of messages D201 corresponding to a certain one row is accumulated (integrated value) d 308 (j = 1 In the small FIFO memory 317, it may not be possible to delay d _v messages D201 corresponding to the one column until Σu _j ) from to d _v is output.

That is, the number d of messages that can be stored in the small FIFO memory 317 is the weight d _v of the parity check matrix corresponding to the variable node to which d _v messages D201 whose stored values are stored in the register 305 are input. If it is smaller than is that in the small FIFO memory 317, of its d _v number of messages D201, when d + 1 th message is stored, 1 th message from being output Therefore, during the period from the register 305, to a small FIFO memory 317 is the new value d _v number of messages D201 greater than the number d of storable messages is accumulated d 308 (integrated value) is output, the d _v All the messages D201 cannot be stored in the small FIFO memory 317.

Therefore, as described above, the control unit 202 (FIG. 25) sets the weight d _{v of} the column corresponding to the variable node to which the branch for which the message is sought is connected to the message that the small FIFO memory 317 can store. When the number d is not less than d, a control signal C204 for instructing the selector 318 to select the second message DD201 from the message memory 104 is supplied to the message calculation unit 201.

  In the message calculation unit 201, the control signal C204 from the control unit 202 is supplied to the selector 318 via the input port P204.

  The selector 318 selects and outputs the second message DD201 from the message memory 104 supplied to the terminal m in accordance with the control signal C204.

On the other hand, the control unit 202 (FIG. 25) is the weight d _v column of the check matrix corresponding to a variable node that branches trying to find a message is connected, the number of messages that can be stored is small FIFO memory 317 d When it is below, the message calculation unit 201 is supplied with a control signal C204 that instructs the selector 318 to select the first message D201 delayed in the small FIFO memory 317.

  In the message calculation unit 201, the control signal C204 from the control unit 202 is supplied to the selector 318 via the input port P204.

  The selector 318 selects and outputs the first message D201 delayed by the small FIFO memory 317 supplied to the terminal f in accordance with the control signal C204.

Here, when the number d of messages that can be small FIFO memory 317 stores is not smaller than the weight d _v column of the check matrix corresponding to d _v number of message D201 that integrated value in the register 305 is stored in the period from the register 305, until a new value d _v number of messages D201 small FIFO memory 317 is not greater than the number d of storable messages are accumulated (integrated value) d 308 is output, the All d _v messages D201 can be stored in the small FIFO memory 317, that is, all d _v messages D201 can be delayed until d _v messages D201 are accumulated. The delayed message D201 can be output after the integration of d _v messages D201 is completed.

Therefore, the control unit 202 (FIG. 25) determines that the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which a message is to be obtained is connected is the number d of messages that the small FIFO memory 317 can store. When the following is true, the control signal C204 for instructing the selector 318 to select the message D201 delayed in the small FIFO memory 317 is supplied to the selector 318 of the message calculation unit 201. The message D201 delayed in the memory 317 is selected and supplied to the selector 311.

  The selector 311 selects the v terminal at the time of variable node calculation, and the message from the selector 318 (second message DD201 or the first time delayed by the small FIFO memory 317) supplied to the v terminal is selected. The message D201) is supplied to the calculator 312 as the message D315.

The calculator 312 subtracts the message D315 from the selector 311 from the integrated value D308 supplied from the register 305. In other words, in the calculator 312, the message from the branch to be obtained from the integrated value D308 (Σu _j from j = 1 to d _v ) of the message D201 (message u _j ) from all the branches over one column of the check matrix. subtracts the message D315 as u _{j (j} = d _v of u _j), we obtain the subtraction value D316 (? uj _j from j = 1 to d _v -1), and supplies to the calculator 313.

Calculator 313 adds the reception data D101 from the input port P101, the calculator 312 subtracts value from D316 by adding the (? Uj _j from j = 1 to d _v -1), the addition value obtained as a result D317 ( The variable node message v _i ) is supplied to the v terminal of the selector 316.

The selector 316 selects the v terminal at the time of variable node calculation, and outputs the addition value D317 from the calculator 313 supplied to the v terminal from the output port P202 as a message D202 (message v _i ).

As described above, in the message calculation unit 201 in which the selectors 301 and 304 have selected the v terminal, the variable node calculation of Expression (1) is performed, and the resulting message (variable node message) v _i is output. Output from port P202.

  FIG. 29 shows a substantial configuration example of the message calculation unit 201 of FIG. 26 at the time of the check node calculation shown on the right side of FIG.

  As described above, in the check node calculation, the selectors 301, 311 and 316 select the c terminal. In FIG. 29, the selectors 301, 311 and 316 of the configuration shown in FIG. A portion that does not function at the time of check node calculation by selecting a terminal (portion not related to the check node calculation) is not shown.

At the time of the check node calculation, the variable node message v _i read from the message memory 104 one by one and corresponding to each column of the check matrix is sequentially supplied as the message D201 to the input port P201. Is done.

The message D201 (message v _i ) supplied to the input port P201 is supplied to the small FIFO memory 317. Further, the low-order bits of the message D201 excluding the most significant bit, that is, the absolute value D303 (| v _i |) of the message D201 is supplied to the LUT 300, and the most significant bit, that is, the sign bit D304 of the message D201 is EXOR. This is supplied to the circuit 306.

  In the LUT 300, the selector 301, the arithmetic unit 302, the register 303, the selector 304, the register 305, the EXOR circuit 306, the register 307, the selector 308, the register 309, the arithmetic unit 312, the LUT 314, the EXOR circuit 315, and the selector 316, FIG. Processing similar to that of the message calculation unit 191 described in the above is performed.

That is, the LUT 300 reads out the operation result D305 (φ (| v _i |)) obtained by performing the operation of the nonlinear function φ (| v _i |) using the absolute value D303 (| v _i |) as an argument. Supply to the c terminal.

The selector 301 selects the c terminal during the check node calculation, and the calculation result D305 (φ (| v _i |)) from the LUT 300 supplied to the c terminal is used as the calculation result D306 (φ (| v _i |). )) To the computing unit 302.

The computing unit 302 adds the calculation result D306 (φ (| v _i |)) and the value D307 stored in the register 303 to integrate the calculation result D306, and the integrated value obtained as a result is registered in the register 303. Store again.

When the message D201 over one row of the check matrix is read one by one and the accumulated value obtained by accumulating the operation result D306 for one row is stored in the register 303, the selector 304 stores the value stored in the register 303. , i.e., phi obtained from the messages D201 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D307 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 305 for storage. The register 305 supplies the stored integrated value D307 as a value D308 to the selector 304 and the calculator 312.

The selector 304 selects the value D308 supplied from the register 305, outputs it to the register 305, and stores it again immediately before the integrated value obtained by integrating the operation results D306 for one row is stored in the register 303. That is, until φ (| v _i |) obtained from the message D201 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 305 accumulates φ (| v _i |) is supplied to the selector 304 and the calculator 312.

New value from the register 305 D 308 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) the output of the start, i.e., calculation results D306 of one row in the register 305 is accumulated integrated value (i = from 1 to _{i = d c Σφ (| v} i |)) immediately after the stored, the message calculation unit 201, the message D201 (message v _i) the same messages DD201, i.e., the message memory The second message v _i from 104 is input one by one from the input port PD 201 and supplied to the m terminal of the selector 318.

On the other hand, the small FIFO memory 317, a new value from the register 305 D 308 (from i = 1 Sigma] [phi to _{d c (| v i |)} ) until it is output, the first message from the message memory 104 D201 Is supplied to the f terminal of the selector 318.

Here, if the number of messages that can be stored in the small FIFO memory 317 is d, the small FIFO memory 317 stores a smaller number of messages than the maximum value of the check matrix weight as described above. since only has capacity, from the register 305, the parity check matrix, phi of d _c number of messages D201 corresponding to a certain one line (| v _i |) new accumulated value from (i = 1 to d _c of Σφ (| v _i |) until) is output, in a small FIFO memory 317, it may not be possible to delay d _c number of messages D201 corresponding to the one line.

That is, the number d of messages that can be small FIFO memory 317 is stored in the in the register 305 φ (| v _i |) integrated value of corresponding to the check node to which d _c pieces of message D201 to be stored is input If it is smaller than the weight d _c line of check matrix, the small FIFO memory 317, when one of its d _c number of messages D201, d + 1 th message is stored, one since the eye of the message from being output, the register 305, the small FIFO memory 317 is φ of more d _c number of messages D201 than the number d of storable messages until is integrated (| | v _i) , all of its d _c number of messages D201, can not be stored in a small FIFO memory 317.

Therefore, the control unit 202 (FIG. 25), as described above, the weight d _c in the row corresponding to the check node branches trying to find a message is connected, a small FIFO memory 317 is possible messages stored When the number d is not less than d, a control signal C204 for instructing the selector 318 to select the second message DD201 from the message memory 104 is supplied to the message calculation unit 201.

  In the message calculation unit 201, the control signal C204 from the control unit 202 is supplied to the selector 318 via the input port P204.

  The selector 318 selects and outputs the second message DD201 from the message memory 104 supplied to the terminal m in accordance with the control signal C204.

On the other hand, the control unit 202 (FIG. 25) is the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, the number of messages that can be stored is small FIFO memory 317 d When it is below, the message calculation unit 201 is supplied with a control signal C204 that instructs the selector 318 to select the first message D201 delayed in the small FIFO memory 317.

  In the message calculation unit 201, the control signal C204 from the control unit 202 is supplied to the selector 318 via the input port P204.

The selector 318 selects and outputs φ (| v _i |) of the first message D201 supplied to the terminal f and delayed by the small FIFO memory 317 in accordance with the control signal C204.

Here, the number d of messages that can be small FIFO memory 317 stores are rows of check matrix corresponding to the check nodes d _c pieces of message D201 that integrated value in the register 305 is stored is input weight d If it is not smaller than _c, a new integrated value (i) of φ (| v _i |) of d _c messages D201 not larger than the number d of messages that can be stored in the small FIFO memory 317 from the register 305. = 1 to d _c until Σφ (| v _i |)) is output, all the d _c messages D201 are stored in the small FIFO memory 317, that is, d _c phi messages D201 (| v _i |) until it is integrated, its d _c number of messages D201 can defer all, the messages D201 after the delay of d _c number of messages D201 phi ( | v _i |) can be output after the integration is completed.

Therefore, the control unit 202 (FIG. 25) determines that the weight d _c of the check matrix row corresponding to the check node to which the branch for which a message is to be obtained is connected is the number d of messages that the small FIFO memory 317 can store. When it is below, the control signal C204 for instructing the selector 318 to select φ (| v _i |) of the message D201 delayed by the small FIFO memory 317 is supplied to the selector 318 of the message calculation unit 201. Accordingly, the selector 318 selects and outputs the first message D201 delayed by the small FIFO memory 317.

Of the messages output by the selector 318 (the first message D201 delayed by the small FIFO memory 317 or the second message DD201), the least significant bits other than the most significant bit, that is, the absolute value D312 (| v _i | ) Is supplied to the LUT 310, and the most significant bit, that is, the sign bit D313 is supplied to the EXOR circuit 315.

The LUT 310 is the same LUT as the LUT 300, and the operation result D314 (φ (| v _i |) obtained by calculating the nonlinear function φ (| v _i |) using the message absolute value D312 (| v _i |) as an argument. ) And is supplied to the c terminal of the selector 311.

The selector 311 at the time of a check node calculation selects the terminal c, the operation result from LUT310 supplied to the terminal c thereof D314 of _{(φ (|) | v i} ), the operation result D315 (φ (| v _i | )) To the calculator 312.

The arithmetic unit 312 subtracts the value D315 supplied from the selector 311 from the value D308 supplied from the register 305, and supplies the subtraction result to the LUT 314 as a subtraction value D316. That is, the calculator 312, phi obtained from the messages D201 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) of the integrated value D 308 (i = 1 from i = d _c Σφ (| v _i |)) until the value D315 of φ (| v _i |) obtained from the message (message v _i ) from the branch to be obtained is subtracted, and the subtraction value (from i = 1) Σφ (| v _i |) up to i = d _c −1) is supplied to the LUT 314 as a subtraction value D316.

The LUT 314 uses the subtraction value D316 (Σφ (| v _i |) from i = 1 to i = d _c −1) as an argument to the inverse function φ ⁻¹ (Σφ (| v _i |)). The calculation result D318 (φ ⁻¹ (Σφ (| v _i |))) obtained by performing the above calculation is output.

  In parallel with the above processing, the EXOR circuit 306 multiplies the sign bits by calculating the exclusive OR of the value D310 stored in the register 307 and the sign bit D304, and obtains the multiplication result D309. The data is stored again in the register 307. When the sign bit D304 of the message D201 from all branches over one row of the check matrix is multiplied, the register 307 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D309 to the sign bit D304 is multiplied by the messages D201 from all of the branches across one line of the parity check matrix stored in the register 307, the selector 308, Paisign the value stored in the register 307, i.e., the value D310 (i = 1 the sign bit D304 of the message D201 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 309 for storage. The register 309 supplies the stored value D311 to the selector 308 and the EXOR circuit 315.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D309 to the sign bit D304 is multiplied by the messages D201 from all of the branches across one line of the parity check matrix until just before is stored in the register 307 The selector 308 selects the value D311 supplied from the register 309, outputs it to the register 309, and stores it again. That is, the register 309 supplies the previously stored value to the selector 308 and the EXOR circuit 315 until the sign bits D304 of the message D201 (message v _i ) from all branches over one row of the parity check matrix are multiplied. .

On the other hand, when the (Paisign of i = 1 through _{i = d c (v i)} ) value D310 to the sign bit D304 is multiplied by the messages D201 from all of the branches across one line to the register 307 is stored, the The value D301 is selected by the selector 308 and stored in the register 309, and at the same time, a new integrated value (i) obtained by integrating φ (| v _i |) of the message D201 for one line in the register 305 as described above. = from 1 to _{i = d c Σφ (| v} i |)) is stored.

New accumulated value in the register 305 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) When is stored, a message as described above, the selector 318, which is delayed by a small FIFO memory 317 D201 or the second message DD201 is selected and output, and the lower bits of the message output by the selector 318 except the most significant bit, that is, the absolute value (| v _i |) is supplied to the LUT 310, The most significant bit, that is, the sign bit D313 is supplied to the EXOR circuit 315.

The EXOR circuit 315 calculates the value D311 of the message from the selector 318 by calculating the exclusive OR of the new value D311 stored and output in the register 309 and the sign bit of the message from the selector 318. Divide by the sign bit D313 and output the division result as a division value D319. That, EXOR circuit 315, branches multiplication value of the sign bit D304 of the messages D201 from all of the branches across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v i)} ), to be obtained Is divided by the sign bit D313 (i = d _c sign (v _i )) of the message v _i and the divided value (Πsign (v _i ) from i = 1 to i = d _c −1) is divided. Output as the value D319.

Then, in the message calculation unit 201, a bit string D320 (message u _j ) having the calculation result D318 output from the LUT 314 as the lower bits and the division value D319 output from the EXOR circuit 315 as the most significant bit (sign bit). Is supplied to the c terminal of the selector 316.

The selector 316 selects the c terminal during the check node calculation, and outputs the bit string D320 (message u _j ) supplied to the c terminal from the output port P202 as the message D202.

As described above, in the message calculation unit 201 in which the selectors 301, 311, and 316 have selected the c terminal, the check node calculation of Expression (7) is performed, and the resulting message (check node message) u _j Is output from the output port P202.

  Although not shown in the figure, in the decoding apparatus of FIG. 25, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1), and the calculation result is the final decoding. Output as a result.

  As described above, in the decoding apparatus of FIG. 25, as the delay memory, the small FIFO memory 317 (FIG. 26) that stores a smaller number of messages than the maximum value of the weight of the parity check matrix is provided. Compared with the case where the FIFO memory 320 (FIG. 22) for storing a number of messages equal to the maximum value of the weights is provided, the scale of the decoding device can be reduced.

  Furthermore, when the weight of the parity check matrix corresponding to the node of interest is less than or equal to the storable number d (when it is not greater than the storable number d), the output of the small FIFO memory 317 is selected and a node (variable node, Since it is used for the computation of the check node), the message is read and written at the same time as the decoding device of FIG. Can do. Therefore, iterative decoding can be performed as many times as the decoding device of FIG. 21 (and FIG. 8) (since the time required for one decoding is the same as that of the decoding device of FIG. 21 (and FIG. 8)). Therefore, it is possible to suppress degradation of the decoding performance.

  Further, when the weight of the check matrix corresponding to the node of interest is larger than the storable number d, the same message is read twice from the message memory 104, the second read message is selected, Since it is used for the node calculation, the LDPC code can be decoded even if the weight of the parity check matrix corresponding to the node of interest is larger than the storable number d.

  From the above, according to the decoding device of FIG. 25, it is possible to suppress degradation of decoding performance while reducing the scale.

Here, the storable number d of the small FIFO memory 317 is 3, for example, and the parity check matrix defining the LDPC code to be decoded is, for example, the weight d _{v of} each column shown in FIG. When the weight of each row is a matrix of 6, 3 that is the storable number d is not smaller than 3 that is the column weight d _v of the parity check matrix. Since all the three messages D201 can be delayed in the small FIFO memory 317 until the number of messages D201 are accumulated, the selector 318 delays in the small FIFO memory 317 supplied to the terminal f. The first message D201 is selected.

In this case, 3 is storable number d is a smaller than 6 is the weight d _c line of the check matrix, therefore, at the time of a check node calculation, six more than 3 is storable number d Until φ (| v _i |) of the message D201 is accumulated, all six messages D201 cannot be delayed in the small FIFO memory 317, and therefore the selector 318 supplies the message D201 to the terminal m. The second message DD201 from the message memory 104 is selected.

  In the decoding apparatus of FIG. 25, in the message calculation unit 201, a part of the circuit that performs the variable node calculation and the circuit that performs the check node calculation (the calculator 302, the register 303, the selector 304, the register 305, and Since the computing unit 312) is shared, the scale of the decoding device can be further reduced by the sharing.

  Next, FIG. 30 is a block diagram illustrating a configuration example of the third embodiment of the decoding device to which the present invention has been applied.

  In the figure, portions corresponding to those of the decoding device of FIG. 25 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the decoding apparatus in FIG. 30 is provided with a message calculation unit 211 instead of the message calculation unit 201 and a control unit 212 in place of the control unit 202. It is configured in the same way as the device.

  In the decoding device of FIG. 30, the message calculation unit 211 is configured to share a part of a circuit that performs variable node calculation and a circuit that performs check node calculation. Further, in the decoding apparatus of FIG. 30, the message calculation unit 211 that performs variable node calculation and check node calculation is a number equal to the maximum value of the check matrix weights as in the FIFO memory 320 of the message calculation unit 191 of FIG. The delay memory stores a number of messages smaller than the maximum value of the check matrix weights.

  In the decoding device of FIG. 30, the control unit 212 performs read / write control similar to that of the control unit 174 of the decoding device in FIG. 12 as described in the flowchart of FIG. Take control.

  Further, the control unit 212 supplies the control signal C603 to the message calculation unit 211, and instructs the message calculation unit 211 to perform variable node calculation or check node calculation with the control signal C603.

  Further, as described with reference to the flowchart of FIG. 20, the control unit 212 performs selector control processing, and supplies a control signal C604 corresponding to the control signal C104 to the message calculation unit 211. The message calculation unit 211 performs variable node calculation and check node calculation by selectively using the message read from the message memory 104 for the second time in accordance with the control signal C604 from the control unit 212.

  In the decoding device of FIG. 30, messages stored in the message memory 104 are read one by one and supplied to the message calculation unit 211. The message calculation unit 211 performs an operation using the message from the message memory 104, and the message obtained by the operation is stored in the message memory 104. In the decoding device of FIG. 30, the above processing is repeated and full serial iterative decoding is performed.

  That is, the reception data memory 105 is supplied with reception data (log likelihood ratio) D100 obtained by receiving the transmitted LDPC code, and the reception data memory 105 stores the reception data D100.

  During the variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 212 and supplies it to the message calculation unit 211 as reception data D101.

  Further, during the variable node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 212, and the message read first time as the message D601. The message read to the message calculation unit 211 and read for the second time is supplied to the message calculation unit 211 as a message DD601.

  The message calculation unit 211 receives the first message D601 supplied from the message memory 104, the reception data D101 supplied from the reception data memory 105, and the second time supplied from the message memory 104 as necessary. Message DD601 is used, variable node calculation is performed based on the check matrix in accordance with control signals C603 and C604 supplied from the control unit 212, and a message obtained as a result of the variable node calculation is set as message D622 in the message memory 104. To supply.

  The message memory 104 stores the message D622 supplied from the message calculation unit 211 in accordance with the control signal supplied from the control unit 212.

  On the other hand, at the time of the check node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 212, and the message read the first time as the message D601. The message read to the message calculation unit 211 and read for the second time is supplied to the message calculation unit 211 as a message DD601.

  The message calculation unit 211 uses the first message D601 supplied from the message memory 104 and, if necessary, the second message DD601 supplied from the message memory 104 to control the control signal C603 from the control unit 212. And a check node operation according to C604, and a message obtained by the check node operation is supplied to the message memory 104 as a message D622.

  The message memory 104 stores the message D622 supplied from the message calculation unit 211 in accordance with the control signal supplied from the control unit 212.

  Here, the calculation performed by the message calculation unit 211 in FIG. 30 will be described.

Now, as a message (data) output from the jth branch of the branches connected to the check node, a message represented by the expression u ′ _j = φ (| u _j |) × sign (u _j ) When u ′ _j is introduced, Equation (1) and Equation (7) can be rewritten as Equation (9) and Equation (10), respectively.

・・・（９）

... (9)

・・・（１０）

... (10)

Here, when the expression u ′ _j = φ (| u _j |) × sign (u _j ) is rewritten for the message u _j , the expression u _j = φ ⁻¹ (| u ′ _j |) × sign (u ′ _j ). By substituting this expression u _j = φ ⁻¹ (| u ′ _j |) × sign (u ′ _j ) into the expression (1) of the variable node calculation, the expression (9 ) Can be obtained.

Further, by substituting the expression (7) of the check node calculation into the expression u ′ _j = φ (| u _j |) × sign (u _j ), the expression (10) as a new check node calculation expression is obtained. Obtainable.

In the variable node calculation of Expression (9), the inverse function φ ⁻¹ (| u ′ _j |) is calculated using the absolute value | u ′ _j | of the input data (message) u ′ _j as an argument. In the check node calculation of 10), the calculation of the nonlinear function φ (| v _i |) using the absolute value | v _i | of the input data v _i as an argument is performed. Here, the nonlinear function φ (x) and its inverse function φ ⁻¹ (x) are equal when x> 0. Therefore, in both formula (9) and formula (10), the function φ (x) is calculated using the absolute value | x | of the input data x as an argument.

In Expression (9), the sign of the input data u ′ _j (sign (u ′ _j )) is considered in the calculation result of the function φ (x) (the calculation result of φ ⁻¹ (| u ′ _j |)). The value (φ ⁻¹ (| u ′ _j |) × sign (u ′ _j )) is integrated, and the received data u _0i is added to the integrated value to obtain the message v _i .

In addition, in Expression (10), the calculation result of the function φ (x) (the calculation result of φ (| u _j |)) is integrated, and separately, the product of the sign bits of the input data v _i (Πsign (v _i )) is obtained, and the integrated value of the operation result of the function φ (x) is multiplied by the product of the sign bits to obtain the message u ′ _j .

  In the message calculation unit 211 of FIG. 30, the variable node calculation of Expression (9) and the check node calculation of Expression (10) are performed.

  FIG. 31 shows a configuration example of the message calculation unit 211 of FIG.

  The message calculation unit 211 is provided with input ports P101, P601, PD601, P603, and P604, and an output port P622.

  The reception data D101 read from the reception data memory 105 is supplied (input) to the input port P101. The input port P601 is supplied (inputted) with the first message D601 (first message) D601 read out of the same message D601 and DD601 read twice from the message memory 104. A message (second message) DD601 read out the second time is supplied. Further, the control signal C603 from the control unit 212 (FIG. 30) is supplied to the input port P603, and the control signal C604 from the control unit 212 is supplied to the input port P604.

  The message calculation unit 211 receives the first message D601 input from the input port P601, the second message DD601 input from the input port PD601, and the message (received data) input from the input port P101. A message obtained as a result of performing a variable node operation of Equation (9) or a check node operation of Equation (10) based on the check matrix in accordance with control signals C603 and C604 input from the input port P603. D622 is output from the output port P622.

  Here, with reference to FIG. 32, the variable node calculation and the check node calculation performed by the message calculation unit 211 of FIG. 31 will be described.

  The left side of FIG. 32 schematically shows the variable node that performs the variable node calculation of Expression (1) and the check node that performs the check node calculation of Expression (7), and is the same diagram as the right side of FIG.

On the left side of FIG. 32, as described on the right side of FIG. 27, after the operation of the nonlinear function φ (x) is performed on the input data input to the check node, the calculation result is input to the check node. , The calculation results of the nonlinear function φ (x) are integrated. Furthermore, (before the calculation of the inverse function phi ^-1 (x) is subjected, the integrated value of the calculation result of the nonlinear function phi (x)) output data output from the check node, the inverse function phi ^-1 (x ) And the message u _j is obtained.

This message u _j is input as input data to the variable node and used for variable node calculation.

Therefore, as shown on the left side of FIG. 32, instead of performing the operation of the inverse function φ ⁻¹ (x) on the output data x output from the check node, it is input to the variable node as shown on the right side of FIG. The variable node calculation and the check node calculation can be performed even if the inverse function φ ⁻¹ (x) is calculated on the input data x.

That is, in FIG. 32 right, as described in equation (9), the input data is input to the variable node calculation of the inverse function phi ^-1 (x) is subjected, in the variable node, the inverse function phi ^{- The} message v _i is obtained by integrating the calculation results of ¹ (x). On the right side of FIG. 32, as described in Expression (10), the input data input to the check node is subjected to the calculation of the nonlinear function φ (x), and the nonlinear function φ (x) is calculated at the check node. The calculation results of are integrated. Furthermore, on the right side of FIG. 32, the integrated value obtained by integrating the calculation results of the nonlinear function φ (x) at the check node is the output data as it is (without the calculation of the inverse function φ ⁻¹ (x)). It is output as _u'j .

In the message calculation unit 211 of FIG. 31, the variable node calculation of Expression (9) and the check node calculation of Expression (10) for obtaining the messages v _i and u ′ _j are performed as shown on the right side of FIG.

As described above, the message calculation unit 211 in FIG. 31 performs both the variable node calculation of Expression (9) and the check node calculation of Expression (10) for obtaining the messages v _i and u ′ _j shown on the right side of FIG. The message calculation unit 211 (FIG. 31) has a calculation result of the nonlinear function φ (x) that can obtain the same calculation result as the inverse function φ ⁻¹ (x) for the input data x input to the check node. And an LUT 600 (and LUT 610) for outputting the calculation result of the inverse function φ ⁻¹ (x) for the input data x input to the variable node.

  Then, the message calculation unit 211 of FIG. 31 performs the variable node calculation of Expression (9) and the check node calculation of Expression (10) by changing the substantial configuration according to the control signal C603 supplied to the input port P603. Selectively.

  That is, the message calculation unit 211 (FIG. 31) includes selectors 601, 611, and 615, and the control signal C603 supplied to the input port P603 is supplied to the selectors 601, 611, and 615.

  The selectors 601, 611, and 615 have a v terminal and a c terminal, select a value supplied to either the v terminal or the c terminal according to the control signal C603, and output the selected value to the subsequent stage. That is, when the control signal C603 is a control signal for instructing variable node calculation, the selectors 601, 611, and 615 select the value supplied to the v terminal and output it to the subsequent stage, and the control signal C603 is checked. In the case of a control signal instructing node calculation, the value supplied to the c terminal is selected and output to the subsequent stage.

  As a result, in the message calculation unit 211 of FIG. 31, when the control signal C603 indicates a variable node calculation, a variable node calculation is performed, and when the control signal C603 indicates a check node calculation, a check node calculation is performed. Is done.

  That is, FIG. 33 shows a substantial configuration example of the message calculation unit 211 of FIG. 31 at the time of variable node calculation shown on the right side of FIG.

  As described above, in the variable node calculation, the selectors 601, 611, and 615 select the v terminal. In FIG. 33, the selectors 601, 611, and 615 of the configuration illustrated in FIG. A portion that does not function during variable node calculation by selecting a terminal (portion not related to variable node calculation) is not shown.

  The message calculation unit 211 performs the variable node calculation of Expression (9) using the messages input from the input ports P101, P601, and PD601, and outputs the resulting message D622 from the output port P622.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the first message D601 (message u ′ _j ) is supplied to the input port P601 from the check node corresponding to each row of the parity check matrix read out from the message memory 104 one by one.

  The reception data D101 supplied to the input port P101 is supplied to the calculator 613.

Further, the low-order bits excluding the most significant bit of the message D601 (message u ′ _j ) supplied to the input port P601, that is, the absolute value D603 (| u ′ _j |) of the message D601 is supplied to the LUT 600. .

The LUT 600 stores the calculation result of the nonlinear function φ (x) (and the inverse function φ ⁻¹ (x)), and takes the absolute value D603 (| u ′ _j |) as an argument and the inverse function φ ⁻¹ (| u _'j |) calculates a calculation result of the ^{D605 (φ -1 (| u'} j |)) to read and output. The operation result D605 (φ ⁻¹ (| u ′ _j |)) output from the LUT 600 is the most significant bit of the message D601 (message u ′ _j ) supplied to the input port P601, that is, the most significant bit. By adding the sign bit D604 (sign (u ′ _j )) of the message D601, the message D606 (check node message u _j ) is obtained and supplied to the v terminal of the selector 601.

As described above, the selector 601 selects the v terminal at the time of the variable node calculation, and the message D606 (check node message u _j ) supplied to the v terminal is supplied to the calculator 602 as the message D607. .

The computing unit 602 adds the message D607 (message u _j ) from the selector 601 and the value D608 stored in the register 603 to add up the message D607, and the integrated value obtained as a result is stored in the register 603. Store again. Note that if the message D607 from all the branches over one column of the check matrix (obtained from the message u ′ _j ) is accumulated, the register 603 is reset.

When the message D601 over one column of the check matrix is read one by one, and the value obtained by accumulating the message D607 for one column is stored in the register 603, that is, all over the one column of the check matrix are stored in the register 603. When the integrated value (Σu _j from j = 1 to d _v ) obtained by integrating the message D607 (message u _j ) from the branch is stored, the selector 604 stores the value stored in the register 603, that is, select the message from all of the branches across one row of the parity check matrix D607 (message u _j) the accumulated integrated values D608 (? uj _j from j = 1 to d _v), is stored in output register 605 .

The register 605 supplies the stored value D608 as the value D609 to the selector 604 and the calculator 612. The selector 604 selects the value D609 supplied from the register 605, outputs it to the register 605, and stores it again until the value obtained by integrating the message D607 for one column is stored in the register 603. That is, until the message D607 (message u _j ) from all the branches over one column of the check matrix is accumulated, the register 605 supplies the previously accumulated value to the selector 604 and the calculator 612.

On the other hand, the message D601 (message u ′ _j ) supplied to the input port P601 is also supplied to the small FIFO memory 616.

The small FIFO memory 616 is a delay memory for delaying a message, but has a number (one or more) smaller than the maximum value of the check matrix weight (column weight d _v and row weight d _c ). This is a small-capacity FIFO memory that has only the capacity to store messages.

  The small FIFO memory 616 delays the first message D601 from the message memory 104 and supplies it to the f terminal of the selector 617.

  The selector 617 has an f terminal and an m terminal as input terminals, and the message D601 delayed by the small FIFO memory 616 is supplied to the f terminal as described above. The second message PD601 supplied from the message memory 104 to the terminal DD601 is supplied to the m terminal of the selector 617.

  Further, the control signal C604 supplied from the control unit 212 (FIG. 30) to the input port P604 is supplied to the selector 617.

  The selector 617 performs one of the first message D601 delayed by the small FIFO memory 616 and the second message DD601 from the message memory 104 according to the control signal C604 from the control unit 212 for variable node calculation. Select and output as a message to use.

  The lower-order bits excluding the most significant bit of the message output from the selector 617, that is, the first message D601 delayed by the small FIFO memory 616 or the second message DD601 from the message memory 104, that is, the absolute value Is supplied to the LUT 610 as a value D613, and the most significant bit, that is, the sign bit D614 is used as the sign bit of the output D615 of the LUT 610.

Here, in the decoding device of FIG. 30, the control unit 212 can store the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is sought is connected, in the small FIFO memory 616. When the number of messages (storable number) is equal to or less than d, a control signal C604 for instructing the selector 617 to select the first message D601 delayed by the small FIFO memory 616 is input to the input port P604 of the message calculation unit 211. Supply.

Furthermore, when the column weight d _v corresponding to the variable node is not less than or equal to the number d that can be stored in the small FIFO memory 616, the control unit 212 selects the second message DD601 from the message memory 104 to the selector 617. The instructing control signal C604 is supplied to the input port P604 of the message calculation unit 211.

  When the control unit 212 supplies the message calculation unit 211 with a control signal C604 that instructs the selector 617 to select the message D601 delayed by the small FIFO memory 616, that is, the control signal C604 is stored in the message memory. In the case where the signal is not a signal for instructing the selector 617 to select the message DD601 read for the second time from 104, for reading the message from the message memory 104, read control for reading the message from the message memory 104 only once. I do.

Therefore, in the control unit 212, when the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is to be obtained is connected is not less than or equal to the storable number d of the small FIFO memory 616, FIG. The readout control for reading the same message twice from the message memory 104 described in 15 is performed, but the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is requested is connected is: If the number of storable memories in the small FIFO memory 616 is less than or equal to d, read control for reading the same message from the message memory 104 twice is not performed, and read control for reading only once, ie, steps S101 and S102 in FIG. Of these, only step S101 is performed.

The register 605 stores a new value (integrated value) D609 (Σu _j from j = 1 to d _v ) obtained by integrating the message D607 (message u _j ) from all branches over one column of the check matrix. When the output is started, that is, immediately after the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D607 for one column is stored in the register 603, it is the same as the LUT 600. The configuration LUT 610 reverses the absolute value D613 (| u ′ _j |) of the message (the first message D601 delayed by the small FIFO memory 616 or the second message DD601) output from the selector 617 as an argument. An operation result D615 (φ ⁻¹ (| u ′ _j |)) obtained by performing the operation of the function φ (| u ′ _j |) is read and output.

The calculation result D615 (φ ⁻¹ (| u ′ _j |)) output from the LUT 610 is stored in the most significant bit of the message output from the selector 617 (the first message D601 delayed by the small FIFO memory 616, or The most significant bit of the second message DD601) (message u ′ _j ), that is, the sign bit D614 (sign (u ′ _j )) is added to obtain a message D616 (check node message u _j ). , And supplied to the v terminal of the selector 611.

As described above, the selector 611 selects the v terminal during the variable node calculation, and the message D616 (check node message u _j ) supplied to the v terminal is supplied to the calculator 612 as the message D617. .

Calculator 612, from the supplied integrated value D609 (? Uj _j from j = 1 to d _v) from the register 605, subtracts the message from the selector 611 D617 (j = d _v message u _j) of. In other words, the computing unit 612 uses the message D607 (message u _j ) from all branches over one column of the parity check matrix to calculate the message from the branch to be obtained from the integrated value D609 (Σu _j from j = 1 to d _v ). subtracts the message D617 as u _{j (j} = d _v of u _j), we obtain the subtraction value D618 (? uj _j from j = 1 to d _v -1), and supplies the arithmetic unit 613.

Calculator 613 adds the reception data D101 from the input port P101, and by adding the subtracted value from the arithmetic unit 612 D618 (? Uj _j from j = 1 to d _v -1), the message D619 (variable node message v _i ) is obtained and supplied to the v terminal of the selector 615.

The selector 615 selects the v terminal during the variable node calculation, and outputs the message D619 (variable node message v _i ) from the calculator 613 supplied to the v terminal as the message D622 from the output port P622.

As described above, in the message calculation unit 211 in which the selectors 601, 611, and 615 have selected the v terminal, the variable node calculation of Expression (9) is performed, and the resulting message (variable node message) v _i Is output from the output port P622.

  Next, FIG. 34 illustrates a substantial configuration example of the message calculation unit 211 of FIG. 31 at the time of the check node calculation illustrated on the right side of FIG.

  As described above, in the check node calculation, the selectors 601, 611, and 615 select the c terminal, but in FIG. 34, the selectors 601, 611, and 615 of the configuration illustrated in FIG. A portion that does not function at the time of check node calculation by selecting a terminal (portion not related to the check node calculation) is not shown.

At the time of the check node calculation, the variable node messages v _i read from the message memory 104 one by one and corresponding to each column of the check matrix are sequentially supplied as the message D601 to the input port P601. Is done.

The low-order bits excluding the most significant bit of the message D601 (message v _i ) supplied to the input port P601, that is, the absolute value D603 (| v _i |) of the message D601 is supplied to the LUT 600, and the most significant bit. That is, the sign bit D604 of the message D601 is supplied to the EXOR circuit 606.

The LUT 600 reads out the calculation result D605 (φ (| v _i |)) obtained by calculating the nonlinear function φ (| v _i |) using the absolute value D603 (| v _i |) as an argument, and the c terminal of the selector 601 To supply.

The selector 601 at the time of a check node calculation selects the terminal c, the operation result from LUT600 supplied to the terminal c thereof D605 of _{(φ (|) | v i} ), the operation result D607 (φ (| v _i | )) To the calculator 602.

The calculator 602 adds the calculation result D607 (φ (| v _i |)) and the value D608 stored in the register 603 to add up the calculation result D607, and the integrated value obtained as a result is registered in the register 603. Store again. Note that when the calculation result D607 (φ (| v _i |)) for the absolute value D603 (| v _i |) of the message D601 from all branches over one row of the check matrix is accumulated, the register 603 is reset. The

When the message D601 over one row of the check matrix is read one by one and the accumulated value obtained by accumulating the operation result D607 for one row is stored in the register 603, the selector 604 stores the value stored in the register 603. , i.e., phi obtained from the messages D601 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) from the integrated value D608 (i = 1, which is accumulated up to i = d _c Σφ (| v _i |)) is selected and output to the register 605 for storage. The register 605 supplies the stored integrated value D608 as the value D609 to the selector 604 and the calculator 612.

The selector 604 selects the value D609 supplied from the register 605, outputs it to the register 605, and stores it again until the integrated value obtained by integrating the operation result D607 for one row is stored in the register 603. That is, until φ (| v _i |) obtained from the message D601 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 605 accumulates φ (| v The integrated value of _i |) is supplied to the selector 604 and the calculator 612.

On the other hand, the message D601 (message v _i ) supplied to the input port P601 is also supplied to the small FIFO memory 616.

  As described above, the small FIFO memory 616 is a delay memory for delaying messages, but has only a capacity for storing a smaller number of messages than the maximum value of the check matrix weight, and has a small capacity FIFO. The first message D601 from the message memory 104 is delayed and supplied to the f terminal of the selector 617.

As described above, in the decoding apparatus of FIG. 30, the control unit 212, the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, a small FIFO memory 616 is stored When the number of possible messages (storable number) is less than or equal to d, the control signal C604 for instructing the selector 617 to select the first message D601 delayed by the small FIFO memory 616 is input to the message calculation unit 211. The data is supplied to the selector 617 via the port P604.

  The selector 617 selects and outputs the first message D601 delayed by the small FIFO memory 616 in accordance with the control signal C604 from the control unit 212.

The control unit 212, the weight d _c of the column corresponding to the check node, when it is not less storable number d of the small FIFO memory 616 to select a second message DD601 from the message memory 104 to the selector 617 The instructing control signal C604 is supplied to the input port P604 of the message calculation unit 211.

Further, the control unit 212, when the weight d _v column of the check matrix corresponding to the check node branches trying to find a message is connected, not less storable number d of the small FIFO memory 616, FIG. 15, the read control for reading the same message twice from the message memory 104 is performed, whereby the message DD601 read from the message memory 104 for the second time is sent to the selector 617 via the input port PD601. Supplied to the m terminal.

  The selector 617 selects and outputs the second message DD601 supplied from the message memory 104 via the input port PD601 in accordance with the control signal C604 from the control unit 212.

Message (message v _i ) output by the selector 617, that is, the lower-order bits excluding the most significant bit of the first message D601 delayed by the small FIFO memory 616 or the second message DD601 from the message memory 104 That is, the absolute value is supplied to the LUT 610 as the value D613, and the most significant bit, that is, the sign bit D614 is supplied to the EXOR circuit 614.

In register 605, (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) a new value D609 when the output of the start, i.e., calculation results D607 of one row in the register 605 are accumulated and (from i = 1 to _{i = d c Σφ (| v} i |)) integrated value immediately after the stored, LUT 610 is outputted from the selector 617 message (first delayed by a small FIFO memory 616 Operation result D615 (φ (| v _i |)) obtained by calculating the nonlinear function φ (| v _i |) using the absolute value D613 (| v _i |) of the message D601 or the second message DD601) as an argument Is supplied to the c terminal of the selector 611.

The selector 611 selects the c terminal during the check node calculation, and the calculation result D615 (φ (| v _i |)) from the LUT 610 supplied to the c terminal is calculated as the calculation result D617 (φ (| v _i |). )) To the calculator 612.

The arithmetic unit 612 subtracts the value D617 supplied from the selector 611 from the value D609 supplied from the register 605, and outputs the subtraction result as a subtraction value D618. That is, the calculator 612, phi obtained from the messages D601 from all of the branches across one line of the parity check matrix (message _{v i) (| v i |} ) of the integrated value D609 (i = 1 from i = d _c up to Σφ (| v _i |) from), obtained from the messages from a desired branch DD601 (message _{v i) φ (| v i} | subtracts the value D617 of), the subtraction value (i = 1 Σφ (| v _i |)) from i to d _c −1 is output as the subtraction value D618.

In parallel with the above processing, the EXOR circuit 606 performs exclusive OR between the value D611 stored in the register 607 and the sign bit D604 that is the most significant bit of the first message D601 (message v _i ). By calculating, the sign bits are multiplied, and the multiplication result D610 is stored again in the register 607. Note that the register 607 is reset when the sign bit D604 of the message D601 from all branches over one row of the check matrix is multiplied.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D610 to the sign bit D604 is multiplied by the messages D601 from all of the branches across one line of the parity check matrix stored in the register 607, the selector 608, Paisign the value stored in the register 607, i.e., the value D611 (i = 1 the sign bit D604 of the message D601 is multiplied from all of the branches across one line of the parity check matrix until i = d _c (v _i )) is selected and output to the register 609 for storage. The register 609 supplies the stored value D612 to the selector 608 and the EXOR circuit 614.

It is (from i = 1 Πsign to d _c (v _i)) multiplication result D610 to the sign bit D604 is multiplied by the messages D601 from all of the branches across one line of the parity check matrix until just before is stored in the register 607 The selector 608 selects the value D612 supplied from the register 609, outputs it to the register 609, and stores it again. That is, the register 609 supplies the previously stored value to the selector 608 and the EXOR circuit 614 until the sign bit D604 of the message D601 (message v _i ) from all branches over one row of the check matrix is multiplied. .

On the other hand, a new value from the register 609 D612 (from i = 1 to _{i = d c Πsign (v i} )) when is supplied to the EXOR circuit 614, i.e., from all of the branches across one line to the register 607 when a new value the sign bit D604 of the message D601 is multiplied D611 to (Paisign of i = 1 through _{i = d c (v i)} ) are stored, the selector 608 selects the value D611, the register causes stored in 609, the register 605, as described above, the integrated value operation result D607 is integrated for one row (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) is stored Is done.

Integration value calculation result D607 is integrated for one row in the register 605 (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) When is stored, as described above, the selector 617 The message to be output (message v _i ), that is, the sign bit D614 which is the most significant bit of the first message D601 delayed in the small FIFO memory 616 or the second message DD601 from the message memory 104, This is supplied to the EXOR circuit 614.

The EXOR circuit 614 calculates an exclusive OR of the new value D612 stored and output in the register 609 and the sign bit D614 of the message from the selector 617, thereby obtaining the value D612 and the message u ′ _j divided by the sign bit D614 of the message v _i from the branches to be obtained, and outputs the division result as a division value D620. That, EXOR circuit 614, branches multiplication value of the sign bit D604 of the message D601 from all of the branches across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v i)} ), to be obtained is divided by the message v _i (sign of _{i = d c (v i)} ) the sign bit D614 of from dividing the (Πsign (v _i) from i = 1 to i = d _c -1) the division value Output as value D620.

Then, the message calculation unit 211 uses the bit string D621 (message u) that uses the subtraction value D618 output from the arithmetic unit 612 as the lower bit and the division value D620 output from the EXOR circuit 614 as the most significant bit (sign bit). ' _j ) is supplied to the c terminal of the selector 615.

The selector 615 selects the c terminal during the check node calculation, and outputs the bit string D621 (message u ′ _j ) supplied to the c terminal from the output port P622 as the message D622.

As described above, in the message calculation unit 211 in which the selectors 601, 611, and 615 have selected the c terminal, the check node calculation of Expression (10) is performed, and the resulting message (message) u ′ _j is , Output from the output port P622.

  In the decoding device of FIG. 30, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (9), and the calculation result is output as the final decoding result. The

  As described above, in the decoding apparatus of FIG. 30, the small FIFO memory 616 (FIG. 31) for storing a smaller number of messages than the maximum weight of the parity check matrix is provided as the delay memory. Compared with the case where the FIFO memory 320 (FIG. 22) for storing a number of messages equal to the maximum value of the weights is provided, the scale of the decoding device can be reduced.

  Further, when the weight of the parity check matrix corresponding to the node of interest is equal to or less than the storable number d (when it is not larger than the storable number d), the output of the small FIFO memory 616 is selected and a node (variable node, Since it is used for the computation of the check node), the message is read and written at the same time as the decoding device of FIG. 21 having the FIFO memory 320 (FIG. 22) storing at least the number of messages equal to the maximum value of the weight of the check matrix. Can do. Accordingly, iterative decoding can be performed the same number of times as the decoding device of FIG. 21 (the time required for one decoding is the same as that of the decoding device of FIG. 21), so that deterioration of decoding performance is suppressed. be able to.

  Further, when the weight of the check matrix corresponding to the node of interest is larger than the storable number d, the same message is read twice from the message memory 104, the second read message is selected, Since it is used for the node calculation, the LDPC code can be decoded even if the weight of the parity check matrix corresponding to the node of interest is larger than the storable number d.

  From the above, according to the decoding device of FIG. 30, it is possible to suppress degradation of decoding performance while reducing the scale.

Here, the storable number d of the small FIFO memory 616 is 3, for example, and the parity check matrix defining the LDPC code to be decoded is, for example, the weight d _{v of} each column shown in FIG. When the weight of each row is a matrix of 6, 3 that is the storable number d is not smaller than 3 that is the column weight d _v of the parity check matrix. Since all three messages D601 can be delayed in the small FIFO memory 616 until the number of messages D601 is accumulated, the selector 617 delays the small FIFO memory 616 supplied to the terminal f. The first message D601 is selected.

In this case, 3 is storable number d is a smaller than 6 is the weight d _c line of the check matrix, therefore, at the time of a check node calculation, six more than 3 is storable number d Until φ (| v _i |) of the message D601 is accumulated, since all the six messages D601 cannot be delayed in the small FIFO memory 616, the selector 617 supplies them to the terminal m. The second message DD601 from the message memory 104 is selected.

  In the decoding apparatus of FIG. 30, in the message calculation unit 211, a part of the circuit that performs the variable node calculation and the circuit that performs the check node calculation (LUT 600, calculator 602, register 603, selector 604, register 605). Since the LUT 610 and the arithmetic unit 612) are shared, the scale of the decoding apparatus can be further reduced by the sharing.

Further, in the message calculation unit 211 of the decoding device in FIG. 30, the inverse function φ ⁻¹ (x) and the nonlinear function that obtain the same calculation result using the absolute value | x | of the input data x input to the node as an argument. The variable node calculation and the check node calculation are performed according to the expressions (9) and (10) including the calculation of φ (x), respectively.

Accordingly, as shown in FIG. 31, the message calculation unit 211 calculates the inverse function φ ⁻¹ (x) and the nonlinear function φ (x) for the first message supplied from the input port P601. There are only two LUTs, the LUT 600 to be performed and the LUT 610 for calculating the inverse function φ ⁻¹ (x) and the nonlinear function φ (x) for the message output from the selector 617, as shown in FIG. In addition, the LUT 300 that calculates the nonlinear function φ (x) for the first message, the LUT 310 that calculates the nonlinear function φ (x) for the message output from the selector 318, and the inverse function φ ⁻¹ (x ), The scale can be reduced as compared with the message calculation unit 201 that requires three LUTs of the LUT 314.

  Next, FIG. 35 is a block diagram illustrating a configuration example of the fourth embodiment of the decoding device to which the present invention has been applied.

  In the figure, portions corresponding to those of the decoding device of FIG. 25 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the decoding device of FIG. 35 is provided with a message calculation unit 221 instead of the message calculation unit 201 and a decoding unit of FIG. 25 except that a control unit 222 is provided instead of the control unit 202. It is configured in the same way as the device.

  In the decoding device of FIG. 35, the message calculation unit 221 is configured to share a part of a circuit that performs variable node calculation and a circuit that performs check node calculation. Furthermore, in the decoding apparatus of FIG. 35, the number of message calculation units 221 that perform variable node calculation and check node calculation is equal to the maximum value of the parity check matrix weight as in the FIFO memory 320 of the message calculation unit 191 of FIG. The delay memory stores a number of messages smaller than the maximum value of the check matrix weights.

  35, as described in the flowchart of FIG. 15, the controller 222 reads / writes the message (data) to / from the message memory 104 in the same manner as the controller 174 of the decoder of FIG. Take control.

  Further, the control unit 232 supplies the control signal C703 to the message calculation unit 211, and instructs the message calculation unit 221 to perform variable node calculation or check node calculation with the control signal C703.

  Further, as described with reference to the flowchart of FIG. 20, the control unit 222 performs selector control processing, and supplies the control signal C704 corresponding to the control signal C104 to the message calculation unit 221. The message calculation unit 221 performs variable node calculation and check node calculation by selectively using the message DD602 read out from the message memory 104 for the second time in accordance with the control signal C704 from the control unit 222.

  35, the messages stored in the message memory 104 are read one by one and supplied to the message calculation unit 221. The message calculation unit 221 performs an operation using the message from the message memory 104, and the message obtained by the operation is stored in the message memory 104. In the decoding device of FIG. 35, the above processing is repeated, and full serial iterative decoding is performed.

  That is, the reception data memory 105 is supplied with reception data (log likelihood ratio) D100 obtained by receiving the transmitted LDPC code, and the reception data memory 105 stores the reception data D100.

  During the variable node calculation, the reception data memory 105 reads the stored reception data in accordance with the control signal supplied from the control unit 222 and supplies it to the message calculation unit 221 as reception data D101.

  Further, during variable node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 222, and the message read first time is used as the message D701. The message read to the message calculation unit 221 and read for the second time is supplied to the message calculation unit 221 as a message DD701. The message calculation unit 221 requires the first message D701 supplied from the message memory 104, the reception data D101 supplied from the reception data memory 105, and the second message DD701 supplied from the message memory 104. In accordance with the control signals C703 and C704 supplied from the control unit 222, the variable node calculation is performed based on the check matrix, and the message obtained as a result of the variable node calculation is stored in the message memory 104 as a message D722. Supply.

  The message memory 104 stores a message D722 supplied from the message calculation unit 221 in accordance with a control signal supplied from the control unit 222.

  On the other hand, at the time of the check node calculation, the message memory 104 reads the same stored message once or twice according to the control signal supplied from the control unit 222, and the message read first time as the message D701. The message read to the message calculation unit 221 and read for the second time is supplied to the message calculation unit 221 as a message DD701.

  The message calculation unit 221 uses the first message D701 supplied from the message memory 104 and the second message DD701 supplied from the message memory 104 as necessary, and controls the control signal C703 from the control unit 222. And C704, a check node operation is performed based on the check matrix, and a message obtained by the check node operation is supplied to the message memory 104 as a message D722.

  The message memory 104 stores a message D722 supplied from the message calculation unit 221 in accordance with a control signal supplied from the control unit 222.

  Here, the calculation performed by the message calculation unit 221 in FIG. 35 will be described.

Now, as a message (data) output from the i-th branch among the branches connected to the variable node, a message represented by the expression v ′ _i = φ (| v _i |) × sign (v _i ) When v ′ _i is introduced, the equations (1) and (7) can be rewritten into the equations (11) to (13).

・・・（１１）

(11)

・・・（１２）

(12)

・・・（１３）

... (13)

  Here, the variable node calculation of Expression (1) corresponds to the calculation of Expression (11) and Expression (12), and the check node calculation of Expression (7) corresponds to the calculation of Expression (13).

In the variable node calculation of Expression (11) and Expression (12), the input data (message) u _j input to the variable node is integrated including the sign (u _j ) (Σu _j ), and the received data By adding u _0i and calculating the nonlinear function φ (| v _i |) with the absolute value | v _i | of the resulting addition value v _i (= u _0i + Σu _j ) as an argument, Message v ' _i is required.

Further, in the check node calculation of Expression (13), the absolute value | v ′ _i | of the input data (message) v ′ _i input to the check node is integrated (Σ | v ′ _i |), and the integrated value Σ While calculating the inverse function φ ^-1 (Σ | v ' _i |) with | v' _i | as an argument, separately, the product of sign bits of input data v ' _i (Πsign (v' _i )), And the result of the inverse function φ ⁻¹ (Σ | v ′ _i |) is multiplied by the product Πsign (v ′ _i ) of the sign bits of the input data v ′ _i , and the message u _j Desired.

Here, as described above, the nonlinear function φ (x) and its inverse function φ ⁻¹ (x) are equal when x> 0. Therefore, in both the variable node calculation of Expressions (11) and (12) and the check node calculation of Expression (13), the function φ (x) (φ ^{− 1} (x)) is calculated.

  In the message calculation unit 221 of FIG. 35, the variable node calculation of the above formulas (11) and (12) and the check node calculation of the formula (13) are performed.

  FIG. 36 shows a configuration example of the message calculation unit 221 of FIG.

  The message calculation unit 221 is provided with input ports P101, P701, PD701, P703, and P704, and an output port P722.

  The reception data D101 read from the reception data memory 105 is supplied (input) to the input port P101. Of the same message D701 and DD701 read twice from the message memory 104, the message (first message) D701 read out the first time is supplied (input) to the input port P701. A message (second message) DD701 read out the second time is supplied. Control signals C703 and C704 from the control unit 222 (FIG. 35) are supplied to the input ports P703 and P704, respectively.

  The message calculation unit 221 receives a first message D701 input from the input port P701, a second message DD701 input from the input port PD701, and a message (received data) D101 input from the input port P101 as necessary. In accordance with the control signals C703 and C704 input from the input port P703, based on the parity check matrix, the variable node calculation of Expression (11) and Expression (12) or the check node calculation of Expression (13) is performed, and the result The obtained message D722 is output from the output port P722.

  Here, with reference to FIG. 37, the variable node calculation and the check node calculation performed by the message calculation unit 221 in FIG. 36 will be described.

  The left side of FIG. 37 schematically shows the variable node that performs the variable node calculation of Expression (1) and the check node that performs the check node calculation of Expression (7), and is the same view as the right side of FIG.

On the left side of FIG. 37, as described on the right side of FIG. 27, after the operation of the nonlinear function φ (x) is performed on the input data input to the check node, the calculation result is input to the check node. , The calculation results of the nonlinear function φ (x) are integrated. Furthermore, (before the calculation of the inverse function phi ^-1 (x) is subjected, the integrated value of the calculation result of the nonlinear function phi (x)) output data output from the check node, the inverse function phi ^-1 (x ) And the message u _j is obtained.

On the left side of FIG. 37, the message v _i as output data output from the variable node is subjected to the calculation of the nonlinear function φ (x) as described above as the input data x input to the check node. Input to the check node.

Therefore, as shown on the left side of FIG. 37, instead of performing the calculation of the nonlinear function φ (x) on the input data x inputted to the check node, the output outputted from the variable node as shown on the right side of FIG. Even if the calculation of the nonlinear function φ (x) is performed on the data x (variable node message v _i ), the variable node calculation and the check node calculation can be performed.

That is, on the right side of FIG. 37, as described in Expression (11) and Expression (12), the message v _i is obtained by integrating the input data u _j input to the variable node in the variable node. Is output as output data. Then, the operation of the nonlinear function φ (x) is performed on (message v _i ) output from the variable node, and the message v ′ _i is obtained. This message v ′ _i (the calculation result obtained by performing the calculation of the nonlinear function φ (x) on the message v _i ) is input to the check node, integrated as described in Expression (13), and output as output data Is done. The output data (the integrated value of the operation result obtained by performing the operation of the nonlinear function φ (x) on the message v _i ) is subjected to the operation of the inverse function φ ⁻¹ (x), whereby the message u _j Is required.

In the message calculation unit 221 of FIG. 36, as shown on the right side of FIG. 37, the variable node calculation of the expressions (11) and (12) for obtaining the messages v ′ _i and u _j and the check node calculation of the expression (13) are performed. Is called.

As described above, the message calculation unit 221 in FIG. 36 performs the variable node calculation of Expressions (11) and (12) and the check node calculation of Expression (13) for obtaining the messages v ′ _i and u _j shown on the right side of FIG. Therefore, the message calculation unit 221 calculates the nonlinear function φ (x) that can obtain the same calculation result as the inverse function φ ⁻¹ (x) for the output data x output from the variable node. A LUT 713 is provided for outputting the result and outputting the operation result of the inverse function φ ⁻¹ (x) for the output data x output from the check node.

  Then, the message calculation unit 221 in FIG. 36 changes the substantial configuration according to the control signal C703 supplied to the input port P703, and performs the variable node calculation of Expression (11) and Expression (12) and Expression (13). The check node operation is selectively performed.

  That is, the message calculation unit 221 includes selectors 700, 705, 712, and 715, and the control signal C703 supplied to the input port P703 is supplied to the selectors 700, 705, 712, and 715.

  The selectors 700, 705, 712, and 715 have a v terminal and a c terminal, select a value supplied to either the v terminal or the c terminal according to the control signal C703, and output the selected value to the subsequent stage. . That is, when the control signal C703 is a control signal for instructing variable node calculation, the selectors 700, 705, 712, and 715 select the value supplied to the v terminal and output it to the subsequent stage, and the control signal C703. Is a control signal for instructing a check node calculation, the value supplied to the c terminal is selected and output to the subsequent stage.

  As a result, in the message calculation unit 221 of FIG. 36, the variable node calculation is performed when the control signal C703 indicates a variable node calculation, and the check node calculation is performed when the control signal C703 indicates a check node calculation. Is done.

  That is, FIG. 38 shows a substantial configuration example of the message calculation unit 221 of FIG. 36 at the time of variable node calculation shown on the right side of FIG.

  As described above, in the variable node calculation, the selectors 700, 705, 712, and 715 select the v terminal, but in FIG. 38, the selectors 700, 705, 712, of the configurations illustrated in FIG. 715 and 715 select the v terminal, and portions that do not function during variable node computation (portions that are not related to variable node computation) are not shown.

  The message calculation unit 221 performs variable node calculation of Expressions (11) and (12) using the messages input from the input ports P101, P701, and PD701 as necessary, and a message D722 obtained as a result. Is output from the output port P722.

That is, the reception data D101 read from the reception data memory 105 is supplied to the input port P101. Further, the first message D701 (message u _j ) is supplied to the input port P701 from the check node corresponding to each row of the parity check matrix read out from the message memory 104 one by one.

  The reception data D101 supplied to the input port P101 is supplied to the calculator 711.

The message D701 (message u _j ) supplied to the input port P701 is supplied to the v terminal of the selector 700 and the small FIFO memory 716.

As described above, the selector 700 selects the v terminal during the variable node calculation, and the message D701 (check node message u _j ) supplied to the v terminal is supplied to the calculator 701 as the message D705. .

The computing unit 701 adds the message D705 (message u _j ) from the selector 700 and the value D706 stored in the register 702 to add up the message D705, and the integrated value obtained as a result is stored in the register 702. Store again. Note that when the message D705 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 702 is reset.

When the message D701 (message u _j ) over one column of the check matrix is read one by one, and as a result, the value obtained by integrating the message D705 (message u _j ) for one column is stored in the register 702, that is, When the accumulated value (Σu _j from j = 1 to d _v ) obtained by accumulating the message D 705 (message u _j ) from all branches over one column of the check matrix is stored in the register 702, the selector 703. is,? uj _j value stored in the register 702, i.e., the integrated value D706 (j = 1 to the message D705 (message u _j) is accumulated from all of the branches across one row of the parity check matrix to d _v ) Is selected and output to the register 704 for storage.

The register 704 supplies the stored value D706 as the value D707 to the selector 703 and the calculator 710. The selector 703 selects the value D707 supplied from the register 704, outputs it to the register 704, and stores it again until the value obtained by integrating the message D705 (message u _j ) for one column is stored in the register 702. Let That is, until the message D705 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 704 supplies the previously accumulated value to the selector 703 and the calculator 710.

On the other hand, the message D701 (message u _j ) supplied to the input port P701 is also supplied to the small FIFO memory 716 as described above.

The small FIFO memory 716 is a delay memory for delaying a message, but is a number (one or more) smaller than the maximum value of the check matrix weight (column weight d _v and row weight d _c ). This is a small-capacity FIFO memory that has only the capacity to store messages.

  The small FIFO memory 716 delays the first message D701 from the message memory 104 and supplies it to the f terminal of the selector 717.

  The selector 717 has an f terminal and an m terminal as input terminals, and the message D701 delayed by the K small FIFO memory 716 is supplied to the f terminal as described above. The second message DD701 supplied from the message memory 104 to the terminal PD701 is supplied to the m terminal of the selector 717.

  Further, the control signal C704 supplied from the control unit 222 (FIG. 35) to the input port P704 is supplied to the selector 717.

  The selector 717 uses one of the first message D701 delayed by the small FIFO memory 716 and the second message DD701 from the message memory 104 according to the control signal C704 from the control unit 222 for variable node calculation. Select and output as a message to use.

  The message output from the selector 717, that is, the first message D701 delayed by the small FIFO memory 716 or the second message DD701 from the message memory 104 is supplied to the v terminal of the selector 705.

Here, in the decoding device of FIG. 35, the control unit 222 can store the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is sought is connected, in the small FIFO memory 716. When the number of messages (storable number) is less than or equal to d, the control signal C704 for instructing the selector 717 to select the first message D701 delayed by the small FIFO memory 716 is input to the input port P704 of the message calculation unit 211. To supply.

Further, when the column weight d _v corresponding to the variable node is not less than or equal to the storable number d of the small FIFO memory 716, the control unit 222 selects the second message DD 701 from the message memory 104 to the selector 717. The instructing control signal C704 is supplied to the input port P704 of the message calculation unit 211.

  Note that the control unit 222 supplies the message calculation unit 211 with a control signal C704 that instructs the selector 717 to select the message D701 delayed by the small FIFO memory 716, that is, the control signal C704 is the message memory. If the signal is not a signal for instructing the selector 717 to select the message DD 701 read for the second time from 104, the read control for reading the message from the message memory 104 is performed once for the message read from the message memory 104. I do.

Therefore, in the control unit 222, when the column weight d _v of the check matrix corresponding to the variable node to which the branch for which the message is to be obtained is connected is not less than or equal to the storable number d of the small FIFO memory 716, The readout control for reading the same message twice from the message memory 104 described in 15 is performed, but the column weight d _v of the parity check matrix corresponding to the variable node to which the branch for which the message is requested is connected is: When the number of storable memories in the small FIFO memory 716 is equal to or less than d, read control for reading the same message from the message memory 104 twice is not performed (it is not necessary), that is, read control for reading only once, that is, FIG. Of these steps S101 and S102, only step S101 is performed.

On the other hand, upon output of a new value from the register 704 D707 (? Uj _j from j = 1 to d _v) is started, namely, the integrated message D705 for one column in the register 702 (message u _j) is accumulated stored value (? uj _j from j = 1 to d _v) is a message the integrated value is selected by the selector 703, immediately after being stored in the register 704, as described above, the selector 717 is output, The first message message D 701 (message u _j ) delayed by the small FIFO memory 716 or the second message DD 701 is supplied to the v terminal of the selector 705.

As described above, the selector 705 selects the v terminal during variable node calculation, and the message (message u _j ) supplied to the v terminal is supplied to the calculator 710 as the message D713.

Calculator 710, from the supplied integrated value D707 (? Uj _j from j = 1 to d _v) from the register 704, subtracts the message from the selector 705 D713 (message u _j). That is, the message of the calculator 710, the message D705 from all of the branches across one row of the parity check matrix (? Uj _j from j = 1 to d _v) integrated value D707 of (message u _j) from a desired branch subtracts the message D713 as u _{j (j} = d _v of u _j), we obtain the subtraction value D714 (? uj _j from j = 1 to d _v -1), and supplies the arithmetic unit 711.

Calculator 711 adds the reception data D101 from the input port P101, and by adding the subtracted value D714 from the calculator 710 (? Uj _j from j = 1 to d _v -1), the message D715 (variable node message v _i ) is obtained and output.

That is, the calculation of Expression (11) is performed as described above, and the variable node message v _i is output from the calculator 711.

The low-order bits excluding the most significant bit of the message D715 (message v _i ) output from the arithmetic unit 711, that is, the absolute value D716 (| v _i |) of the message D715 is supplied to the v terminal of the selector 712, The upper bit, that is, the sign bit D717 (sign (v _i )) of the message D715 (message v _i ) is supplied to the v terminal of the selector 715.

The selector 712 selects the v terminal at the time of variable node calculation, and uses the absolute value D716 (| v _i |) of the message D715 (message v _i ) output from the calculator 711 supplied to the v terminal as the absolute value. This is supplied to the LUT 713 as D718.

The LUT 713 reads out and outputs the calculation result D719 (φ (| v _i |)) obtained by calculating the nonlinear function φ (| v _i |) using the absolute value D718 (| v _i |) from the selector 712 as an argument. To do.

The selector 715 also selects the v terminal at the time of variable node calculation, and the sign bit D717 (sign (v _i )) of the message D715 (message v _i ) output from the calculator 711 supplied to the v terminal is encoded. Output as bit D721 (sign (v _i )).

The message calculation unit 211 adds the sign bit D721 (sign (v _i )) output from the selector 715 to the most significant bit as the sign bit of the operation result D719 (φ (| v _i |)) output from the LUT 713. Thus, the message D722 (message v ′ _i ) is obtained and output from the output port P722.

As described above, the calculation of Expression (12) is performed, and the message v ′ _i is obtained.

As described above, in the message calculation unit 221 in which the selectors 700, 705, 712, and 715 have selected the v terminal, the variable node calculation of Expression (11) and Expression (12) is performed, and the message obtained as a result v ′ _i is output from the output port P722.

  Next, FIG. 39 shows a substantial configuration example of the message calculation unit 221 of FIG. 36 at the time of the check node calculation shown on the right side of FIG.

  As described above, in the check node calculation, the selectors 700, 705, 712, and 715 select the c terminal, but in FIG. 39, the selectors 700, 705, 712, of the configuration illustrated in FIG. 715 and 715 select the c terminal, and a portion that does not function at the time of the check node calculation (portion not related to the check node calculation) is not shown.

At the time of the check node calculation, the message obtained from the variable node message v _i from the variable node corresponding to each column of the check matrix, read out from the message memory 104 one by one, is input to the input port P701. 11) and the message (v ′ _i obtained by the variable node calculation of Expression (12)) are sequentially supplied as the message D701.

Of the message D701 (message v ′ _i ) supplied to the input port P701, the lower bits excluding the most significant bit, that is, the absolute value D703 (| v ′ _i |) of the message D701 is supplied to the c terminal of the selector 700. The most significant bit, that is, the sign bit D704 of the message D701 is supplied to the EXOR circuit 706.

The selector 700 selects the c terminal during the check node calculation, and the absolute value D703 (| v ′ _i |) of the message D701 supplied to the c terminal is used as the absolute value D705 (| v ′ _i |). , And supplied to the calculator 701.

The computing unit 701 adds the absolute value D705 (| v ′ _i |) and the value D706 stored in the register 702 to add up the absolute value D705, and re-adds the obtained integrated value to the register 702. Store. If the absolute values D705 (D703) (| v ' _i |) of the message D701 (v ′ _i ) (obtained from the message v _i ) from all branches over one row of the check matrix are accumulated, Register 702 is reset.

When the message D701 (obtained from the message v _i ) over one row of the check matrix is read one by one and the accumulated value obtained by accumulating the absolute value D705 for one row is stored in the register 702, the selector 703 , the value stored in the register 702, i.e., from the integrated value D706 (i = 1 to the message D701 (message v _'i) is accumulated from all of the branches across one line of the parity check matrix until i = d _c Σ | v ′ _i |) is selected and output to the register 704 for storage. The register 704 supplies the stored integrated value D706 as a value D707 to the selector 703 and the calculator 710.

The selector 703 selects the value D707 supplied from the register 704, outputs it to the register 704, and stores it again until the integrated value obtained by integrating the absolute value D705 for one row is stored in the register 702. That is, until the absolute value | v ′ _i | of the message D701 (message v ′ _i ) from all branches over one row of the check matrix is accumulated, the register 704 stores the absolute value | v ′ _i accumulated last time. | Is supplied to the selector 703 and the calculator 710.

On the other hand, the message D701 (message v ′ _i ) supplied to the input port P701 is also supplied to the small FIFO memory 716.

  As described above, the small FIFO memory 716 is a delay memory for delaying messages, but has only a capacity for storing a smaller number of messages than the maximum value of the check matrix weight, and has a small capacity FIFO. The first message D701 from the message memory 104 is delayed and supplied to the f terminal of the selector 717.

Here, in the decoding apparatus of FIG. 35, the control unit 222, the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, a small FIFO memory 716 is capable of storing When the number of messages (storable number) is equal to or less than d, the control signal C704 for instructing the selector 717 to select the first message D701 delayed by the small FIFO memory 716 is input to the input port P704 of the message calculation unit 221. To the selector 717.

  The selector 717 selects and outputs the first message D701 delayed by the small FIFO memory 716 in accordance with the control signal C704 from the control unit 222.

The control unit 222, the weight d _c in the row corresponding to the check node, when it is not less storable number d of the small FIFO memory 716 to select a second message DD701 from the message memory 104 to the selector 717 A control signal C704 to be instructed is supplied to the input port P704 of the message calculation unit 221.

Further, the control unit 222, when the weight d _c line of the check matrix corresponding to the check node branches trying to find a message is connected, not less storable number d of the small FIFO memory 716, in Figure 15 The above-described read control for reading the same message from the message memory 104 twice is performed, whereby the message DD701 read from the message memory 104 for the second time is input to the m terminal of the selector 717 via the input port PD701. To be supplied.

  The selector 717 selects and outputs the second message DD701 supplied from the message memory 104 via the input port PD701 in accordance with the control signal C704 from the control unit 222.

The message (message v ′ _i ) output by the selector 717, that is, the lower order except the most significant bit of the first message D 701 delayed by the small FIFO memory 716 or the second message DD 701 from the message memory 104 The bit, that is, the absolute value D711 (| v ′ _i |) is supplied to the c terminal of the selector 705, and the most significant bit, that is, the sign bit D 712 (sign (v ′ _i )) is supplied to the EXOR circuit 714. The

The selector 705 selects the c terminal at the time of the check node calculation, and the absolute value D711 (| v ′ _i |) of the message (v ′ _i ) supplied to the c terminal is converted into the absolute value D713 (| v ′ _i |) Is supplied to the computing unit 710.

That is, in the register 704, a new value D707 (Sigma] [phi of i = 1 through _{i = d c (| v '} i |)) the output of the start, that is, the absolute value of one row in the register 702 D705 There accumulated the new integrated value (Sigma] [phi of i = 1 through _{i = d c (| v '} i |)) is stored, is selected by the selector 703, immediately after being stored in the register 704, the selector 705 The absolute value D711 (| v ′ _i |) of the message (message v ′ _i ) output from the selector 717 is supplied to the computing unit 710 as the absolute value D713 (| v ′ _i |).

Calculator 710, the value supplied D707 from the register 704 | '| from supplied from the selector 705 the value _{D713 (i (| v Σ v} )' i |) subtracted, the subtraction result, the subtraction value D714 Output as. That is, the calculator 710, 'the absolute value of _(i | v messages D701 from all of the branches across one line of the parity check matrix message v)' _i | of the integrated value D707 (i = 1 to i = d _c sigma | v _'i | from), the message (i = d _c of v from a desired branch' absolute value of _{i) D713 (| v 'i} |) is subtracted, i from the subtraction value (i = 1 Σ | v ′ _i |) up to = d _c −1 is supplied to the c terminal of the selector 712 as a value D714.

The selector 712 selects the c terminal at the time of the check node calculation, and uses the value D714 (Σ | v ′ _i | from i = 1 to i = d _c −1) supplied to the c terminal to the value D718. Is supplied to the LUT 713.

The LUT 713 uses the value D718 (Σ | v ′ _i |) from the selector 712 as an argument, and the operation result D719 (φ ⁻¹ (Σ | v) where the inverse function φ ⁻¹ (Σ | v ′ _i |) is calculated. ' _i |)) is read and output.

In parallel with the above processing, the EXOR circuit 706 generates the value D709 stored in the register 707 and the sign bit D704 (sign (v ′ _i ) that is the most significant bit of the first message D701 (message v ′ _i ). )) Is multiplied by the sign bit D704 and the multiplication result D708 is re-stored in the register 707. When the sign bit D704 of the message D701 from all branches over one row of the check matrix is multiplied, the register 707 is reset.

If the multiplication result of the sign bit D704 of the message D701 is multiplied from all of the branches across one line of the parity check matrix D708 (Πsign from i = 1 to d _c (v _'i)) is stored in the register 707, the selector 708, the value stored in the register 707 D709, i.e., the value D709 (i = 1 the sign bit D704 of the message D701 is multiplied from all of the branches across one line of the parity check matrix until i = d _c Πsign (v ′ _i )) is selected and output to the register 709 for storage. The register 709 supplies the stored value D710 to the selector 708 and the EXOR circuit 714.

Until just before is stored in the register 707 (Πsign to d _c (v _'i) from i = 1) the multiplication result D708 to the sign bit D704 is multiplied by the message D701 from all of the branches across one line of the parity check matrix The selector 708 selects the value D710 supplied from the register 709, outputs it to the register 709, and stores it again. That is, the register 709 supplies the previously stored value to the selector 708 and the EXOR circuit 714 until the sign bit D704 of the message D701 (message v ′ _i ) from all the branches over one row of the check matrix is multiplied. To do.

On the other hand, when the new value from the register 709 D710 which (Paisign of i = 1 through _{i = d c (v 'i} )) is supplied to the EXOR circuit 714, i.e., all of the branches across one line to the register 707 new value sign bit D704 of the message D701 is multiplied in D709 (Πsign of i = 1 through _{i = d c (v 'i} )) are stored, the new value D709 is selected by the selector 708 registers when stored in 709, the register 704, as described above, the absolute value of one row D705 (| v _'i |) is accumulated integrated values from (i = 1 to i = d _c Σ | v ' _i |) is stored.

Integrated value absolute value D705 for one row is accumulated in the register 704 (i = from 1 to _{i = d c Σ | v '} i |) when is stored, as described above, the selector 717 outputs Message (message v ′ _i ), that is, the first bit D701 delayed in the small FIFO memory 716 or the sign bit D712 (sign (v) that is the most significant bit of the second message DD701 from the message memory 104 ' _i )) is supplied to the EXOR circuit 714.

The EXOR circuit 714 calculates the exclusive DOR of the new value D710 supplied from the register 709 and the sign bit D712 of the message (v ′ _i ) output from the selector 717 to obtain the value D710 as the sign bit. Divide by D712 and supply the result of division as a division value D720 to the c terminal of the selector 715. That, EXOR circuit 714, the multiplication value of the sign bit D704 of the message D701 from all of the branches across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v 'i} )), to be obtained is divided by the message v from the branch 'sign bit of the _i D712 _(i = d _c of sign (v' _i)), the division value from (i = 1 to _{i = d c -1 Πsign (v} 'i )) Is supplied to the c terminal of the selector 715 as a division value D720.

The selector 715 selects the c terminal at the time of the check node calculation, and uses a division value D720 (Πsign (v ′ _i ) from i = 1 to i = d _c −1) supplied to the c terminal as a sign bit. Output as D721.

Then, the message calculation unit 221 uses the sign bit D721 (Πsign (v ′ _i )) output from the selector 715 as described above, and the calculation result D719 (φ ⁻¹ (Σ | v ′ _i |) output from the LUT 713. )) Is added (multiplied) as a sign bit to obtain a message (check node message) u _j represented by Expression (13), and is output from the output port P722 as a message D722.

As described above, in the message calculation unit 221 in which the selectors 700, 705, 712, and 715 have selected the c terminal, the check node calculation of Expression (13) is performed, and the message u _j obtained as a result is output. Output from port P722.

  35, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (11) and Expression (12), and the calculation result is the final result. Output as decryption result.

  As described above, in the decoding apparatus of FIG. 35, as the delay memory, the small FIFO memory 716 (FIG. 32) for storing a smaller number of messages than the maximum value of the weight of the parity check matrix is provided. Compared with the case where the FIFO memory 320 (FIG. 22) for storing a number of messages equal to the maximum value of the weights is provided, the scale of the decoding device can be reduced.

  Further, when the weight of the parity check matrix corresponding to the node of interest is equal to or less than the storable number d (when it is not larger than the storable number d), the output of the small FIFO memory 716 is selected and used for the node calculation. Therefore, it is possible to read and write messages in the same time as the decoding apparatus of FIG. 21 having the FIFO memory 320 (FIG. 22) storing at least the number of messages equal to the maximum value of the weight of the parity check matrix. Accordingly, iterative decoding can be performed the same number of times as the decoding device of FIG. 21 (the time required for one decoding is the same as that of the decoding device of FIG. 21), so that deterioration of decoding performance is suppressed. be able to.

  Further, when the weight of the check matrix corresponding to the node of interest is larger than the storable number d, the same message is read twice from the message memory 104, the second read message is selected, Since it is used for the node calculation, the LDPC code can be decoded even if the weight of the parity check matrix corresponding to the node of interest is larger than the storable number d.

  From the above, according to the decoding device of FIG. 35, it is possible to suppress degradation in decoding performance while reducing the scale.

Here, the storable number d of the small FIFO memory 716 is 3, for example, and the parity check matrix defining the LDPC code to be decoded is, for example, the weight d _{v of} each column shown in FIG. When the weight of each row is a matrix of 6, 3 that is the storable number d is not smaller than 3 that is the column weight d _v of the parity check matrix. Since all three messages D701 can be delayed in the small FIFO memory 716 until the number of messages D701 are accumulated, the selector 717 delays the small FIFO memory 716 supplied to the terminal f. The first message D701 thus selected is selected.

In this case, 3 is storable number d is a smaller than 6 is the weight d _c line of the check matrix, therefore, at the time of a check node calculation, six more than 3 is storable number d Since all the six messages D701 cannot be delayed in the small FIFO memory 716 until the absolute value | v ′ _i | of the message D701 (message v ′ _i ) is accumulated, the selector 717 The second message DD701 from the message memory 104 supplied to the terminal m is selected.

  In the decoding apparatus of FIG. 35, the message calculation unit 221 includes a part of a circuit that performs a variable node operation and a circuit that performs a check node operation (an arithmetic unit 701, a register 702, a selector 703, a register 704, an operation Since the unit 710 and the LUT 713) are shared, the scale of the decoding device can be further reduced by the amount of sharing.

In the message calculation unit 221 of the decoding device in FIG. 35, the inverse function φ ⁻¹ (x) and the nonlinear function that can obtain the same calculation result using the absolute value | x | of the output data x output from the node as an argument. A variable node calculation and a check node calculation using Expression (12) and Expression (13) respectively including the calculation of φ (x) are performed.

Therefore, as shown in FIG. 36, the message calculation unit 221 performs LUT 713 for calculating the inverse function φ ⁻¹ (x) and the nonlinear function φ (x) with respect to the absolute value | x | of the output data x. 26, and the message calculation unit 201 that requires three LUTs 300, 310, and 314 shown in FIG. 26, and two LUTs 600 and 610 shown in FIG. 31 are required. Thus, the scale can be reduced as compared with the message calculation unit 211.

  As described above, in the decoding devices of FIGS. 17, 25, 30, and 35, the delay memory (the small FIFO memory 161 of FIG. 18 and the number of messages smaller than the maximum value of the parity check matrix weight) is stored. The small FIFO memories 141 and 143 in FIG. 19, the small FIFO memory 317 in FIG. 26, the small FIFO memory 616 in FIG. 31, and the small FIFO memory 716 in FIG. 36) are provided, so that at least the maximum value of the weight of the parity check matrix In a decoding device (FIG. 8, FIG. 21) having a delay memory (for example, FIFO memory 155 of FIG. 9, FIFO memories 127 and 133 of FIG. 10, and FIFO memory 320 of FIG. 22). In comparison, the scale of the decoding device can be reduced.

  Compared to a decoding device that does not have a delay memory (FIG. 12), the operation efficiency is improved by increasing the scale, such as a delay memory that stores a smaller number of messages than the maximum value of the check matrix weight. That is, at least, it is possible to perform decoding repeatedly as many times as the decoding device having a delay memory that stores the same number of messages as the maximum value of the weight of the parity check matrix.

  Here, as described above, providing a delay memory that stores a smaller number of messages than the maximum value of the weight of the parity check matrix in the decoding device is that the code length of the LDPC code is long and the row weight of the parity check matrix is increased. On the other hand, when the column weight is small, when a delay memory that delays by the same number as the maximum value of the column weight (however, a number smaller than the maximum value of the row weight) is adopted, Especially effective.

  That is, in this case, the variable node operation is performed using a message delayed by a delay memory that stores a smaller number of messages than the maximum value of the check matrix weight, and thus the maximum value of the check matrix weight. It is possible to repeatedly perform decoding as many times as a decoding device having a delay memory that stores the same number of messages, and to further reduce the scale of the decoding device while further suppressing deterioration of decoding performance be able to.

  Further, in order to obtain a message of a plurality of nodes in parallel, when a plurality of message calculation units are provided and a decoding device is configured, as many delay memories as the number of message calculation units are required. Even in this case, the effect of reducing the scale of the decoding apparatus by providing a delay memory that stores a smaller number of messages than the maximum value of the check matrix weight is significant.

  In the present embodiment, a delay memory that stores three messages (for example, the small FIFO memory 317 in FIG. 26) is used as a delay memory that stores a smaller number of messages than the maximum value of the check matrix weight. Although adopted, the delay memory is not limited to a memory that stores three messages, and may be a memory that stores a smaller number of messages than the maximum value of the check matrix weight.

  Further, the message memory 104 is composed of two banks, RAM # A and RAM # B, but the message memory 104 can be composed of three or more RAMs and three or more banks.

  Next, the read / write control process for the message memory 104 shown in FIG. 15 and the selector control process shown in FIG. 20 performed by the control unit 202 (FIG. 25) and the like can be performed by dedicated hardware. It can also be done by software. When a series of processing is performed by software, a program constituting the software is installed in a computer such as a microcomputer (so-called microcomputer).

  Therefore, FIG. 40 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.

  The program can be recorded in advance in a nonvolatile memory 905 or a ROM 903 as a recording medium built in the computer.

  Alternatively, the program is temporarily or permanently stored on a removable recording medium such as a flexible disk, CD-ROM (Compact Disc Read Only Memory), MO (Magneto Optical) disk, DVD (Digital Versatile Disc), magnetic disk, or semiconductor memory. Can be stored (recorded).

  The program can be installed on the computer from the above-described removable recording medium or via a network.

  The computer includes a CPU (Central Processing Unit) 902. An input / output interface 906 is connected to the CPU 902 via a bus 901, and the CPU 902 loads a program installed in a ROM (Read Only Memory) 903 or a nonvolatile memory 905 into a RAM (Random Access Memory) 904. Load and execute. As a result, the CPU 902 performs read / write control (FIG. 15) and selector control (FIG. 20) on the message memory 104 via the input / output interface 906.

  Here, in this specification, the processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).

  Further, the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a figure explaining the check matrix H of an LDPC code. It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure explaining the flow of a message. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the Tanner graph of a check matrix. It is a figure which shows a variable node. It is a figure which shows a check node. It is a block diagram which shows the structure of an example of the conventional decoding apparatus. It is a block diagram which shows the structural example of the variable node calculator 102 which calculates a message one by one. It is a block diagram which shows the structural example of the check node calculator 103 which calculates a message one by one. 6 is a timing chart showing conventional timings for reading and writing messages to and from the message memory 104. It is a block diagram which shows the structural example of the decoding apparatus which does not have a delay memory for delaying a message. 6 is a block diagram illustrating a configuration example of a variable node calculator 172. FIG. 6 is a block diagram illustrating a configuration example of a check node calculator 173. FIG. 5 is a flowchart for explaining processing of read / write control for a message memory 104. 6 is a timing chart showing message read / write timing with respect to the message memory 104; It is a block diagram which shows the structural example of 1st Embodiment of the decoding apparatus to which this invention is applied. 6 is a block diagram illustrating a configuration example of a variable node calculator 182. FIG. 6 is a block diagram illustrating a configuration example of a check node calculator 183. FIG. It is a flowchart explaining the process of selector control. FIG. 10 is a block diagram illustrating a configuration example of a decoding device in which a circuit that performs variable node calculation and a circuit that performs check node calculation are partially shared. 3 is a block diagram illustrating a configuration example of a message calculation unit 191. FIG. It is a block diagram which shows the substantial structure of the message calculation part 191 at the time of variable node calculation. It is a block diagram which shows the substantial structure of the message calculation part 191 at the time of a check node calculation. It is a block diagram which shows the structural example of 2nd Embodiment of the decoding apparatus to which this invention is applied. 3 is a block diagram illustrating a configuration example of a message calculation unit 201. FIG. It is a figure explaining the variable node calculation and check node calculation which the message calculation part 201 performs. It is a block diagram which shows the substantial structure of the message calculation part 201 at the time of variable node calculation. It is a block diagram which shows the substantial structure of the message calculation part 201 at the time of check node calculation. It is a block diagram which shows the structural example of 3rd Embodiment of the decoding apparatus to which this invention is applied. 3 is a block diagram illustrating a configuration example of a message calculation unit 211. FIG. It is a figure explaining the variable node calculation and check node calculation which the message calculation part 211 performs. It is a block diagram which shows the substantial structure of the message calculation part 211 at the time of variable node calculation. It is a block diagram which shows the substantial structure of the message calculation part 211 at the time of a check node calculation. It is a block diagram which shows the structural example of 4th Embodiment of the decoding apparatus to which this invention is applied. 3 is a block diagram illustrating a configuration example of a message calculation unit 221. FIG. It is a figure explaining the variable node calculation and check node calculation which the message calculation part 221 performs. It is a block diagram which shows the substantial structure of the message calculation part 221 at the time of variable node calculation. It is a block diagram which shows the substantial structure of the message calculation part 221 at the time of a check node calculation. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

104 message memory, 105 received data memory, 121 LUT, 122
Arithmetic unit, 123 register, 124 selector, 125 register, 126 arithmetic unit, 128 LUT, 129 EXOR circuit, 130 register, 131 selector, 132 register, 134 EXOR circuit, 135 LUT, 141 small FIFO memory, 142 selector, 143 small FIFO Memory, 144 selector, 151 calculator, 152 register, 153 selector, 154 register, 156, 157 calculator, 161 small FIFO memory, 162 selector, 171 message calculator, 172 variable node calculator, 173 check node calculator, 174 Control unit, 181 message calculation unit 181, 182 variable node calculator, 183 check node calculator, 184 control unit, 191 message calculation unit, 192 control unit, 201 message calculation unit, 202 Control unit, 211 message calculation unit, 212 control unit, 221 message calculation unit, 222 control unit, 231 message calculation unit, 232 control unit, 300 LUT, 301 selector, 302 computing unit, 303 register, 304 selector, 305 register, 306 EXOR circuit, 307 register, 308 selector, 309 register, 310 LUT, 311 selector, 312, 313 calculator, 314 LUT, 315 EXOR circuit, 316 selector, 317 small FIFO memory, 318 selector, 320 FIFO memory, 600 LUT, 601 Selector, 602 calculator, 603 register, 604 selector, 605 register, 606 EXOR circuit, 607 register, 608 selector, 609 register, 610 LUT, 611 selector, 612, 613 calculator, 61 4 EXOR circuit, 615 selector, 616 small FIFO memory, 617, 700 selector, 701 calculator, 702 register, 703 selector, 704 register, 705 selector, 706 EXOR circuit, 707 register, 708 selector, 709 register, 710, 711 operation 712 selector, 713 LUT, 714 EXOR circuit, 715 selector, 716 small FIFO memory, 717 selector, 901 bus, 902 CPU, 903 ROM, 904 RAM, 905 non-volatile memory, 906 I / O interface

Claims (8)

In a decoding device that decodes LDPC (Low Density Parity Check) code,
Storage means for storing a message used for variable node calculation or check node calculation for decoding the LDPC code;
Message calculation means for performing an operation of the variable node or an operation of the check node based on a parity check matrix defining the LDPC code using a message stored in the storage means and outputting a message obtained as a result of the operation And
The message calculation means has a delay memory that delays by temporarily storing a message used for the variable node calculation or the check node calculation,
The delay memory stores a number of messages less than a maximum weight of the parity check matrix ;
Write control for writing a message output by the message calculation means to the storage means, and read control for reading the same message used for calculation in the message calculation means twice from the storage means and supplying the same to the message calculation means Control means for performing
Selecting means for selecting one of the message delayed in the delay memory and the message read out for the second time from the storage means as a message used in the variable node calculation or the check node calculation;
Further comprising
The selection means includes
In the calculation of the variable node, when the column weight of the check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected, When the weight of the column is not less than or equal to the number of messages that the delay memory can store, select the message read from the storage means a second time;
In the operation of the check node, when the weight of the row of the check matrix corresponding to the check node is equal to or less than the number of messages that can be stored in the delay memory, a message delayed in the delay memory is selected, A decoding device that selects a message read out second from the storage means when the weight of the row is not less than the number of messages that can be stored in the delay memory . The message calculation means includes:
A part of the circuit that performs the operation of the variable node and the circuit that performs the operation of the check node are shared,
Wherein the variable node calculation, and a calculation of the check node decoding apparatus according to claim 1 selectively perform. The message calculation means includes:
1 LUT (Look Up Table) that outputs the calculation result of the nonlinear function φ (x) =-ln (tanh (x / 2)) for the input data x input to the check node;
With respect to the output data x output from the check node, another LUT that outputs the operation result of the inverse function φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ) of the nonlinear function, and
When calculating the check node, the data is passed through the one LUT and the other LUT,
The decoding device according to claim 2 , wherein during the variable node calculation, the data is bypassed between the one LUT and the other LUT. The message calculation means is a non-linear function φ (x) for obtaining the same operation result as the inverse function φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ) for the input data x input to the check node. = -ln (tanh (x / 2)) Outputs the operation result and outputs the inverse function φ ^-1 (x) operation result for the input data x input to the variable node. The decoding device according to claim 2 , further comprising: Up Table). The message calculation means is a non-linear function φ (x) for obtaining the same operation result as the inverse function φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ) for the output data x output from the variable node. = -ln (tanh (x / 2)) Outputs the operation result and outputs the operation result of the inverse function φ ^-1 (x) to the output data x output from the check node. The decoding device according to claim 2 , further comprising: Up Table). The decoding device according to claim 2 , wherein the storage unit includes two or more banks. In a control method for controlling a decoding device that decodes an LDPC (Low Density Parity Check) code,
The decoding device
Storage means for storing a message used for variable node calculation or check node calculation for decoding the LDPC code;
Message calculation means for performing an operation of the variable node or an operation of the check node based on a parity check matrix defining the LDPC code using a message stored in the storage means and outputting a message obtained as a result of the operation And
The message calculation means has a delay memory that delays by temporarily storing a message used for the variable node calculation or the check node calculation,
In the case where the delay memory stores a smaller number of messages than the maximum weight of the parity check matrix,
Write control for writing a message output by the message calculation means to the storage means, and read control for reading the same message used for calculation in the message calculation means twice from the storage means and supplying the same to the message calculation means And
In the calculation of the variable node, when the column weight of the check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected, When the weight of the column is not less than or equal to the number of messages that the delay memory can store, select the message read from the storage means a second time;
In the operation of the check node, when the weight of the row of the check matrix corresponding to the check node is equal to or less than the number of messages that can be stored in the delay memory, a message delayed in the delay memory is selected, A message delayed in the delay memory so as to select a message read out a second time from the storage means when the weight of the row is not less than or equal to the number of messages that the delay memory can store; A control method including a step of controlling selection means for selecting one of the messages read out from the storage means for the second time as a message used for the variable node calculation or the check node calculation. In a program executed by a computer that controls a decoding device that decodes LDPC (Low Density Parity Check) code,
The decoding device
Storage means for storing a message used for variable node calculation or check node calculation for decoding the LDPC code;
Message calculation means for performing an operation of the variable node or an operation of the check node based on a parity check matrix defining the LDPC code using a message stored in the storage means and outputting a message obtained as a result of the operation And
The message calculation means has a delay memory that delays by temporarily storing a message used for the variable node calculation or the check node calculation,
In the case where the delay memory stores a smaller number of messages than the maximum weight of the parity check matrix,
Write control for writing a message output by the message calculation means to the storage means, and read control for reading the same message used for calculation in the message calculation means twice from the storage means and supplying the same to the message calculation means And
In the calculation of the variable node, when the column weight of the check matrix corresponding to the variable node is equal to or less than the number of messages that can be stored in the delay memory, the message delayed in the delay memory is selected, When the weight of the column is not less than or equal to the number of messages that the delay memory can store, select the message read from the storage means a second time;
In the operation of the check node, when the weight of the row of the check matrix corresponding to the check node is equal to or less than the number of messages that can be stored in the delay memory, a message delayed in the delay memory is selected, A message delayed in the delay memory so as to select a message read out a second time from the storage means when the weight of the row is not less than or equal to the number of messages that the delay memory can store; Control processing including a step of controlling selection means for selecting one of the messages read out from the storage means for the second time as a message used for the variable node calculation or the check node calculation is performed on the computer. The program to be executed.

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