JP4341646B2 - Decoding device - Google Patents

Description

  The present invention relates to a decoding apparatus, and more particularly to a decoding apparatus that decodes a low density parity check code.

  When constructing a data communication system, high-speed communication, low power consumption, high communication quality (low bit error rate), and the like are required. An error correction technique for detecting and correcting an error in a received code is widely used in wireless, wired and recording systems as one technique that satisfies these requirements.

  In recent years, low density parity check (LDPC) codes and sum-product decoding methods have attracted attention as one of the error correction techniques. Decoding operation using this LDPC code is discussed in Non-Patent Document 1. This Non-Patent Document 1 shows that a decoding characteristic of 0.004 dB can be obtained up to the Shannon limit of a white Gaussian channel using an irregular LDPC code with a coding rate of 1/2. The irregular LDPC code indicates a code in which the row weight (number where 1 stands in a row) and the column weight (number where 1 stands in a column) of the parity check matrix are not constant. An LDPC code whose row weights and column weights are constant in each row and each column is called a regular LDPC code.

  This Non-Patent Document 1 shows a mathematical algorithm for decoding an LDPC code according to a sum-product decoding method, but does not show any circuit configuration that specifically performs enormous calculations.

  Non-Patent Document 2 examines the circuit configuration of an LDPC code decoding device. In Non-Patent Document 2, the posterior probability of an information symbol is calculated based on a received sequence according to a trellis-based MAP (maximum posterior probability) algorithm, that is, a BCJR algorithm. In this trellis, forward and backward repetitions are calculated for each state, and posterior probabilities are obtained based on the forward and backward repetition values. In this calculation formula, calculation is performed using an addition / comparison / selection / addition device. In calculating the LDPC code, a circuit is configured to generate a check matrix based on the sum-product decoding method and calculate an estimated value using values from different check nodes.

  Non-Patent Document 3 describes a min-sum decoding method in a logarithmic domain. In Non-Patent Document 3, according to the min-sum decoding method, a process according to the Gallager f function is implemented by only four types of basic operations of addition, minimum, positive / negative determination, and positive / negative sign multiplication. It is shown that the circuit configuration at the time of mounting can be simplified.

  In the sum-product decoding method and the min-sum decoding method described in Non-Patent Document 3 and Non-Patent Document 4, the external value log ratio α is updated using the parity check matrix (row processing), The process (column process) for calculating the prior value logarithmic ratio γ of the symbol based on the value logarithmic ratio α is repeated.

  Patent Document 1 discloses a method for reducing the amount of calculation of row processing in the min-sum decoding method. In this patent document, among data used in row processing, the absolute value stores the minimum value and the second minimum value, and when the processing data matches the minimum value, the second minimum value is output. However, when the processing data does not match the minimum value, the minimum value is output.

Further, Non-Patent Document 5 proposes a decoding method of UMP-APP (the Uniformly most powerful APP-based iterative decoding algorithm) as another method for simplifying the circuit configuration at the time of mounting.
JP 2005-269535 A SY Chung et al., “On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit” IEEE COMMUNICATIONS LETTERS, VOL.5, No.2, Feb. 2001, pp.58-60 E. Yeo et al., “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels” IEEE Trans. ON Magnetics, Vol.37, No.2, March 2001, pp.748-755 Wadayama Tadashi, “About Low Density Parity Check Codes and Decoding Methods”, IEICE Technical Report, MR2001-83, December 2001 Haotian Zhang et al., “The Design of Structured Regular LDPC Codes With Larger Girth” IEEE Globecom 2003, pp.4022-4027 Marc PC Fossorier, “Reduced Complexity Iterative Decoding of Low-Density Parity Check Codes Based on Belief Propagation”, IEEE Trans. ON Communications, Vol. 47, No. 5, May 1999, pp.673-680

  However, in the decoding methods of Non-Patent Documents 1-5 and Patent Document 1 described above, the log likelihood ratio is always used as a constant in the decoding process. For this reason, it is necessary to secure a work variable storage area separately from this constant, and the memory capacity has to be increased.

  Therefore, an object of the present invention is to provide a decoding apparatus capable of decoding a low density parity check code with a small memory capacity.

  In order to solve the above problems, the present invention provides a decoding device that performs decoding in a predetermined number of units using a parity check matrix, and uses a pseudo log likelihood ratio to determine the elements in the row direction of the parity check matrix. A row processing unit that performs row processing using, and updates the external value log ratio, and based on the external value log ratio, performs column processing using elements in the column direction of the parity check matrix to obtain a pseudo prior value log ratio. A row processing unit including a storage unit that stores a pseudo log likelihood ratio, the row processing unit performs row processing using the pseudo log likelihood ratio in the storage unit, and performs row processing. The unit adds the pseudo prior value log ratio updated by the column processing unit and the pseudo log likelihood ratio stored in the storage unit, and updates the pseudo log likelihood ratio in the storage unit with the addition result.

  The present invention is also a decoding apparatus that decodes input data in N units using a low density parity check matrix of M rows and N columns, and stores pseudo log likelihood ratios for N columns. And a row process of N input signals, which is one unit, using a pseudo log likelihood ratio for N columns in the storage unit based on the corresponding blocks included in the parity check matrix. A plurality of block row processing units for updating the external value logarithmic ratio for N columns for the corresponding block and the external value logarithmic ratio for N columns respectively output from the plurality of block row processing units are added. Then, the first addition unit that updates the pseudo prior value log ratio for N columns, the updated pseudo prior value log ratio for N columns, and the pseudo log likelihood for N columns stored in the storage unit Add the frequency ratio and update the pseudo log likelihood ratio for N columns in the storage unit with the addition result. That and a second addition unit.

  Preferably, the storage unit stores a log likelihood ratio of N input signals, which is one unit, as an initial value.

  The present invention is also a decoding apparatus that decodes input data in N units using a low density parity check matrix of M rows and N columns, and stores pseudo log likelihood ratios for N columns. And a row process of N input signals, which is one unit, using a pseudo log likelihood ratio for N columns in the storage unit based on the corresponding blocks included in the parity check matrix. A plurality of block row processing units for updating the external value logarithmic ratio for N columns for the corresponding block, and an external value logarithmic ratio and storage for N columns respectively output from the plurality of block row processing units An adder that adds the pseudo log likelihood ratios for N columns stored in the unit and updates the pseudo log likelihood ratios for N columns in the storage unit with the addition result.

  According to another aspect of the present invention, there is provided a decoding device for decoding input data in N units using a low density parity check matrix of M rows and N columns, and comprising a plurality of cascade-connected arithmetic processing units. Each arithmetic processing unit includes a storage unit storing pseudo log likelihood ratios for N columns, and each of the pseudo log likelihoods for N columns in the storage unit based on a corresponding block included in the parity check matrix. A plurality of block row processing units that perform row processing of N input signals, which are one unit, based on the degree ratio, and update the external value logarithmic ratio for N columns for the corresponding block, and a plurality of block row processing units A first addition unit for updating the pseudo prior value logarithmic ratio for N columns by adding the external value logarithmic ratio for N columns respectively output from the block row processing unit, and the updated pseudo preliminary for N columns Value log ratio and pseudo log likelihood for N columns stored in the storage unit It includes a second adder for adding the door, the second addition unit, in addition result, and updates the pseudo log likelihood ratio of N columns worth in the storage unit included in the next stage of the arithmetic processing unit.

  Preferably, the storage unit of the first-stage arithmetic processing unit stores a log likelihood ratio of N input signals, which is one unit, as an initial value.

  In addition, the present invention is a decoding device that performs decoding in a predetermined number of units using a parity check matrix, and performs row processing using elements in the row direction of the parity check matrix using a pseudo log likelihood ratio. A row processing unit that updates the external value log ratio and performs a column process using elements in the column direction of the parity check matrix based on the external value log ratio to update the prior value log ratio. The row processing unit includes a storage unit that stores a pseudo log likelihood ratio, the row processing unit performs row processing using the pseudo log likelihood ratio in the storage unit, and the row processing unit is a column processing unit. The updated prior value log ratio and the pseudo log likelihood ratio stored in the storage unit are added, and the pseudo log likelihood ratio in the storage unit is updated with the addition result.

  According to the decoding apparatus of the present invention, a low density parity check code can be decoded with a small memory capacity.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
[First Embodiment]
The embodiment of the present invention is a decoding device based on the UMP-APP decoding method.

  FIG. 1 is a diagram showing an example of a configuration of a communication system using a decoding device according to an embodiment of the present invention. In FIG. 1, in the communication system, on the transmission side, an encoder 1 that adds a redundant bit for error correction to transmission information to generate a transmission code, and (K + M) (= N) from the encoder 1 And a modulator 2 that modulates a bit code according to a predetermined method and outputs the modulated signal to the communication path 3.

  The encoder 1 adds M bits of redundant bits for parity calculation to the K bits of information to generate a (K + M) -bit LDPC code (low density parity check code). If the information side and the M redundant bits are arranged in which bits of the (K + M) -bit LDPC code, the transmission side and the reception side may decide how to arrange them. In the embodiment of the present invention, the transmitting side and the receiving side are arranged so that redundant bits are arranged in M bits from the beginning (MSB: Most Significant Bit) of the LDPC code and information bits are arranged in the next K bits. Suppose that it is decided by the side.

In the parity check matrix, rows correspond to redundant bits and columns correspond to code bits.
The modulator 2 performs modulation such as amplitude modulation, phase modulation, code modulation, frequency modulation or direct frequency division multiplexing modulation according to the configuration of the communication path 3. For example, when the communication path 3 is an optical fiber, the modulator 2 performs light intensity modulation (a kind of amplitude modulation) by changing the luminance of the laser diode according to the transmission information bit value. For example, when the transmission data bit is “0”, the emission intensity of the laser diode is increased and transmitted as “+1”, and when the transmission data bit is “1”, the emission intensity of the laser diode is decreased. Then, it is converted to “−1” and transmitted.

  In the reception unit, the demodulator 4 that demodulates the modulated signal transmitted via the communication path 3 to demodulate the (K + M) bit digital code, and the (K + M) bit code from the demodulator 4 Is provided with a decoder 5 for performing parity check matrix operation processing to reproduce the original K-bit information.

  The demodulator 4 performs demodulation processing according to the transmission form in the communication path 3. For example, in the case of amplitude modulation, phase modulation, code modulation, frequency modulation, and orthogonal frequency division multiplexing modulation, the demodulator 4 performs processing such as amplitude demodulation, phase demodulation, code demodulation, and frequency demodulation.

  FIG. 2 is a diagram showing a list of correspondence relationships between the output data of the modulator 2 and the demodulator 4 when the communication path 3 is an optical fiber. In FIG. 2, as described above, when the communication path 3 is an optical fiber, when the transmission data is “0”, the modulator 2 increases the emission intensity of the laser diode (light emitting diode) for transmission, When “1” is output and the transmission data bit is “1”, the emission intensity is weakened and bit “−1” is transmitted.

  The light intensity transmitted to the demodulator 4 due to transmission loss in the communication path 3 has an analog intensity distribution from the strongest intensity to the weakest intensity. The demodulator 4 performs a quantization process (analog / digital conversion) on the input optical signal to detect the received light level. FIG. 2 shows the received signal intensity when the light reception level is quantized in eight steps. That is, when the light reception level is data “7”, the light emission intensity is considerably high, and when the light reception level is “0”, the light intensity is considerably low. Each light reception level is associated with signed data and output from the demodulator 4. The output of the demodulator 4 is data “3” when the light reception level is “7”, and data “−4” when the light reception level is “0”. Therefore, the demodulator 4 outputs a multi-level quantized signal for a 1-bit received signal.

  The decoder 5 receives (K + M) -bit received information (each bit includes multi-value information) given from the demodulator 4 and converts an LDPC parity check matrix according to a decoding method, which will be described in detail later. Apply to restore the original K-bit information.

  In FIG. 2, the demodulator 4 generates bits quantized to 8 levels. However, in general, the demodulator 4 can perform decoding using bits quantized to L values (L ≧ 2).

  In FIG. 2, a binary signal may be generated by using a comparator to determine the level of the received signal using a certain threshold value.

  FIG. 3 schematically shows a configuration of decoder 5 according to the embodiment of the present invention. In FIG. 3, the demodulator 4 and the communication path 3 are also shown. The demodulator 4 includes a demodulation circuit 4a that demodulates a signal applied from the communication path 3, and an analog / digital conversion circuit 4b that converts an analog demodulated signal generated by the demodulation circuit 4a into a digital signal. The output data In of the analog / digital conversion circuit 4b is applied to the decoder 5. The data In given to the decoder 5 is L value (L ≧ 2) data. Hereinafter, data In is referred to as a symbol because it is multilevel quantized data. The decoder 5 performs a decoding process on the input symbol In sequence to generate decoded bits Cn.

  The decoder 5 includes a log likelihood ratio calculation unit 6 that generates a log likelihood ratio λn of the demodulated symbol In from the demodulator 4, and an external value logarithm by iterative calculation based on the log likelihood ratio λn and the parity check matrix. The update unit 7 that updates the ratio αmn (t), the pseudo prior value log ratio Sn (t), and the pseudo log likelihood ratio γn (t), and generates a decoded word based on the pseudo log likelihood ratio γn (t) A decoded word generation unit 16.

The log likelihood ratio calculation unit 6 generates a log likelihood ratio λn independently of the noise information of the received signal. Normally, when noise information is taken into consideration, this log likelihood ratio λ n is given by 2 × In / σ ² . Here, σ represents noise variance. Although the log likelihood ratio λn may be used, in the description of the embodiment of the present invention, the log likelihood ratio calculation unit 6 is formed by a buffer circuit or a constant multiplication circuit, and the log likelihood ratio λn is expressed as In It shall be given by xf. Here, f is a non-zero positive number. By calculating the log likelihood ratio without using this noise information, the circuit configuration is simplified and the calculation process is also simplified.

ここで、上式（１）において、ｎ′∈Ａ（ｍ）＼ｎ、自身を除く要素を意味する。つまり、外部値対数比αmn(t)について、ｎ′≠ｎである。
また、α、Ｓ、γ、の添え字“mn”、“n”は、通常は下付文字で示されるが、本明細書においては、読みやすさのために、「横並びの文字」で示す。 The updating unit 7 performs arithmetic processing according to the following equations (1), (2), and (3), performs processing for each element of the parity check matrix row (row processing) and processing for each element for the column (column) (Process) is executed repeatedly.

Here, in the above formula (1), n′εA (m) \ n means an element excluding itself. That is, n ′ ≠ n with respect to the external value log ratio αmn (t).
Further, the subscripts “mn” and “n” of α, S, γ are usually indicated by subscripts, but in this specification, they are indicated by “horizontal characters” for the sake of readability. .

ここで、関数ｍｉｎは、最小値を求める演算を示す。 The function sign (x) is defined by the following equation (4).

Here, the function min indicates an operation for obtaining the minimum value.

In addition, the sets A (m) and B (n) have the binary M · N matrix H = [Hmn] as the parity check matrix of the LDPC code to be decoded, as shown in the equations (5) and (6). The subset [1, N] = {1, 2,..., N}.
A (m) = {n: Hmn = 1} (5)
B (n) = {m: Hmn = 1} (6)
That is, the subset A (m) means a set of column indexes where 1 stands in the m-th row of the parity check matrix H, and the subset B (n) means the n-th column of the parity check matrix H. A set of row indexes where 1 stands in FIG.

Specifically, consider the parity check matrix H shown in FIG. In the parity check matrix H shown in FIG. 4, “1” stands in the first to third columns of the first row, “1” stands in the third and fourth columns of the second row, and “1” stands in the fourth to sixth columns of the third row. Therefore, in this case, the subset A (m) is as follows.
A (1) = {1, 2, 3},
A (2) = {3,4},
A (3) = {4, 5, 6}.

Similarly, the subset B (n) is as follows.
B (1) = B (2) = {1},
B (3) = {1, 2},
B (4) = {2, 3},
B (5) = B (6) = {3}.

  In the parity check matrix of FIG. 4, the number of “1” is equal to the number of “0”, but the parity check matrix H used in the embodiment of the present invention has a small number of “1” and a low-density parity check matrix. Thus, the amount of calculation can be reduced.

The decoded word generation unit 16 follows the pseudo-log-likelihood ratio γn (t) (= γ1 (t), γ2 (t),..., ΓN (t)) output from the update unit 7 by the following formula ( 7), primary estimated words (C1 (t), C2 (t),..., CN (t)) are calculated. Here, the notation of (C1 (t), C2 (t),..., CN (t)) indicates that the first bit (LSB: Least Significant Bit) of the N-bit primary estimation word is C1 (t). Yes, the second bit is C2 (t), and the Nth bit (MSB) is CN (t).

Furthermore, the decoded word generation unit 16 determines whether or not the primary estimated words (C1 (t), C2 (t),..., CN (t)) constitute codewords according to the calculation of the following equation (8). Inspect. When the following equation (8) is satisfied, that is, when the syndrome becomes “0”, the decoded word generation unit 16 ends the repetitive calculation of the update unit 7 and performs primary estimation words (C1 (t), C2 (t),..., CN (t)) of K bits, ie, (C1 (t), C2 (t),..., CK (t)) are decoded as decoded words. To the outside of the generator 5. Also, the decoded word generation unit 16 ends the iterative operation of the update unit 7 even when the number of loops, that is, the number of repetitions of the operation of the update unit 7 exceeds a predetermined value, so that the primary estimated word (C1 (t ), C2 (t),..., CN (t)), that is, the information bits of K, that is, (C1 (t), C2 (t),..., CK (t)) are decoded. The word is output to the outside of the decoder 5.
(C1 (t), C2 (t),..., CN (t)) · H ^t = 0 (8)
However, H ^t, the table the transpose of H.

  In the embodiment of the present invention, a parity check matrix H having low density and having two or more column weights is used.

FIG. 5 is a diagram for explaining a method of generating a parity check matrix having a column weight X.
Referring to FIG. 5, the parity check matrix H is divided into X blocks (H1, H2,..., HX). When the number of row weights is 6, first, “1” is arranged in the first column to the sixth column of the first row in the first block (H1), and the seventh column of the second row. “1” is arranged in the first to eleventh columns, and the following lines are arranged in the same manner. Then, an arbitrary column in the first block is rearranged using a random number, and this is repeated an appropriate number of times, thereby determining an element in the first block.

  In the second and subsequent blocks as well, the elements in the block are determined by performing column replacement processing using random numbers in the same manner as described above.

FIG. 6 is a diagram illustrating a schematic configuration of the updating unit 7.
Referring to FIG. 6, update unit 7 includes an S / P conversion unit 8 that converts the log likelihood ratio λn from serial data to parallel data, and an arithmetic processing unit 11. The arithmetic processing unit 11 includes a row processing unit 10 that performs row processing of a parity check matrix and a column processing unit 12 that performs column processing of the parity check matrix.

  The S / P converter 8 receives the log-likelihood ratio λn input serially, converts the number of columns of the parity check matrix to N, and outputs the converted data as parallel data of N bits.

  The row processing unit 10 uses the log-likelihood ratio λn sent from the S / P conversion unit 8 and the pseudo prior value logarithmic ratio Sn (t) sent from the column processing unit 12 for each step of the iterative calculation, The pseudo log likelihood ratio γn (t) is updated according to the equation (3), and the external value log ratio αmn (t) is updated according to the equation (1).

  The column processing unit 12 updates the pseudo prior value logarithmic ratio Sn (t) according to the equation (2) using the external value logarithmic ratio αmn (t) given from the row processing unit 10.

FIG. 7 is a diagram illustrating a detailed configuration of the updating unit 7.
Referring to FIG. 7, the row processing unit 10 includes a first block row processing unit 23, a second block row processing unit 24, a third block row processing unit 25, a pseudo log likelihood ratio storage unit 22, And an adding unit 21.

  The first block row processing unit 23 includes a first row processing unit 27 and a second row processing unit 28. The second block row processing unit 24 includes a third row processing unit 29 and a fourth row processing unit 30. The third block row processing unit 25 includes a fifth row processing unit 31 and a sixth row processing unit 32.

  The m-th row processing unit (m = 1 to 6) reads a plurality of pseudo-log likelihood ratios that are columns in which “1” in the m-th row of the parity check matrix stands from the pseudo-log likelihood ratio storage unit 22. put out. In order to calculate the external value log ratio for the j-th column, the m-th row processing unit specifies a set excluding the element in the j-th column from the read elements, and the elements included in this set Specify the minimum value of the absolute value, specify the product of the sign of the elements included in this set, add the sign of the product of the specified element to the minimum value of the absolute value of the specified element, and logarithm ratio of the external value Update.

  The pseudo log likelihood ratio storage unit 22 stores the pseudo log likelihood ratio γn (t) in the t-th phase. In the 0th phase, log likelihood ratios λn (n = 1, 2,... N) for N columns are sent from the S / P converter 8 to the pseudo log likelihood ratio storage unit 22. The pseudo log likelihood ratio storage unit 22 stores the received log likelihood ratio λ n for N columns as a pseudo log likelihood ratio γ n (t) for N columns of the zeroth phase.

  FIG. 8A is a diagram showing data stored in the pseudo log likelihood ratio storage unit 22 in the 0th phase.

  Referring to FIG. 8 (a), in the 0th phase, the pseudo log likelihood ratio γn (0) (n = 1, 2,... N) of the 0th phase is output from the S / P conversion unit 8. The log likelihood ratios λn (n = 1, 2,... N) for the N columns are stored.

  FIG. 8B is a diagram representing data stored in the pseudo log likelihood ratio storage unit 22 in the first phase.

  Referring to FIG. 8 (b), in the first phase, the pseudo log likelihood of the 0th phase is set as the pseudo log likelihood ratio γ n (1) (n = 1, 2,... N) of the first phase. The sum of the ratio γn (0) and the pseudo prior value log ratio Sn (1) of the first phase is stored.

  FIG. 8C is a diagram illustrating data stored in the pseudo log likelihood ratio storage unit 22 in the second phase.

  Referring to FIG. 8C, in the second phase, the pseudo log likelihood of the first phase is set as the pseudo log likelihood ratio γ n (2) (n = 1, 2,..., N) of the second phase. The sum of the ratio γn (1) and the pseudo prior value logarithmic ratio Sn (2) of the second phase is stored.

  The adder 21 has N adders corresponding to N columns. Each adder performs addition for the corresponding column. For example, the adder corresponding to the i-th column is stored in the t-phase pseudo prior value log ratio Si (t) output from the column processing unit 12 and the pseudo log likelihood ratio storage unit 22. (T-1) The pseudo log likelihood ratio γ i (t−) is added to the pseudo log likelihood ratio γ i (t) of the t-th phase, which is the addition result, by adding the phase pseudo log likelihood ratio γ i (t). Update 1) (ie overwrite).

The column processing unit 12 includes an adding unit 26.
Each adder 26 has N adders. Each adder performs addition for the corresponding column. For example, the adder corresponding to the i-th column is the t-phase external value logarithmic ratio αmi output from the first block row processing unit 23, the second block row processing unit 24, and the third block row processing unit 25, respectively. The pseudo prior value log ratio Si (t), which is the sum of (t), is calculated and output to the adding unit 21 of the row processing unit 10.

(Concrete example)
Next, a specific operation of the updating unit 7 when the parity check matrix of FIG. 9 is used will be described.

  In the 0th phase, the S / P converter 8 receives the log-likelihood ratios λ1 to λN that are serially input, and N units of parallel data (λ1 (0), λ2 (0),. ... ΛN (0)) and sent to the pseudo log likelihood ratio storage unit 22 of the arithmetic processing unit 11, and the pseudo log likelihood ratio storage unit 22 stores the parallel data (λ1 (0), λ2 (0)). ,..., ΛN (0)) are stored as pseudo log likelihood ratios (γ1 (0), γ2 (0),..., ΓN (0)) of the zeroth phase.

  In the first phase, the following processes of the first block row processing unit 23, the second block row processing unit 24, and the third block row processing unit 25 are performed in parallel.

  The first row processing unit 27 includes the first column, the third column, the fourth column, the first column, which are the columns in which “1” in the first row of the parity check matrix stands from the pseudo log likelihood ratio storage unit 22. The pseudo log likelihood ratios γ1 (0) (= λ1), γ3 (0) (= λ3), γ4 (0) (= λ4), γ5 (0) in the fifth column, the tenth column, and the twelfth column (= Λ5), γ10 (0) (= λ10), and γ12 (0) (= λ12) are read.

  In order to calculate the logarithmic ratio of the external value for the first column, the first row processing unit 27 collects {γ3 (0), γ4 (0) , Γ5 (0), γ10 (0), γ12 (0)}. The first row processing unit 27 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The first row processing unit 27 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value logarithmic ratio α1,1 (1). In the same manner as described above, the first row processing unit 28 uses the external value logarithmic ratio α1,3 (1) for the third column, the fourth column, the fifth column, the tenth column, and the twelfth column. , Α1,4 (1), α1,5 (1), α1,10 (1), α1,12 (1) are output.

  The second row processing unit 28 stores the second column, the sixth column, the seventh column, the second column, which are columns in which “1” in the second row of the parity check matrix is set from the pseudo log likelihood ratio storage unit 22. Pseudo log likelihood ratios γ2 (0) (= λ2), γ6 (0) (= λ6), γ7 (0) (= λ7), γ8 (0) in the 8th, 9th and 11th columns (= Λ8), γ9 (0) (= λ9), and γ11 (0) (= λ11) are read.

  In order to calculate the external value log ratio for the second column, the second row processing unit 28 sets a set {γ6 (0), γ7 (0) excluding the elements in the second column among the read elements. , Γ8 (0), γ9 (0), γ11 (0)}. The second row processing unit 28 specifies the minimum value of the absolute values of the elements included in this set and specifies the product of the codes of the elements included in this set. The second row processing unit 28 adds the sign of the product of the identified element to the minimum value of the absolute value of the identified element, and outputs the external value log ratio α2,2 (1). In the same manner as described above, the second row processing unit 28 performs the external value logarithmic ratio α2,6 (1) for the sixth column, the seventh column, the eighth column, the ninth column, and the eleventh column. , Α2,7 (1), α2,8 (1), α2,9 (1), α2,11 (1) are output.

  The third row processing unit 29 is the third column, the fifth column, the sixth column, the first column, which is the column in which “1” in the third row of the parity check matrix stands from the pseudo log likelihood ratio storage unit 22. The pseudo log likelihood ratios γ3 (0) (= λ3), γ5 (0) (= λ5), γ6 (0) (= λ6), γ7 (0) in the seventh column, the eleventh column, and the twelfth column (= Λ7), γ11 (0) (= λ11), and γ12 (0) (= λ12) are read.

  The third row processing unit 29 calculates a set {γ5 (0), γ6 (0) excluding the elements in the third column among the read elements in order to calculate the external value log ratio for the third column. , Γ7 (0), γ11 (0), γ12 (0)}. The third row processing unit 29 specifies the minimum value of the absolute values of the elements included in this set and specifies the product of the codes of the elements included in this set. The third row processing unit 29 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value log ratio α3,3 (1). In the same manner as described above, the third row processing unit 29 performs external value logarithmic ratio α3,5 (1) for the fifth column, the sixth column, the seventh column, the eleventh column, and the twelfth column. , Α3,6 (1), α3,7 (1), α3,11 (1), α3,12 (1) are output.

  The fourth row processing unit 30 includes, from the pseudo log likelihood ratio storage unit 22, the first column, the second column, the fourth column, Pseudo log likelihood ratios γ1 (0) (= λ1), γ2 (0) (= λ2), γ4 (0) (= λ4), γ8 (0) in the 8th, 9th and 10th columns (= Λ8), γ9 (0) (= λ9), and γ10 (0) (= λ10) are read.

  The fourth row processing unit 30 calculates a set {γ2 (0), γ4 (0) excluding the elements in the first column among the read elements in order to calculate the external value log ratio for the first column. , Γ8 (0), γ9 (0), γ10 (0)}. The fourth row processing unit 30 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The fourth row processing unit 30 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value log ratio α4,1 (1). In the same manner as described above, the fourth row processing unit 30 performs the external value logarithmic ratio α4,2 (1) for the second column, the fourth column, the eighth column, the ninth column, and the tenth column. , Α4,4 (1), α4,8 (1), α4,9 (1), α4,10 (1) are output.

  The fifth row processing unit 31 includes the second column, the third column, the sixth column, the first column, and the fifth column of the parity check matrix where “1” stands from the pseudo log likelihood ratio storage unit 22. Pseudo log likelihood ratios γ2 (0) (= λ2), γ3 (0) (= λ3), γ6 (0) (= λ6), γ8 (0) in the 8th, 10th and 12th columns (= Λ8), γ10 (0) (= λ10), and γ12 (0) (= λ12) are read.

  The fifth row processing unit 31 calculates a set {γ3 (0), γ6 (0) excluding the elements in the second column among the read elements in order to calculate the external value log ratio for the second column. , Γ8 (0), γ10 (0), γ12 (0)}. The fifth row processing unit 31 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The fifth row processing unit 31 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value logarithmic ratio α5,2 (1). In the same manner as described above, the fifth row processing unit 31 sets the external value log ratio α5,3 (0) for the third column, the sixth column, the eighth column, the tenth column, and the twelfth column. , Α5,6 (0), α5,8 (0), α5,10 (0), α5,12 (0) are output.

  The sixth row processing unit 32 includes the first column, the fourth column, the fifth column, the first column, which are columns in which “1” of the sixth row of the parity check matrix stands from the pseudo log likelihood ratio storage unit 22. The pseudo log likelihood ratios γ1 (0) (= λ1), γ4 (0) (= λ4), γ5 (0) (= λ5), γ7 (0) in the seventh column, the ninth column, and the eleventh column (= Λ7), γ9 (0) (= λ9), and γ11 (0) (= λ11) are read.

  The sixth row processing unit 32 calculates a set {γ4 (0), γ5 (0) excluding the elements in the first column among the read elements in order to calculate the external value log ratio for the first column. , Γ7 (0), γ9 (0), γ11 (0)}. The sixth row processing unit 32 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The sixth row processing unit 32 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value logarithmic ratio α6,1 (1). In the same manner as described above, the sixth row processing unit 32 performs the external value log ratio α6,4 (1) for the fourth column, the fifth column, the seventh column, the ninth column, and the eleventh column. , Α6,5 (1), α6,7 (1), α6,9 (1), α6,11 (1) are output.

  For the first column, the adding unit 26 receives the external value logarithmic ratio α1,1 (1) from the first block row processing unit 23, and receives the external value logarithmic ratio α4,1 (1) from the second block row processing unit 24. And the external block logarithmic ratio α6,1 (1) is received from the third block row processing unit 25, and these are added together to obtain a pseudo prior value logarithmic ratio S1 (1) (= α1,1 (1) ) + Α4,1 (1) + α6,1 (1)) is output to the adder 21. The adder 26 outputs the pseudo prior value log ratios S2 (1) to S12 (1) for the second column to the twelfth column to the adder 21 in the same manner as described above.

  For the first column, the adding unit 21 has a pseudo prior value log ratio S1 (1) sent from the adding unit 26 and a pseudo log likelihood ratio γ1 (0) stored in the pseudo log likelihood ratio storage unit 22. ) And the pseudo log likelihood ratio γ1 (0) in the pseudo log likelihood ratio storage unit 22 is updated (that is, overwritten) with the pseudo log likelihood ratio γ1 (1) that is the addition result. . In the same manner as described above, the adding unit 21 calculates pseudo log likelihood ratios γ2 (1) to γ12 (1) for the second column to the twelfth column, and the pseudo log likelihood ratios γ2 (1) to The pseudo log likelihood ratios γ2 (0) to γ12 (0) in the pseudo log likelihood ratio storage unit 22 are updated (that is, overwritten) with γ12 (1).

  In the second phase, the following processes of the first block row processing unit 23, the second block row processing unit 24, and the third block row processing unit 25 are performed in parallel.

  The first row processing unit 27 stores pseudo log likelihood ratios γ1 (1), γ3 (1), γ4 (1), γ5 (1), γ10 (1), γ12 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the first row processing unit 27 performs external value logarithmic ratios α1,1 (2), α1,3 (2), α1,4 (2), α1,5 (2), α1, 10 (2) and α1,12 (2) are output.

  The second row processing unit 28 receives pseudo log likelihood ratios γ2 (1), γ6 (1), γ7 (1), γ8 (1), γ9 (1), γ11 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the second row processing unit 28 performs external value logarithmic ratios α2,2 (2), α2,6 (2), α2,7 (2), α2,8 (2), α2, 9 (2) and α2,11 (2) are output.

  The third row processing unit 29 receives pseudo log likelihood ratios γ3 (1), γ5 (1), γ6 (1), γ7 (1), γ11 (1), γ12 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the third row processing unit 29 performs external value logarithmic ratios α3,3 (2), α3,5 (2), α3,6 (2), α3,7 (2), α3. , 11 (2) and α3,12 (2) are output.

  The fourth row processing unit 30 stores pseudo log likelihood ratios γ1 (1), γ2 (1), γ4 (1), γ8 (1), γ9 (1), γ10 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the fourth row processing unit 30 performs external value logarithmic ratios α4,1 (2), α4,2 (2), α4,4 (2), α4,8 (2), α4, 9 (2) and α4,10 (2) are output.

  The fifth row processing unit 31 stores pseudo log likelihood ratios γ2 (1), γ3 (1), γ6 (1), γ8 (1), γ10 (1), γ12 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the fifth row processing unit 31 performs external value logarithmic ratios α5,2 (2), α5,3 (2), α5,6 (2), α5,8 (2), α5, 10 (2) and α5,12 (2) are output.

  The sixth row processing unit 32 receives pseudo log likelihood ratios γ1 (1), γ4 (1), γ5 (1), γ7 (1), γ9 (1), γ11 (1) from the pseudo log likelihood ratio storage unit 22. ). Similarly to the first phase, the sixth row processing unit 32 performs external value logarithmic ratios α6,1 (2), α6,4 (2), α6,5 (2), α6,7 (2), α6, 9 (2) and α6,11 (2) are output.

  In the same manner as in the first phase, the adding unit 26 receives the external value logarithmic ratio α1,1 (2) from the first block row processing unit 23 and receives the external value from the second block row processing unit 24 for the first column. The logarithmic ratio α4,1 (2) is received, the external value logarithmic ratio α6,1 (2) is received from the third block row processing unit 25, they are added together, and the pseudo prior value logarithmic ratio S1 (2 ) (= Α1,1 (2) + α4,1 (2) + α6,1 (2)) is output to the adder 21. The adder 26 outputs the pseudo prior value log ratios S2 (2) to S12 (2) for the second column to the twelfth column to the adder 21 in the same manner as described above.

  For the first column, the adding unit 21 has a pseudo prior value log ratio S1 (2) sent from the adding unit 26 and a pseudo log likelihood ratio γ1 (1) stored in the pseudo log likelihood ratio storage unit 22. ) And the pseudo log likelihood ratio γ1 (1) in the pseudo log likelihood ratio storage unit 22 is updated (that is, overwritten) with the pseudo log likelihood ratio γ1 (2) that is the addition result. . In the same manner as described above, the adding unit 21 calculates pseudo-log likelihood ratios γ2 (2) to γ12 (2) for the second column to the twelfth column and calculates the pseudo-log likelihood ratios γ2 (2) to The pseudo log likelihood ratios γ2 (1) to γ12 (1) in the pseudo log likelihood ratio storage unit 22 are updated (that is, overwritten) with γ12 (2).

Similar processing is repeated for the third and subsequent phases.
(Row and column processing unit of conventional decoding device)
For comparison with the update unit of the embodiment of the present invention, the update unit of the UMP-APP decoding device described in Non-Patent Document 5 will be described.

FIG. 10 is a diagram showing a detailed configuration of updating unit 37 of the conventional decoding device.
Referring to FIG. 10, the row processing unit 30 includes a first block row processing unit 23, a second block row processing unit 24, and a third block row processing unit 25 that are the same as those in the embodiment of the present invention.

  The conventional row processing unit 30 includes a log likelihood ratio storage unit 33 different from the pseudo log likelihood ratio storage unit 22 of the embodiment of the present invention.

FIG. 11 is a diagram illustrating data stored in the log likelihood ratio storage unit 33.
Referring to FIG. 11, log likelihood ratio storage unit 33 stores log likelihood ratio λn in all phases. That is, in the 0th phase, the log likelihood ratio λn (n = 1, 2,... N) for N columns is sent from the S / P converter 8 to the pseudo log likelihood ratio storage unit 22. The pseudo log likelihood ratio storage unit 22 continues to store the received log likelihood ratios λn for N columns over all phases.

  Referring to FIG. 10 again, an adder 34 different from adder 24 of the embodiment of the present invention is included.

  The adder 34 has N adders corresponding to N columns. Each adder performs addition for the corresponding column. For example, the adder corresponding to the i-th column includes the t-phase pseudo prior value log ratio Si (t) output from the column processing unit 12 and the log likelihood stored in the log likelihood ratio storage unit 33. The degree ratio λi is added, and the addition result (Si (t) + λi) is output.

  The column processing unit 32 includes the same addition unit 26 as in the embodiment of the present invention. The conventional column processing unit 32 includes a pseudo prior value log ratio storage unit 35.

  FIG. 12A is a diagram illustrating data stored in the pseudo prior value log ratio storage unit 35 in the 0th phase.

  12A, in the 0th phase, the pseudo prior value logarithmic ratio Sn (0) (n = 1, 2,... N) of the 0th phase output from the adding unit 26 is stored. The

  FIG. 12B is a diagram showing data stored in the pseudo prior value log ratio storage unit 35 in the first phase.

  Referring to FIG. 12B, in the first phase, the pseudo prior value logarithmic ratio Sn (1) (n = 1, 2,..., N) output from the adding unit 26 is stored. The

  As can be seen from comparison between FIG. 7 and FIG. 10, in the decoding device of Non-Patent Document 5, a log likelihood ratio storage unit 33 that stores log likelihood ratios λn for N columns, and a pseudo prior value logarithm for N columns. Whereas the pseudo prior value log ratio storage unit 35 for storing the ratio Sn (t) is required, the decoding apparatus according to the embodiment of the present invention stores the pseudo log likelihood ratio γn (t) for N columns. Since only the pseudo log likelihood ratio storage unit 22 is required, the memory capacity can be reduced.

  In addition, since the log-likelihood ratio λn is stored as an initial value in the pseudo log-likelihood ratio storage unit 22 of the decoding apparatus according to the embodiment of the present invention, an appropriate value can be given as the initial value of the update calculation. .

[Modification 1 of the first embodiment]
In the embodiment of the present invention, an adder 21 and an adder 26 are provided. The adder 21 includes a t-phase pseudo prior value log ratio output from the column processing unit 12 and a pseudo log likelihood ratio storage unit 22. Is added to the (t−1) -phase pseudo log likelihood ratio γ i (t), and the t-th phase pseudo prior value log ratio, which is the addition result, is added to the (t−1) phase. The pseudo-log likelihood ratio γi (t−1) of is updated. On the other hand, the adding unit 26 is a pseudo total that is the sum of the logarithmic ratios of the three t-th phase external values output from the first block row processing unit 23, the second block row processing unit 24, and the third block row processing unit 25. The prior value logarithm ratio Si (t) is calculated and output to the adder 21.

  On the other hand, the adding unit 21 and the adding unit 25 may be combined into one adding unit. That is, one adder unit performs three logarithmic ratios of t-phase external values output from the first block row processing unit 23, the second block row processing unit 24, and the third block row processing unit 25, and the pseudo logarithm. The pseudo log likelihood ratio is obtained by adding the pseudo log likelihood ratio of the (t−1) phase stored in the likelihood ratio storage unit 22 and the pseudo prior value log ratio of the t phase as the addition result. The pseudo log likelihood ratio of the (t−1) phase stored in the storage unit 22 may be updated.

  Thus, in this modification, in addition to the memory capacity, the number of adders can be further reduced compared to the conventional decoding device of FIG.

[Second Embodiment]
FIG. 13 is a diagram illustrating the update unit 17 according to the second embodiment.

  Referring to FIG. 13, the updating unit 17 includes an S / P conversion unit 8 and n arithmetic processing units 11-1 to 11-n connected in cascade.

  Similar to the arithmetic processing unit 11 of the first embodiment, the first stage arithmetic processing unit 11-1 includes an adding unit 21-1, a pseudo log likelihood ratio storage unit 22-1, and a first block row process. A unit 23-1, a second block row processing unit 24-1, a third block row processing unit 25-2, and an adding unit 26-1.

  The arithmetic processing units 11-2 to 11-n in the other stages are the same as the arithmetic processing units 11-1 in the first stage.

However, in the second embodiment, in the t-th phase, the S / P converter 8 converts the serial N log likelihood ratios λ1 to λN of the k-th group into parallel data (λ1 (t), λ2 (t),..., λN (t)) are converted into _k and sent to the pseudo log likelihood ratio storage units 22-1 of the N first stage arithmetic processing units 11.

  In addition, the adding unit 21-1 sends the addition result to the pseudo log likelihood ratio storage unit 22-2 in the arithmetic processing unit 11-2 at the next stage.

  The adding unit 21-n of the n-th arithmetic processing unit 11-n outputs the pseudo log likelihood ratio for N columns, which is the addition result, to the decoded word generating unit 16.

  The decoded word generation unit 16 generates primary estimated words (C1 (t), C2 (t),..., CN (t)) from the received pseudo log likelihood ratio according to the equation (7), and performs primary estimation. Information bits of K bits in the word (C1 (t), C2 (t),..., CN (t)), that is, (C1 (t), C2 (t),. t)) is output to the outside of the decoder 5 as a decoded word.

(Concrete example)
Next, the operation of the updating unit 17 of the second embodiment will be specifically described.

In the 0th phase, the following processing is performed.
The S / P converter 8 receives the log-likelihood ratios λ1 to λN of the first group serially input in the 0th phase, and 1 unit of N parallel data (λ1 (0), λ2 (0) ,..., ΛN (0)) ₁ and sent to the pseudo log likelihood ratio storage unit 22-1 of the arithmetic processing unit 11-1, where the pseudo log likelihood ratio storage unit 22-1 is parallel data. (Λ1 (0), λ2 (0),..., ΛN (0)) ₁ is a pseudo log likelihood ratio (γ1 (0), γ2 (0)) for N columns of the first group of the 0th update. ,..., ΓN (0)) ₁ is stored.

In the first phase, the following processing is performed.
The first block row processing unit 23-1, the second block row processing unit 24-1, and the third block row processing unit 25-1 of the arithmetic processing unit 11-1 are included in the pseudo log likelihood ratio storage unit 22-1. The pseudo log likelihood ratio (γ1 (0), γ2 (0),..., ΓN (0)) ₁ for N columns of the first group performs row processing based on ₁ , and the external value logarithmic ratio αmn (1) calculates the adding unit 26-1, N column fraction pseudo priori value log ratio of the first group of 1st update (S1 (1), S2 ( 1), ···, SN (1)) 1 Is output to the adder 21-1. The adding unit 21-1 of the arithmetic processing unit 11-1 includes a pseudo prior value logarithmic ratio (S1 (1), S2 (1),..., N columns of the first group sent from the adding unit 26-1. SN (1)) ₁ and pseudo log likelihood ratios (γ1 (0), γ2 (0),..., ΓN (0) for N columns stored in the pseudo log likelihood ratio storage unit 22-1. )) ₁ is added, and the addition result is sent to the pseudo log likelihood ratio storage unit 22-2 of the arithmetic processing unit 11-2. The pseudo log likelihood ratio storage unit 22-2 adds the result of the addition to the first group of pseudo log likelihood ratios (γ1 (1), γ2 (1),..., ΓN (1)) _1. Remember as.

The S / P converter 8 receives the log likelihood ratios λ1 to λN of the second group serially input in the first phase and receives parallel data (λ1 (1), λ2 (1) whose unit is N bits. ,..., ΛN (1)) ₂ and sent to the pseudo log likelihood ratio storage unit 22-1 of the arithmetic processing unit 11-1, and the pseudo log likelihood ratio storage unit 22-1 stores the parallel data ( λ1 (1), λ2 (1),..., λN (1)) ₂ is a pseudo log likelihood ratio (γ1 (0), γ2 (0), 2) for N columns of the 0th update of the second group. ..., .Gamma.N (0)) ₂ are stored instead of (.gamma.1 (0), .gamma.2 (0),..., .Gamma.N (0)) ₁ .

In the second phase, the following processing is performed.
The first block row processing unit 23-2, the second block row processing unit 24-2 and the third block row processing unit 25-2 of the arithmetic processing unit 11-2 are included in the pseudo log likelihood ratio storage unit 22-2. 1st update of N columns worth pseudo log likelihood ratio of the first group (γ1 (1), γ2 ( 1), ···, γN (1)) outer value log perform the row processing based on ₁ The ratio αmn (2) is calculated, and the adder 26-2 calculates the pseudo prior value logarithmic ratio (S1 (2), S2 (2),..., SN) for N columns of the second update of the first group. (2)) ₁ is output to the adder 21-2. The adder 21-2 sends a pseudo prior value logarithmic ratio (S1 (2), S2 (2),..., SN () for N columns of the second update of the first group sent from the adder 26-2. 2)) ₁ and pseudo log likelihood ratios (γ1 (1), γ2 (1), γ1 (1), γ2 (1), N columns for the first update of the first group stored in the pseudo log likelihood ratio storage unit 22-2. ..., [Gamma] N (1)) ₁ is added and the addition result is sent to the pseudo log likelihood ratio storage unit 22c of the arithmetic processing unit 11c. The pseudo log likelihood ratio storage unit 22c stores the addition result as a pseudo log likelihood ratio (γ1 (2), γ2 (2),..., ΓN (2)) ₁ of the second update of the first group. To do.

The first block row processing unit 23-1, the second block row processing unit 24-1, and the third block row processing unit 25-1 of the arithmetic processing unit 11-1 are included in the pseudo log likelihood ratio storage unit 22-1. Pseudo log likelihood ratio (γ1 (0), γ2 (0), ..., γN (0)) ₂ for N columns of the 0th update of the second group 2 The ratio αmn (2) is calculated, and the adder 26-1 calculates the pseudo prior value logarithmic ratio (S1 (1), S2 (1),..., SN) for N columns of the first update of the second group. (1)) ₂ is output to the adder 21-1. The adder 21-1 sends the pseudo prior value logarithmic ratio (S1 (1), S2 (1),..., SN () for the N columns of the first update of the second group sent from the adder 26-1. 1)) ₂ and pseudo log likelihood ratios (γ1 (0), γ2 (0), N columns for the 0th update of the second group stored in the pseudo log likelihood ratio storage unit 22-1 ..., [Gamma] N (0)) ₂ are added and the addition result is sent to the pseudo log likelihood ratio storage unit 22-2 of the arithmetic processing unit 11-2. The pseudo log likelihood ratio storage unit 22-2 displays the addition result as the pseudo log likelihood ratio (γ1 (1), γ2 (1),..., ΓN (1)) ₂ of the first update of the second group _2. Are stored in place of (γ1 (1), γ2 (1),..., ΓN (1)) ₁ .

The S / P converter 8 receives the third group of log likelihood ratios λ1 to λN that are serially input in the first phase, and receives N-bit parallel data (λ1 (2), λ2 (2)). ,..., ΛN (2)) ₃ and sent to the pseudo log likelihood ratio storage unit 22-1 of the arithmetic processing unit 11-1, and the pseudo log likelihood ratio storage unit 22-1 stores the parallel data ( λ1 (2), λ2 (2),..., λN (2)) ₃ is a pseudo log likelihood ratio (γ1 (0), γ2 (0), 3) for N columns of the 0th update of the third group. ..., ΓN (0)) ₃ are stored in place of (γ1 (0), γ2 (0),..., ΓN (0)) ₂ .

In the nth phase, the following processing is performed.
The first block row processing unit 23-n, the second block row processing unit 24-n, and the third block row processing unit 25-n of the arithmetic processing unit 11-n are included in the pseudo log likelihood ratio storage unit 22-n. The pseudo log likelihood ratio (γ1 (n−1), γ2 (n−1),..., ΓN (n−1)) for N columns of the (n−1) th update of the first group is ₁ . Based on this, row processing is performed to calculate the external value logarithmic ratio αmn (n), and the adder 26-n calculates the pseudo prior value logarithmic ratio (S1 (n), N columns of the nth update of the first group). S2 (n),..., SN (n)) ₁ is output to the adder 21-n. The adder 21-n is a pseudo prior value logarithmic ratio (S1 (n), S2 (n),..., SN () for N columns of the nth update of the first group sent from the adder 26-n. n)) ₁ and the pseudo log likelihood ratio (γ1 (n-1) for N columns of the (n-1) th update of the first group stored in the pseudo log likelihood ratio storage unit 22-n. , Γ2 (n-1),..., ΓN (n-1)) ₁ and adding the result to the pseudo log likelihood ratio (γ1 (n), γ2 of the nth update of the first group (n),..., γN (n)) ₁ are output to the decoded word determination unit 16.

The arithmetic processing unit 11-1 to the arithmetic processing unit 11- (n-1) perform the same processing, and simulate the (n + 1-K) th update of the Kth (2 ≦ K ≦ n) group. Log-likelihood ratios γ1 (n + 1-K), γ2 (n + 1-K),..., ΓN (n + 1-K)) _K is calculated by the arithmetic processing unit 11- (n + 2-K). It is stored in the pseudo log likelihood ratio storage unit 22- (n + 2-K).

The S / P converter 8 receives logarithmic likelihood ratios λ1 to λN of the (n + 1) th group serially inputted in the nth phase, and 1 unit of N-bit parallel data (λ1 (n), λ2 ( n),..., λN (n)) _{n + 1} and sent to the pseudo log likelihood ratio storage unit 22-1 of the arithmetic processing unit 11-1, and the pseudo log likelihood ratio storage unit 22-1 , Parallel data (λ1 (n), λ2 (n),..., ΛN (n)) _{n + 1} is a pseudo log likelihood ratio (γ1 (0) for N columns of the 0th phase of the (n + 1) th group. ), Γ2 (0),..., ΓN (0)) _{n + 1} , instead of (γ1 (0), γ2 (0),..., ΓN (0)) _n .

Thereafter, the above process is repeated.
As described above, according to the decoding device of the second embodiment, decoding can be performed at high speed by pipeline processing. Specifically, the update unit operates at 100 MHz and the number of columns N is 1000. It is assumed that the updating unit 7 performs 10 repetitive calculations until the syndrome becomes “0”. When the pipeline processing as in the embodiment of the present invention is not performed, only 100 × 1000/10 = 10 Gbps can be realized, which is not sufficient in the present situation where high speed is required. On the other hand, when pipeline processing is performed as in the embodiment of the present invention, 100 × 1000 = 100 Gbps can be realized, and epoch-making improvement can be achieved in practical use.

ここで、上式（９）および（１０）それぞれにおいて、ｎ′∈Ａ（ｍ）＼ｎおよびｍ′∈Ｂ（ｎ）＼ｍは、自身を除く要素を意味する。外部値対数比αmnについては、ｎ′≠ｎであり、事前値対数比βmnについては、ｍ′≠ｍである。 [Third Embodiment]
The embodiment of the present invention is a decoding device based on the min-sum decoding method.
The update unit according to the embodiment of the present invention performs arithmetic processing according to the following formulas (9), (10), and (11), performs processing (row processing) for each element in the row of the parity check matrix and each element for the column The process (column process) is repeatedly executed.

Here, in each of the above formulas (9) and (10), n′εA (m) \ n and m′εB (n) \ m mean elements other than themselves. For the external value log ratio αmn, n ′ ≠ n, and for the prior value log ratio βmn, m ′ ≠ m.

FIG. 14 is a diagram illustrating the configuration of the updating unit 77 according to the third embodiment.
Referring to FIG. 14, update unit 77 includes an S / P conversion unit 8 and an arithmetic processing unit 51. The arithmetic processing unit 51 includes a row processing unit 50 and a column processing unit 52.

  The row processing unit 50 uses the log likelihood ratio λn sent from the S / P conversion unit 8 and the prior value logarithmic ratio βmn (t) sent from the column processing unit 52 for each step of the iterative calculation. The pseudo log likelihood ratio γmn (t) is updated according to (11), and the external value log ratio αmn (t) is updated according to equation (9).

  The column processing unit 52 uses the external value log ratio αmn (t) given from the row processing unit 50 to update the prior value log ratio βmn (t) according to the equation (10).

  The row processing unit 50 includes a first block row processing unit 53, a second block row processing unit 54, a third block row processing unit 55, and an addition unit 68 arranged corresponding to the first block row processing unit 53. And an adding unit 69 arranged corresponding to the second block row processing unit 54 and an adding unit 70 arranged corresponding to the third block row processing unit 55.

  The first block row processing unit 53 includes a first block pseudo log likelihood ratio storage unit 56 that stores the latest value of the pseudo log likelihood ratio γ for N columns corresponding to the first block of the parity check matrix H; 1 line processing part 57 and 2nd line processing part 58 are included.

  The second block row processing unit 54 includes a second block pseudo log likelihood ratio storage unit 59 that stores the latest value of the pseudo log likelihood ratio γ for N columns corresponding to the second block of the parity check matrix H; A three-row processing unit 60 and a fourth-row processing unit 61 are included.

  The third block row processing unit 55 includes a third block pseudo log likelihood ratio storage unit 62 that stores the latest value of the pseudo log likelihood ratio γ for N columns corresponding to the third block of the parity check matrix H; A 5-line processing unit 63 and a sixth-line processing unit 64 are included.

  The column processing unit 52 includes an adding unit 65 arranged corresponding to the first block row processing unit 53, an adding unit 66 arranged corresponding to the second block row processing unit 54, and a third block row processing unit. And an adder 67 arranged corresponding to 55.

  The adders 65 to 70 each have N adders corresponding to N columns, and each adder performs addition for a corresponding column.

  Next, taking the case where the parity check matrix of FIG. 9 is used as an example, the first block pseudo-log likelihood ratio storage unit 56, the second block pseudo-log likelihood ratio storage unit 59, and the third block pseudo-log likelihood ratio Data stored in the storage unit 62 will be described.

  FIG. 15A shows data stored in the first block pseudo log likelihood ratio storage unit 56 in the 0th phase.

  Referring to FIG. 15 (a), in the 0th phase, the pseudo log likelihood ratio γmn (0) (n = 1, 2,... N) of the 0th phase is output from the S / P converter 8. The log likelihood ratios λn (n = 1, 2,... N) for the N columns are stored. However, m is 1 or 2. For example, since “1” stands in the first column in the first block of the parity check matrix is in the first row, γ1 is in the first column of the first block pseudo log likelihood ratio storage unit 56. , 1 (0) is stored. Also, since “1” stands in the second column in the first block of the parity check matrix is in the second row, γ 2 is in the second column of the first block pseudo log likelihood ratio storage unit 56. , 2 (0) is stored.

  FIG. 15B shows data stored in the second block pseudo log likelihood ratio storage unit 59 in the 0th phase.

  Referring to FIG. 15B, in the 0th phase, the pseudo log likelihood ratio γmn (0) (n = 1, 2,... N) of the 0th phase is output from the S / P conversion unit 8. The log likelihood ratios λn (n = 1, 2,... N) for the N columns are stored. However, m is 3 or 4. For example, since “1” stands in the first column in the second block of the parity check matrix is in the fourth row, γ 4 is in the first column of the second block pseudo log likelihood ratio storage unit 59. , 1 (0) is stored. Also, since “1” stands in the second column in the second block of the parity check matrix is in the fourth row, γ 4 is in the second column of the second block pseudo log likelihood ratio storage unit 59. , 2 (0) is stored.

  FIG. 15C is a diagram illustrating data stored in the third block pseudo log likelihood ratio storage unit 62 in the 0th phase.

  Referring to FIG. 15C, in the 0th phase, the pseudo log likelihood ratio γmn (0) (n = 1, 2,... N) of the 0th phase is output from the S / P conversion unit 8. The log likelihood ratios λn (n = 1, 2,... N) for the N columns are stored. However, m is 5 or 6. For example, since “1” stands in the first column in the third block of the parity check matrix is in the sixth row, γ6 is in the first column of the third block pseudo log likelihood ratio storage unit 62. , 1 (0) is stored. In the third block of the parity check matrix, “1” stands in the second column in the fifth row, so that the second column of the third block pseudo log likelihood ratio storage unit 62 has γ 5 , 2 (0) is stored.

  FIG. 16A illustrates data stored in the first block pseudo log likelihood ratio storage unit 56 in the first phase.

  Referring to FIG. 16A, in the first phase, the pseudo log likelihood of the 0th phase is set as the pseudo log likelihood ratio γmn (1) (n = 1, 2,..., N) of the first phase. The sum of the ratio γmn (0) and the prior value logarithmic ratio βmn (1) of the first phase is stored. However, m is 1 or 2.

  FIG. 16B is a diagram illustrating data stored in the second block pseudo log likelihood ratio storage unit 59 in the first phase.

  Referring to FIG. 16 (b), in the first phase, the pseudo log likelihood of the 0th phase is set as the pseudo log likelihood ratio γmn (1) (n = 1, 2,..., N) of the first phase. The sum of the ratio γmn (0) and the prior value logarithmic ratio βmn (1) of the first phase is stored. However, m is 3 or 4.

  FIG. 16C shows data stored in the third block pseudo log likelihood ratio storage unit 62 in the first phase.

  Referring to FIG. 16C, in the first phase, the pseudo log likelihood of the 0th phase is set as the pseudo log likelihood ratio γmn (1) (n = 1, 2,..., N) of the first phase. The sum of the ratio γmn (0) and the prior value logarithmic ratio βmn (1) of the first phase is stored. However, m is 5 or 6.

  FIG. 17A is a diagram illustrating data stored in the first block pseudo log likelihood ratio storage unit 56 in the second phase.

  Referring to FIG. 17A, in the second phase, the pseudo log likelihood of the first phase is set as the pseudo log likelihood ratio γmn (2) (n = 1, 2,... N) of the second phase. The sum of the ratio γmn (1) and the prior value logarithmic ratio βmn (2) of the second phase is stored. However, m is 1 or 2.

  FIG. 17B is a diagram illustrating data stored in the second block pseudo log likelihood ratio storage unit 59 in the second phase.

  Referring to FIG. 17B, in the second phase, the pseudo log likelihood of the first phase is set as the pseudo log likelihood ratio γmn (2) (n = 1, 2,..., N) of the second phase. The sum of the ratio γmn (1) and the prior value logarithmic ratio βmn (2) of the second phase is stored. However, m is 3 or 4.

  FIG. 17C illustrates data stored in the third block pseudo log likelihood ratio storage unit 62 in the second phase.

  Referring to FIG. 17C, in the second phase, the pseudo log likelihood of the first phase is set as the pseudo log likelihood ratio γmn (2) (n = 1, 2,..., N) of the second phase. The sum of the ratio γmn (1) and the prior value logarithmic ratio βmn (2) of the second phase is stored. However, m is 5 or 6.

(Concrete example)
Next, a specific operation of the updating unit 77 when the parity check matrix of FIG. 9 is used will be described.

  In the 0th phase, the S / P converter 8 receives the log-likelihood ratios λ1 to λN that are serially input, and N units of parallel data (λ1 (0), λ2 (0),. ... ΛN (0)), the first block pseudo log likelihood ratio storage unit 56, the second block pseudo log likelihood ratio storage unit 59, and the third block pseudo log likelihood ratio of the arithmetic processing unit 51 The data is sent to the storage unit 62.

  The first block pseudo log likelihood ratio storage unit 56 converts the parallel data (λ1 (0), λ2 (0),..., ΛN (0)) into the pseudo log likelihood ratio (γm1 (0)) of the 0th phase. , Γm2 (0),..., ΓmN (0)). However, m is 0 or 1.

  The second block pseudo log likelihood ratio storage unit 59 converts the parallel data (λ1 (0), λ2 (0),..., ΛN (0)) into the pseudo log likelihood ratio (γm1 (0)) of the 0th phase. , Γm2 (0),..., ΓmN (0)). However, m is 3 or 4.

  The third block pseudo log likelihood ratio storage unit 62 converts the parallel data (λ1 (0), λ2 (0),..., ΛN (0)) into the pseudo log likelihood ratio (γm1 (0)) of the 0th phase. , Γm2 (0),..., ΓmN (0)). However, m is 5 or 6.

  In the first phase, the following processing of the first block row processing unit 53, the second block row processing unit 54, and the third block row processing unit 55 is performed in parallel.

  The first row processing unit 57 includes the first column, the third column, and the fourth column that are columns in which “1” in the first row of the parity check matrix is set from the first block pseudo log likelihood ratio storage unit 56. Pseudo log likelihood ratios γ1,1 (0) (= λ1), γ1,3 (0) (= λ3), γ1,4 (0) in the fifth, tenth and twelfth columns (= Λ4), γ1,5 (0) (= λ5), γ1,10 (0) (= λ10), and γ1,12 (0) (= λ12) are read.

  The first row processing unit 57 calculates a set {γ1,3 (0), γ1,1 excluding the elements in the first column among the read elements in order to calculate the external value log ratio for the first column. 4 (0), γ1,5 (0), γ1,10 (0), γ1,12 (0)} are specified. The first row processing unit 57 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The first row processing unit 57 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value log ratio α1,1 (1). In the same manner as described above, the first row processing unit 28 uses the external value logarithmic ratio α1,3 (1) for the third column, the fourth column, the fifth column, the tenth column, and the twelfth column. , Α1,4 (1), α1,5 (1), α1,10 (1), α1,12 (1) are output.

  The second row processing 58 includes the second column, the sixth column, and the seventh column that are columns in which “1” in the second row of the parity check matrix is set from the first block pseudo log likelihood ratio storage unit 56. , Pseudo log likelihood ratios γ2, 2 (0) (= λ2), γ2, 6 (0) (= λ6), γ2, 7 (0) (in the 8th, 9th and 11th columns) = Λ7), γ2,8 (0) (= λ8), γ2,9 (0) (= λ9), and γ2,11 (0) (= λ11) are read.

  In order to calculate the external value log ratio for the second column, the second row processing unit 58 sets {γ2,6 (0), γ2, 7 (0), γ2,8 (0), γ2,9 (0), γ2,11 (0)} are specified. The second row processing unit 58 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The second row processing unit 58 adds the sign of the product of the specified element to the minimum value of the absolute value of the specified element, and outputs the external value logarithmic ratio α2,2 (1). In the same manner as described above, the second row processing unit 58 performs the external value logarithmic ratio α2,6 (1) for the sixth column, the seventh column, the eighth column, the ninth column, and the eleventh column. , Α2,7 (1), α2,8 (1), α2,9 (1), α2,11 (1) are output.

  The third row processing unit 60, the third column, the fifth column, and the sixth column, which are columns in which “1” in the third row of the parity check matrix stands from the second block pseudo log likelihood ratio storage unit 59 , Seventh column, eleventh column and twelfth column pseudo log likelihood ratios γ3,3 (0) (= λ3), γ3,5 (0) (= λ5), γ3,6 (0) (= Λ6), γ3,7 (0) (= λ7), γ3,11 (0) (= λ11), and γ2,12 (0) (= λ12) are read.

  The third row processing unit 60 calculates a set {γ3,5 (0), γ3,... Excluding the elements in the third column among the read elements in order to calculate the external value log ratio for the third column. 6 (0), γ3, 7 (0), γ3, 11 (0), γ3, 12 (0)} are specified. The third row processing unit 60 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The third row processing unit 60 appends the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value logarithmic ratio α3,3 (1). In the same manner as described above, the third row processing unit 60 performs the external value logarithmic ratio α3,5 (1) for the fifth, sixth, seventh, eleventh and twelfth columns. , Α3,6 (1), α3,7 (1), α3,11 (1), α3,12 (1) are output.

  The fourth row processing unit 61 includes the first column, the second column, and the fourth column that are columns in which “1” in the fourth row of the parity check matrix is set from the second block pseudo log likelihood ratio storage unit 59. Pseudo log likelihood ratios γ4,1 (0) (= λ1), γ4,2 (0) (= λ2), and γ4,4 (0) in the 8th, 8th, 9th and 10th columns (= Λ4), γ4,8 (0) (= λ8), γ4,9 (0) (= λ9), and γ4,10 (0) (= λ10) are read.

  The fourth row processing unit 61 calculates a set {γ2 (0), γ4 (0) excluding the elements in the first column among the read elements in order to calculate the external value log ratio for the first column. , Γ8 (0), γ9 (0), γ10 (0)}. The fourth row processing unit 61 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The fourth row processing unit 61 adds the sign of the product of the identified element to the minimum absolute value of the identified element, and outputs the external value log ratio α4,1 (1). In the same manner as described above, the fourth row processing unit 30 performs the external value logarithmic ratio α4,2 (1) for the second column, the fourth column, the eighth column, the ninth column, and the tenth column. , Α4,4 (1), α4,8 (1), α4,9 (1), α4,10 (1) are output.

  The fifth row processing unit 63 includes the second column, the third column, and the sixth column that are columns in which “1” in the fifth row of the parity check matrix is set from the third block pseudo log likelihood ratio storage unit 62. Pseudo log likelihood ratios γ5,2 (0) (= λ2), γ5,3 (0) (= λ3), γ5,6 (0) in the 8th, 8th, 10th and 12th columns (= Λ6), γ5,8 (0) (= λ8), γ5,10 (0) (= λ10), and γ5,12 (0) (= λ12) are read.

  In order to calculate the external value log ratio for the second column, the fifth row processing unit 63 sets {γ5,3 (0), γ5, 6 (0), γ5,8 (0), γ5,10 (0), γ5,12 (0)} are specified. The fifth row processing unit 63 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The fifth row processing unit 63 adds the sign of the product of the specified element to the minimum absolute value of the specified element, and outputs the external value logarithmic ratio α5,2 (1). In the same manner as described above, the fifth row processing unit 63 sets the external value log ratio α5,3 (0) for the third column, the sixth column, the eighth column, the tenth column, and the twelfth column. , Α5,6 (0), α5,8 (0), α5,10 (0), α5,12 (0) are output.

  The sixth row processing unit 64 includes the first column, the fourth column, and the fifth column that are columns in which “1” in the sixth row of the parity check matrix is set from the third block pseudo log likelihood ratio storage unit 62. Pseudo log likelihood ratios γ6,1 (0) (= λ1), γ6,4 (0) (= λ4), γ6,5 (0) in the first, seventh, ninth and eleventh columns (= Λ5), γ6,7 (0) (= λ7), γ6,9 (0) (= λ9), and γ6,11 (0) (= λ11) are read.

  In order to calculate the external value log ratio for the first column, the sixth row processing unit 64 sets {γ6,4 (0), γ6, 5 (0), γ6,7 (0), γ6,9 (0), γ6,11 (0)} are specified. The sixth row processing unit 64 specifies the minimum value of the absolute values of the elements included in this set, and specifies the product of the codes of the elements included in this set. The sixth row processing unit 64 adds the sign of the product of the identified element to the minimum value of the absolute value of the identified element, and outputs the external value log ratio α6,1 (1). In the same manner as described above, the sixth row processing unit 64 performs external value logarithmic ratio α6,4 (1) for the fourth column, the fifth column, the seventh column, the ninth column, and the eleventh column. , Α6,5 (1), α6,7 (1), α6,9 (1), α6,11 (1) are output.

  The addition unit 65 receives the external value logarithmic ratio α4,1 (1) from the second block row processing unit 54 and the external value logarithmic ratio α6,1 (1) from the third block row processing unit 55 for the first column. Then, they are added together, and the prior value logarithmic ratio β1,1 (1) (= α4,1 (1) + α6,1 (1)), which is the addition result, is output to the adding unit 68. Similarly to the above, the adding unit 65 outputs the prior value log ratios βm2 (1) to βm12 (1) for the second column to the twelfth column to the adding unit 68. However, m is 1 or 2.

  The adding unit 66 receives the external value log ratio α1,1 (1) from the first block row processing unit 53 and receives the external value logarithmic ratio α6,1 (1) from the third block row processing unit 55 for the first column. Then, they are added together, and the prior value logarithmic ratio β4,1 (1) (α1,1 (1) + α6,1 (1)), which is the addition result, is output to the adder 69. The adding unit 66 outputs the prior value log ratios βm2 (1) to βm12 (1) for the second column to the twelfth column to the adding unit 69 in the same manner as described above. However, m is 3 or 4.

  The adder 67 receives the external value logarithmic ratio α1,1 (1) from the first block row processing unit 53 and receives the external value logarithmic ratio α6,1 (1) from the third block row processing unit 55 for the first column. Then, they are added together, and the prior value logarithmic ratio β6,1 (1) (= α1,1 (1) + α4,1 (1)), which is the addition result, is output to the adding unit 70. The adding unit 70 outputs the prior value log ratios βm2 (1) to βm12 (1) for the second column to the twelfth column to the adding unit 70 in the same manner as described above. However, m is 5 or 6.

  For the first column, the adding unit 68 has a prior value log ratio β1,1 (1) sent from the adding unit 65 and a pseudo log likelihood ratio stored in the first block pseudo log likelihood ratio storage unit 56. γ1,1 (0) is added, and the pseudo log likelihood ratio γ1,1 (1), which is the addition result, is added to the pseudo log likelihood ratio γ1,1 in the first block pseudo log likelihood ratio storage unit 56. Update (ie, overwrite) (0). Similarly to the above, the adding unit 68 calculates pseudo log likelihood ratios γm2 (1) to γm12 (1) (where m is 1 or 2) for the second column to the twelfth column. Then, the pseudo log likelihood ratios γm2 (0) to γm12 (0) in the first block pseudo log likelihood ratio storage unit 56 are updated with the pseudo log likelihood ratios γm2 (1) to γm12 (1) (that is, overwriting). To do).

  For the first column, the adding unit 69 sends the prior value logarithmic ratio β4,1 (1) sent from the adding unit 66 and the pseudo log likelihood ratio stored in the second block pseudo log likelihood ratio storage unit 59. γ4,1 (0) is added and a pseudo log likelihood ratio γ4,1 (2) in the second block pseudo log likelihood ratio storage unit 59 is obtained with the pseudo log likelihood ratio γ4,1 (1) as the addition result. Update (ie, overwrite) (0). Similarly to the above, the adding unit 69 calculates pseudo log likelihood ratios γm2 (1) to γm12 (1) (where m is 3 or 4) for the second column to the twelfth column. The pseudo log likelihood ratios γm2 (0) to γm12 (0) in the second block pseudo log likelihood ratio storage unit 59 are updated with the pseudo log likelihood ratios γm2 (1) to γm12 (1) (that is, overwriting). To do).

  For the first column, the adding unit 70, the prior value logarithmic ratio β6,1 (1) sent from the adding unit 67, and the pseudo log likelihood ratio stored in the third block pseudo log likelihood ratio storage unit 62 γ6,1 (0) is added, and the pseudo log likelihood ratio γ6,1 (1) in the third block pseudo log likelihood ratio storage unit 62 is obtained as a pseudo log likelihood ratio γ6,1 (1) as the addition result. Update (ie, overwrite) (0). The adder 70 calculates pseudo log likelihood ratios γm2 (1) to γm12 (1) (where m is 5 or 6) for the second column to the twelfth column in the same manner as described above. The pseudo log likelihood ratios γm2 (0) to γm12 (0) in the third block pseudo log likelihood ratio storage unit 62 are updated with the pseudo log likelihood ratios γm2 (1) to γm12 (1) (that is, overwriting). To do).

  In the second phase, the following processes of the first block row processing unit 53, the second block row processing unit 54, and the third block row processing unit 55 are performed in parallel.

  The first row processing unit 57 receives the pseudo log likelihood ratios γ1,1 (1), γ1,3 (1), γ1,4 (1), γ1,5 (from the first block pseudo log likelihood ratio storage unit 56. 1) Read out γ1,10 (1) and γ1,12 (1). Similarly to the first phase, the first row processing unit 57 performs external value logarithmic ratios α1,1 (2), α1,3 (2), α1,4 (2), α1,5 (2), α1, 10 (2) and α1,12 (2) are output.

  The second row processing unit 58 stores the pseudo log likelihood ratios γ2,2 (1), γ2,6 (1), γ2,7 (1), γ2,8 (from the first block pseudo log likelihood ratio storage unit 56. 1), γ2,9 (1), γ2,11 (1) are read. Similarly to the first phase, the second row processing unit 58 performs external value logarithmic ratios α2,2 (2), α2,6 (2), α2,7 (2), α2,8 (2), α2, 9 (2) and α2,11 (2) are output.

  The third row processing unit 60 receives the pseudo log likelihood ratios γ3,3 (1), γ3,5 (1), γ3,6 (1), γ3,7 (from the second block pseudo log likelihood ratio storage unit 59. 1), γ3,11 (1) and γ3,12 (1) are read. The third row processing unit 60 performs the external value logarithmic ratios α3,3 (2), α3,5 (2), α3,6 (2), α3,7 (2), α3 in the same manner as in the first phase. , 11 (2) and α3,12 (2) are output.

  The fourth row processing unit 61 receives pseudo log likelihood ratios γ4,1 (1), γ4,2 (1), γ4,4 (1), γ4,8 (from the second block pseudo log likelihood ratio storage unit 59. 1), γ4,9 (1) and γ4,10 (1) are read. The fourth row processing unit 61 performs the external value logarithmic ratios α4,1 (2), α4,2 (2), α4,4 (2), α4,8 (2), α4, 9 (2) and α4,10 (2) are output.

  The fifth row processing unit 63 stores the pseudo log likelihood ratios γ5,2 (1), γ5,3 (1), γ5,6 (1), γ5,8 (from the third block pseudo log likelihood ratio storage unit 62. 1), γ5, 10 (1) and γ5, 12 (1) are read. Similarly to the first phase, the fifth row processing unit 63 performs external value logarithmic ratios α5,2 (2), α5,3 (2), α5,6 (2), α5,8 (2), α5, 10 (2) and α5,12 (2) are output.

  The sixth row processing unit 64 receives the pseudo log likelihood ratios γ6,1 (1), γ6,4 (1), γ6,5 (1), γ6,7 (from the third block pseudo log likelihood ratio storage unit 62. 1), γ6,9 (1) and γ6,11 (1) are read. The sixth row processing unit 64 performs the external value logarithmic ratios α6,1 (2), α6,4 (2), α6,5 (2), α6,7 (2), α6, as in the first phase. 9 (2) and α6,11 (2) are output.

  The adding unit 65 is the same as in the first phase. For the first column, the external value logarithmic ratio α4,1 (2) is received from the second block row processing unit 54, and the external value logarithmic ratio α6,1 (2) is received from the third block row processing unit 55. And the prior value logarithmic ratio β1,1 (2) (= α4,1 (2) + α6,1 (2)) as an addition result is output to the adding unit 68. In the same manner as described above, the adding unit 65 outputs the prior value log ratios βm2 (2) to βm12 (2) for the second column to the twelfth column to the adding unit 68. However, m is 1 or 2.

  In the same manner as in the first phase, the adding unit 66 receives the external value logarithmic ratio α1,1 (2) from the first block row processing unit 53 and receives the external value from the third block row processing unit 55 for the first column. The logarithmic ratio α6,1 (2) is received and added, and the prior value logarithmic ratio β4,1 (2) (α1,1 (2) + α6,1 (2)), which is the addition result, is added to the adding unit 69. Output. The adder 66 outputs the prior value log ratios βm2 (2) to βm12 (2) for the second column to the twelfth column to the adder 69 in the same manner as described above. However, m is 3 or 4.

  The adder 67 receives the external value logarithmic ratio α1,1 (2) from the first block row processing unit 53 and receives the external value from the third block row processing unit 55 in the same manner as in the first phase. The logarithmic ratio α6,1 (2) is received, added, and the prior value logarithmic ratio β6,1 (2) (= α1,1 (2) + α4,1 (2)), which is the addition result, is added to the adding unit 70 Output to. In the same manner as described above, the adding unit 70 outputs the prior value log ratios βm2 (2) to βm12 (2) for the second column to the twelfth column to the adding unit 70. However, m is 5 or 6.

  Similar to the first phase, the adding unit 68 stores the prior value log ratio β1,1 (2) sent from the adding unit 65 and the first block pseudo log likelihood ratio storage unit 56 for the first column. Is added to the pseudo log likelihood ratio γ1,1 (1), and the pseudo log likelihood ratio γ1,1 (2) as the addition result is stored in the first block pseudo log likelihood ratio storage unit 56. Update (ie, overwrite) the pseudo-log likelihood ratio γ1,1 (1). Similarly to the above, the adding unit 68 calculates pseudo log likelihood ratios γm2 (2) to γm12 (2) (where m is 1 or 2) for the second column to the twelfth column. Then, the pseudo log likelihood ratios γm2 (1) to γm12 (1) in the first block pseudo log likelihood ratio storage unit 56 are updated with the pseudo log likelihood ratios γm2 (2) to γm12 (2) (that is, overwriting). To do).

  Similar to the first phase, the adding unit 69 stores the prior value log ratio β4,1 (2) sent from the adding unit 66 and the second block pseudo log likelihood ratio storage unit 59 for the first column. Is added to the pseudo log likelihood ratio γ4,1 (1), and the pseudo log likelihood ratio γ4,1 (2), which is the addition result, is stored in the second block pseudo log likelihood ratio storage unit 59. The pseudo log likelihood ratio γ4,1 (1) is updated (that is, overwritten). Similarly to the above, the adding unit 69 calculates pseudo log likelihood ratios γm2 (2) to γm12 (2) (where m is 3 or 4) for the second column to the twelfth column. , Update the pseudo log likelihood ratios γm2 (1) to γm12 (1) in the second block pseudo log likelihood ratio storage unit 59 with the pseudo log likelihood ratios γm2 (2) to γm12 (2) (that is, overwrite) To do).

Similarly to the first phase, the adding unit 70 stores the prior value logarithmic ratio β6,1 (2) sent from the adding unit 67 and the third block pseudo log likelihood ratio storage unit 62 for the first column. Is added to the pseudo log likelihood ratio γ6,1 (1), and the pseudo log likelihood ratio γ6,1 (2), which is the addition result, is stored in the third block pseudo log likelihood ratio storage unit 62. The pseudo log likelihood ratio γ6,1 (1) is updated (that is, overwritten). Similarly to the above, the adding unit 70 calculates pseudo log likelihood ratios γm2 (2) to γm12 (2) (where m is 5 or 6) for the second column to the twelfth column. Then, the pseudo log likelihood ratios γm2 (1) to γm12 (1) in the third block pseudo log likelihood ratio storage unit 62 are updated with the pseudo log likelihood ratios γm2 (2) to γm12 (2) (that is, overwriting). To do).
Similar processing is repeated for the third and subsequent phases.

Also, the decoded word generation unit of the embodiment of the present invention receives the pseudo log likelihood ratio γmn (t) from the first block row processing unit 53, the second block row processing unit 54, and the third block row processing unit 55. Then, according to the pseudo log likelihood ratio γmn (t) of one block row processing unit, according to the following equation (12), the primary estimated words (C1 (t), C2 (t),..., CN ( t)) is calculated, and based on this, a decoded word is generated in the same manner as in the first embodiment.

  As described above, in the decoding device according to the third embodiment, the first block pseudo log likelihood ratio storage unit 56 that stores the pseudo log likelihood ratio γmn (t) for N columns, the second block pseudo log likelihood Only the ratio storage unit 59 and the third block pseudo log likelihood ratio storage unit 62 need be provided, and the storage unit for storing the prior value log ratio βmn (t) for N columns is not necessary. Can be reduced.

[Modification 1 of the third embodiment]
Also in the embodiment of the present invention, as in Modification 1 of the first embodiment, the two adders may be combined into one as shown below.

  The adding unit 65 and the adding unit 68 may be combined into one adding unit. That is, one adder unit outputs the t-phase two external value logarithmic ratios αmn (t) output from the second block row processing unit 54 and the third block row processing unit 55 and the first block pseudo logarithm. The pseudo-log likelihood ratio γmn (t−1) of the (t−1) phase stored in the likelihood ratio storage unit 56 is added, and the pseudo prior value log ratio γmn of the t-th phase, which is the addition result, is added. At (t), the (t−1) -phase pseudo log likelihood ratio γmn (t) stored in the first block pseudo log likelihood ratio storage unit 56 is updated. However, m is 1 or 2.

  Similarly, the adding unit 66 and the adding unit 69 may be combined into one adding unit. That is, one adder is configured to output two external value logarithmic ratios αmn (t) of the t-th phase output from the first block row processing unit 53 and the third block row processing unit 55 and the second block pseudo logarithm. The pseudo log likelihood ratio γmn (t−1) of the (t−1) phase stored in the likelihood ratio storage unit 59 is added, and the pseudo prior value log ratio γmn of the t th phase, which is the addition result, is added. At (t), the (t−1) -phase pseudo log likelihood ratio γmn (t) stored in the second block pseudo log likelihood ratio storage unit 59 is updated. However, m is 3 or 4.

  Similarly, the adding unit 67 and the adding unit 70 may be combined into one adding unit. That is, one adder is configured to output two external value logarithmic ratios αmn (t) of the t-th phase output from the second block row processing unit 54 and the third block row processing unit 55 and the third block pseudo logarithm. The pseudo-log likelihood ratio γmn (t−1) of the (t−1) phase stored in the likelihood ratio storage unit 62 is added, and the pseudo prior value log ratio γmn of the t-th phase, which is the addition result, is added. At (t), the (t−1) -phase pseudo log likelihood ratio γmn (t) stored in the third block pseudo log likelihood ratio storage unit 62 is updated. However, m is 5 or 6.

[Modification 2 of the third embodiment]
Also in the embodiment of the present invention, as in the second embodiment, the updating unit may include an S / P conversion unit and n arithmetic processing units connected in cascade.

  In this case, the adder corresponding to the first block in the row processing unit of the first to (n-1) th arithmetic processing units stores the addition result in the first block pseudo log likelihood ratio storage unit in the next stage. The adder corresponding to the second block outputs the addition result to the second block pseudo log likelihood ratio storage unit in the next stage, and the adder corresponding to the third block outputs the addition result to the second block in the next stage. Output to the 3-block pseudo log likelihood ratio storage unit.

  Then, the S / P converter is provided in the first block pseudo log likelihood ratio storage unit, the second block pseudo log likelihood ratio storage unit, and the third block pseudo log likelihood ratio storage unit in the first stage arithmetic processing unit. The log likelihood ratio is output as an initial value.

  Also, the three adders in the row processing unit of the nth stage arithmetic processing unit output the pseudo log likelihood ratios for N columns, which are the respective addition results, to the decoded word generation unit.

(Modifications throughout)
The present invention is not limited to the above-described embodiment, and includes, for example, the following modifications.

(1) Sum-product decoding method etc. In the embodiment of the present invention, the case based on the min-sum decoding method and the UMP-APP decoding method has been described as an example, but even when the sum-product decoding method or the like is used. Only the contents of the row processing of the first to sixth row processing units in FIG. 14 are changed, and the processing described in the embodiment of the present invention can be performed.

(2) Minimum Value Detection Method Various methods can be used as a method for obtaining the minimum value excluding itself in each row processing unit of the embodiment of the present invention. In particular, the frequency distribution sorting is performed by an improved method. Good. In this method, each element included in a target set is converted according to a first rule to generate first conversion data, and a logical operation in units of bits of the plurality of converted first conversion data is performed. This is a method of generating the second conversion data representing the minimum value or the approximate value of the minimum value by converting the result of the operation according to the second rule.

  According to this method, the minimum value or its approximate value can be detected at high speed by a logical operation in units of bits. Further, according to this method, it is not necessary to store a work variable for detecting the minimum value, and only the pseudo log likelihood ratio needs to be stored, so that the memory capacity can be further reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows an example of a structure of the communication system using the decoding apparatus according to embodiment of this invention. It is a figure which lists and shows the correspondence of the output data of the modulator 2 and the demodulator 4 when the communication path 3 is an optical fiber. It is a figure which shows schematically the structure of the decoder 5 according to embodiment of this invention. 7 is a diagram illustrating an example of a parity check matrix H. FIG. It is a figure for demonstrating the production | generation method of the parity check matrix whose column weight is X. FIG. 3 is a diagram illustrating a schematic configuration of an update unit 7. FIG. 3 is a diagram illustrating a detailed configuration of an update unit 7. FIG. (A) is a figure showing the data memorize | stored in the pseudo log likelihood ratio memory | storage part 22 in the 0th phase. (B) is a figure showing the data memorize | stored in the pseudo log likelihood ratio memory | storage part 22 in a 1st phase. (C) is a figure showing the data memorize | stored in the pseudo log likelihood ratio memory | storage part 22 in a 2nd phase. It is a figure showing the example of a parity check matrix. It is a figure showing the detailed structure of the update part 37 of the conventional decoding apparatus. FIG. 4 is a diagram illustrating data stored in a log likelihood ratio storage unit 33. (A) is a figure showing the data memorize | stored in the pseudo prior value logarithm ratio memory | storage part 35 in a 0th phase. (B) is a figure showing the data memorize | stored in the pseudo prior value logarithm ratio memory | storage part 35 in a 1st phase. It is a figure showing the update part 17 of 2nd Embodiment. It is a figure showing the structure of the update part 77 of 3rd Embodiment. (A) is a figure showing the data memorize | stored in the 1st block pseudo log likelihood ratio memory | storage part 56 in a 0th phase. (B) is a figure showing the data memorize | stored in the 2nd block pseudo log likelihood ratio memory | storage part 59 in a 0th phase. (C) is a figure showing the data memorize | stored in the 3rd block pseudo log likelihood ratio memory | storage part 62 in a 0th phase. (A) is a figure showing the data memorize | stored in the 1st block pseudo log likelihood ratio memory | storage part 56 in a 1st phase. (B) is a figure showing the data memorize | stored in the 2nd block pseudo log likelihood ratio memory | storage part 59 in a 1st phase. (C) is a figure showing the data memorize | stored in the 3rd block pseudo log likelihood ratio memory | storage part 62 in a 1st phase. (A) is a figure showing the data memorize | stored in the 1st block pseudo log likelihood ratio memory | storage part 56 in a 2nd phase. (B) is a figure showing the data memorize | stored in the 2nd block pseudo log likelihood ratio memory | storage part 59 in a 2nd phase. (C) is a figure showing the data memorize | stored in the 3rd block pseudo log likelihood ratio memory | storage part 62 in a 2nd phase.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Encoder, 2 Modulator, 3 Communication path, 4 Demodulator, 4a Demodulator circuit, 4b Analog / digital modulation circuit, 5 Decoder, 6 Log likelihood ratio calculation part, 7, 17, 37, 77 Update part , 8 S / P converter, 10, 30, 50 line processor, 11, 11-1, 11-2, 11-n, 31, 51 arithmetic processor, 12, 32, 52 column processor, 21, 21 -1,21-2, 21-n, 34, 65, 66, 67, 68, 69 adder, 22, 22-1, 22-2, 22-n pseudo log likelihood ratio storage unit, 23, 23- 1, 23-2, 23-n, 53 First block row processing unit, 24, 24-1, 24-2, 24-n, 54 Second block row processing unit, 25, 25-1, 25-2, 25-n, 55 third block row processing unit, 26, 26-1, 26-2, 26-n addition unit, 27 57 1st line processing part, 28, 58 2nd line processing part, 29, 60 3rd line processing part, 30, 61 4th line processing part, 31, 63 5th line processing part, 32, 64 6th line process , 16 decoded word generation unit, 33 log likelihood ratio storage unit, 35 pseudo prior value log ratio storage unit, 56 first block pseudo log likelihood ratio storage unit, 59 second block pseudo log likelihood ratio storage unit, 62 A third block pseudo log likelihood ratio storage unit.

Claims (7)

A decoding device that performs decoding in a predetermined number of units using a parity check matrix,
A row processing unit that performs row processing using elements in the row direction of the parity check matrix using a pseudo log likelihood ratio and updates the external value log ratio,
A column processing unit that performs column processing using elements in the column direction of the parity check matrix based on the external value log ratio and updates the pseudo prior value log ratio;
The row processing unit includes a storage unit that stores the pseudo log likelihood ratio,
The row processing unit performs the row processing using a pseudo log likelihood ratio in the storage unit,
The row processing unit adds the pseudo prior value log ratio updated by the column processing unit and the pseudo log likelihood ratio stored in the storage unit, and the pseudo log likelihood in the storage unit is obtained by the addition result. A decoding device that updates the degree ratio. A decoding device that decodes input data in N units using a low-density parity check matrix of M rows and N columns,
A storage unit for storing pseudo log likelihood ratios for N columns;
Each performs row processing of N input signals, which is one unit, using a pseudo log likelihood ratio for N columns in the storage unit based on a corresponding block included in the parity check matrix. A plurality of block row processing units for updating an external value logarithmic ratio of N columns for the corresponding block;
A first addition unit that adds the external value logarithmic ratio for N columns output from each of the plurality of block row processing units to update the pseudo prior value logarithmic ratio for N columns;
The updated pseudo prior value logarithmic ratio for N columns and the pseudo log likelihood ratio for N columns stored in the storage unit are added, and the pseudo result for N columns in the storage unit is added as a result of the addition. A decoding apparatus comprising: a second adding unit that updates a log likelihood ratio.   The decoding device according to claim 2, wherein the storage unit stores, as an initial value, a log likelihood ratio of the N input signals that are one unit. A decoding device that decodes input data in N units using a low-density parity check matrix of M rows and N columns,
A storage unit for storing pseudo log likelihood ratios for N columns;
Each performs row processing of N input signals, which is one unit, using a pseudo log likelihood ratio for N columns in the storage unit based on a corresponding block included in the parity check matrix. A plurality of block row processing units for updating an external value logarithmic ratio of N columns for the corresponding block;
The external value logarithmic ratio for N columns respectively output from the plurality of block row processing units and the pseudo log likelihood ratio for N columns stored in the storage unit are added, and the result of addition is stored in the storage unit. And an adder that updates a pseudo log likelihood ratio for N columns of the decoding apparatus. A decoding device that decodes input data in N units using a low-density parity check matrix of M rows and N columns,
It has a plurality of arithmetic processing units connected in cascade,
Each arithmetic processing unit
A storage unit for storing pseudo log likelihood ratios for N columns;
Each performs row processing of N input signals, which is one unit, based on the pseudo log likelihood ratio for N columns in the storage unit, based on the corresponding block included in the parity check matrix. A plurality of block row processing units for updating an external value logarithmic ratio of N columns for the corresponding block;
A first addition unit that adds the external value logarithmic ratio for N columns output from each of the plurality of block row processing units to update the pseudo prior value logarithmic ratio for N columns;
A second adding unit that adds the updated pseudo prior value log ratio for N columns and the pseudo log likelihood ratio for N columns stored in the storage unit;
The second adding unit is a decoding device that updates a pseudo log likelihood ratio for N columns in the storage unit included in the calculation processing unit in the next stage, based on the addition result.   6. The decoding device according to claim 5, wherein the storage unit of the first stage arithmetic processing unit stores a log likelihood ratio of N input signals as the unit as an initial value. A decoding device that performs decoding in a predetermined number of units using a parity check matrix,
A row processing unit that performs row processing using elements in the row direction of the parity check matrix using a pseudo log likelihood ratio and updates the external value log ratio,
A column processing unit that performs column processing using elements in the column direction of the parity check matrix based on the external value log ratio and updates the prior value log ratio;
The row processing unit includes a storage unit that stores the pseudo log likelihood ratio,
The row processing unit performs the row processing using a pseudo log likelihood ratio in the storage unit,
The row processing unit adds the prior value logarithmic ratio updated by the column processing unit and the pseudo log likelihood ratio stored in the storage unit, and the pseudo log likelihood in the storage unit is obtained as a result of the addition. A decoding device that updates the ratio.

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