JP4806649B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a multi-chip module including a plurality of semiconductor chips.

In recent years, higher density and smaller size have been required for semiconductor devices. As a semiconductor device for satisfying such a requirement, there are a multi-chip module (MCM, see Patent Document 1) and a chip scale package (CSP, see Patent Document 2).
FIG. 8 is a schematic cross-sectional view showing the structure of a conventional semiconductor device having a multichip module structure.

  The semiconductor device 81 includes a wiring substrate 82, a semiconductor chip 83 stacked on the wiring substrate 82, and a semiconductor chip 84 stacked on the semiconductor chip 83. Functional elements 83a and 84a are formed on the respective one surfaces of the semiconductor chips 83 and 84, respectively. The semiconductor chip 83 is bonded onto the wiring substrate 82 in a so-called face-up state in which the surface on which the functional element 83 a is formed is directed to the side opposite to the wiring substrate 82. On this semiconductor chip 83, the semiconductor chip 84 is bonded in a face-up posture with the functional element 84 a facing away from the semiconductor chip 83. An interlayer sealing material 86 is interposed between the semiconductor chips 83 and 84.

  The semiconductor chip 83 is larger than the semiconductor chip 84 when viewed from the direction perpendicular to the surface on which the functional elements 83a and 84a are formed, and the semiconductor chip 84 is formed at the periphery of the surface of the semiconductor chip 83 where the semiconductor chip 84 is bonded. There are areas that are not facing each other. In this region, an electrode pad 83b connected to the functional element 83a is formed. An electrode pad 84b connected to the functional element 84a is formed on the periphery of the surface of the semiconductor chip 84 where the functional element 84a is formed.

  When viewed from the direction perpendicular to the wiring board 82, the wiring board 82 is larger than the semiconductor chip 83, and there is a region where the semiconductor chip 83 is not opposed to the periphery of the surface of the wiring board 82 to which the semiconductor chip 83 is bonded. is doing. In this region, an electrode pad (not shown) is provided, and the electrode pad and the electrode pads 83b and 84b are connected through bonding wires 87 and 88, respectively.

The semiconductor chips 83 and 84 and the bonding wires 87 and 88 are sealed with a mold resin 89.
A metal ball 85 as an external connection member is provided on the surface of the wiring substrate 82 opposite to the surface to which the semiconductor chip 83 is bonded. An electrode pad (not shown) of the wiring board 82 is rewired on the surface or inside of the wiring board 82 and connected to the metal ball 85.

The semiconductor device 81 can be bonded to another wiring board via the metal ball 85.
FIG. 9 is a schematic sectional view showing the structure of a conventional semiconductor device having a chip scale package structure.
The semiconductor device 91 includes a semiconductor chip 92. A functional element 92a is formed on one surface of the semiconductor chip 92, and an insulating film 93 is formed so as to cover the functional element 92a. An opening is formed in a predetermined portion of the insulating film 93.

A rewiring 94 having a predetermined pattern is formed on the insulating film 93. The rewiring 94 is connected to the functional element 92 a through the opening of the insulating film 93. A columnar external connection terminal 95 is erected from a predetermined portion of the rewiring 94, and a metal ball 96 as an external connection member is joined to the tip of the external connection terminal 95.
A protective resin 97 is provided on the surface of the semiconductor chip 92 on the functional element 92 a side so as to cover the insulating film 93 and the rewiring 94. The external connection terminal 95 penetrates the protective resin 97. The side surface of the semiconductor chip 92 and the side surface of the protective resin 97 are flush with each other, and the outer shape of the semiconductor device 91 is substantially rectangular parallelepiped due to the protective resin 97. Therefore, the size of the semiconductor device 91 substantially matches the size of the semiconductor chip 92 when viewed from the direction perpendicular to the semiconductor chip 92.

The semiconductor device 91 can be bonded to the wiring board via the metal ball 96.
JP 2000-188369 A JP 2002-118224 A JP 2002-9223 A

  However, the semiconductor device 81 shown in FIG. 8 requires a wiring substrate 82 larger than the semiconductor chip 83 in order to secure a connection region for the bonding wires 87 and 88. For this reason, the size of the semiconductor device 81 (package), in particular, the size in the direction parallel to the wiring board 82 becomes larger than the semiconductor chips 83 and 84. For this reason, the mounting area with respect to the other wiring board of this semiconductor device 81 will become large.

The same problem occurs when a lead frame is used instead of the wiring board 82 (see, for example, Patent Document 3).
The semiconductor device 91 of FIG. 9 does not have a wiring board. However, with such a structure, a semiconductor device incorporating a plurality of chips (semiconductor chips 92) cannot be realized. For this reason, if a plurality of semiconductor chips 92 are to be mounted on the wiring board, a plurality of semiconductor devices 91 must be mounted side by side on the wiring board, and consequently a large mounting area is required. In addition, since the connection between the semiconductor chips 92 must be performed through the wiring board, the wiring length becomes long, and it is difficult to increase the signal processing speed of the entire system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a chip size and being a multichip module.
Another object of the present invention is to provide a semiconductor device which can shorten the wiring length and is a multichip module.

In order to achieve the above object, the first aspect of the present invention is the first functional surface (3F) on which the first functional element (3a) is formed, and a first functional surface opposite to the first functional surface. A first semiconductor chip (3) having one back surface (3R) and a second functional element (2a) are formed, a facing region facing the first functional surface of the first semiconductor chip, and a region other than the facing region in it have a second functional surface having a non-opposed region (7) (2F), the first semiconductor chip and second semiconductor chip that is flip-chip bonded to (2), the first functional surface and the second In a portion facing the functional surface, a connecting material (4) for electrically connecting the first functional element and the second functional element, a non-opposing region of the second semiconductor chip, and the first semiconductor chip successive formed insulated so as to cover the side surface and the first back surface (8, 22), a rewiring (9, 32A, 32B) formed on the surface of the insulating film and electrically connected to the second functional element, and a protective resin (12) covering the rewiring The external connection terminal (10) erected from the rewiring through the protective resin, and the heat radiating terminal (42) erected from the first back surface of the first semiconductor chip through the protective resin (42) ) And an interlayer sealing material (86) formed between the first semiconductor chip and the second semiconductor chip, and the heat dissipation terminal has the same size and shape as the external connection terminal A multi-chip module type semiconductor device (41) .

The alphanumeric characters in parentheses indicate corresponding components in the embodiments described later. The same applies hereinafter.
The semiconductor device according to the present invention is a multi-chip module including first and second semiconductor chips. According to the present invention, the first functional element of the first semiconductor chip and the second functional element of the second semiconductor chip are electrically connected with the first functional surface and the second functional surface facing each other. Yes. For this reason, compared with the case where a plurality of semiconductor devices having a single semiconductor chip are mounted on a wiring board, the wiring length between the semiconductor chips can be significantly shortened, and the operation of the semiconductor device is speeded up. it can.

  The connecting material for electrically connecting the first functional element of the first semiconductor chip and the second functional element of the second semiconductor chip includes, for example, bumps (projection electrodes) formed on the first and second functional surfaces, respectively. It may be joined. Further, the connecting material may be one in which a bump formed on only one of the first and second functional surfaces is bonded to the other functional surface. Such a connecting material can also achieve mechanical joining between the first semiconductor chip and the second semiconductor chip.

  The semiconductor device may include a plurality of the first semiconductor chips. In this case, each first semiconductor chip is electrically connected to the second semiconductor chip with its first functional surface opposed to the second functional surface. Can be connected to. In this case, the wiring length between the first functional element of each first semiconductor chip and the second functional element of the second semiconductor chip, or the wiring length between the first functional elements of the first semiconductor chip via the second semiconductor chip. Since this is equivalent to the wiring length between the plurality of second functional elements in the second semiconductor chip, the operation of the semiconductor device can be speeded up.

This semiconductor device can be mounted on a wiring board via an external connection terminal. An external connection member such as a metal ball may be joined to the tip of the external connection terminal. In this case, the semiconductor device can be mounted on the wiring board via the external connection member.
The size and arrangement of the first semiconductor chip are preferably such that the first semiconductor chip is almost completely included in the region of the second semiconductor chip when viewed from the direction perpendicular to the second functional surface. In this case, the mounting area of the semiconductor device with respect to the wiring board is substantially equal to the area of the second semiconductor chip viewed from the direction perpendicular to the second functional surface. That is, this semiconductor device can increase the density of the semiconductor chip with respect to the mounting area.

  The insulating film is continuously formed from the non-opposing region of the second semiconductor chip to the first back surface of the first semiconductor chip, and rewiring is performed at an arbitrary position on the surface of the insulating film at an arbitrary wiring pattern. Can be formed. Therefore, the number of external connection terminals formed on the rewiring can be increased as long as the size of the external connection terminals and the gap between adjacent external connection terminals are not reduced so as to adversely affect the mounting accuracy.

The insulating film may also be formed on the side surface of the semiconductor chip.
The redistribution wiring formed surface of the upper Symbol insulating film, a substantially planar surface over on the first semiconductor chip from the non-facing region may also do free.
According to this configuration , each external connection terminal is erected from a rewiring formed on the flat insulating film surface. On the other hand, since the semiconductor device is mounted on the wiring board through the tips of the external connection terminals, the tips of the external connection terminals are placed on substantially the same plane. Therefore, in the semiconductor device having this configuration , the external connection terminal formed on the non-opposing region and the external connection terminal formed on the first semiconductor chip can be made substantially the same length and short.

The external connection terminal can be formed, for example, by previously forming a protective resin having an opening in a portion corresponding to the external connection terminal and supplying a metal material to the opening by plating. External connection terminals designed to be approximately the same length and short can be formed in a short time. That is, in the semiconductor device having this configuration , the external connection terminals can be easily formed.
At least a part of the rewiring may be electrically connected to the first back surface of the first semiconductor chip.

According to this configuration , the first back surface of the first semiconductor chip is set to the predetermined potential via the rewiring electrically connected to the first back surface of the first semiconductor chip, and the first back surface of the first semiconductor chip is The potential can be stabilized. Thereby, the characteristics of the first semiconductor chip can be stabilized.
The rewiring electrically connected to the first back surface of the first semiconductor chip may be grounded.

By semi-conductor device (41) comprises a radiating terminals, the heat generated by the first semiconductor chip, a short distance through the heat radiating terminals, can be dissipated to the outside of the semiconductor device. In order to improve heat dissipation, it is preferable that a plurality of heat dissipation terminals are formed.

The heat dissipation terminal can be made of, for example, the same material as the external connection terminal. In this case, for example, the external connection terminal and the heat dissipation terminal can be collectively formed by electrolytic plating.
A conductive film may be formed between the first back surface of the first semiconductor chip and the heat radiating terminal. In this case, the conductive film and the rewiring may be made of the same material. In this case, the rewiring and the conductive film can be formed together.

The semiconductor device can further also do including the diffusion preventing film is formed a conductive material (45) between the first back surface and the insulating film and the heat radiating terminal of the first semiconductor chip.
According to this configuration , the diffusion preventing film is formed between the first back surface of the first semiconductor chip and the insulating film, that is, below the insulating film. Therefore, in the manufacturing process of the semiconductor device, after forming a diffusion prevention film on the first back surface of the first semiconductor chip, an insulating film having an opening at a predetermined position is formed on the diffusion prevention film. A heat radiating terminal connected to the first back surface of the first semiconductor chip can be formed.

  An insulating film is formed on the first back surface of the first semiconductor chip without previously forming a diffusion preventing film, and then a diffusion preventing film is formed on the first back surface of the first semiconductor chip exposed in the opening of the insulating film. In some cases, the diffusion prevention film may not be formed so as to completely cover the exposed portion of the first back surface of the first semiconductor chip. In this case, for example, when a hole is formed in the diffusion prevention film in the vicinity of the inner wall surface of the opening of the insulating film and a heat dissipation terminal made of metal is formed on the diffusion prevention film, the metal atoms constituting the heat dissipation terminal are It may diffuse into the first semiconductor chip through the hole. In this case, the characteristics of the first semiconductor chip vary.

On the other hand, in the semiconductor device having the above structure in which the diffusion preventing film is formed , the diffusion preventing film is formed on the first back surface (preferably, the entire first back surface) of the first semiconductor chip before forming the insulating film in the manufacturing process. Since it can be formed, a diffusion preventing film without a hole can be formed, and the first back surface of the first semiconductor chip can be completely covered with the diffusion preventing film. Therefore, it can suppress that the metal atom which comprises a thermal radiation terminal diffuses in a 1st semiconductor chip, and the characteristic of a 1st semiconductor chip fluctuates.

The diffusion preventing film can be made of, for example, the same material as a known UBM (Under Bump Metal).
A conductive film made of the same material as the rewiring may be formed between the diffusion prevention film formed on the first back surface of the first semiconductor chip and the heat dissipation terminal. In this case, the diffusion preventing film can suppress (prevent) diffusion of atoms (metal atoms) constituting the conductive film into the first semiconductor chip.

The heat dissipation pins may be used for fixing the first back surface potential of the upper Symbol first semiconductor chip.
The semiconductor device can further also do including the diffusion preventing film is formed a conductive material (45) between the first back surface and the insulating film and the rewiring of the first semiconductor chip.

According to this configuration , the diffusion preventing film is formed between the first back surface of the first semiconductor chip and the insulating film, that is, below the insulating film. Therefore, in the manufacturing process of the semiconductor device, after forming a diffusion prevention film on the first back surface of the first semiconductor chip, an insulating film having an opening at a predetermined position is formed on the diffusion prevention film. Through this, a rewiring connected to the first back surface of the first semiconductor chip can be formed.

By forming the diffusion prevention film before forming the insulating film, a diffusion prevention film without a hole can be formed, and the first back surface of the first semiconductor chip can be completely covered with the diffusion prevention film. Therefore, it is possible to prevent the atoms (metal atoms) constituting the rewiring from diffusing into the first semiconductor chip and changing the characteristics of the first semiconductor chip.
The diffusion prevention film can be made of the same material as that of a known UBM, for example.

The invention according to claim 49 is characterized in that the second semiconductor chip further includes a back surface protective film (62) formed on a second back surface (2R) which is a surface opposite to the second functional surface. The semiconductor device according to claim 1 .
According to this invention, the second back surface of the second semiconductor chip can be mechanically and electrically protected by the back surface protection film.

  When the back surface protective film is not formed, the stress balance is maintained in the thickness direction of the second semiconductor chip by forming an insulating film, a protective resin, etc. on the one surface (functional surface) side of the second semiconductor chip. Without warping, the second semiconductor chip may be warped. In the semiconductor device of the present invention, the back surface protective film is formed on the other surface side (back surface side) of the second semiconductor chip, so that the stress balance in the thickness direction of the second semiconductor chip is maintained, and the second semiconductor chip The occurrence of warping can be reduced (prevented).

The back surface protective film can be made of, for example, a resin.
The semiconductor device further includes a via conductor (72) standing from the non-opposing region of the second semiconductor chip through the insulating film and electrically connecting the second functional element and the rewiring. But you can.
When manufacturing such a semiconductor device, the via conductor can be formed so as to protrude from the non-opposing region of the second semiconductor chip prior to the formation of the insulating film. Thereafter, an insulating film can be formed so as to penetrate the via conductor, and the rewiring can be electrically connected to the via conductor.

When such a via conductor is not formed, after forming an insulating film, it is necessary to form an opening for arranging a rewiring or the like in the insulating film. The forming step can be omitted.
The semiconductor device includes a semiconductor chip (3) in which a functional element (3a) is formed on one surface (3F), and a back surface (3R) which is a surface opposite to the surface on which the functional element is formed. An insulating film (8, 22) covering the substrate, conductive members (32B, 44) electrically connected to the back surface of the semiconductor chip through openings (8a, 22a) formed in the insulating film, and A diffusion prevention film (45) formed between the back surface of the semiconductor chip and the insulating film and the conductive member may be included.

In such a semiconductor device, the back surface of the semiconductor chip can be set to a predetermined potential via the conductive member. Thereby, the electric potential of the back surface of the semiconductor chip can be stabilized, and the characteristics of the semiconductor chip can be stabilized. The conductive member may be grounded, for example.
The diffusion preventing film is formed between the back surface of the semiconductor chip and the insulating film, that is, below the insulating film. Therefore, in the manufacturing process of the semiconductor device, after forming an insulating film having an opening at a predetermined position on the diffusion prevention film formed on the back surface of the semiconductor chip, the back surface of the semiconductor chip is formed through the opening. An electrically connected conductive member can be formed.

By forming the diffusion preventive film before forming the insulating film, a diffusion preventive film that completely covers the back surface of the semiconductor chip can be formed. By this diffusion preventive film, atoms (metal atoms) constituting the conductive member are formed on the semiconductor chip. It can suppress that the characteristic of a semiconductor chip fluctuates by diffusing.
In this semiconductor device, a diffusion prevention film of a conductive material is formed on the back surface (preferably the entire back surface) which is the surface opposite to the surface on which the functional element is formed of a semiconductor chip having a functional element formed on one surface. A step of forming an insulating film having an opening exposing the diffusion preventing film on the diffusion preventing film; and an electrical connection to the back surface of the semiconductor chip through the opening of the insulating film. It can be manufactured by a method for manufacturing a semiconductor device including a step of forming a conductive member.
The invention described in claim 2 is the semiconductor device according to claim 1, wherein the semiconductor chip is a chip scale package.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first and second functional elements include at least a transistor.
According to a fourth aspect of the present invention, the first semiconductor chip and the second semiconductor chip are arranged in parallel so that the first functional surface and the second functional surface face each other with a gap. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
According to a fifth aspect of the present invention, in the connection material, the bump formed on only one of the first and second functional surfaces is bonded to the other functional surface. 5. A semiconductor device according to any one of items 4 to 4.
According to a sixth aspect of the present invention, the first semiconductor chip is smaller than the second semiconductor chip when viewed from a direction perpendicular to the second functional surface, and is completely included in the region of the second semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
According to a seventh aspect of the present invention, the first semiconductor chip is located at a central portion of the second functional surface of the second semiconductor chip so that the non-facing region exists at a peripheral portion of the second functional surface. The semiconductor device according to claim 1, wherein the semiconductor device is arranged.
The invention according to claim 8 is characterized in that the second functional element is formed from the region facing the first semiconductor chip to the non-facing region. The semiconductor device according to the item.
The invention according to claim 9 is characterized in that the insulating layer is formed so as to cover the formation region of the second functional element in the non-facing region, the end surface of the interlayer sealant, and the side surface and the first back surface of the first semiconductor chip. 9. The semiconductor device according to claim 1, wherein the film is formed continuously.
The invention according to claim 10 is characterized in that the insulating film is made of any one of polyimide, polybenzoxazole, epoxy, silicon oxide, and silicon nitride. It is a semiconductor device.
An eleventh aspect of the present invention is the semiconductor device according to any one of the first to tenth aspects, wherein the insulating film has a certain thickness.
The invention according to claim 12 is characterized in that the rewiring is formed on the insulating film on the non-facing region and on the insulating film on the first semiconductor chip. The semiconductor device according to any one of the above.
According to a thirteenth aspect of the present invention, an opening is formed in the insulating film on the non-opposing region, and an electrode pad provided on a predetermined region of the second functional element appears in the opening. 13. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
The invention according to claim 14 is characterized in that the rewiring is electrically connected to the electrode pad on the second functional element through the opening of the insulating film. is a semiconductor equipment described.
The invention according to claim 15 is the semiconductor device according to claim 13 or 14, wherein the electrode pad on the second functional element and the rewiring are made of different materials.
The invention according to claim 16 is the semiconductor device according to any one of claims 13 to 15, wherein the electrode pad is made of aluminum and the rewiring is made of copper.
The invention described in claim 17 is characterized in that a UBM layer is interposed between the electrode pad on the second functional element and the rewiring. The semiconductor device according to the item.
The invention according to claim 18 is the semiconductor device according to claim 13 or 14, wherein the electrode pad on the second functional element and the rewiring are made of the same kind of material.
The invention according to claim 19 is characterized in that the protective resin is provided so as to cover the insulating film and the rewiring on the second functional surface side of the second semiconductor chip. 19. A semiconductor device according to any one of items 18 to 18.
According to a twentieth aspect of the invention, the side surface of the second semiconductor chip and the side surface of the protective resin are flush with each other, and the outer shape of the semiconductor device is a rectangular parallelepiped shape by the protective resin. 20. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
According to a twenty-first aspect of the present invention, in the rewiring, from a predetermined position of a portion formed on the non-opposing region and a portion formed on the first semiconductor chip, the protective resin is penetrated, 21. The semiconductor device according to claim 1, wherein a plurality of external connection terminals each made of metal are provided upright.
According to a twenty-second aspect of the present invention, in the semiconductor device according to any one of the first to twenty-first aspects, the external connection terminal is made of any one of copper, nickel, gold, and tungsten.
The invention described in claim 23 is the semiconductor device according to any one of claims 1 to 22, wherein an external shape of the external connection terminal is a columnar shape or a quadrangular prism shape.
According to a twenty-fourth aspect of the present invention, the external connection terminal erected from a portion on the non-facing region of the rewiring is erected from a portion of the rewiring on the first semiconductor chip. The semiconductor device according to claim 21, wherein the semiconductor device is longer than the external connection terminal.
The invention according to claim 25 is the semiconductor device according to any one of claims 1 to 24, wherein a metal ball as an external connection member is joined to a tip of the external connection terminal. is there.
According to a twenty-sixth aspect of the present invention, in the insulating film, the insulating film is formed thicker in a portion on the non-opposing region than in a portion on the first semiconductor chip. Or a semiconductor device according to item 1.
In a twenty-seventh aspect of the present invention, a plurality of the external connection terminals are provided, and a surface of the insulating film on which the rewiring is formed is a flat surface extending from the non-opposing region to the first semiconductor chip. 27. The semiconductor device according to claim 26, wherein the plurality of external connection terminals have the same length.
The invention according to claim 28 is characterized in that the rewiring is connected to an electrode pad on the second functional element through an opening formed in the insulating film. It is a semiconductor device of description.
29. The semiconductor device according to claim 26, wherein in the opening, the rewiring is formed along an inner wall surface of the opening. It is.
The invention described in claim 30 is the semiconductor device according to claim 29, wherein an inner region of the opening is filled with the protective resin.
According to a thirty-first aspect of the present invention, an opening is formed in the insulating film, and the rewiring includes a first rewiring connected to the second functional element through the opening of the insulating film; And a second rewiring connected to the second functional element through the opening of the insulating film and connected to the first back surface of the first semiconductor chip. 1. The semiconductor device according to 1.
The invention according to claim 32 is characterized in that a central portion of the first back surface of the first semiconductor chip is not covered with the insulating film but covered with the second rewiring. 31. The semiconductor device according to 31.
A thirty-third aspect of the present invention is the semiconductor device according to the thirty-first or thirty-second aspect, wherein a metal ball is connected to the rewiring via the external connection terminal.
According to a thirty-fourth aspect of the present invention, a plurality of the external connection terminals are provided, and a part of the plurality of external connection terminals is connected to the first back surface of the first semiconductor chip via the second rewiring. The semiconductor device according to claim 31, wherein the semiconductor device is electrically connected to the semiconductor device.
The invention according to claim 35 is characterized in that the first back surface of the first semiconductor chip can be set to a predetermined potential via the external connection terminal connected to the second rewiring. A semiconductor device according to any one of claims 31 to 34.
According to a thirty-sixth aspect of the present invention, the external connection terminal electrically connected to the first back surface of the first semiconductor chip through the second rewiring is a grounding terminal. A semiconductor device according to claim 34.
According to a thirty-seventh aspect of the present invention, an opening having a slightly smaller width than the external connection terminal is formed in a portion of the insulating film covering the first semiconductor chip. It is a semiconductor device as described in above.
The invention according to claim 38 is the semiconductor device according to claim 37, wherein the heat radiation terminal and the external connection terminal are made of the same metal material.
A thirty-ninth aspect of the present invention is the semiconductor device according to the thirty-third or thirty-eighth aspect, wherein a metal ball is bonded to the tip of the heat radiation terminal.
40. The conductive film according to claim 40, wherein the conductive film is made of the same material as that of the rewiring between the first back surface of the first semiconductor chip and the heat dissipation terminal, and has substantially the same thickness as the rewiring. 40. The semiconductor device according to any one of claims 37 to 39, wherein: is interposed.
The invention according to claim 41 is the semiconductor device according to any one of claims 37 to 40, wherein the heat radiation terminal is a terminal for grounding.
42. The invention according to claim 42, wherein the first back surface of the first semiconductor chip can be grounded via the heat dissipation terminal. This is a semiconductor device.
The invention according to claim 43 is characterized in that the heat radiating terminal is bonded to the first back surface of the first semiconductor chip in proximity to the first back surface with the conductive film interposed therebetween. A semiconductor device according to claim 40.
The invention according to claim 44 is the semiconductor device according to claim 39, wherein a plurality of the heat radiating terminals and the metal balls are bonded to the first back surface of the first semiconductor chip.
According to a 45th aspect of the present invention, in the semiconductor device according to the first aspect, an anti-diffusion film of a conductive material is formed over the entire first back surface of the first semiconductor chip.
The invention according to claim 46 is characterized in that the diffusion preventing film is formed between the first back surface of the first semiconductor chip, the insulating film and the heat radiating terminal. This is a semiconductor device.
A 47th aspect of the present invention is the semiconductor device according to the 45th or 46th aspect, wherein the diffusion preventive film is also formed on a side surface of the first semiconductor chip.
48. The invention according to claim 48, wherein the diffusion preventing film is made of any one of titanium, titanium tungsten, nickel, titanium nitride, and tantalum nitride. It is a semiconductor device.
A 50th aspect of the present invention is the semiconductor device according to the 49th aspect, wherein the back surface protection film is made of a resin that is one of polyimide, polyimide amide, and epoxy.
The invention according to claim 51 is the semiconductor device according to claim 1, wherein an opening is formed in the insulating film of the semiconductor device, and the opening is filled with a via conductor. is there.
The invention according to claim 52 is characterized in that the second functional element of the second semiconductor chip and the rewiring are electrically connected via the via conductor. It is a semiconductor device.
The invention according to claim 53 is the semiconductor device according to any one of claims 1 to 52, wherein the semiconductor device comprises a plurality of the first semiconductor chips.
According to a 54th aspect of the present invention, each first semiconductor chip is electrically connected to the second semiconductor chip with the first functional surface facing the second functional surface of the second semiconductor chip. 54. A semiconductor device according to claim 53, wherein:
The invention according to claim 55 is characterized in that a diffusion preventing film of a conductive material is formed between the first back surface of the first semiconductor chip and the insulating film and the rewiring. 37. The semiconductor device according to any one of 31 to 36.
56. The semiconductor device according to claim 13, wherein the opening is filled with a via conductor having a height substantially equal to the thickness of the insulating film in the non-opposing region. It is.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Figure 1 is a schematic sectional view showing the structure of a semi-conductor device.
The semiconductor device 1 is a so-called chip scale package (CSP) and a multi-chip module including semiconductor chips 2 and 3.
The first semiconductor chip 3 has a first functional surface 3F on which the first functional element 3a is formed and a back surface 3R which is a surface opposite to the first functional surface 3F. The second semiconductor chip 2 has a second functional surface 2F on which the second functional element 2a is formed. The first functional element 3a and the second functional element 2a may be transistors, for example. The first semiconductor chip 3 and the second semiconductor chip 2 are arranged substantially in parallel with a slight gap so that the first functional surface 3F and the second functional surface 2F face each other.

The first functional element 3a and the second functional element 2a are a connecting member 4 disposed at a facing portion between the first semiconductor chip 3 (first functional surface 3F) and the second semiconductor chip 2 (second functional surface 2F). Is electrically connected. For example, the connecting member 4 may be formed by bonding a bump formed at a predetermined position on the first functional surface 3F and a bump (projection electrode) formed at a predetermined position on the second functional surface 2F. Good. Further, the connecting material 4 may be one in which bumps formed only on one of the first and second functional surfaces 3F, 2F are joined to the other functional surfaces 2F, 3F. With such a connection material 4, mechanical joining between the first semiconductor chip 3 and the second semiconductor chip 2 can also be achieved.
The gap between the first semiconductor chip 3 and the second semiconductor chip 2 is filled with an interlayer sealant (underfill) 5.

The first semiconductor chip 3 is smaller than the second semiconductor chip 2 and completely included in the region of the second semiconductor chip 2 when viewed from the direction perpendicular to the second functional surface 2F. The first semiconductor chip 3 is disposed substantially at the center of the second functional surface 2F of the second semiconductor chip 2. For this reason, a region (hereinafter referred to as “non-opposing region”) 7 where the first semiconductor chip 3 does not face is present in the peripheral portion of the second functional surface 2F.
The second functional element 2a is formed from the region where the first semiconductor chip 3 is opposed to the non-facing region 7.

An insulating film 8 is continuously formed so as to cover the formation region of the second functional element 2 a in the non-facing region 7, the end surface of the interlayer sealing agent 5, and the side surface and the back surface 3 </ b> R of the first semiconductor chip 3. The insulating film 8 is made of, for example, polyimide, polybenzoxazole, epoxy, silicon oxide, or silicon nitride. The insulating film 8 has a substantially constant thickness.
A rewiring 9 having a predetermined pattern is formed on the insulating film 8. The rewiring 9 is formed on the insulating film 8 on the non-facing region 7 and the insulating film 8 on the first semiconductor chip 3.

An opening 8a is formed in the insulating film 8 on the non-facing region 7, and an electrode pad (not shown) provided on a predetermined region of the second functional element 2a appears in the opening 8a. The rewiring 9 is electrically connected to the electrode pad on the second functional element 2 a through the opening 8 a of the insulating film 8.
The electrode pad on the second functional element 2a and the rewiring 9 may be made of different materials. For example, the electrode pad is made of aluminum (Al) and the rewiring 9 is made of copper (Cu). Good. In this case, it is preferable that a UBM (Under Bump Metal) layer (not shown) is interposed between the electrode pad on the second functional element 2a and the rewiring 9. The electrode pad on the second functional element 2a and the rewiring 9 may be made of the same kind of material.

A protective resin 12 is provided on the second functional surface 2F side of the second semiconductor chip 2 so as to cover the insulating film 8 and the rewiring 9. The side surface of the second semiconductor chip 2 and the side surface of the protective resin 12 are substantially flush with each other, and the outer shape of the semiconductor device 1 is substantially rectangular parallelepiped due to the protective resin 12.
In the rewiring 9, a plurality of external parts each made of metal penetrate through the protective resin 12 from a predetermined position of the part formed on the non-facing region 7 and the part formed on the first semiconductor chip 3. A connection terminal 10 is erected. The external connection terminal 10 is made of metal (for example, copper, nickel (Ni), gold (Au), tungsten (W)) and has a columnar outer shape (for example, a columnar shape or a square columnar shape).

The tips of the external connection terminals 10 are on substantially the same plane. The joint interface between the external connection terminal 10 and the metal ball 11 is substantially flush with the surface of the protective resin 12. That is, the external connection terminal 10 erected from the portion on the non-facing region 7 of the rewiring 9 is longer than the external connection terminal 10 erected from the portion of the rewiring 9 on the first semiconductor chip 3.
A metal ball 11 as an external connection member is joined to the tip of each external connection terminal 10. The semiconductor device 1 can be mounted on a wiring board via metal balls 11.

As described above, the semiconductor device 1 has substantially the same size as the second semiconductor chip 2 which is the largest chip when viewed from the direction perpendicular to the second functional surface 2F. Mounting area is small. That is, in the semiconductor device 1, the density of the first and second semiconductor chips 3 and 2 is increased with respect to the mounting area.
The first and second functional surfaces 3F and 2F are opposed to each other, and the first functional element 3a and the second functional element 2a are connected face-to-face, whereby the semiconductor device 1 includes a plurality of conventional semiconductors. When the device 91 (see FIG. 9) is mounted on a wiring board, or compared with the conventional semiconductor device 81 (see FIG. 8), the first functional element of each chip (first and second semiconductor chips 3 and 2) The wiring length between 3a and the second functional element 2a is short. For this reason, the operation of the semiconductor device 1 can be speeded up.

Further, the rewiring 9 can be formed with an arbitrary wiring pattern at an arbitrary position on the surface of the insulating film 8. Therefore, the number of external connection terminals 10 formed on the rewiring 9 can be increased as long as the size of the external connection terminals 10 and the gap between adjacent external connection terminals 10 are not reduced so as to adversely affect the mounting accuracy.
The semiconductor device 1 can be manufactured, for example, at a wafer level, and a first substrate is formed on a large substrate (for example, a semiconductor wafer) in which a plurality of regions corresponding to the second semiconductor chips 2 are densely formed. Bonding of the semiconductor chip 3, filling of the gap between the substrate and the first semiconductor chip 3 with the interlayer sealant 5, formation of the insulating film 8, formation of the rewiring 9, formation of the protective resin 12, formation of the external connection terminal 10 Then, the metal balls 11 are sequentially joined to the regions corresponding to the second semiconductor chips 2 in sequence, and the substrate is bonded together with the protective resin 12 to the individual second semiconductor chips 2. It can be manufactured by cutting into pieces.

  The insulating film 8 is formed by, for example, bonding the first semiconductor chip 3 to the substrate, filling the interlayer sealing agent 5, and then spin-coating a low-viscosity resin so that the substrate (second semiconductor chip 2) does not face the substrate. It can be formed by coating the region 7 and the side and back surfaces 3R of the first semiconductor chip 3 and curing the resin. The insulating film 8 can be formed using a photosensitive resin. In this case, a liquid photosensitive resin is applied to the entire surface of the substrate to which the first semiconductor chip 3 is bonded and filled with the interlayer sealing agent 5, and then exposed and developed to insulate a predetermined pattern having openings 8a. A film 8 can be formed.

  For the external connection terminal 10, for example, the protective resin 12 is formed on the entire surface of the substrate on which the insulating film 8 is formed on the insulating film 8 side, and the protective resin 12 corresponding to the external connection terminal 10 is removed. In addition, a seed layer is formed on the entire surface (including the inside of the opening) of the surface of the substrate on which the protective resin 12 is formed, and then the opening is filled by electrolytic plating through the seed layer. Thus, it can be formed by supplying a metal material.

Figure 2 is a schematic sectional view showing the structure of a semi-conductor device. 2, parts corresponding to those shown in FIG. 1 are denoted by the same reference numerals as those in FIG.
The semiconductor device 21 includes an insulating film 22 instead of the insulating film 8 of FIG. The insulating film 22 is formed over the first semiconductor chip 3 from the non-opposing region 7, and is formed thicker in the portion on the non-opposing region 7 than the portion on the first semiconductor chip 3. Thereby, the surface of the insulating film 22 on which the rewiring 9 is formed has a substantially flat surface extending from the non-opposing region 7 to the first semiconductor chip 3. For this reason, the lengths of the plurality of external connection terminals 10 are substantially the same.

The rewiring 9 is connected to an electrode pad on the second functional element 2 a through an opening 22 a formed in the insulating film 22. In the opening 22 a, the rewiring 9 is formed along the inner wall surface of the opening 22 a, and the inner region of the opening 22 a is filled with the protective resin 12.
When the short external connection terminal 10 is formed, since the opening of the protective resin 12 corresponding to the external connection terminal 10 becomes shallow, the external connection terminal 10 can be formed by filling the opening with a metal material in a short time.

  Further, since the lengths of the external connection terminals 10 to be formed are substantially the same, for example, the metal material supplied by plating as described above fills the openings formed in the protective resin 12 almost simultaneously. For this reason, plating can be completed in a state where the metal material hardly protrudes from the opening. That is, the step of removing the metal material protruding from the opening of the protective resin 12 can be omitted or completed in a short time. Therefore, the external connection terminal 10 of the semiconductor device 21 can be easily formed.

Figure 3 is a schematic sectional view showing the structure of a semi-conductor device. 3, parts corresponding to those shown in FIGS. 1 and 2 are denoted by the same reference numerals as those in FIGS. 1 and 2, and description thereof is omitted.
The semiconductor device 31 includes a rewiring 32A connected to the second functional element 2a via the opening 22a of the insulating film 22 instead of the rewiring 9, and a second functional element 2a via the opening 22a of the insulating film 22. And a rewiring 32B connected to the back surface 3R of the first semiconductor chip 3.

The central portion of the back surface 3R of the first semiconductor chip 3 is not covered with the insulating film 8, and this region is covered with the rewiring 32B.
A part of the metal ball 11 is connected to the rewiring 32A or the rewiring 32B via the external connection terminal 10 outside the cross section of FIG.
With the configuration as described above, some of the external connection terminals 10 are electrically connected to the back surface 3R of the first semiconductor chip 3 through the rewiring 32B. Via the external connection terminal 10, the back surface 3R of the first semiconductor chip 3 can be set to a predetermined potential, and the potential of the back surface 3R of the first semiconductor chip 3 can be fixed. Thereby, the operating characteristics of the first semiconductor chip 3 are stabilized.

The external connection terminal 10 electrically connected to the back surface 3R of the first semiconductor chip 3 via the rewiring 32B may be a grounding (ground) terminal. In this case, the back surface 3R of the first semiconductor chip 3 can be grounded to fix the potential.
FIG. 4 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. 4, parts corresponding to those shown in FIGS. 1 to 3 are denoted by the same reference numerals as those in FIGS. 1 to 3, and description thereof is omitted.

  In the semiconductor device 41, most of the back surface 3 </ b> R of the first semiconductor chip 3 is covered with the insulating film 22. In the portion of the insulating film 22 covering the first semiconductor chip 3, an opening having a slightly smaller width than the external connection terminal 10 is formed. Through this opening, an external connection terminal (hereinafter referred to as “heat dissipation terminal”) 42 for radiating heat and fixing the potential of the back surface 3R of the first semiconductor chip 3 is connected to the back surface 3R of the first semiconductor chip 3. . The heat dissipation terminal 42 has the same size and shape as the external connection terminal 10. The heat radiation terminal 42 is made of the same material (metal) as that of the external connection terminal 10. The metal ball 11 is joined to the tip of the heat radiating terminal 42.

A conductive film 44 made of the same material as the rewiring 32A and having substantially the same thickness as the rewiring 32A is interposed between the back surface 3R of the first semiconductor chip 3 and the heat radiating terminal 42.
The heat dissipation terminal 42 can be, for example, a grounding terminal. By grounding the back surface 3R of the first semiconductor chip 3 via the heat radiation terminal 42, the potential of the back surface 3R of the first semiconductor chip 3 is fixed, and the operating characteristics of the first semiconductor chip 3 are stabilized.

The semiconductor device 3 1 according to FIG. 3, rewiring 32B connected to the rear surface 3R of the first semiconductor chip 3 is extended over the non-opposed region 7, the external connection terminals 10 This extending portion of the redistribution 32B It is joined to. On the other hand, in the semiconductor device 41 according to the embodiment of the present invention , the heat radiation terminal 42 is adjacently bonded to the back surface 3R of the first semiconductor chip 3 with the conductive film 44 interposed therebetween. For this reason, the semiconductor device 41 can efficiently dissipate the heat generated in the first semiconductor chip 3 to the outside of the semiconductor device 41 through a heat radiation terminal 42 at a short distance.

  One heat radiating terminal 42 and the metal ball 11 may be connected to the back surface 3R of the first semiconductor chip 3, and in this case also, the potential fixing (grounding) of the back surface 3R of the first semiconductor chip 3 and the first semiconductor are performed. The heat generated in the chip 3 can be dissipated. However, as shown in FIG. 4, when the plurality of heat dissipation terminals 42 and the metal balls 11 are joined to the back surface 3R of the first semiconductor chip 3, heat from the first semiconductor chip 3 can be dissipated more efficiently. Can do.

FIG. 5 is an illustrative cross-sectional view showing an enlarged joint portion between the back surface 3 </ b> R of the first semiconductor chip 3 and the heat dissipation terminal 42.
A conductive material diffusion prevention film 45 is formed over the entire back surface 3R of the first semiconductor chip 3. The diffusion prevention film 45 is formed between the back surface 3R of the first semiconductor chip 3, the insulating film 22, and the heat dissipation terminal 42 (conductive film 44). The diffusion prevention film 45 may be formed also on the side surface of the first semiconductor chip 3.

The diffusion prevention film 45 is a material that can prevent (suppress) the metal atoms constituting the heat radiation terminal 42 and the conductive film 44 from diffusing into the first semiconductor chip 3, for example, UBM (Under Bump Metal of public land). ) (For example, titanium (Ti), titanium tungsten (TiW), nickel, titanium nitride (TiN), tantalum nitride (TaN)).
In order to manufacture the semiconductor device 41, for example, first, the process up to the step of bonding the first semiconductor chip 3 on the substrate on which the regions corresponding to the plurality of second semiconductor chips 2 are densely formed is shown in FIG. This is carried out in the same manner as in the first manufacturing method. Next, a diffusion prevention film 45 is formed on the entire surface of the substrate on the side to which the first semiconductor chip 3 is bonded, and the diffusion prevention film 45 is not on the back surface 3R (and side surfaces) of the first semiconductor chip 3. The part of is removed.

Thereafter, an insulating film 22 having a predetermined opening 22b (see FIG. 5) is formed, and a conductive film is formed in a predetermined pattern region including the back surface 3R (diffusion prevention film 45) of the first semiconductor chip 3 exposed in the opening 22b. By forming 44, the semiconductor device 41 having the structure shown in FIGS. 4 and 5 can be manufactured.
If the diffusion prevention film 45 is to be formed after the formation of the insulation film 22 rather than before the formation of the insulation film 22, the diffusion prevention film closes the back surface 3 </ b> R of the first semiconductor chip 3 in the vicinity of the inner wall surface of the insulation film 22 in the opening 22 b. The film cannot be completely covered (covered), and a hole may be formed in the diffusion prevention film.

On the other hand, since the back surface 3R of the first semiconductor chip 3 before the formation of the insulating film 22 is flat, a diffusion prevention film 45 that does not have a hole and completely covers the back surface 3R can be formed on the back surface 3R. Such a diffusion prevention curtain 45 can prevent (suppress) the diffusion of metal atoms constituting the heat radiating terminal 42 and the conductive film 44 into the first semiconductor chip 3.
Figure 6 is a schematic sectional view showing the structure of a semi-conductor device. 6, parts corresponding to those shown in FIGS. 1 to 4 are given the same reference numerals as those in FIGS. 1 to 4 and description thereof is omitted.

In the semiconductor device 61, the back surface protective film 62 is formed on the back surface 2R that is the surface opposite to the second functional surface 2F in the second semiconductor chip 2. With the back surface protective film 62, the back surface 2R of the second semiconductor chip 2 can be protected mechanically and electrically.
As in the semiconductor device 2 1 in FIG. 2, when the back surface protective film 62 is not formed, an insulating film 22 and the protective resin 12 is formed on one surface (second functional surface 2F) side of the second semiconductor chip 2 As a result, the stress balance may not be maintained in the thickness direction of the second semiconductor chip 2, and the second semiconductor chip 2 may be warped. In this semiconductor device 61, the back surface protective film 62 is formed on the other surface (back surface 2R) of the second semiconductor chip 2, whereby the stress balance in the thickness direction of the second semiconductor chip 2 is maintained, and the second semiconductor chip 61 is provided. The warpage of the chip 2 can be reduced (prevented).

The back surface protective film 62 can be made of, for example, a resin (for example, polyimide, polyimide amide, epoxy).
FIG. 7 is a schematic cross-sectional view showing the structure of a semiconductor device which is a chip scale package and a multi-chip module. 7, parts corresponding to those shown in FIGS. 1 to 4 are denoted by the same reference numerals as those in FIGS. 1 to 4 and description thereof is omitted.

An opening 22 a formed in the insulating film 22 of the semiconductor device 71 is filled with a via conductor 72. The second functional element 2 a of the second semiconductor chip 2 and the rewiring 9 are electrically connected via the via conductor 72.
When the semiconductor device 71 is manufactured, the via conductor 72 can be formed so as to protrude from the second functional surface 2F of the second semiconductor chip 2 prior to the formation of the insulating film 22. Thereafter, the insulating film 22 is formed so as to penetrate the via conductor 72, and the rewiring 9 electrically connected to the via conductor 72 can be formed.

Such a semiconductor device having no via conductors 72, for example, when manufacturing the semiconductor device 2 1 in FIG. 2, after forming the insulating film 22, an opening for disposing the rewiring 9 in the insulating film 22 Although it has to be formed (patterned), in the manufacturing process of the semiconductor device 71, the process of forming such an opening can be omitted.
Further, the material constituting the via conductor 72 and the material constituting the rewiring 9 can be individually selected.

  Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms. For example, the semiconductor device of the present invention may include a plurality of first semiconductor chips 3. In this case, each first semiconductor chip 3 is electrically connected to the second semiconductor chip 2 with the first functional surface 3F facing the second functional surface 2F of the second semiconductor chip 2. Can do. In this case, the wiring length between the first functional element 3 a of each first semiconductor chip 3 and the second functional element 2 a of the second semiconductor chip 2, and the wiring length between the first functional elements 3 a of each first semiconductor chip 3. Since this is equivalent to the wiring length between the plurality of second functional elements 2a in the second semiconductor chip 2, the operation of the semiconductor device can be speeded up.

Oite the semiconductor device 3 1 of FIG. 3, between the first semiconductor chip 3 on the back surface 3R and the insulating film 22 and the rewiring 32B, the diffusion preventing film 45 of the semiconductor device 41 according to the embodiment of the present invention (FIG. 5 A diffusion preventing film similar to that of (see) may be formed. In this case, the diffusion preventing film can prevent (suppress) the metal atoms constituting the rewiring 32 </ b> B from diffusing into the first semiconductor chip 3.

In the semiconductor device 1 of FIG. 1, the rewiring 9 is formed in the opening 8a, but the opening 8a is shorter than the via conductor 72 (see FIG. 7) (the thickness of the insulating film 8 in the non-facing region 7). It may be filled with via conductors (of the same height). In this case, the via conductor may be formed simultaneously with the connection material 4 or the bump for forming the connection material 4.
In addition, various modifications can be made within the scope of the matters described in the claims.

It is a schematic sectional view illustrating the structure of a semi-conductor device. It is a schematic sectional view illustrating the structure of a semi-conductor device. It is a schematic sectional view illustrating the structure of a semi-conductor device. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. FIG. 5 is an illustrative cross-sectional view showing an enlarged joint portion between the back surface of the first semiconductor chip and the heat dissipation terminal in the semiconductor device shown in FIG. 4. It is a schematic sectional view illustrating the structure of a semi-conductor device. It is an illustration sectional view showing the structure of the semiconductor device which is a chip scale package and is a multichip module. It is an illustrative sectional view showing the structure of a conventional semiconductor device having a multichip module structure. It is an illustrative sectional view showing the structure of a conventional semiconductor device having a chip scale package structure.

Explanation of symbols

1, 2, 31, 41, 61 Semiconductor device 2 2nd semiconductor chip 2a 2nd functional element 2F 2nd functional surface 2R 2nd back surface 3 1st semiconductor chip 3a 1st functional element 3F 1st functional surface 3R 1st back surface 4 Connecting material 7 Non-facing region 8, 22 Insulating film 8a, 22a, 22b Insulating film opening 9, 32A, 32B Rewiring 10 External connection terminal 12 Protective resin 42 Heat radiation terminal 44 Conductive film 45 Diffusion prevention film 62 Back surface protection film

Claims (56)

A first functional chip on which a first functional element is formed, and a first semiconductor chip having a first back surface that is a surface opposite to the first functional surface;
A second functional surface formed with a second functional surface having a facing region facing the first functional surface of the first semiconductor chip and a non-facing region other than the facing region; A second semiconductor chip in which the chip is flip-chip connected;
A connecting material for electrically connecting the first functional element and the second functional element at a facing portion between the first functional surface and the second functional surface;
An insulating film continuously formed so as to cover the non-facing region of the second semiconductor chip, the side surface of the first semiconductor chip, and the first back surface;
A rewiring formed on the surface of the insulating film and electrically connected to the second functional element;
A protective resin covering the rewiring;
An external connection terminal erected from the rewiring through the protective resin;
A heat radiating terminal erected from the first back surface of the first semiconductor chip through the protective resin;
An interlayer sealing material formed between the first semiconductor chip and the second semiconductor chip,
The multichip module type semiconductor device, wherein the heat dissipation terminal has the same size and shape as the external connection terminal.   The semiconductor device according to claim 1, wherein the semiconductor chip is a chip scale package.   The semiconductor device according to claim 1, wherein the first and second functional elements include at least a transistor.   2. The first semiconductor chip and the second semiconductor chip are arranged in parallel so that the first functional surface and the second functional surface face each other with a gap therebetween. 4. The semiconductor device according to any one of items 3 to 3.   5. The connection member according to claim 1, wherein a bump formed on only one of the first and second functional surfaces is bonded to the other functional surface. 6. The semiconductor device described.   The first semiconductor chip is smaller than the second semiconductor chip when viewed from a direction perpendicular to the second functional surface, and is completely included in a region of the second semiconductor chip. 6. The semiconductor device according to any one of 1 to 5.   The first semiconductor chip is disposed in a central portion of the second functional surface of the second semiconductor chip so that the non-opposing region exists in a peripheral portion of the second functional surface. The semiconductor device according to any one of claims 1 to 6.   The semiconductor device according to claim 1, wherein the second functional element is formed from a region where the first semiconductor chip is opposed to the non-opposing region.   The insulating film is continuously formed so as to cover the formation region of the second functional element in the non-opposing region, the end surface of the interlayer sealant, and the side surface and the first back surface of the first semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The semiconductor device according to claim 1, wherein the insulating film is made of any one of polyimide, polybenzoxazole, epoxy, silicon oxide, and silicon nitride.   The semiconductor device according to claim 1, wherein the insulating film has a certain thickness.   12. The rewiring is formed on the insulating film on the non-opposing region and the insulating film on the first semiconductor chip. 12. Semiconductor device.   An opening is formed in the insulating film on the non-opposing region, and an electrode pad provided on a predetermined region of the second functional element appears in the opening. Item 13. The semiconductor device according to any one of Items 1 to 12. The redistribution wiring through the opening of the insulating film, a semiconductor equipment according to claim 13, characterized in that it is electrically connected to the electrode pads on the second functional element.   15. The semiconductor device according to claim 13, wherein the electrode pad on the second functional element and the rewiring are made of different materials.   The semiconductor device according to claim 13, wherein the electrode pad is made of aluminum, and the rewiring is made of copper.   17. The semiconductor device according to claim 13, wherein a UBM layer is interposed between the electrode pad on the second functional element and the rewiring.   15. The semiconductor device according to claim 13, wherein the electrode pad on the second functional element and the rewiring are made of the same kind of material.   The protective resin is provided on the second functional surface side of the second semiconductor chip so as to cover the insulating film and the rewiring. The semiconductor device described.   The side surface of the second semiconductor chip and the side surface of the protective resin are flush with each other, and the outer shape of the semiconductor device is a rectangular parallelepiped shape by the protective resin. The semiconductor device according to any one of the above.   In the rewiring, a plurality of the exteriors each made of metal, penetrating the protective resin from a predetermined position of a part formed on the non-opposing region and a part formed on the first semiconductor chip. 21. The semiconductor device according to claim 1, wherein the connection terminal is erected.   The semiconductor device according to any one of claims 1 to 21, wherein the external connection terminal is made of any one of copper, nickel, gold, and tungsten.   23. The semiconductor device according to claim 1, wherein an external shape of the external connection terminal is a columnar shape or a quadrangular prism shape.   The external connection terminal erected from a portion on the non-opposing region of the rewiring is longer than the external connection terminal erected from a portion of the rewiring on the first semiconductor chip. The semiconductor device according to claim 21.   25. The semiconductor device according to claim 1, wherein a metal ball as an external connection member is bonded to a tip of the external connection terminal.   10. The semiconductor device according to claim 1, wherein the insulating film is formed thicker in a portion on the non-opposing region than a portion on the first semiconductor chip. 11. . A plurality of the external connection terminals are provided,
The surface of the insulating film on which the rewiring is formed has a flat surface extending from the non-opposing region to the first semiconductor chip,
27. The semiconductor device according to claim 26, wherein the plurality of external connection terminals have the same length.   28. The semiconductor device according to claim 26, wherein the rewiring is connected to an electrode pad on the second functional element through an opening formed in the insulating film.   29. The semiconductor device according to claim 26, wherein in the opening, the rewiring is formed along an inner wall surface of the opening.   30. The semiconductor device according to claim 29, wherein an inner region of the opening is filled with the protective resin. An opening is formed in the insulating film,
The rewiring is connected to the second functional element through the opening of the insulating film, to the second functional element through the opening of the insulating film, and to the second functional element. The semiconductor device according to claim 1, further comprising a second rewiring connected to the first back surface of the first semiconductor chip.   32. The semiconductor device according to claim 31, wherein a central portion of the first back surface of the first semiconductor chip is not covered with the insulating film but covered with the second rewiring.   33. The semiconductor device according to claim 31, wherein a metal ball is connected to the rewiring through the external connection terminal. A plurality of the external connection terminals are provided,
34. The part of the plurality of external connection terminals is electrically connected to the first back surface of the first semiconductor chip through the second rewiring. 2. The semiconductor device according to claim 1.   35. The any one of claims 31 to 34, wherein the first back surface of the first semiconductor chip can be set to a predetermined potential via the external connection terminal connected to the second rewiring. 2. The semiconductor device according to claim 1.   35. The semiconductor device according to claim 34, wherein the external connection terminal electrically connected to the first back surface of the first semiconductor chip through the second rewiring is a grounding terminal. .   2. The semiconductor device according to claim 1, wherein an opening having a width slightly smaller than that of the external connection terminal is formed in a portion of the insulating film covering the first semiconductor chip.   38. The semiconductor device according to claim 37, wherein the heat dissipation terminal and the external connection terminal are made of the same metal material.   The semiconductor device according to claim 37 or 38, wherein a metal ball is bonded to a tip of the heat radiating terminal.   Between the first back surface of the first semiconductor chip and the heat radiating terminal, a conductive film made of the same material as the rewiring and having substantially the same thickness as the rewiring is interposed. 40. The semiconductor device according to any one of claims 37 to 39, wherein:   41. The semiconductor device according to claim 37, wherein the heat radiating terminal is a terminal for grounding.   The semiconductor device according to any one of claims 37 to 41, wherein the first back surface of the first semiconductor chip can be grounded via the heat radiating terminal.   41. The semiconductor device according to claim 40, wherein the heat radiating terminal is bonded to the first back surface of the first semiconductor chip in proximity to the first back surface with the conductive film interposed therebetween. .   40. The semiconductor device according to claim 39, wherein a plurality of the heat radiating terminals and the metal balls are joined to the first back surface of the first semiconductor chip.   2. The semiconductor device according to claim 1, wherein an anti-diffusion film of a conductive material is formed over the entire first back surface of the first semiconductor chip.   46. The semiconductor device according to claim 45, wherein the diffusion prevention film is formed between the first back surface of the first semiconductor chip, the insulating film, and the heat dissipation terminal.   47. The semiconductor device according to claim 45, wherein the diffusion barrier film is also formed on a side surface of the first semiconductor chip.   48. The semiconductor device according to claim 45, wherein the diffusion prevention film is made of any one of titanium, titanium tungsten, nickel, titanium nitride, and tantalum nitride.   2. The semiconductor device according to claim 1, further comprising a back surface protective film formed on a second back surface that is a surface opposite to the second functional surface in the second semiconductor chip.   50. The semiconductor device according to claim 49, wherein the back surface protective film is made of a resin that is one of polyimide, polyimide amide, and epoxy.   2. The semiconductor device according to claim 1, wherein an opening is formed in the insulating film of the semiconductor device, and the opening is filled with a via conductor.   52. The semiconductor device according to claim 51, wherein the second functional element of the second semiconductor chip and the rewiring are electrically connected through the via conductor.   53. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of the first semiconductor chips.   54. Each of the first semiconductor chips is electrically connected to the second semiconductor chip with the first functional surface opposed to the second functional surface of the second semiconductor chip. The semiconductor device described.   37. A diffusion prevention film made of a conductive material is formed between the first back surface of the first semiconductor chip, the insulating film, and the rewiring. A semiconductor device according to 1.   The semiconductor device according to claim 13, wherein the opening is filled with a via conductor having a height substantially equal to the thickness of the insulating film in the non-opposing region.

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