KR20240049104A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package according to the present invention includes a base semiconductor chip, a chip structure mounted on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a base semiconductor chip surrounding the chip structure and the connection terminal. A molding film, wherein the chip structure includes a first semiconductor chip including a first front pad and a first back pad, and a second semiconductor chip located on the first semiconductor chip and including a second front pad and a second back pad. It includes a semiconductor chip, wherein a side surface of the first semiconductor chip and a side surface of the second semiconductor chip are aligned, the first semiconductor chip and the second semiconductor chip have the same integrated circuit, and the first back pad and The second front pad is in direct contact with the first back pad and a portion of the second front pad overlaps in plan view, and the first back pad and the second front pad include the same metal, and are integrated. can be formed.

Description

Semiconductor package and manufacturing method thereof}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a chip structure and a method of manufacturing the same.

A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, a semiconductor package mounts a semiconductor chip on a printed circuit board and electrically connects them using bonding wires or bumps. With the development of the electronics industry, various researches are being conducted to improve the reliability, high integration, and miniaturization of semiconductor packages.

The problem to be solved by the present invention is to provide a semiconductor package with improved structural stability.

Another problem to be solved by the present invention is to provide a semiconductor package with improved productivity.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the description below.

A semiconductor package according to an embodiment of the present invention for solving the above problem includes a base semiconductor chip, a chip structure mounted on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and the base semiconductor chip on the base semiconductor chip. It includes a chip structure and a molding film surrounding the connection terminal, wherein the chip structure is located on the first semiconductor chip and a first semiconductor chip including a first front pad and a first back pad, and a second front pad and An integrated circuit comprising a second semiconductor chip including a second back pad, wherein side surfaces of the first semiconductor chip and side surfaces of the second semiconductor chip are aligned, and the first semiconductor chip and the second semiconductor chip are identical to each other. wherein the first back pad and the second front pad are in direct contact with each other, and a portion of the first back pad and the second front pad overlap in a plan view, and the first back pad and the second front pad are overlapped. contains the same metal and is formed as a single piece.

A semiconductor package according to an embodiment of the present invention for solving the above problem includes a base semiconductor chip, a chip stack mounted on the base semiconductor chip and including chip structures, and a connection terminal located on the lower surface of each of the chip structures. and a molding film located on the base semiconductor chip and surrounding the chip stack and the connection terminals, wherein each of the chip structures includes an even number of semiconductor chips, wherein each of the semiconductor chips includes a circuit layer, a protective film, Comprising a through electrode and a semiconductor substrate, wherein the semiconductor substrate includes an active surface and an inactive surface opposite to the active surface, the circuit layer is located on the active surface, and the protective film is located on the inactive surface, In each of the chip structures, the semiconductor chips are stacked with the active surface and the inactive surface facing each other.

A method of manufacturing a semiconductor package according to an embodiment of the present invention to solve the above problem includes forming a chip structure including a first semiconductor chip and a second semiconductor chip, and providing the chip structure on a base semiconductor chip. , bonding the base semiconductor chip and the chip structure to each other by performing a heat treatment process, and forming a molding film surrounding the chip structure on the base semiconductor chip, wherein forming the chip structure is performed using the first 1 Forming a first substrate including a plurality of semiconductor chips, wherein the first substrate has a first active surface and a first inactive surface facing each other, and a second substrate including a plurality of second semiconductor chips. wherein the second substrate has a second active surface and a second inactive surface facing each other, and the first inactive surface of the first substrate is bonded to the second active surface of the second substrate to face each other. and cutting the first and second substrates by performing a sawing process.

In the semiconductor package according to an embodiment of the present invention, the semiconductor chips constituting the chip structure are directly bonded, so the volume of the non-conductive layer in the semiconductor package can be reduced. As a result, defects caused by a non-conductive layer with a high thermal expansion rate can be prevented, and a semiconductor package with improved structural stability can be provided. That is, as there is little bending within the chip structure, delamination between semiconductor chips bonded through hybrid bonding may not occur.

In the method of manufacturing a semiconductor package according to an embodiment of the present invention, substrates are bonded together in a face-to-back manner, and then a plurality of chip structures can be formed simultaneously through a sawing process. Since the semiconductor package is composed of semiconductor chips of the same type, the manufacturing method of the semiconductor package can be simplified.

1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.
Figure 2 is an enlarged view of portion A of Figure 1.
Figure 3 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.
Figures 4 and 5 are diagrams showing a semiconductor package according to another embodiment of the present invention, and Figure 5 is an enlarged view of portion B of Figure 4.
Figure 6 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.
7 is a cross-sectional view showing a semiconductor module or semiconductor package according to an embodiment of the present invention.
FIGS. 8 to 11 are drawings for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention, and FIG. 9 is an enlarged view of portion B of FIG. 8.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. The same reference signs may refer to the same elements throughout the specification.

1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor package may be provided. The semiconductor package may include a base semiconductor chip 100, a chip structure (UCS), a non-conductive layer 400, and a molding film 500. For example, the semiconductor package may be a stacked package using through vias. That is, a chip structure (UCS) in which semiconductor chips are stacked may be located on the base semiconductor chip 100.

A base semiconductor chip 100 may be provided. The base semiconductor chip 100 may include a circuit directly therein. Specifically, the base semiconductor chip 100 may include an electronic device such as a transistor. For example, the base semiconductor chip 100 may be a wafer level die made of a semiconductor such as silicon (Si). However, the present invention is not limited thereto. The base semiconductor chip 100 may be a printed circuit board (PCB) that does not include electronic devices such as transistors.

The base semiconductor chip 100 may include a circuit layer 110, a through via 120, a rear pad 130, a protective film 140, and a front pad 150.

The circuit layer 110 may be provided on the lower surface of the base semiconductor chip 100. Circuit layer 110 may include the integrated circuit described above. For example, the circuit layer 110 may be a memory circuit, a logic circuit, or a combination thereof. The circuit layer 110 may include electronic devices such as transistors, insulating patterns, and wiring patterns.

The through via 120 may vertically penetrate the base semiconductor chip 100. For example, the through via 120 may connect the top surface of the base semiconductor chip 100 and the circuit layer 110. The through via 120 and the circuit layer 110 may be electrically connected. A plurality of through vias 120 may be provided. Although not shown in the drawing, an insulating film surrounding the through via 120 may be provided. For example, the insulating film may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k film.

The rear pad 130 may be disposed on the top surface of the base semiconductor chip 100. The rear pad 130 may be connected to the through via 120. A plurality of rear pads 130 may be provided. In this case, each of the rear pads 130 may be connected to the corresponding through vias 120, so the arrangement of the rear pads 130 may follow the arrangement of the through vias 120. The rear pad 130 may be connected to the circuit layer 110 through a through via 120. The back pad 130 may include various metal materials such as copper (Cu), aluminum (Al), and/or nickel (Ni).

The protective film 140 may be disposed on the upper surface of the base semiconductor chip 100 and surround the rear pad 130. The protective film 140 may expose the rear pad 130. That is, the top surface of the protective film 140 may be coplanar with the top surface of the rear pad 130. The base semiconductor chip 100 may be protected by a protective film 140 . For example, the protective film 140 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

The front pad 150 may be disposed on the lower surface of the base semiconductor chip 100. Specifically, the front pad 150 may be exposed on the lower surface of the circuit layer 110. That is, the lower surface of the front pad 150 may be coplanar with the lower surface of the circuit layer 110. The front pad 150 may be electrically connected to the circuit layer 110. A plurality of front pads 150 may be provided. For example, the front pad 150 may include various metal materials such as copper (Cu), aluminum (Al), and/or nickel (Ni).

Although not shown in the drawing, the base semiconductor chip 100 may further include a lower protective layer. The lower protective film may be disposed on the lower surface of the base semiconductor chip 100 to cover the circuit layer 110. The circuit layer 110 may be protected by a lower protective film. The lower protective film may expose the front pad 150. For example, the lower protective layer may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

An external terminal 160 may be provided on the lower surface of the base semiconductor chip 100. The external terminal 160 may be disposed on the front pad 150. The external terminal 160 may be electrically connected to the circuit layer 110 and the via 120. A plurality of external terminals 160 may be provided. Each of the external terminals 160 may be connected to a plurality of front pads 150 provided. The semiconductor package may be electrically connected to another semiconductor package or external electronic device through the external terminal 160. For example, the external terminal 160 is tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce). It may be an alloy containing at least one or more of the following.

Alternatively, the external terminal 160 may be disposed below the through via 120. In this case, the through via 120 may penetrate the circuit layer 110 and be exposed on the lower surface of the circuit layer 110. The external terminal 160 may be directly connected to the through via 120.

A chip structure (UCS) may be located on the base semiconductor chip 100. The chip structure (UCS) may include a first semiconductor chip 210 and a second semiconductor chip 220. The first and second semiconductor chips 210 and 220 may be of the same type. For example, the first and second semiconductor chips 210 and 220 may be memory chips. The first and second semiconductor chips 210 and 220 may be sequentially stacked on the base semiconductor chip 100.

The first semiconductor chip 210 is located on the base semiconductor chip 100 and includes a first semiconductor substrate 210a, a first circuit layer 211, a first through via 212, and a first backside pad 213. , may include a first protective film 214, a first front pad 215, and a connection terminal 219.

The first circuit layer 211 may be provided on the lower surface of the first semiconductor substrate 210a. The first circuit layer 211 may include an integrated circuit. The first circuit layer 211 may include electronic devices such as transistors, insulating patterns, and wiring patterns.

The first through via 212 may penetrate the first semiconductor substrate 210a in a vertical direction. The first through via 212 may connect the first front pad 215 and the first rear pad 213. That is, the first through via 212 may be electrically connected to the first circuit layer 211. A plurality of first through vias 212 may be provided. An insulating film (not shown) may be provided to surround the first through via 212. For example, the insulating film (not shown) may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k film.

The first protective film 214 may be provided on the top surface of the first semiconductor substrate 210a. The first protective film 214 may protect the first semiconductor chip 210. For example, the first protective layer 214 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

A first rear pad 213 may be disposed within the first protective film 214. The top surface of the first rear pad 213 may be exposed by the first protective film 214. The top surface of the first protective film 214 may be coplanar with the top surface of the first rear pad 213. The first rear pad 213 may be connected to the first through via 212.

A first front pad 215 may be disposed within the first circuit layer 211. Specifically, the lower surface of the first front pad 215 may be exposed by the first circuit layer 211. The lower surface of the first front pad 215 may be coplanar with the lower surface of the first circuit layer 211. The first front pad 215 may be connected to the first circuit layer 211. The first rear pad 213 and the first front pad 215 may be electrically connected by the first circuit layer 211 and the first through via 212. Each of the first rear pad 213 and the first front pad 215 may be provided in plural numbers. In this case, each of the first rear pads 213 and the first front pads 215 may be connected to the corresponding first through via 212. For example, the first rear pad 213 and the first front pad 215 may include various metal materials such as copper (Cu), aluminum (Al), and/or nickel (Ni).

The connection terminal 219 may be located below the first front pad 215 of the first semiconductor chip 210. That is, the connection terminal 219 may be disposed between the first front pad 215 of the first semiconductor chip 210 and the rear pad 130 of the base semiconductor chip 100. A plurality of connection terminals 219 are provided and can electrically connect the chip structure (UCS) and the base semiconductor chip 100. For example, the connection terminal 219 is tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), or cerium (Ce). It may be a solder ball or a solder bump made of an alloy containing at least one of the following.

Due to the connection terminal 219, the chip structure UCS and the base semiconductor chip 100 may be spaced apart from each other in the vertical direction. That is, the chip structure UCS may have a first distance H1 in a direction perpendicular to the base semiconductor chip 100. For example, the first distance H1 may be about 10 μm to 15 μm. Therefore, even if a large external particle with a size of about 10 μm is located between the chip structure (UCS) and the base semiconductor chip 100, the connection terminal 219 prevents the chip structure (UCS) from being connected to the base semiconductor chip 100. ) can prevent electrical short circuits. In other words, defects in the semiconductor package caused by external particles can be prevented.

The second semiconductor chip 220 is located on the first semiconductor chip 210 and includes a second semiconductor substrate 220a, a second circuit layer 221, a second protective film 224, a second through via 222, It may include a second front pad 225 and a second rear pad 223.

The second circuit layer 221 may be provided on the lower surface of the second semiconductor substrate 220a. The second protective film 224 may be provided on the top surface of the second semiconductor substrate 220a. The second through via 222 may penetrate the second semiconductor substrate 220a in a vertical direction and connect the second front pad 225 and the second back pad 223. The second rear pad 223 may be disposed within the second protective film 224 . The second front pad 225 may be disposed within the second circuit layer 221.

In other words, each of the configurations of the second semiconductor chip 220 may be substantially the same as the configuration of the corresponding first semiconductor chip 210. That is, the second semiconductor chip 220 may be the same semiconductor chip as the first semiconductor chip 210.

A non-conductive layer 400 may be provided between the chip structure (UCS) and the base semiconductor chip 100. That is, the non-conductive layer 400 may fill the space between the first semiconductor chip 210 and the base semiconductor chip 100 and surround the connection terminal 219. The non-conductive layer 400 may contact the lower surface of the first semiconductor chip 210 and the upper surface of the base semiconductor chip 100. Additionally, the non-conductive layer 400 may protrude outside the side of the first semiconductor chip 210. That is, the horizontal length of the non-conductive layer 400 may be greater than the horizontal length of the first semiconductor chip 210. Because of this, the non-conductive layer 400 may cover a portion of the side surface of the first semiconductor chip 210.

For example, the non-conductive layer 400 is an epoxy-based material that does not contain conductive particles, such as a non-conductive film (NCF), a non-conductive paste (NCP), and/or an insulating polymer. May contain substances. That is, by using the non-conductive layer 400 without conductive particles, it may be possible to miniaturize the connection terminals 219 without electrical shorting between adjacent connection terminals 219. Additionally, the non-conductive layer 400 serves as an underfill to fill the space between the chip structure (UCS) and the base semiconductor chip 100, thereby improving the mechanical durability of the connection terminals 219.

A molding film 500 may be provided on the base semiconductor chip 100. The molding film 500 may cover the top surface of the base semiconductor chip 100. The side of the molding film 500 may be aligned with the side of the base semiconductor chip 100. The molding film 500 may surround the chip structure (UCS). That is, the molding film 500 may cover the side surfaces of the first and second semiconductor chips 210 and 220 and the top surface of the second semiconductor chip 220. Alternatively, the molding film 500 may expose the top surface of the second semiconductor chip 220. The outer surface of the molding film 500 may be spaced apart from the non-conductive layer 400. The molding film 500 may include an insulating material. For example, the molding film 500 may include epoxy molding compound (EMC).

The first semiconductor chip 210 and the second semiconductor chip 220 constituting the chip structure (UCS) may be in direct contact with each other without a separate connection terminal. That is, the non-conductive layer 400 may not be provided between the first semiconductor chip 210 and the second semiconductor chip 220. That is, the volume of the non-conductive layer 400 in the semiconductor package may be reduced. As a result, warpage caused by the non-conductive layer 400 with a high coefficient of thermal expansion can be prevented, and separation between the first and second semiconductor chips 210 and 220 may not occur. Accordingly, a semiconductor package with improved structural stability can be provided.

Figure 2 is an enlarged view of portion A of Figure 1.

Hereinafter, for convenience of explanation, description of the same items as those described with reference to FIG. 1 will be omitted and differences will be described in detail.

Referring to FIG. 2 , the first semiconductor substrate 210a of the first semiconductor chip 210 may include a first upper surface 210t and a first lower surface 210b. The first upper surface 210t of the first semiconductor substrate 210a and the first lower surface 210b of the first semiconductor substrate 210a may face each other. The first circuit layer 211 may be located on the first lower surface 210b of the first semiconductor substrate 210a. The first protective film 214 may be positioned on the first upper surface 210t of the first semiconductor substrate 210a. That is, the first lower surface 210b of the first semiconductor substrate 210a may be an active surface of the first semiconductor chip 210. The first upper surface 210t of the first semiconductor substrate 210a may be an inactive surface of the first semiconductor chip 210. The active surface and the inactive surface of the first semiconductor chip 210 may face each other.

Like the first semiconductor substrate 210a, the second semiconductor substrate 220a of the second semiconductor chip 220 may include a second upper surface 220t and a second lower surface 220b facing each other. That is, the second lower surface 220b of the second semiconductor substrate 220a may be the active surface of the second semiconductor chip 210. The second upper surface 220t of the second semiconductor substrate 220a may be an inactive surface of the second semiconductor chip 210. The active surface and the inactive surface of the second semiconductor chip 210 may face each other.

Hereinafter, in this specification, the interface between the semiconductor substrate and the circuit layer of each semiconductor chip may correspond to the active surface of the corresponding semiconductor chip. Additionally, the interface between the semiconductor substrate and the protective film of each semiconductor chip may correspond to an inactive surface of the semiconductor chip.

The first circuit layer 211 of the first semiconductor chip 210 may include a first integrated circuit 211a, a first wiring pattern 211b, and a first insulating pattern 211c. The first integrated circuit 211a may be located on the active surface of the first semiconductor chip 210. For example, the first integrated circuit 211a may include a memory circuit. The first integrated circuit 211a may be connected to the first through via 212 and the first front pad 215 through the first wiring pattern 211b. The first insulating pattern 211c may cover the first integrated circuit 211a and the first wiring pattern 211b on the active surface of the first semiconductor chip 210.

The second circuit layer 221 of the second semiconductor chip 220 may include a second integrated circuit 221a, a second wiring pattern 221b, and a second insulating pattern 221c. The second integrated circuit 221a may be located on the active surface of the second semiconductor chip 210. For example, the second integrated circuit 221a may include a memory circuit. The second integrated circuit 221a may be connected to the second through via 222 and the second front pad 225 through the second wiring pattern 221b. The second insulating pattern 221c may cover the second integrated circuit 211a and the second wiring pattern 211b on the active surface of the second semiconductor chip 210.

Since the second semiconductor chip 220 is the same semiconductor chip as the first semiconductor chip 210, the second integrated circuit 221a and the first integrated circuit 211a may include the same memory circuit. Additionally, the second wiring pattern 221b may have the same shape as the first wiring pattern 211b.

The second semiconductor chip 220 is located on the first semiconductor chip 210, and the second semiconductor chip 220 and the first semiconductor chip 210 may be in contact with each other. The first protective film 214 of the first semiconductor chip 210 and the second circuit layer 221 of the second semiconductor chip 220 may be in direct contact. In other words, the inactive side of the first semiconductor chip 210 and the active side of the second semiconductor chip 220 may face each other. That is, the first and second semiconductor chips 210 and 220 may be bonded in a face-to-back manner.

The first rear pad 213 of the first semiconductor chip 210 and the second front pad 225 of the second semiconductor chip 220 may be in direct contact. At this time, the first rear pad 213 and the second front pad 225 may form inter-metal hybrid bonding. In this specification, hybrid bonding refers to bonding in which two components containing the same type of material fuse at their interface. For example, the first rear pad 213 and the second front pad 225 bonded to each other may have a continuous configuration, and the boundary between the first rear pad 213 and the second front pad 225 is It may not be visible visually. In other words, the first back pad 213 and the second front pad 225 may be made of the same material, so there may be no interface between the first back pad 213 and the second front pad 225. That is, the first rear pad 213 and the second front pad 225 may be provided as one component. The first rear pad 213 and the second front pad 225 may be combined with each other to form an integrated unit.

However, the side surface of the first rear pad 213 and the side surface of the second front pad 225 may not be aligned. That is, the first rear pad 213 is in direct contact with the second front pad 225, but the first rear pad 213 may not be vertically aligned with the second front pad 225. From a plan view, the first rear pad 213 may only partially overlap the second front pad 225 . In other words, a portion of the first back pad 213 may be in contact with the second insulating pattern 221c of the second circuit layer 221, and the second front pad 225 may be in contact with a portion of the first protective film 214. You can access it.

Alternatively, the side surface of the first rear pad 213 and the side surface of the second front pad 225 may be aligned. From a plan view, the first rear pad 213 and the second front pad 225 may completely overlap.

The first protective layer 214 of the first semiconductor chip 210 and the second insulating pattern 221c of the second circuit layer 221 of the second semiconductor chip 220 may contact each other. At this time, the first protective film 214 and the second insulating pattern 221c may form oxide, nitride, or oxynitride hybrid bonding. That is, the first protective film 214 and the second insulating pattern 221c bonded to each other may have a continuous configuration, and the boundary between the first protective film 214 and the second insulating pattern 221c is not visually visible. You can. In other words, the first protective film 214 and the second insulating pattern 221c are made of the same material (for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), etc. ), and there may be no interface between the first protective film 214 and the second insulating pattern 221c. That is, the first protective film 214 and the second insulating pattern 221c can be combined with each other to form an integrated body.

In another embodiment, the first protective layer 214 and the second insulating pattern 221c may be made of different materials. In this case, the first protective film 214 and the second insulating pattern 221c may not have a continuous configuration, and the boundary between the first protective film 214 and the second insulating pattern 221c may be visually visible. .

The side surface 210s of the first semiconductor chip 210 may be aligned with the side surface 220s of the second semiconductor chip 220. In other words, the side surfaces of the first and second semiconductor substrates 210a and 220a, the side surfaces of the first and second circuit layers 211 and 221, and the first and second protective films 214 and 224. The sides can all be aligned.

Figure 3 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

Hereinafter, for convenience of explanation, description of the same items as those described with reference to FIGS. 1 and 2 will be omitted and differences will be described in detail.

Referring to FIG. 3, a chip stack CS may be provided on the base semiconductor chip 100. The chip stack (CS) may include a plurality of chip structures (UCS). Each of the plurality of chip structures (UCS) may be substantially the same as the chip structure (UCS) described in FIGS. 1 and 2 .

The chip structure UCS may include a first semiconductor chip 210 and a second semiconductor chip 220 . The first and second semiconductor chips 210 and 220 may be in direct contact with each other. The inactive side of the first semiconductor chip 210 may face the active side of the second semiconductor chip 220. That is, the first semiconductor chip 210 and the second semiconductor chip 220 may be bonded in a face-to-back manner.

Additionally, the first back pad 213 of the first semiconductor chip 210 and the second front pad 225 of the second semiconductor chip 220 may include the same metal material and be formed as one piece. That is, the first rear pad 213 and the second front pad 225 may form hybrid bonding.

A connection terminal 219 may be provided between the plurality of chip structures (UCS). Specifically, the connection terminal 219 may be located between the first front pad 215 of the first semiconductor chip 210 and the second rear pad 223 of the second semiconductor chip 220.

Because of this, the plurality of chip structures UCS may be spaced apart from each other in the vertical direction. The vertical distance between the plurality of chip structures UCS may be the second distance H2. For example, the second distance H2 may be about 10 μm to about 15 μm. That is, the second distance H2 may be substantially the same as the first distance H1 in FIG. 1 . Therefore, even if a large external particle with a size of about 10 μm is located between the chip structures UCS, an electrical short circuit may not occur between the chip structures UCS due to the connection terminal 219. In other words, defects in the semiconductor package caused by external particles can be prevented.

Each of the non-conductive layers 400 is provided between a plurality of chip structures (UCS) and may surround the connection terminal 219. That is, the non-conductive layers 400 may cover the lower surface of the first semiconductor chip 210 and the upper surface of the second semiconductor chip 220. The non-conductive layers 400 may cover a portion of the side surface of the first semiconductor chip 210 and a portion of the side surface of the second semiconductor chip 220 . The lower the non-conductive layers 400 are, the greater the load they receive from above, so their length in the horizontal direction can be increased. That is, the horizontal length of the non-conductive layer 400 located at the bottom may be greater than the horizontal length of the non-conductive layer 400 located at the top.

The molding film 500 may surround the chip stack CS on the base semiconductor chip 100. In other words, the molding film 500 may surround a plurality of chip structures (UCS) and non-conductive layers 400 on the base semiconductor chip 100. The side of the molding film 500 may be aligned with the side of the base semiconductor chip 100.

Figures 4 and 5 are diagrams showing a semiconductor package according to another embodiment of the present invention, and Figure 5 is an enlarged view of portion B of Figure 4.

Hereinafter, for convenience of explanation, description of the same items as those described with reference to FIG. 1 will be omitted and differences will be described in detail.

Referring to FIGS. 4 and 5 , a chip stack CS may be provided on the base semiconductor chip 100 . The chip stack (CS) may include a plurality of chip structures (UCS). Each of the chip structures UCS may include first to fourth semiconductor chips 210, 220, 230, and 240. The first to fourth semiconductor chips 210, 220, 230, and 240 each include first to fourth semiconductor substrates 210a, 220a, 230a, and 240a, and first to fourth circuit layers 211, 221, and 231. , 241), and first to fourth protective films 214, 224, 234, and 244.

In one chip structure (UCS), the first to fourth semiconductor chips 210, 220, 230, and 240 may be stacked in order while directly contacting each other. The first protective film 214 of the first semiconductor chip 210 and the second circuit layer 221 of the second semiconductor chip 220 may be in contact with each other. The second protective film 224 of the second semiconductor chip 220 and the third circuit layer 231 of the third semiconductor chip 230 may be in contact with each other. The third protective film 234 of the third semiconductor chip 230 and the fourth circuit layer 244 of the fourth semiconductor chip 240 may be in contact with each other. In other words, the inactive side of the first semiconductor chip 210 and the active side of the second semiconductor chip 220 may face each other. The inactive side of the second semiconductor chip 220 and the active side of the third semiconductor chip 230 may face each other. The inactive side of the third semiconductor chip 230 and the active side of the fourth semiconductor chip 240 may face each other. That is, the first to fourth semiconductor chips 210, 220, 230, and 240 may be bonded to each other in a face-to-back manner.

Specifically, the first rear pad 213 and the second front pad 225 may be in direct contact. The first rear pad 213 and the second front pad 225 may include the same metal material and be formed as one piece. That is, the first rear pad 213 and the second front pad 225 can form hybrid bonding. The second rear pad 223 and the third front pad 235 and the third rear pad 233 and the fourth front pad 245 are substantially similar to the first rear pad 213 and the second front pad 225. may be the same. In other words, the second rear pad 223 and the third front pad 235 may form hybrid bonding with each other. The third rear pad 233 and the fourth front pad 245 may form hybrid bonding with each other.

From a plan view, the back pad and front pad that are in contact with each other may only partially overlap. In other words, the sides of the rear pad and the sides of the front pad that are in contact with each other may not be aligned. That is, the side of the first rear pad 213, the side of the second front pad 225, the side of the second rear pad 223, the side of the third front pad 235, and the third rear pad 233. The side surface and the side surface of the fourth front pad 245 may not be aligned.

Unlike the back pad and front pad that contact each other, side surfaces of the first to fourth semiconductor chips 210, 220, 230, and 240 may be aligned. That is, the side surfaces of the first to fourth circuit layers 211, 221, 231, and 241, the side surfaces of the first to fourth semiconductor substrates 210a, 220a, 230a, and 240a, and the first to fourth protective films. The sides of fields 214, 224, 234, and 244 may be aligned.

The first to fourth semiconductor chips 210, 220, 230, and 240 may be of the same type. More specifically, the first to fourth semiconductor chips 210, 220, 230, and 240 may be memory semiconductor chips. That is, the first to fourth integrated circuits 211a, 221a, 231a, and 241a of the first to fourth circuit layers 211, 221, 231, and 241 may be the same memory circuit.

The non-conductive layer 400 of FIG. 3 may not be provided between the chip structures (UCS). That is, the molding film 500 may surround the connection terminals 219 while contacting the lower and upper surfaces of the chip structure UCS. Because of this, warpage caused by the non-conductive layer 400 with a high coefficient of thermal expansion can be prevented. Separation may not occur between the first to fourth semiconductor chips 210, 220, 230, and 240 of the chip structure UCS. Accordingly, a semiconductor package with improved structural stability can be provided.

Figure 6 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

Hereinafter, for convenience of explanation, description of the same items as those described with reference to FIGS. 1 to 5 will be omitted and differences will be described in detail.

Referring to FIG. 6, a chip stack CS may be provided on the base semiconductor chip 100. The chip stack (CS) may include one chip structure (UCS). That is, the chip stack CS may be substantially the same as the chip structure UCS. The chip structure UCS may include first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280. The first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280 may be the same memory semiconductor chip.

The first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280 may be stacked in order while directly contacting each other on the base semiconductor chip 100. The contact between the first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280 may be substantially the same as that described in FIGS. 1 to 5. That is, the first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280 may be bonded in a face-to-back manner. Between adjacent semiconductor chips, the active surface of one semiconductor chip may face the inactive surface of another semiconductor chip.

In addition, the front pads (215, 225, 235, 245, 255, 265, 275, 285) and rear pads (213, 223, 233, 243, 253, 263, 273, 283) in contact with each other can form hybrid bonding. . From a plan view, the front pads (215, 225, 235, 245, 255, 265, 275, 285) and rear pads (213, 223, 233, 243, 253, 263, 273, 283) that are in contact with each other only partially overlap. You can. Side surfaces of the first to eighth semiconductor chips 210, 220, 230, 240, 250, 260, 270, and 280 may be aligned.

The chip structure (UCS) may include a plurality of semiconductor chips. Specifically, an even number of identical semiconductor chips may be provided in one chip structure (UCS). For example, one chip structure (UCS) may be provided with 2, 4, 6, or 8 semiconductor chips. The semiconductor package of the present invention may include an even number of semiconductor chips. That is, in the method of manufacturing a semiconductor package, a semiconductor package can be efficiently manufactured if an even number of semiconductor chips constituting one chip structure (UCS) are provided.

7 is a cross-sectional view showing a semiconductor module or semiconductor package according to an embodiment of the present invention.

Referring to FIG. 7, the semiconductor module or semiconductor package includes a module substrate 910, a chip stack package 930 and a graphics processing unit 940 (GPU) mounted on the module substrate 910, and a chip stack package 930. It may be, for example, a memory module including an external molding film 950 covering the graphics processing unit 940. The semiconductor module may further include an interposer 920 provided on the module substrate 910.

A module substrate 910 may be provided. The module board 910 may include a printed circuit board (PCB).

Module terminals 912 may be disposed below the module substrate 910. The module substrate 910 may include solder balls or solder bumps, and may include a ball grid array (BGA) or a fine ball grid depending on the type and arrangement of the module substrate 910. It may be provided in the form of an array (fine ball-grid array: FBGA) or land grid array (LGA).

An interposer 920 may be provided on the module substrate 910. The interposer 920 may include first substrate pads 922 exposed on the top surface of the interposer 920, and second substrate pads 924 exposed on the bottom surface of the interposer 920. The interposer 920 can rewire the chip stack package 930 and the graphics processing unit 940.

The interposer 920 may be mounted on the module board 910 using a flip chip method. For example, the interposer 920 may be mounted on the module board 910 using board terminals 926 provided on the second board pads 924. The board terminals 926 may include solder balls or solder bumps. A first underfill film 928 may be provided between the module substrate 910 and the interposer 920.

A chip stack package 930 may be placed on the interposer 920. The chip stack package 930 may have a structure that is substantially the same as or similar to the semiconductor package described with reference to FIGS. 1 to 5 .

The chip stack package 930 may be mounted on the interposer 920. For example, the chip stack package 930 may be connected to the first substrate pads 922 of the interposer 920 through the external terminals 160 of the base semiconductor chip 100. A second underfill layer 932 may be provided between the chip stack package 930 and the interposer 920. The second underfill film 932 may fill the space between the interposer 920 and the base semiconductor chip 100 and surround the external terminals 160 of the base semiconductor chip 100.

A graphics processing unit 940 may be disposed on the interposer 920. The graphics processing unit 940 may be spaced apart from the chip stack package 930 in the horizontal direction. The graphics processing unit 940 may include logic circuitry. That is, the graphics processing unit 940 may be a logic chip. Bumps 942 may be provided on the lower surface of the graphics processing unit 940. For example, the graphics processing unit 940 may be connected to the first substrate pads 922 of the interposer 920 through bumps 942 . A third underfill film 944 may be provided between the interposer 920 and the graphics processing unit 940. The third underfill film 944 may fill the space between the interposer 920 and the graphics processing unit 940 and surround the bumps 942 .

An external molding film 950 may be provided on the interposer 920. The external molding film 950 may cover the top surface of the interposer 920. The external molding film 950 may surround the chip stack package 930 and the graphics processing unit 940. The external molding film 950 may include an insulating material. For example, the external molding film 950 may include epoxy molding compound (EMC).

FIGS. 8 to 11 are diagrams for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention, and FIG. 10 is an enlarged view of portion B of FIG. 9.

Referring to FIG. 8, the first substrate 10 may be formed. Forming the first substrate 10 may include forming a plurality of first semiconductor chips 210 of FIG. 1 on the base substrate 217 of the first substrate 10 . Forming the first substrate 10 may be performed through a semiconductor process. For example, a semiconductor process may include an exposure process, an etching process, a deposition process, an ion implantation process, and a cleaning process. The first substrate 10 may include a first circuit layer 211, a first semiconductor substrate 210a, a first through via 212, and a first protective film 214. Additionally, the first substrate 10 may include a first active surface 10b and a first inactive surface 10a. The first active surface 10b and the first inactive surface 10a may face each other. The first active surface 10b may be an interface between the first circuit layer 211 and the first semiconductor substrate 210a, and the integrated circuit of the first semiconductor chip 210 is on the first active surface 10b. can be located The first inactive surface 10a may be an interface between the first protective film 214 and the first semiconductor substrate 210a. That is, the first substrate 10 may be in a state before the plurality of first semiconductor chips 210 are separated.

A second substrate 20 may be formed. Forming the second substrate 20 may be substantially the same as forming the first substrate 10 . That is, a plurality of second semiconductor chips 220 of FIG. 1 may be formed on the base substrate (not shown) of the second substrate 20 . The second substrate 20 may include a second circuit layer 221, a second semiconductor substrate 220a, a second through via 222, and a second protective film 224. Additionally, the second substrate 20 may also include a second active surface 20b and a second inactive surface 20a facing each other. The second active surface 20b may be an interface between the second circuit layer 221 and the second semiconductor substrate 220a, and the integrated circuit of the second semiconductor chip 220 is on the second active surface 20b. can be located The first inactive surface 20a may be an interface between the second protective film 224 and the second semiconductor substrate 220a. Thereafter, the base substrate of the second substrate 20 may be removed through a polishing process.

Afterwards, the second substrate 20 is placed on the first substrate 10 and can be in direct contact with each other. That is, the upper surface of the first substrate 10 and the lower surface of the second substrate 20 may be located on the same plane. The first protective film 214 of the first substrate 10 and the second circuit layer 221 of the second substrate 20 may be in direct contact.

Afterwards, a heat treatment process may be performed on the first substrate 10 and the second substrate 20. The first rear pad 213 and the second front pad 225 may be bonded through a heat treatment process. For example, the first rear pad 213 and the second front pad 225 may be combined to form an integrated body. The combination of the first rear pad 213 and the second front pad 225 may proceed naturally. Specifically, the first rear pad 213 and the second front pad 225 may be made of the same metal material (eg, copper (Cu), etc.). By intermetallic hybrid bonding by surface activation at the interface of the first back pad 213 and the second front pad 225 that are in contact with each other, the first back pad 213 and the second front pad (225) 225) can be combined.

Additionally, the first protective film 214 and the second circuit layer 221 may be bonded through a heat treatment process. For example, the bonding of the first protective film 214 and the second circuit layer 221 may be a hybrid bonding of oxide, nitride, oxynitride, or carbonitride.

As a result, the second substrate 20 can be directly bonded to the first substrate 10. The first inactive surface 10a of the first substrate 10 and the second active surface 20b of the second substrate 20 may face each other. That is, the first substrate 10 and the second substrate 20 may be bonded in a wafer-to-wafer form and in a face-to-back manner.

Referring to FIG. 9, a polishing process may be performed on the lower surface of the first substrate 10. Polishing the lower surface of the first substrate 10 may be performed with the first and second substrates 10 and 20 turned over. That is, the lower surface of the first substrate 10 may be positioned highest. The base substrate 217 of the first substrate 10 may be removed due to the polishing process. Because of this, the thickness of the first substrate 10 may be reduced. The thickness of the first substrate 10 may be the same as the thickness of the second substrate 20. The first front pad 215 of the first substrate 10 may be exposed to the outside.

Thereafter, connection terminals 219 may be attached to the lower surface of the first substrate 10 . Specifically, each of the connection terminals 219 may be formed on the first front pad 215 exposed through a polishing process.

9 and 10, after forming the connection terminals 219, a sawing process may be performed. The sawing process may be performed along the sawing line (SL) of the first and second substrates 10 and 20. The first and second substrates 10 and 20 may be cut due to the sawing process. That is, the chip structures (UCS) of FIG. 1 may be formed through the sawing process. For example, the sawing process may utilize blades, lasers, or plasma.

That is, the first and second substrates 10 and 20 can be bonded in a wafer-to-wafer form and then cut through a single sawing process. Accordingly, the first and second substrates 10 and 20 may have the same cut surface, but the first rear pad 213 and the second front pad 215 may not be aligned. Cut surfaces of the first and second substrates 10 and 20 may be side surfaces of the chip structures UCS. That is, the side surfaces of each of the chip structures UCS may be aligned, but the side surfaces of the first back pad 213 and the side surfaces of the second front pad 225 may not be aligned. From a plan view, the first rear pad 213 and the second front pad 225 may only partially overlap.

According to the method of manufacturing a semiconductor package of the present invention, since the first and second substrates 10 and 20 do not contact each other face to face or back to back, the first and the second substrates 10 and 20 do not have structures that are mirror symmetrical to each other and may have the same structure. In other words, each of the first circuit layer 211, the first semiconductor substrate 210a, the first through via 212, and the first protective film 214 of the first substrate 10 is the first circuit layer 211 of the first substrate 10. It may be the same as the second circuit layer 221, the second semiconductor substrate 220a, the second through via 222, and the second protective film 224. The integrated circuit, wiring pattern, and insulation pattern constituting each of the first and second circuit layers 211 and 221 may also be the same. That is, the first substrate 10 may be a substrate formed through the same semiconductor process as the second substrate 20. Because of this, the manufacturing method for forming the first and second substrates 10 and 20 can be simplified.

Additionally, since the first and second substrates 10 and 20 are bonded in a wafer-to-wafer form and then a sawing process is performed, identical chip structures UCS can be formed simultaneously. Since the semiconductor package of the present invention includes identical chip structures (UCS), the manufacturing method of the semiconductor package can be simplified.

Referring to FIG. 11 , chip structures UCS may be located on the base semiconductor chip 100. For example, four chip structures (UCS) may be arranged vertically on the base semiconductor chip 100. The connection terminals 219 of the chip structures UCS may contact the upper surface of the chip structure UCS located below. The connection terminal 219 of the lowermost chip structure (UCS) may be in contact with the upper surface of the base semiconductor chip 100.

Thereafter, a thermocompression bonding process may be performed on the base semiconductor chip 100 and the chip structures (UCS) using the bonding tool 1000. Due to the thermocompression bonding process, the connection terminals 219 may reflow. The chip structures UCS may be combined with each other to form a chip stack CS. The chip stack CS may be mounted on the base semiconductor chip 100. That is, forming the chip stack CS and mounting the chip stack CS on the base semiconductor chip 100 may be performed simultaneously.

Referring again to FIG. 3, a molding film 500 may be formed on the base semiconductor chip 100. Forming the molding film 500 may include applying an insulating member on the chip stack CS and curing the insulating member. The molding film 500 may cover the chip stack CS. That is, the molding film 500 may surround the chip structures UCS on the base semiconductor chip 100. After the molding film 500 is formed, a planarization process may be performed on the molding film 500 to expose the chip structure (UCS), if necessary.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims (10)

Base semiconductor chip;
a chip structure mounted on the base semiconductor chip;
a connection terminal between the base semiconductor chip and the chip structure; and
A molding film surrounding the chip structure and the connection terminal on the base semiconductor chip,
The chip structure is:
A first semiconductor chip including a first front pad and a first back pad; and
A second semiconductor chip located on the first semiconductor chip and including a second front pad and a second back pad,
The side surfaces of the first semiconductor chip and the side surfaces of the second semiconductor chip are aligned,
The first semiconductor chip and the second semiconductor chip have the same integrated circuit,
The first back pad and the second front pad are in direct contact, and a portion of the first back pad and the second front pad overlap from a plan view,
The first back pad and the second front pad include the same metal and are formed as one piece. According to claim 1,
Each of the first and second semiconductor chips includes an active surface and an inactive surface opposing the active surface,
The integrated circuit of each of the first and second semiconductor chips is located on the active surface,
A semiconductor package wherein the inactive surface of the first semiconductor chip and the active surface of the second semiconductor chip face each other. According to claim 1,
A semiconductor package wherein the integrated circuit of the base semiconductor chip is of a different type from the integrated circuits of the first and second semiconductor chips. According to claim 1,
A semiconductor package in which a side surface of the molding film is vertically aligned with a side surface of the base semiconductor chip. According to claim 1,
A semiconductor package further comprising a non-conductive layer positioned between the chip structure and the base semiconductor chip. According to claim 1,
A semiconductor package wherein the distance between the chip structure and the base semiconductor chip is 10μm to 15μm. According to claim 1,
The connection terminal is provided on a lower surface of the base semiconductor chip and the first front pad of the first semiconductor chip, and includes a solder ball or solder bump. According to claim 1,
A semiconductor package in which a plurality of the chip structures are provided and stacked in a vertical direction. Base semiconductor chip;
a chip stack mounted on the base semiconductor chip and including chip structures;
Connection terminals located on the lower surfaces of each of the chip structures; and
A molding film located on the base semiconductor chip and surrounding the chip stack and the connection terminals,
Each of the chip structures includes an even number of semiconductor chips, each of the semiconductor chips including a circuit layer, a protective film, a through electrode, and a semiconductor substrate,
The semiconductor substrate includes an active surface and an inactive surface opposing the active surface,
The circuit layer is located on the active side, and the protective film is located on the inactive side,
In each of the chip structures, the semiconductor chips are stacked with the active surface and the inactive surface facing each other. According to clause 9,
Each of the semiconductor chips includes a front pad located in the circuit layer and a rear pad located in the protective film,
In each of the chip structures, the front pad includes the same metal as the back pad directly contacting the front pad, and is integrally formed.

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