JP4790237B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of embedding a silicon film in a recess.

  In general, a semiconductor device having a structure in which a conductive film such as a silicon film is embedded in a recess such as a groove or a step is conventionally known.

  In such a conventional method for manufacturing a semiconductor device, when a conductive film such as a silicon film is embedded in the recess, a seam portion extending in the height direction is generated at the center of the embedded silicon film.

  Conventionally, as a method for solving the generation of a seam portion in such a silicon film, for example, a method of positioning the upper surface of the silicon film above the contact hole when forming the silicon film in the contact hole is known. It has been.

  According to this method, the seam portion formed in the silicon film is not exposed on the surface of the silicon film, and the semiconductor device can be satisfactorily manufactured without being affected by the seam portion in a subsequent process. (See Patent Document 1 below).

  In addition, as a method for preventing the seam portion formed in the silicon film from being exposed in the contact hole, the etch back amount is set so that the impurity concentration distribution of the silicon film embedded in the contact hole is uniform. There is known a method for suppressing the non-uniformity of the image.

According to this method, since the impurity concentration distribution of the silicon film that causes the non-uniformity of the etch back of the silicon film is made uniform, the etch back amount is adjusted so that the formed seam portion is not exposed. (See Patent Document 2).
JP 2001-196477 A JP 2001-244335 A

  By the way, in the conventional method for manufacturing a semiconductor device, since the seam portion itself formed in the silicon film cannot be eliminated, depending on the etch back amount of the silicon film, the seam portion formed in the silicon film may be May be exposed.

  Thus, when an insulating film or the like is deposited on the silicon film in a state where the seam portion is exposed, the insulating film enters the exposed seam portion, and then the silicon film is etched back into the seam portion. There has been a problem that the insulating film that has entered remains as a residue.

  Furthermore, when the silicon film is etched, if the seam portion is exposed on the surface, the portion around the seam portion is first scraped, which makes it difficult to perform etching well. there were.

  In addition, when the silicon film is oxidized with the seam portion exposed, the silicon film is also oxidized through the seam portion.

  The present invention has been made in view of the above problems, and an object of the present invention is to eliminate a seam portion formed in silicon so that a residue remains after the silicon film is etched back. An object of the present invention is to provide a method of manufacturing a semiconductor device that can solve various problems.

The method of manufacturing a semiconductor device according to the present invention includes the steps of depositing a silicon film on an insulating film formed on the main surface of the recess or the semiconductor substrate formed on the main table surface of the semiconductor substrate, at least 1% oxygen And a step of eliminating the seam portion formed in the silicon film by performing a heat treatment at 1000 ° C. or higher in an atmosphere including the same . The silicon film after the step of eliminating the seam portion is a conductive film.

  According to the present invention, the seam portion formed in silicon can be eliminated by heat treatment. It is possible to prevent the seam portion from being exposed to the outside. As a result, it is possible to prevent residues from remaining after etching back the silicon film, and to perform etching well and to prevent the silicon film from being oxidized when the silicon film is oxidized. can do.

  A first embodiment of the present invention will be described with reference to FIG.

(Embodiment 1)
FIG. 1 is a cross-sectional view of an AG-AND type flash memory nonvolatile semiconductor memory device 20 to which the semiconductor device manufacturing method according to the first embodiment can be applied.

  As shown in FIG. 1, the AG-AND flash memory 20 includes, for example, a semiconductor substrate 10, an insulating film (first insulating film) 11 formed on the main surface of the semiconductor substrate 10, and an insulating film 11. A plurality of first electrodes 12a to 12d that are formed on the semiconductor substrate 10 and extend in one direction, and the insulating film 11 is formed between the first electrodes (first conductive films) 12a to 12d. Floating gate electrodes 13a to 13c and a word line (second conductive film) 14 disposed above the floating gate electrodes 13a to 13c and the first electrodes 12a to 12d.

  The semiconductor substrate 10 includes, for example, a substrate 15a made of P-type silicon (Si) single crystal, an n-type buried region 15b formed with (P) introduced therein, for example, The well 15c is formed on the upper surface side of the buried region and formed by introducing, for example, boron (B).

  The first electrodes 12a to 12d function as assist gate electrodes, a cap film 16 is formed on the upper surface side of the first electrodes 12a to 12d, and the side surfaces of the first electrodes 12a to 12d are made of, for example, silicon oxide. An insulating film 17 is formed. On the side surfaces of the insulating film 17 and the cap film 16, an insulating film 46 made of, for example, silicon oxide is formed.

  The floating gate electrodes 13a to 13c are formed so as to protrude upward from the first electrodes 12a to 12d. An insulating film (third insulating film) 18 is formed on the surfaces of the floating gate electrodes 13a to 13c. The insulating film 18 is formed by sequentially laminating silicon oxide, silicon nitride, and silicon oxide sequentially from the lower layer, and is formed of a so-called ONO film (laminated film). The thickness of the insulating film 18 is a silicon dioxide equivalent film thickness, for example, about 16 nm.

The word line 14 is formed so as to extend in a direction intersecting the first electrodes 12a to 12d, and is formed on the upper surface side of the conductive film 14a and the conductor film 14a formed on the upper surface side of the insulating film 18. Further, it is composed of a laminated film with the refractory metal silicide film 14b. The conductor film 14a is made of, for example, low-resistance polycrystalline silicon, and the refractory metal silicide film 14b is made of, for example, tungsten silicide (WSi _x ). On the upper surface of the word line 14 thus configured, an insulator film 19 made of, for example, silicon oxide is formed.

  Next, writing, reading and erasing operations of the AG-AND type flash memory 20 configured as described above will be described.

  As shown in FIG. 2, in the data write operation, for example, about 15 V is applied to the word line 14 connected to the selected memory cell, and 0 V is applied to the other word lines.

  Further, about 1V is applied to the first electrode 12b for forming the source of the selected memory cell, and about 7V is applied to the first electrode 12c for forming the drain of the selected memory cell.

  Thereby, an n-type inversion layer 20a for forming a source is formed on the main surface of the semiconductor substrate 10 below the first electrode 12b, and on the main surface of the semiconductor substrate 10 below the first electrode 12c, An n-type inversion layer 20b for forming the drain is formed.

  At this time, by applying 0 V to the other first electrodes 12a and 12d, an inversion layer is not formed below the first electrodes 12a and 12d, so that the selected memory cell and the non-selected Isolation between memory cells is performed.

  In this state, about 4V is applied to the common drain wiring connected to the formed inversion layer 20b, while 0V is applied to the global bit line connected to the formed inversion layer 20a.

  Therefore, a write current I1 flows from the formed inversion layer 20a to the inversion layer 20b. At this time, the charge accumulated in the n-type inversion layer 20a on the source side flows as a certain channel current, and the charge is efficiently injected into the floating gate electrode through the insulating film 11 (constant voltage injection method). As a result, data can be written to the selected memory cell at high speed.

  As shown in FIG. 3, in the data read, the direction of the read current I2 is opposite to the write operation. That is, the read current I2 flows from the global bit line to the common drain line. In this data read operation, for example, about 2 to 5 V is applied to the word line 14 to which the selected memory cell is connected. Further, by applying, for example, about 5 V to the first electrode 12b and the first electrode 12c for forming the source and drain of the selected memory cell, the main surface portion of the semiconductor substrate 10 facing the first electrode 12b An inversion layer 20c for forming a source is formed, and an inversion layer 20d for forming a drain is formed on the main surface of the semiconductor substrate 10 facing the first electrode 12c. At this time, for example, 0 V is applied to the other first electrodes 12a and 12d so that the inversion layer is not formed on the main surface portion of the semiconductor substrate 10 facing the first electrodes 12a and 12d. To isolate.

  Here, for example, about 0 V is applied to the global bit line to which the n-type inversion layer 20c for the source of the selected memory cell is connected. In this state, a voltage of about 1 V applied to the common drain wiring is supplied to the drain of the selected memory cell through the n-type inversion layer 20d. In this way, the selected memory cell is read.

  That is, since the threshold voltage of each memory cell changes depending on the state of the accumulated charge in the floating gate electrodes 13a to 13c, the current of the selected memory cell is changed depending on the current flowing between the source and drain of the selected memory cell. Data can be judged.

  Next, the data erasing operation will be described with reference to FIG. The data erasing operation is performed by FN (Fowlor Nordheim) tunnel emission from the floating gate electrodes 13 a to 13 c to the semiconductor substrate 10 by applying a negative voltage to the word line 14 to be selected.

  As shown in FIG. 4, for example, about −16 V is applied to the word line to be selected, while a positive voltage is applied to the semiconductor substrate 10. As a result, data charges accumulated in the floating gate electrodes 13a to 13c are discharged to the semiconductor substrate 10 through the insulator film 11 by utilizing the FN tunnel phenomenon, and data of a plurality of memory cells is obtained. Erase all at once.

  Next, a method for manufacturing the AG-AND type flash memory 20 configured as described above will be described.

  As shown in FIG. 5, first, an insulating film (first insulating film) 11 made of, for example, silicon oxide or the like is formed on the main surface of the semiconductor substrate 10 to have a thickness of, for example, about 9 nm in terms of silicon dioxide. Further, it is formed by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method.

  A conductor film (first conductor film) 40 made of, for example, low-resistance polycrystalline silicon is deposited thereon by a CVD (Chemical Vapor Deposition) method or the like so as to have a thickness of about 50 nm, for example. Further thereon, a cap film 16 made of, for example, silicon nitride is deposited by a CVD method or the like so as to have a thickness of about 70 nm, for example. Subsequently, an insulating film 41 made of, for example, silicon oxide is deposited on the cap film 16 by, for example, a CVD method using TEOS (Tetraethoxysilane) gas so as to have a thickness of about 250 nm. In this state, annealing is performed at 850 ° C. for 10 minutes in a nitrogen (N 2) atmosphere.

  Then, a hard mask film 42 made of, for example, low-resistance polycrystalline silicon is deposited on the insulating film 41 by a CVD method or the like so as to have a thickness of about 150 nm, for example. Furthermore, an antireflection film 43 made of, for example, silicon oxynitride (SiON) is deposited thereon by a plasma CVD method or the like so as to have a thickness of about 80 nm, for example.

  In FIG. 6, a resist pattern for forming the first electrode is formed on the antireflection film 43. In the exposure process at the time of forming the resist pattern, a Levenson type phase shift mask is used as a photomask. That is, a phase shift mask having a configuration in which the phase of light transmitted through adjacent transmission regions is inverted by 180 degrees is used.

  Using the resist pattern as an etching mask, the antireflection film 43 and the hard mask film 42 exposed therefrom are etched. Thus, the length in the width direction between the antireflection film 43 and the hard mask film 42 is set to 75 nm, and the interval between the stacked layers of the adjacent antireflection film 43 and the hard mask film 42 is formed to be 105 nm. . Patterns of the antireflection film 43 and the hard mask film 42 for forming the first electrodes 12a to 12d are formed by the etching process.

  Subsequently, as shown in FIG. 7, using the antireflection film 43 and the hard mask film 42 as an etching mask, the insulating film 41 and the cap film 16 exposed therefrom are etched. In the etching process, the antireflection film 43 is etched when the insulating film 41 and the cap film 16 are etched.

  8, the conductive film 40 is etched using the hard mask 42 as an etching mask, and the hard mask film 42 is etched when the conductive film 40 is etched. Therefore, the antireflection film 43 and the hard mask film 42 are not left after the etching process.

  The first electrodes 12a to 12d are patterned by etching the conductor film 40. At this time, the width direction dimension of the first electrodes 12a to 12d is, for example, about 75 nm, and the distance between the first electrodes 12a to 12d is, for example, about 105 nm.

  As shown in FIG. 9, an impurity such as boron is introduced into a region without the first electrodes 12 a to 12 d on the main surface portion of the semiconductor substrate 10 (wafer) by a normal ion implantation method or the like. This impurity introduction process makes a difference between the threshold voltage of the semiconductor substrate 10 below the first electrodes 12a to 12d and the threshold voltage of the semiconductor substrate 10 below the floating gate electrodes 13a to 13c. Process.

  By this process, the p-type impurity concentration under the floating gate electrodes 13a to 13c becomes higher than the p-type impurity concentration under the first electrodes 12a to 12d, so that the first electrodes 12a to 12a having relatively low p-type impurity concentrations. The threshold voltage of the semiconductor substrate 10 below 12d is lower than the threshold voltage of the semiconductor substrate 10 below the floating gate electrodes 13a to 13c. This boron introduction step may not be performed depending on circumstances. The inventors have confirmed that the flash memory 20 operates normally regardless of whether or not boron is introduced.

  Subsequently, as shown in FIG. 10, the semiconductor substrate 10 is subjected to a thermal oxidation process such as an ISSG oxidation method. Here, the insulating film 17 made of, for example, silicon oxide (SiO 2) is formed on the side surfaces of the first electrodes 12a to 12d by the thermal oxidation treatment. By forming the insulating film 17 with a thermal oxide film having good film quality, it is possible to improve the withstand voltage between the first electrodes 12a to 12d and the floating gate electrodes 13a to 13c. The thickness of the insulating film 17 (dimension in the direction horizontal to the main surface of the semiconductor substrate 10) is about 10 nm in terms of silicon dioxide. Moreover, the dimension of the width direction of the 1st electrodes 12a-12d will be set to about 65 nm by this thermal oxidation process, for example.

  Subsequently, as shown in FIG. 11, an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate 10 by, for example, a CVD method, and then etched back. By this insulating film etch-back process, a sidewall of the insulating film 46 is formed on the side surface of the laminated film of the first electrodes 12 a to 12 d, the cap film 16 and the insulating film 41.

  For this reason, the first electrodes 12 a to 12 d are covered with a stacked body (second insulating film) including the cap film 15, the insulating film 41, and the insulating film 46. Moreover, the recessed part 28 is formed between several laminated bodies.

  The crossing angle between the inner side surface (inner side surface) of the recess 28 and the main surface of the semiconductor substrate 10 is 87 ° or more and 90 ° or less with respect to the semiconductor substrate 10. That is, the crossing angle between the side surface of the laminated body including the cap film 15, the insulating film 41, and the insulating film 46 and the main surface of the semiconductor substrate 10 is 87 ° or more and 90 ° or less. .

  At this time, the insulating film 11 at the bottom of the recess 28 is removed, and the main surface of the semiconductor substrate 10 is exposed. Further, due to the formation of the sidewall of the insulating film 46, the dimension in the width direction of the recess 28 becomes, for example, about 65 nm.

  Here, when the boron introduction process is not performed, the boron introduction process can be performed after the formation of the insulating film 46 (side wall in the periphery).

  As shown in FIG. 12, by subjecting the semiconductor substrate 10 (wafer) to a thermal oxidation process such as an ISSG oxidation method, for example, oxidation is performed on the main surface of the semiconductor substrate 10 at the bottom of the recess 28, for example. After forming the insulating film made of silicon, heat treatment (oxynitriding treatment) is performed in a gas atmosphere containing nitrogen (N), so that nitrogen is segregated at the interface between the insulating film and the semiconductor substrate 10, thereby forming the recess 28. The insulating film 11 made of silicon oxynitride (SiON) is formed on the bottom. This insulating film 11 is a film functioning as a tunnel insulating film of the memory cell, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 9 nm.

  Subsequently, as shown in FIG. 13, a silicon film 50 made of, for example, low-resistance polycrystalline silicon is deposited on the main surface of the semiconductor substrate 10 by a CVD method or the like. The silicon film 50 may be a poly silicon film or an amorphous silicon film.

  At this time, the recess 28 is completely filled with the silicon film 50 so that no “void” is formed in the recess 28. In the first embodiment, as described above, the side surface of the recess 28 is made as vertical as possible with respect to the main surface of the semiconductor substrate 10, so that the “void” is not formed in the recess 28. Can be embedded well.

  When the silicon film 50 is deposited in the recess 50, a seam portion 51 is formed in the silicon film 50 along the height direction.

  The seam 51 is generated regardless of the aspect ratio which is the ratio of the bottom dimension of the recess 28 and the height dimension of the recess 28, but the silicon film 50 is formed in the recess 28 having an aspect ratio of 4 or more. In the case of depositing, it occurs with a high probability.

  As shown in FIG. 14, with the silicon film 50 deposited in the recess 28, the silicon film 50 is subjected to heat treatment at 1000 ° C. or more and 1200 ° C. or less in a nitrogen atmosphere containing 1% or more oxygen. When this heat treatment is performed, the silicon film 50 is recrystallized. During recrystallization, silicon diffuses into the seam portion 51, and the seam portion 51, which is a low-concentration silicon region, disappears.

  When the heat treatment temperature is 1000 ° C. or lower, silicon is not diffused well, and it is difficult to eliminate the seam portion 51. In addition, since the silicon film 50 recrystallized once does not diffuse silicon, it is difficult to eliminate the seam portion 51 in the subsequent heat treatment.

  The reason why the heat treatment is performed in an oxygen atmosphere of 1% or more is to suppress the generation of minute foreign matters caused by the heat treatment. That is, when heat treatment is performed in an atmosphere containing only nitrogen, there is a problem that the silicon film 50 is oxidized in the form of dots by residual oxygen, which becomes a mask for the subsequent silicon film 50.

Here, it is preferable to perform ion implantation toward the seam portion 51 formed in the silicon film 50 before the heat treatment. If ion implantation is performed before the heat treatment, the bond between the silicon structures in the seam portion 51 can be weakened. By applying the heat treatment to the silicon film 50 in such a state that the bonding of the silicon structure is weakened, the seam portion 51 is surely disappeared. Further, by setting the dose amount of ion implantation to 1 × 10 ¹⁵ / cm ³ or more, the bonding between the silicon structures in the seam portion 50 can be surely weakened, and the seam portion 51 is surely ensured by the heat treatment performed thereafter. Can be extinguished. Examples of ion species for ion implantation include As, B, BF2, N2, P, Sb, Si, and Ge.

  After the heat treatment of the silicon film 50, the oxide film generated on the surface of the silicon film 50 by the heat treatment is removed using hydrofluoric acid.

  Subsequently, as shown in FIG. 15, the silicon film 50 on the entire main surface of the semiconductor substrate 10 is etched back by anisotropic dry etching or chemical mechanical polishing (CMP). Apply. At this time, since the seam portion 51 is not formed in the silicon film 50, it is possible to etch back satisfactorily. That is, when the seam portion 51 is formed, the seam portion 51 is first removed, but the seam portion 51 has disappeared due to the heat treatment, so that the silicon film 50 can be etched back satisfactorily. Can do.

  By the etch back process or the CMP process, the silicon film 50 is left only in the recess 28. At this time, the depression from the upper surface of the insulating film 41 to the upper surface of the silicon film 50 is preferably within about 30 nm, for example.

  Next, as shown in FIG. 16, first, a resist pattern in which a memory region (a region where a memory cell group is arranged) is exposed and the rest is covered on the main surface of the semiconductor substrate 10 (wafer). Then, using this as an etching mask, the insulating films 41 and 46 exposed therefrom are etched by a dry etching method or the like. Thereby, the insulating film 46 is formed on the side surfaces of the first electrodes 12 a to 12 b and the cap film 16.

  Next, as shown in FIG. 17, first, an insulating film made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 10 (wafer) with a thickness of about 5 nm, and silicon nitride is formed on the upper surface of the insulating film. An insulating film 18 for the interlayer film is formed by depositing an insulating film having a thickness of about 8 nm on the upper surface of the insulating film by a CVD method or the like.

  At this time, the insulating film 18 is also formed on the upper surface of the silicon film 50. However, in the first embodiment, since the seam portion is not formed in the silicon film 50, the insulating film 18 enters the seam portion. Is prevented.

  Subsequently, a conductive film (conductive film) 14a made of, for example, low-resistance polycrystalline silicon on the insulating film 18 of the semiconductor substrate 10 and a conductive film having a lower resistance than the conductive film 14a, such as tungsten silicide, are used. A refractory metal silicide film (conductive film) 14b is deposited sequentially from the lower layer by a CVD method or the like. The conductor films 14a and 14b are patterned in a subsequent process to form the word line 14 of the memory cell MC. The thickness of the conductor film 14a is, for example, about 100 to 150 nm, and the thickness of the refractory metal silicide film 14b is, for example, about 100 nm.

  Thereafter, an insulating film 19 made of, for example, silicon oxide is deposited on the refractory metal silicide film 14b by a CVD method using TEOS gas or the like, and then a hard mask film made of, for example, low-resistance polycrystalline silicon is formed thereon. An antireflection film made of, for example, silicon oxynitride (SiON) is deposited thereon by the CVD method or the like.

  Next, a resist pattern for word line formation is formed on the antireflection film, and the antireflection film and the hard mask film are patterned using the resist pattern as an etching mask, and then the resist pattern for word line formation is removed.

  Subsequently, the insulating film 19, the refractory metal silicide film 14 b and the conductor film 14 a exposed from the stacked film of the remaining hard mask film and antireflection film are etched. In this etching, the interlayer insulating film 18 functions as an etch stopper. For this reason, as shown in FIG. 18, the insulator 18 is exposed in the portion where the insulating film 19, the refractory metal silicide film 14b and the conductor film 14a are etched. That is, the word lines 14 are formed in a direction intersecting with the extending direction of the first electrodes 12a to 12d, and the word lines 14 are formed so as to be separated from each other by the etching.

  As shown in FIG. 19, a resist pattern is formed on the main surface of the semiconductor substrate 10 so that the memory region is exposed and the other regions are covered.

  Subsequently, as shown in FIG. 20, floating gate electrodes 13 a to 13 c as shown in FIG. 1 are formed by selective etching of the silicon film 50 using the word line 14 as an etching mask. That is, the floating gate electrodes 13a to 13c are formed in a region where the first electrodes 12a to 12d and the word line 14 intersect.

  When the silicon film 50 is etched using the word line 14 as a mask, the seam portion is not formed in the silicon film 50 and the insulating film 18 is prevented from entering the seam portion. Even if etching is performed, generation of oxide film residues is prevented.

  In the method of manufacturing a semiconductor device as described above, since the seam portion 51 generated by depositing the silicon film 50 in the recess can be eliminated, the insulating film 18 is prevented from entering the seam portion 51, and thereafter In the step of etching the silicon film 50, it is possible to prevent the insulator 18 that has entered the seam portion 51 from remaining as a residue.

  In the first embodiment, since the silicon film 50 is etched after the seam portion 51 generated in the silicon film 50 is eliminated, the portion of the seam portion 51 is shaved first when etching is performed. There is no, and it can etch well.

  Furthermore, in the first embodiment, even when annealing is performed, the inside of the silicon film 50 is oxidized through the seam portion 51 by performing after the seam portion 51 formed in the silicon film 50 has disappeared. This can be prevented.

  In addition, after the heat treatment of the silicon film 50, the oxide film formed on the silicon film 50 is removed using hydrofluoric acid, so that the subsequent steps can be performed satisfactorily.

  Furthermore, in the case where ion implantation is performed toward the seam portion 51 formed in the silicon film 50 before heat treatment is performed on the formed seam portion, the bonding between the silicon structures in the seam portion 51 can be weakened. The seam portion 51 can be surely eliminated by the heat treatment performed thereafter.

  In this embodiment, the example applied to the manufacturing method of the AG-AND type flash memory is shown, but the present invention is not limited to this. That is, the concept of the present embodiment is applied to the case where the silicon film on which the seam portion is formed after the seam portion is generated by depositing the silicon film in the concave portion such as the step portion or the groove portion. be able to.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 21, in the second embodiment, the idea of the present invention is applied to a method for manufacturing a contact portion between conductive layer portions.

  As shown in FIG. 21, contact hole 120 is formed in interlayer insulating film 115 disposed above diffusion layer 114 formed on the main surface of substrate 111. A contact hole 116 reaching the diffusion layer 114 is formed in the interlayer insulating film 115, and a polycrystalline silicon film 117 is embedded in the contact hole 116, and a tungsten wiring 118 is formed on the upper surface of the polycrystalline silicon film 117. Has been.

  An example of a method for manufacturing the contact part 120 configured as described above will be described.

  After the diffusion layer 114 is formed on the substrate 111 by a known means, an interlayer insulating film 115 is formed so as to cover them. The interlayer insulating film 115 is subjected to anisotropic etching to form a contact hole 116. Then, a polycrystalline silicon layer 117 is deposited in the contact hole 116 formed in the interlayer insulating film 115. At this time, a seam portion is formed along the contact hole 116 in the polycrystalline silicon layer 117.

  Here, the seam portion generated in the polycrystalline silicon layer 117 is generated without depending on the aspect ratio of the contact hole 116, but particularly when the silicon film 50 is deposited in the contact hole 116 having an aspect ratio of 4 or more. It occurs with high probability. The aspect ratio is represented by the ratio of the height to the diameter of the contact hole 116.

Here, ion implantation is performed toward the seam portion formed in the polycrystalline silicon layer 117. When ion implantation is performed, the bond between the silicon structures in the seam portion can be weakened. Note that the dose amount of ion implantation is set to 1 × 10 ¹⁵ / cm ³ or more. Subsequently, the polycrystalline silicon layer 117 is subjected to a heat treatment of 1000 ° C. or more in a nitrogen atmosphere having an oxygen concentration of 1% or more, and silicon diffusion is generated in the formed seam portion so that the seam portion disappears. .

  After the heat treatment, the polycrystalline silicon layer 117 is etched to bury the polycrystalline silicon layer 117 in the contact hole 116 to form the contact hole 120. Thereafter, a tungsten wiring 118 is formed.

  According to the manufacturing method of the contact portion 120 as described above, when the polycrystalline silicon layer 117 is etched, the seam portion is not formed, and the etching can be performed satisfactorily.

  That is, since the seam portion is not formed when the polycrystalline silicon layer 117 is etched, it is possible to prevent the seam portion from being scraped first during the etching, and the etch back amount is slightly large. Even if it passes, etching can be prevented from proceeding at once, and etching can be performed satisfactorily.

  Furthermore, since the etching is performed after the seam portion formed in the polycrystalline silicon layer 117 is eliminated, the seam portion is not exposed to the surface by the etching, and the conduction between the polycrystalline silicon layer 117 and the tungsten wiring 118 is established. Can be good.

  Since the seam portion formed in the silicon film 150 can be eliminated in the second embodiment, as in the first embodiment, the same operation and effect as in the first embodiment can be obtained. .

(Embodiment 3)
Embodiment 3 of the present invention will be described with reference to FIG. In the third embodiment, the idea of the present invention is applied to a method of manufacturing a semiconductor device having a trench gate structure.

  As shown in FIG. 22, semiconductor device 201 according to the present embodiment is formed on P + region 222, N− drift layer 220 formed on the upper surface of P + region 222, and on the upper surface of N− drift layer 220. P-bases 232 and 224, an N + drift region 234 formed on the upper surface of the P-base 232, a P + region 227 formed on the upper surface of the P-base 224, an N + region 226, and a trench gate structure 200. Have

  The trench gate structure 200 includes a groove portion 250 formed between the P− base 224 and the N + region 226, the P− base 232 and the N + drift region 234, and an oxide wall portion 238 formed on the inner peripheral surface of the groove portion 250. And an oxidized bottom surface 240 formed on the bottom surface of the groove portion 250, and a silicon film 251 formed in the groove portion (concave portion) 250 via the oxidized wall portion 238 and the oxidized bottom portion 240.

  The trench gate structure 200 separates the P− base 224 and the N + region 226 from the P− base 232 and the N + drift region 234.

  The silicon film 251 is polysilicon doped with a large amount of donors. Note that the silicon film 251 may be any material that can fill the trench and give excellent conductivity.

  An electrode 260 is provided on the upper surface of the silicon film 251.

In manufacturing the semiconductor device 201 having the trench gate structure 200 configured as described above, first, the P + region 222, the N− drift layer 220, the P− bases 232 and 224, and the N + drift region 234 are well-known. Then, a P + region 227 and an N + region 226 are formed. Thereafter, a groove (recess) 250 is formed, and a silicon film 251 is deposited in the groove 250. At this time, a seam portion is formed in the center portion of the silicon film 251 along the height direction. Here, ion implantation is performed toward the seam portion where the silicon film 251 is formed. At this time, the dose of ion implantation is set to 1 × 10 ¹⁵ / cm ³ or more. Then, a heat treatment at 1000 ° C. or higher is performed on the silicon film 251 in an atmosphere containing 1% or higher oxygen. By this heat treatment, the seam portion formed in the silicon film 251 disappears.

  After the heat treatment, the oxide film formed on the surface of the silicon film 251 by the heat treatment is removed using hydrofluoric acid.

  Subsequently, the silicon film 251 is etched, and the silicon film 251 is embedded in the groove portion 250. At this time, since the seam portion is not formed in the silicon film 251, etching can be performed satisfactorily.

  Then, an electrode 260 is formed by depositing and etching a conductive film on the upper surface of the silicon film 251. At this time, since the seam portion is not formed in the silicon film 251, conduction between the silicon film 251 and the electrode 260 can be improved.

  Also in the third embodiment, since the seam portion formed in the silicon film 251 embedded in the groove portion 250 can be eliminated, the same functions and operations as those in the first embodiment and the second embodiment can be achieved. An effect can be obtained.

  Although the embodiment of the present invention has been described above, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be effectively applied to a method for manufacturing a semiconductor device having a silicon film embedded in a recess.

1 is a partial cross-sectional view of an AG-AND type flash memory according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a write operation of the AG-AND type flash memory shown in FIG. 1. FIG. 2 is a cross-sectional view showing a read operation of the AG-AND type flash memory shown in FIG. 1. FIG. 3 is a cross-sectional view showing an erase operation of the AG-AND type flash memory shown in FIG. 1. FIG. 6 is a cross-sectional view showing a first step of a manufacturing process of the AG-AND type flash memory in the first embodiment of the invention. 7 is a cross-sectional view showing a second step of the manufacturing process of the AG-AND type flash memory in the first embodiment of the invention. FIG. It is sectional drawing which shows the 3rd process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 4th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 5th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 6th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 7th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 8th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 9th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 10th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 11th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 12th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 13th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 14th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 15th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing which shows the 16th process of the manufacturing process of the AG-AND type flash memory in Embodiment 1 of this invention. It is sectional drawing of the contact part which can apply the manufacturing method which concerns on Embodiment 2 of this invention. It is sectional drawing of the trench gate structure which can apply the manufacturing method concerning Embodiment 3 of this invention.

Explanation of symbols

  10 semiconductor substrate, 12a, 12b, 12c, 12d, first electrode (first conductive film), 13a, 13b, 13c floating gate electrode, 14 word line (second conductive film), 18 insulating film (third insulating film) 50 Silicon film.

Claims (10)

Depositing a silicon film in a recess formed in an insulating film formed on the main surface of the recess or the semiconductor substrate formed on the main table surface of a semiconductor substrate,
A step of eliminating a seam portion formed in the silicon film by performing a heat treatment at 1000 ° C. or higher in an atmosphere containing 1% or more oxygen ,
The method of manufacturing a semiconductor device, wherein the silicon film after the step of eliminating the seam portion is a conductive film . A silicon oxide film is formed on the surface of the silicon by the heat treatment,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the silicon oxide film after the heat treatment.   The method of manufacturing a semiconductor device according to claim 2, wherein the silicon oxide film is removed with hydrofluoric acid.   4. The method of manufacturing a semiconductor device according to claim 1, wherein an aspect ratio that is a ratio of a height to a width of a bottom portion of the recess is 4 or more. 5.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of depositing an insulating film on the silicon film.   The method for manufacturing a semiconductor device according to claim 5, wherein the insulating film is a stacked film of an oxide film, a nitride film, and an oxide film. Etching the insulating film; and
Etching the silicon film;
The method for manufacturing a semiconductor device according to claim 5, further comprising: Depositing a conductive film on the insulating film;
Patterning the conductive film;
The method for manufacturing a semiconductor device according to claim 5, further comprising:   The method of manufacturing a semiconductor device according to claim 8, wherein the silicon film and the insulating film are etched using the conductive film as a mask. Further comprising a step of implanting ions into the silicon film before the heat treatment;
A method for manufacturing a semiconductor device according to claim 1.

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