JP2008108787A - Nonvolatile semiconductor storage device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor storage device by which it can be possible to prevent a silicon oxide film formed on the side wall of a tungsten silicide film from swelling than that formed on the side wall of a polycrystal silicon film when oxidizing the side wall of a gate electrode, and to provide a nonvolatile semiconductor storage device having a desired gate electrode's shape that is obtained by the manufacturing method. <P>SOLUTION: A tungsten silicide film 6 is etched at 4 to 10 mmTorr of pressure, at 200 to 400 W of RF source power and 100 to 200 W of bias power, and under a mixed gas of CF<SB>4</SB>/Cl<SB>2</SB>/N<SB>2</SB>at a flow rate of 1 to 50 sccm of CF<SB>4</SB>gas, 100 to 150 sccm of Cl<SB>2</SB>gas and 7 sccm or less of N<SB>2</SB>gas, and the tungsten silicide film 6 is made to have a constricted shape beforehand. Thus, even when the tungsten silicide film 6 is oxidized more than a first polycrystal silicon film 3 and a second polycrystal silicon film 5 during oxidation of the side wall of the gate electrode, a desired gate electrode's shape can be obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  Conventionally, a nonvolatile semiconductor memory device has been developed that uses charges injected from a channel region to a charge storage layer through a tunnel insulating film to store digital bit information. Such a nonvolatile semiconductor memory device generally has a laminated structure of a polycrystalline silicon film and a tungsten silicide film, and is produced by, for example, the following process.

  First, a silicon oxide film is formed as a tunnel insulating film on a P-type silicon semiconductor substrate, and a polycrystalline silicon film doped with phosphorus is formed as a floating gate electrode on the tunnel insulating film.

  Next, an insulating film is formed on the floating gate electrode, and a polycrystalline silicon film is formed on the insulating film as a control gate electrode. Further, a tungsten silicide film is formed as a control gate low resistance metal film on the control gate electrode. Thereafter, a silicon nitride film or the like is formed on the control gate resistance-reducing metal film as an etching mask for processing the gate electrode.

  The laminated structure formed as described above is subjected to anisotropic etching after the lithography process to form a gate electrode pattern. Next, sidewall oxidation of the floating gate electrode is performed in order to recover damage due to anisotropic etching and prevent leakage current from the polycrystalline silicon film serving as the floating gate electrode through the gate sidewall.

  Here, when the control gate low-resistance metal film is made of tungsten silicide, the control gate low-resistance metal film is oxidized more than the floating gate electrode and the control gate electrode made of polycrystalline silicon. A silicon oxide film containing a metal element formed on the sidewall of the gate low resistance metal film is formed on the side surfaces of the polycrystalline silicon film as the floating gate electrode and the polycrystalline silicon film as the control gate electrode, respectively. The shape is larger than the oxide film.

  For this reason, in the step of ion-implanting N-type impurities such as phosphorus or arsenic to form source / drain regions after oxidation of the gate electrode sidewall, the oxide film formed on the sidewall of the control gate low resistance metal film becomes a soot. As a result, there is a problem that N-type impurities are not sufficiently supplied to the underlying semiconductor substrate.

  After that, when an interlayer insulating film such as a TEOS film is embedded between the gate electrodes, the oxide film formed on the side wall of the control gate low resistance metal film is formed to swell, so that the embedding property is poor and the gap is not formed. A problem arises.

  Further, since the distance between the gate electrodes becomes shorter at the side wall portion of the control gate low resistance metal film, there is a possibility that the gate-contact is electrically short-circuited.

  To solve the above problems, a method is disclosed in which the sidewall of the control gate low resistance metal film is covered with an insulating film such as a silicon nitride film to prevent abnormal oxidation of tungsten or tungsten silicide (for example, see Patent Document 1). .)

However, in the method disclosed in Patent Document 1, it is necessary to cover the side wall of the control gate low resistance metal film with an insulating film such as a silicon nitride film in advance, which increases the number of processes compared to the conventional method. there were.
Japanese Patent Laid-Open No. 2005-44844

  In the present invention, the number of steps is increased so that the silicon oxide film formed on the side wall of the tungsten silicide film is swelled more than the silicon oxide film formed on the side wall of the polycrystalline silicon film during the oxidation of the side wall of the gate electrode. The present invention provides a method for manufacturing a nonvolatile semiconductor memory device that can be prevented without fail, and a nonvolatile semiconductor memory device having a desired gate electrode shape obtained by the method.

  A method for manufacturing a nonvolatile semiconductor memory device according to one embodiment of the present invention includes a first insulating film, a first polycrystalline silicon film, a second insulating film, and a second polycrystalline silicon over a semiconductor substrate. A step of sequentially forming a film, a tungsten silicide film, and a silicon oxide film; a step of forming a resist pattern on the silicon oxide film; and a first etching for patterning the silicon oxide film using the resist pattern as a mask A second etching step of patterning the tungsten silicide film into a shape in which a width of an intermediate portion is narrower than a width of an upper end portion and a lower end portion of the tungsten silicide film, using the silicon oxide film as a mask, and the silicon Using the oxide film as a mask, the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film are patterned. Characterized by comprising a third etching step of Ningu.

  In addition, a method for manufacturing a nonvolatile semiconductor memory device according to another aspect of the present invention includes a first insulating film, a first polycrystalline silicon film, a second insulating film, and a second multi-layer on a semiconductor substrate. A step of sequentially forming a crystalline silicon film, a tungsten silicide film, and a first silicon oxide film, a step of forming a resist pattern on the first silicon oxide film, and the first pattern using the resist pattern as a mask. A first etching step of patterning the silicon oxide film, and the tungsten silicide film using the first silicon oxide film as a mask, the width of the intermediate portion is larger than the width of the upper end portion and the lower end portion of the tungsten silicide film. A second etching step for patterning into a narrow shape; and the second polycrystalline silicon film and the second insulating film using the first silicon oxide film as a mask. And a third etching step of patterning the first polycrystalline silicon film, the first silicon oxide film patterned by the first etching step to the third etching step, the tungsten silicide film, By depositing silicon oxide on the second polycrystalline silicon film, the second insulating film, the exposed portion of the first polycrystalline silicon film, and the surface of the first insulating film, and then depositing silicon oxide And an oxide film forming step for forming a second silicon oxide film, and in the oxide film forming step, a width of the tungsten silicide film formed by the second etching step and a sidewall of the tungsten silicide film are formed. The width combined with the film thickness of the formed second silicon oxide film has a width that is formed by the third etching step. And forming a width below a combination of the thickness of the width and the first polycrystalline silicon film and the second silicon oxide film formed on the side wall of the polycrystalline silicon film.

  In addition, a nonvolatile semiconductor memory device according to still another aspect of the present invention includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a first insulating film formed on the first insulating film. A polycrystalline silicon film, a second insulating film formed on the first polycrystalline silicon film, a second polycrystalline silicon film formed on the second insulating film, and the second A tungsten silicide film formed on the polycrystalline silicon film; a first silicon oxide film formed on the tungsten silicide film; the first insulating film; the first polycrystalline silicon film; An insulating film, a second polysilicon film, a tungsten silicide film, and a second silicon oxide film covering the surface of the first silicon oxide film, and the width of the tungsten silicide film is 1 polycrystalline silicon A width that is narrower than the width of the film and the second polycrystalline silicon film, and the combined width of the tungsten silicide film and the thickness of the second silicon oxide film formed on the sidewall of the tungsten silicide film is The width of the first polycrystalline silicon film and the thickness of the second silicon oxide film formed on the side wall of the first polycrystalline silicon film are equal to or smaller than the combined width.

  In the present invention, the number of steps is increased so that the silicon oxide film formed on the side wall of the tungsten silicide film is swelled more than the silicon oxide film formed on the side wall of the polycrystalline silicon film during the oxidation of the side wall of the gate electrode. It is possible to provide a method for manufacturing a nonvolatile semiconductor memory device that can be prevented without any problem, and a nonvolatile semiconductor memory device having a desired gate electrode shape obtained by the method.

  Embodiments of the present invention will be described below with reference to the drawings.

  An element cross-sectional structure in the channel length direction of the nonvolatile semiconductor memory device according to the first embodiment of the invention will be described with reference to FIG.

  In FIG. 1, for example, a gate insulating film made of, for example, a silicon oxide film is formed as a first insulating film 2 on a P-type silicon semiconductor substrate 1, and a first polycrystalline silicon film 3 is formed on the first insulating film 2. A floating gate electrode made of is formed.

  On the first polycrystalline silicon film 3, for example, an ONO film (silicon oxide film, silicon nitride film, silicon oxide film) is stacked as the second insulating film 4. A control gate electrode composed of the crystalline silicon film 5 and the tungsten silicide film 6 is formed. The tungsten silicide film 6 can reduce the resistance of the control gate, shorten the gate delay, and reduce the writing time.

  An etching mask made of the first silicon oxide film 7 remains on the tungsten silicide film 6, and the surface of the first insulating film 2, the first polycrystalline silicon film 3, the second insulating film 4, and the second The side walls of the polycrystalline silicon film 2 and the tungsten silicide film 6 and the surface of the first silicon oxide film 7 are covered with a second silicon oxide film 8. Hereinafter, a laminated structure having a control gate electrode made of the second polycrystalline silicon film 5 and the tungsten silicide film 6 and a floating gate electrode made of the first polycrystalline silicon film 3 is referred to as a gate electrode.

  Further, N-type impurities are ion-implanted in a surface layer portion between adjacent gate electrodes in the P-type silicon semiconductor substrate 1, and an N-type impurity diffusion layer 9 serving as a source and drain region is formed. A channel region exists between the two N-type impurity diffusion layers 9.

  The N-type impurity diffusion layer 9 is shared between adjacent gate electrodes, and for example, NAND connection or NOR connection is realized.

  Further, a silicon nitride film 10 is formed on the surface of the second silicon oxide film 8 with a uniform thickness, and an interlayer insulating film (not shown) made of, for example, a TEOS (Tetraethoxysilane) film so as to be embedded between the gate electrodes. Is deposited.

  In this embodiment, the width of the tungsten silicide film 6 is formed to be narrower than that of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5, and further, the width of the tungsten silicide film 6 and the tungsten silicide film 6. The width A combined with the thickness of the second silicon oxide film 8 formed on the side wall of the first polysilicon film 3 is equal to the width of the first polycrystalline silicon film 3 and the first thickness formed on the side wall of the first polycrystalline silicon film 3. The second silicon oxide film 8 is formed to have a width B or less combined with the film thickness of the silicon oxide film 8.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS.

  First, a gate insulating film made of, for example, a silicon oxide film is formed as a first insulating film 2 on a P-type silicon semiconductor substrate 1, and a first polycrystalline silicon film 3 is further formed on the first insulating film 2. .

  Next, an ONO film, for example, is stacked as the second insulating film 4 on the first polycrystalline silicon film 3, and a second polycrystalline silicon film 5 is formed on the second insulating film 4. Further, a tungsten silicide film 6 is formed on the second polycrystalline silicon film 5, and a first silicon oxide film 7 is formed on the tungsten silicide film 6.

  The first silicon oxide film 7 is used as an etching mask during gate processing, and may be a silicon oxynitride film or a laminated structure of a silicon oxide film and a silicon nitride film in addition to the silicon oxide film. The uppermost layer is preferably a film containing no nitrogen. Therefore, when a laminated structure of a silicon oxide film and a silicon nitride film is used, it is desirable that the silicon oxide film is an upper layer.

Next, the first silicon oxide film 7 is patterned under a CF-based gas condition (first etching process) using the resist film patterned by the lithography process as a mask. Then, the structure shown in FIG. 2 is obtained by exposing the P-type silicon semiconductor substrate 1 in an O ₂ plasma atmosphere and removing the resist film.

Next, using the first silicon oxide film 7 as a mask, the tungsten silicide film 6 is subjected to a pressure of 4 to 10 mmTorr, an RF source power of 200 to 400 W, a bias power of 100 to 200 W, and a mixed gas condition of CF ₄ / Cl ₂ / N _2. Patterning (second etching process) is performed. Under this gas condition, N ₂ gas is used to control the etching rate of the tungsten silicide film 6 in the direction horizontal to the P-type silicon semiconductor substrate 1, the flow rate of CF ₄ is 1 to 50 sccm, and Cl ₂ Etching is performed with a flow rate of 100 to 150 sccm and an N ₂ flow rate of 16 sccm or less, whereby the tungsten silicide film 6 is constricted, that is, the width of the intermediate portion is narrower than the width of the upper end portion and the lower end portion of the tungsten silicide film 6 It can be processed into a shape. As a result, the structure shown in FIG. 3 is obtained.

Since the etching rate is sensitive to the N ₂ flow rate, it is desirable that the first silicon oxide film 7 serving as an etching mask does not contain nitrogen in the uppermost layer as described above.

  Next, using the first silicon oxide film 7 as a mask, the second polycrystalline silicon film 5 is patterned under a gas condition mainly composed of a halogen gas, and further the second insulating film 4 is patterned under a CF-based gas condition. After that, the first polycrystalline silicon film 3 is patterned (third etching step) under gas conditions mainly containing halogen gas. As a result, the gate laminated structure 11 patterned into the gate shape shown in FIG. 4 is obtained.

Here, in the patterned tungsten silicide film 6, the width C near the interface (upper end) with the first silicon oxide film 7, the width E near the interface (lower end) with the second polycrystalline silicon film 5, FIG. 6 shows the relationship between the width D and the N ₂ gas flow rate at the intermediate portion located approximately equidistant from each of the interfaces. In FIG. 6, the horizontal axis represents the N ₂ gas flow rate (sccm), the vertical axis represents the difference between the width C and the width D or the difference between the width E and the width D (nm), and the N ₂ gas flow rate is 0, 8, and 15 sccm. The measured values are plotted. FIG. 6 shows that the etching rate of the tungsten silicide film 6 in the direction horizontal to the P-type silicon semiconductor substrate 1 can be controlled by changing the N ₂ gas flow rate.

Further, the intercept of the linear approximation curve obtained from the measurement value of the difference between the width C and the width D and the horizontal axis is about 20.8 sccm, and the linear approximation curve obtained from the measurement value of the difference between the width E and the width D and the horizontal axis. Therefore, it is predicted that the tungsten silicide film 6 can be processed into a constricted shape when the N ₂ gas flow rate is 16 sccm or less.

Next, the sidewall of the gate stacked structure 11 is oxidized by a rapid thermal oxidation (RTO) method, for example, in an O ₂ atmosphere at 1000 ° C. In the present embodiment, since the tungsten silicide film 6 is processed into a constricted shape in advance, the tungsten silicide film 6 is more likely to be the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5 during thermal oxidation by the RTO method. Even if more oxidation is performed, a silicon oxide film containing a metal element formed on the sidewalls of the tungsten silicide film 6 is formed on the sidewalls of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5. The shape does not swell more than the film.

  Thereafter, a silicon oxide film is further deposited on the gate laminated structure 11 subjected to the sidewall oxidation process with a uniform thickness by a CVD method or the like, so that the silicon oxide film formed by the oxidation process on the surface of the gate laminated structure 11 and the CVD are formed. A second silicon oxide film 8 made of a silicon oxide film formed by the method is formed. Thus, the gate shape shown in FIG. 5 is obtained.

Here, in FIG. 5, the width A, which is the sum of the width of the tungsten silicide film 6 and the thickness of the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6, and the first polycrystalline silicon film 3. FIG. 7 shows the relationship between the width B and the N ₂ gas flow rate of the width B of the first polysilicon film 3 and the thickness of the second silicon oxide film 8 formed on the side wall of the first polycrystalline silicon film 3. In FIG. 7, the horizontal axis is the N ₂ gas flow rate (sccm), the vertical axis is the difference between the width A and the width B (nm), and the measured values when the N ₂ gas flow rates are 0, 8, and 15 sccm are plotted. Yes. From Figure 7, the change in the difference between the width A and the width B to N ₂ gas flow rate is considered to be linear, since regarded as substantially equal to the width A and the width B in the N ₂ gas flow rate 8 sccm, N ₂ gas The second silicon formed on the sidewall of the tungsten silicide film 6 by performing etching under the condition that the flow rate is within a range of 16 sccm or less, which is a condition for processing the tungsten silicide film 6 into a constricted shape, and 7 sccm or less. It can be seen that the oxide film 8 can be prevented from swelling more than the second silicon oxide film 8 formed on the side walls of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5.

  Next, phosphorus, arsenic, antimony, or the like is implanted into the P-type silicon semiconductor substrate 1 by ion implantation or the like to form the N-type impurity diffusion layer 9.

  Further, after forming a silicon nitride film 10 on the surface of the second silicon oxide film 8, an interlayer insulating film (not shown) made of a TEOS film or the like is deposited on the entire surface to obtain the shape shown in FIG.

  As described above, in the present embodiment, the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6 during the gate electrode sidewall oxidation is the first polycrystalline silicon film 3 and the second polycrystalline silicon film. Unlike the prior art, it is possible to prevent a swelled shape from the second silicon oxide film 8 formed on the side wall of the silicon film 5 without increasing the number of steps, and a desired gate electrode shape as shown in FIG. Obtainable.

  The desired gate electrode shape is a width A that is the sum of the width of the tungsten silicide film 6 and the thickness of the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6, and the first polycrystalline silicon. This includes the case where the width B of the width of the film 3 and the thickness of the second silicon oxide film 8 formed on the side wall of the first polycrystalline silicon film 3 are equal.

  In this embodiment, since the tungsten silicide film 6 is processed into a constricted shape in advance, the width of the tungsten silicide film 6 is the first polycrystal even in the gate electrode shape finally obtained as shown in FIG. The width is narrower than that of the silicon film 3 and the second polycrystalline silicon film 5.

  In the present embodiment, the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6 has a shape swelled more than the second silicon oxide film 8 formed on the sidewall of the polycrystalline silicon film 5. Therefore, when the N-type impurity diffusion layer 9 is formed by an ion implantation method or the like, a uniform impurity diffusion layer can be formed without causing defects.

  In the present embodiment, the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6 has a shape swelled more than the second silicon oxide film 8 formed on the sidewall of the polycrystalline silicon film 5. Therefore, it is possible to reduce the possibility that a gap is generated between the gate electrodes when an unillustrated interlayer insulating film made of a TEOS film or the like is deposited on the entire surface.

Further, even when an oxidation condition other than the RTO oxidation condition is used, the tungsten silicide film 6 is set in a direction parallel to the P-type silicon semiconductor substrate 1 by appropriately setting the N ₂ gas flow rate within a range of 16 sccm or less. The second silicon oxide film 8 on the side wall of the tungsten silicide film 6 becomes the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5 after the gate electrode side wall oxidation is changed by adjusting the etching rate. It is possible to prevent the shape of the second silicon oxide film 8 formed on the side walls of the second silicon oxide film from expanding.

Further, since the tungsten silicide film 6 can be processed into a narrower shape as the N ₂ gas flow rate is smaller, it may not be added depending on the subsequent oxidation conditions.

Moreover, the oxidation amount of the tungsten silicide film 6 can be suppressed by using the RTO method in the H ₂ / O ₂ atmosphere as the oxidation condition. Also in this case, the N ₂ gas flow rate may be appropriately adjusted within the range of 16 sccm or less in accordance with the oxidation amount of the tungsten silicide film.

  Further, it is known that when a tungsten film is used instead of a tungsten silicide film in order to reduce the resistance of the control gate, abnormal oxidation occurs during the oxidation of the side wall of the gate electrode. In this case as well, the metal oxide film formed on the side wall of the tungsten film is processed in a constricted shape in advance, as in the present embodiment, than the silicon oxide film formed on the side wall of the polycrystalline silicon film. It is possible to prevent a bulging shape.

  In the present embodiment, a silicon oxide film is used as the first insulating film 2, but the present invention is not limited to this, and an oxynitride film, a silicon nitride film, or the like may be used.

In the present embodiment, the ONO film is used as the second insulating film 4. However, the present invention is not limited to this, and an Al ₂ O ₃ film, a single-layer silicon oxide film, or the like may be used.

  In this embodiment, the TEOS film is used as the interlayer insulating film. However, the present invention is not limited to this, and a BSG (Boron Silicate Glass), a PSG (Phosphor Silicate Glass), a BPSG (Boro phospho silicate grass) film, or the like may be used. .

This embodiment is an example in which the etching conditions of the tungsten silicide film 6 in Example 1 are changed. In this embodiment, a mixed gas of Cl ₂ / N ₂ is used, a pressure of 4 to 10 mmTorr, an RF source power of 200 to 400 W, a bias power of 100 to 200 W, a flow rate of Cl ₂ of 100 to 150 sccm, and a flow rate of N ₂ gas. The tungsten silicide film 6 is etched into a constricted shape by etching the tungsten silicide film 6 under the condition of 5 sccm or less.

In the present embodiment, the tungsten silicide film 6 and the second silicon oxide film 8 formed on the sidewalls of the tungsten silicide film 6 when the RTO oxidation condition of 1000 ° C. is used in an O ₂ atmosphere as in the first embodiment. Width A combined with the thickness of the first polysilicon film 3 and the thickness of the second silicon oxide film 8 formed on the side wall of the first polysilicon film 3. FIG. 8 shows the relationship between N _{2 and} the N ₂ gas flow rate. In FIG. 8, the horizontal axis is the N ₂ flow rate (sccm), the vertical axis is the difference (nm) between the width A and the width B, and the measured values when the N ₂ gas flow rates are 0, 8, and 15 sccm are plotted. Yes. From Figure 8, the change in the difference between the width A and the width B for the N ₂ flow rate is considered to be linear, since the width of the width A and the width B in the N ₂ gas flow rate 8sccm can be considered approximately equal, N ₂ Etching is performed under the condition that the flow rate is 5 sccm or less as described above, and the tungsten silicide film 6 is processed into a constricted shape in advance, whereby the second silicon oxide film 8 formed on the sidewall of the tungsten silicide film 6 is formed. It can be seen that it is possible to prevent the swelled shape from the second silicon oxide film 8 formed on the side walls of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5.

Further, since the tungsten silicide film 6 can be processed into a narrower shape as the N ₂ gas flow rate is smaller, it may not be added depending on the subsequent oxidation conditions.

  Since other steps and the obtained gate electrode shape are the same as those in the first embodiment, the description thereof is omitted.

This embodiment is an example in which the etching conditions of the tungsten silicide film in Example 1 are changed. In this embodiment, a mixed gas of NF ₃ / O ₂ is used, the pressure is 4 to 10 mmTorr, the RF source power is 200 to 400 W, the bias power is 100 to 200 W, and the flow rate ratio of O ₂ gas to NF ₃ gas is 80% or more. Under this condition, the tungsten silicide film 6 is etched. In the present embodiment, the tungsten silicide film 6 is processed into a constricted shape by utilizing the fact that the selection ratio with respect to the second lower polycrystalline silicon film can be increased by adding O ₂ gas.

When the RTO oxidation condition of 1000 ° C. is used in the O ₂ atmosphere as in Example 1, the etching is performed with the flow rate ratio of O ₂ gas to NF ₃ gas being 80% or more as described above, and the tungsten silicide film 6 is previously formed. The second silicon oxide film 8 formed on the side wall of the tungsten silicide film 6 is formed on the side walls of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5. It is possible to prevent the bulging shape from the formed second silicon oxide film 8.

  Since other steps and the obtained gate electrode shape are the same as those in the first embodiment, the description thereof is omitted.

  FIG. 9 shows a circuit configuration of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. This embodiment corresponds to a case where the gate electrode structure obtained by using the method described in the first to third embodiments is applied to a cell array of a NOR type flash memory. FIG. 10 shows an example of a layout obtained by extracting a part of the NOR type cell array of FIG.

  The NOR type cell array shown in FIGS. 1 and 2 includes memory cells MC arranged in a matrix on a P type silicon semiconductor substrate 1. Each memory cell MC has an N-type impurity diffusion layer 9 and a channel region formed in the surface layer portion of the P-type silicon semiconductor substrate 1, and a two-layer gate structure formed on the P-type silicon semiconductor substrate 1 via a gate insulating film. Have The gate electrode structure in the first to third embodiments is applied to the memory cell MC.

  In the NOR-type cell array, two adjacent memory cells MC form a common drain region D, and two adjacent memory cells share a source region S. Each column is separated by a trench type element isolation region (STI region).

  Further, a plurality of word lines WL are formed in the row direction so as to be connected in common to the control gate electrodes of the memory cells MC in the same row on the cell array, and are commonly connected to the source regions S of the memory cells MC in the same row. A plurality of local source lines LS made of metal wiring are formed in the row direction.

  In addition, a plurality of bit lines BL made of metal wiring are formed in the column direction so as to be in common contact with the drain regions D of the memory cells MC in the same column on the cell array, and are in common contact with the plurality of local source lines LS. A plurality of main source lines MS made of wiring are arranged at regular intervals in the bit line BL array.

  As described above, the drain region D shared by two adjacent cell transistors is connected to the low-resistance bit line BL via the drain contact DC. The source region S shared by two adjacent cell transistors is connected to a local source line LS that exists in parallel with the word line WL between the word lines WL, and the local source line LS is connected via a source contact SC. And connected to the low-resistance main source line, and a potential is applied from outside the cell array.

  In the NOR flash memory having the above-described configuration, a ground potential is applied to the source region S and the P-type silicon semiconductor substrate 1 when electrons are injected into the floating gate electrode in order to write data in the cell. The control gate electrode and the drain region D are given potentials through the word line WL and the bit line BL, respectively, so that the efficiency of generating injected electrons is maximized.

  FIG. 11 shows an element cross-sectional view corresponding to the NOR circuit configuration of the nonvolatile semiconductor memory device according to the present embodiment. FIG. 11 shows an AA 'cross section of FIG.

  In FIG. 11, in addition to the gate electrode structure obtained by using the method described in the first to third embodiments, there are a source contact SC and a drain contact DC. In the present embodiment, the second silicon oxide film 8 formed on the sidewalls of the tungsten silicide film 6 is formed on the sidewalls of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 5. Since the shape does not swell more than the silicon oxide film 8, the possibility of short-circuiting with the gate electrode during contact formation can be reduced.

1 is a cross-sectional view showing a cross-sectional configuration of a nonvolatile semiconductor memory device according to a first embodiment. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment to process order. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment to process order. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment to process order. Sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on 1st Embodiment to process order. 6 is a graph showing the relationship between the gate electrode shape and the N ₂ gas flow rate in the nonvolatile semiconductor memory device according to the first embodiment. 6 is a graph showing the relationship between the gate electrode shape and the N ₂ gas flow rate in the nonvolatile semiconductor memory device according to the first embodiment. Graph showing the relationship between a gate electrode shape and the N ₂ gas flow rate of the non-volatile semiconductor memory device according to the second embodiment. The equivalent circuit diagram which shows a part of cell array of the NOR type flash memory which concerns on 4th Embodiment. FIG. 9 is a layout diagram showing a part of a cell array of a NOR flash memory according to a fourth embodiment. Sectional drawing which shows a part of cell array of the NOR type flash memory which concerns on 4th Embodiment.

Explanation of symbols

1 P-type silicon semiconductor substrate 2 First insulating film 3 First polycrystalline silicon film 4 Second insulating film 5 Second polycrystalline silicon film 6 Tungsten silicide film 7 First silicon oxide film 8 Second silicon Oxide film 9 N-type impurity diffusion layer 10 Silicon nitride film 11 Gate stacked structure MC Memory cell WL Word line LS Local source line MS Main source line S Source region D Drain region SC Source contact DC Drain contact

Claims (14)

Step of sequentially forming a first insulating film, a first polycrystalline silicon film, a second insulating film, a second polycrystalline silicon film, a tungsten silicide film, and a silicon oxide film on a semiconductor substrate When,
Forming a resist pattern on the silicon oxide film;
A first etching step of patterning the silicon oxide film using the resist pattern as a mask;
A second etching step of patterning the tungsten silicide film with the silicon oxide film as a mask into a shape in which the width of the upper end portion and the width of the lower end portion of the tungsten silicide film are narrower than the intermediate portion;
And a third etching step of patterning the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film using the silicon oxide film as a mask. For manufacturing a conductive semiconductor memory device.   2. The non-volatile device according to claim 1, wherein a silicon nitride film is further formed between the tungsten silicide film and the silicon oxide film, and the silicon nitride film is etched using the silicon oxide film as a mask. Manufacturing method of semiconductor memory device. A first insulating film, a first polycrystalline silicon film, a second insulating film, a second polycrystalline silicon film, a tungsten silicide film, and a first silicon oxide film are sequentially formed on a semiconductor substrate. Forming, and
Forming a resist pattern on the first silicon oxide film;
A first etching step of patterning the first silicon oxide film using the resist pattern as a mask;
A second etching step of patterning the tungsten silicide film with the first silicon oxide film as a mask into a shape in which the width at the upper end and the width at the lower end of the tungsten silicide film are narrower than the width;
A third etching step of patterning the second polycrystalline silicon film, the second insulating film, and the first polycrystalline silicon film using the first silicon oxide film as a mask;
The first silicon oxide film, the tungsten silicide film, the second polycrystalline silicon film, the second insulating film, and the first patterned by the first etching process to the third etching process An oxide film forming step of forming a second silicon oxide film by depositing silicon oxide on the exposed portion of the polycrystalline silicon film and the surface of the first insulating film after performing an oxidation treatment;
In the oxide film forming step, a width obtained by combining a width of the tungsten silicide film formed in the second etching step and a film thickness of the second silicon oxide film formed on a sidewall of the tungsten silicide film is set. The width of the first polycrystalline silicon film formed by the third etching step and the thickness of the second silicon oxide film formed on the side wall of the first polycrystalline silicon film are combined. A non-volatile semiconductor memory device manufacturing method, wherein the non-volatile semiconductor memory device is formed with a width or less.   The silicon nitride film is further formed between the tungsten silicide film and the first silicon oxide film, and the silicon nitride film is etched using the first silicon oxide film as a mask. 4. A method for manufacturing a nonvolatile semiconductor memory device according to 3. The second etching process is a dry etching step carried out using an activated reactive gas, any one of claims 1 to 4 said reaction gas is characterized in that it comprises a Cl ₂ gas A method for manufacturing a nonvolatile semiconductor memory device according to claim 1. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the reaction gas further contains CF ₄ gas. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the reaction gas further contains N ₂ gas. The second etching process is a dry etching process performed using an activated reaction gas, and the reaction gas includes CF ₄ gas, Cl ₂ gas, and N ₂ gas having a flow rate of 16 sccm or less. A method for manufacturing a nonvolatile semiconductor memory device according to claim 1. The second etching process is a dry etching process performed using an activated reaction gas, and the reaction gas includes CF ₄ gas, Cl ₂ gas, and N ₂ gas at a flow rate of 7 sccm or less, and The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the oxidation treatment is rapid heating oxidation treatment in an O ₂ gas atmosphere. The second etching process is a dry etching process performed using an activated reaction gas, the reaction gas including Cl ₂ gas and N ₂ gas having a flow rate of 5 sccm or less, and the oxidation treatment is performed using O 2. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the method is a rapid thermal oxidation process in a _two- gas atmosphere. 5. The method according to claim 1, wherein the second etching step is a dry etching step performed using an activated reaction gas, and the reaction gas includes NF ₃ gas and O ₂ gas. The manufacturing method of the non-volatile semiconductor memory device of any one of Claims 1. The second etching process is a dry etching process performed using an activated reaction gas, and the reaction gas is NF ₃ gas and an O ₂ gas having a flow rate ratio of 80% or more to the NF ₃ gas flow rate. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the oxidation treatment is rapid thermal oxidation treatment in an O ₂ gas atmosphere. A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A first polycrystalline silicon film formed on the first insulating film;
A second insulating film formed on the first polycrystalline silicon film;
A second polycrystalline silicon film formed on the second insulating film;
A tungsten silicide film formed on the second polycrystalline silicon film;
A first silicon oxide film formed on the tungsten silicide film;
A second covering the surface of the first insulating film, the first polycrystalline silicon film, the second insulating film, the second polycrystalline silicon film, the tungsten silicide film, and the first silicon oxide film; A silicon oxide film,
The width of the tungsten silicide film is narrower than the width of the first polycrystalline silicon film and the second polycrystalline silicon film, and is formed on the width of the tungsten silicide film and the sidewall of the tungsten silicide film. The total width of the second silicon oxide film is equal to the width of the first polycrystalline silicon film and the film of the second silicon oxide film formed on the side wall of the first polycrystalline silicon film. A non-volatile semiconductor memory device having a width equal to or less than a total thickness.   The nonvolatile semiconductor memory device according to claim 13, further comprising a silicon nitride film between the tungsten silicide film and the first silicon oxide film.

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