KR20020095547A - Gate structure of non-volatile memory device and Method of manufacturing the same - Google Patents

Abstract

PURPOSE: A gate structure of a non-volatile memory(NVM) device is provided to eliminate the possibility of particles and defects caused by an etch process, by forming a control gate through a damascene process so that an etch process is performed only once until the control gate is formed after a floating gate is formed. CONSTITUTION: An active region and a field region are defined in a semiconductor substrate(100). A plurality of floating gates(106) are formed on the semiconductor substrate. The first stop layer(108) is formed on the floating gates and the semiconductor substrate. An interlayer dielectric(110) and the second stop layer(112) are sequentially formed on the first stop layer, having a plurality of trenches(114) which penetrate a part of the first stop layer over each floating gate and partially expose the upper surface of each floating gate. A dielectric layer(116) is formed on the inner wall and the bottom surface of the trenches. A plurality of control gates(120) fill the trenches, planarized with the surface of the second stop layer.

Description

Gate structure of non-volatile memory device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device for forming a gate using a damascene process and a method for manufacturing the same.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory that can electrically input and output data. The flash memory device is an advanced form of EEPROM that can be electrically erased at high speed. The flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.

Looking at the flash memory device from a circuit point of view, a NAND type in which n cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. Each of the cell transistors can be classified into a NOR type in which a parallel connection is made between a bit line and a ground line. The NOR type is advantageous for high speed operation, while the NAND type is advantageous for high integration.

1A to 1G are cross-sectional views and perspective views illustrating a method of manufacturing a conventional NAND type flash memory device.

FIG. 1A is a cross-sectional view along the bit line direction, and FIG. 1B is a perspective view along the word line direction, illustrating a step of forming the first polysilicon film pattern 15. First, a semiconductor substrate divided into a field region 12 and an active region 11 extending in a first direction that is the same as the bit line direction, that is, in the Y-axis and repeated in a second direction that is orthogonal to the first direction, that is, in the X-axis. A tunnel oxide film (ie, a gate oxide film) 14 is formed on (10).

After depositing a first polysilicon layer on the resultant as a floating gate layer, a plurality of first polysilicon layer patterns 15 are formed by etching the first polysilicon layer on the field oxide layer 12 by a photolithography process. do. The first polysilicon layer patterns 15 extend in the first direction and repeat in the second direction, similarly to the field region 12.

Referring to FIG. 1C, after the ONO film 17 is formed on the first polysilicon film pattern 15 and the substrate 10, the second polysilicon film 19 and tungsten are formed thereon as a control gate layer. The silicide film 21 is deposited sequentially. The second polysilicon film 19 and the tungsten silicide film 21 are formed to have a thickness of about 1000 GPa each.

Subsequently, the oxide film was deposited on the tungsten silicide layer 21 by a plasma-enhanced chemical vapor deposition (PE-CVD) method or a low pressure chemical vapor deposition (LPCVD) method. The hard mask 23 is formed by evaporating to the above thickness. An insulating film such as silicon oxynitride (SiON) is deposited on the hard mask 23 to form an anti-reflective layer (ALL) (not shown).

Referring to FIG. 1D, a hard mask pattern 24 is formed by etching the anti-reflection film and the hard mask 23 into a gate pattern by a photolithography process. Subsequently, the tungsten silicide layer 21, the second polysilicon layer 19, the ONO layer 17, and the self-align etch method using the hard mask pattern 24 as an etching mask. The first polysilicon film pattern 15 is continuously anisotropically etched. Then, gates of the memory cell transistor and the selection transistor, which are composed of the floating gate 16, the dielectric film 18, and the control gate 25, are formed. In the above-described self-aligned etching process, the anti-reflection layer is also etched and the thickness of the anti-reflection layer remaining on the hard mask pattern 24 is almost negligible.

As a result of the above-described self-aligned etching process, the floating gate 16 is formed over the edge portion of the active region 11 and the field regions 12 on both sides thereof and arranged in a checkerboard shape. The control gate 25 has a polyside structure in which a second polysilicon layer pattern 20 and a tungsten silicide layer pattern 22 are stacked, and controls neighboring memory cells along a second direction orthogonal to a bit line. It is connected to the gate to form a word line.

Referring to FIG. 1E, the hard mask layer pattern 24 and the control over the field region 12 between each input / output (I / O) in a photolithography process to prevent signal delay caused by the resistance of the select transistors. The butting contact hole 26 is formed by removing the gate 25. Then, in the subsequent metal contact process, the metal layer connects the control gate 25 and the floating gate 16 of the selection transistor through the butting contact hole 26 to form a gate structure of one layer.

Referring to FIG. 1F, a nitride film such as silicon nitride (SiN) is deposited on the entire surface of the resultant to form an etch stop layer 28, and an oxide film is deposited thereon to a thickness of 5000 Å or more to form a memory cell transistor and a selection transistor. An interlayer insulating film 30 is formed to insulate the gate of and the common source line CSL to be formed in a subsequent process.

Subsequently, the interlayer insulating layer 30 and the etch stop layer 28 are partially etched by a photolithography process to form a contact hole 32 in which a common source line CSL is to be formed.

Referring to FIG. 1G, after depositing a third polysilicon layer to cover the interlayer insulating layer 30 while filling the contact hole 32, the interlayer may be etched back or chemical mechanical polishing (CMP). The third polysilicon film is removed until the surface of the insulating film 30 is exposed. Then, the common source line 34 made of the third polysilicon film is formed only inside the contact hole 32.

According to the conventional method described above, the following problems arise.

① Hard mask etching => control gate layer etching => ONO film etching => floating gate layer etching steps must be performed in order to form the gate of the memory cell transistor and the selection transistor. Particles and defects can occur. These defects can cause defects in which the contact holes are not-opened in subsequent bit line contact hole forming processes.

(2) Since a hard mask made of oxide is used for gate patterning, the hard mask is etched together when the ONO film is etched after the control gate layer is etched, so that a thickness thereof is lost. In this case, since the hard mask may not be used as an etching mask when etching the floating gate layer, the thickness of the hard mask should be increased to at least 2000 μs in consideration of the thickness loss. However, when the thickness of the hard mask is increased in this way, an aspect ratio increases when the floating gate layer is etched, thereby causing a profile defect such as undercutting of the floating gate layer.

③ After the gate is formed, a butt contact forming step for forming the gate of the selection transistor into a single layer structure must be performed, and thus a photolithography process is added.

④ Since the height of the common source line is higher than the height of the gate, the gap between the gate and the common source line not only makes it difficult to form a stable gap filling in the formation of subsequent bit line contact holes or metal contact holes, There is a problem that the alignment margin of the photolithography process is reduced.

⑤ If the above-described tungsten silicide film forming step is skipped and the control gate is formed only of the polysilicon film, the metal silicidation should be selectively performed only on the surface of the polysilicon control gate for high speed. For this purpose, after the deposition of the interlayer insulating film, the interlayer insulating film must be planarized by a chemical mechanical polishing (CMP) process until the surface of the polysilicon control gate is exposed. However, since the selectivity ratio between the oxide film and the polysilicon film for the CMP process is low, a poor metal silication may be caused due to the poor CMP uniformity.

Accordingly, an object of the present invention is to provide a nonvolatile memory device that forms a gate using a damascene process.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device in which a gate is formed using a damascene process.

1A to 1G are cross-sectional views and perspective views illustrating a method of manufacturing a conventional NAND type flash memory device.

2 is a layout diagram of a NAND flash memory device to which a preferred embodiment of the present invention is applied.

3 is a cross-sectional view of the flash memory device taken along the line AA ′ of FIG. 2.

4A through 11 are cross-sectional views and perspective views illustrating a method of manufacturing a flash memory device along the lines A-A 'and B-B' of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 101 active region

102: field region 104: gate oxide film

106: floating gate 108: first blocking film

110: interlayer insulating film 112: second blocking film

113: butting contact hole 114: trench

116: dielectric film 118: contact hole

120: control gate 122: common source line

124: metal silicide film

150: bit line contact hole

160: metal contact hole

In order to achieve the above object, the present invention is a semiconductor substrate divided into an active region and a field region; A plurality of floating gates formed on the semiconductor substrate; A first blocking layer formed on the floating gates and the semiconductor substrate; An interlayer insulating film and a second blocking film sequentially stacked on the first blocking film and having a plurality of trenches penetrating a portion of the first blocking film over each floating gate to partially expose an upper surface of each floating gate. ; A dielectric film formed on inner walls and bottom surfaces of the trenches; And a plurality of control gates planarized with a surface of the second blocking layer and formed in the trenches.

In order to achieve the above object, the present invention comprises the steps of: dividing a semiconductor substrate into an active region and a field region; Forming a plurality of floating gates on the semiconductor substrate; Sequentially forming a first blocking film, an interlayer insulating film, and a second blocking film on the floating gates and the semiconductor substrate; Partially etching the second blocking layer, the interlayer insulating film, and the first blocking film to form a plurality of trenches exposing the top surface of each floating gate; Forming a dielectric layer on the trenches and the second stop layer; Depositing a conductive layer on the dielectric layer to completely fill the trenches; And removing the conductive layer to the surface of the second blocking layer by chemical mechanical polishing to form a plurality of control gates in the trenches.

According to the present invention, the floating gate is first patterned and then the control gate is formed using a damascene process. In the damascene process, an insulating layer is etched to form a trench (or a hole), and then a conductive layer is deposited to completely fill the trench, and an excess conductive layer on the insulating layer is removed by chemical mechanical polishing (CMP) method. It is a process of forming wiring in the said trench.

That is, a first blocking film provided as an etch stop layer in a subsequent etching process, an interlayer insulating film, and a second stop serving as an abrasive stop layer in a subsequent CMP process on a semiconductor substrate having a plurality of floating gates arranged in a checkered pattern. The films are formed sequentially. The second blocking layer, the interlayer insulating layer, and the first blocking layer are etched to form a trench for control gate patterning, and then a control gate conductive layer is deposited to completely fill the trench. Subsequently, the conductive layer is removed by the CMP method until the surface of the second blocking film provided as the polishing blocking layer is exposed to form a control gate inside the trench.

As such, since the damascene process requires only one etching process after forming the floating gate and forming the control gate, particles and defects caused by the etching process can be prevented. In addition, when the trenches for the control gate patterning are formed, a butting contact hole for connecting the floating gate and the control gate is formed together, thereby simplifying the process. In addition, since the common source line is formed together when forming the control gate, the step difference between the gate and the common source line is eliminated.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a layout diagram of a NAND type flash memory device to which a preferred embodiment of the present invention is applied. FIG. 3 is a cross-sectional view of the flash memory device taken along line AA ′ of FIG. 2.

2 and 3, the active regions 101 in which the channel and the source / drain of the memory cell transistor are to be formed are spaced apart by the field regions 102 and extend in the first direction, that is, the Y axis, in parallel with each other. It is arranged repeatedly in the second direction, that is, the X axis.

On the active region 101, n word lines W / L ₁ , W / L ₂ ,..., W / L _n extend in the second direction (ie, X-axis) and in the first direction (ie, Y-axis). And arranged repeatedly, thereby forming a memory cell transistor having a stacked gate structure composed of the floating gate 106 and the control gate 120. Thus, high concentration source / drain regions are formed on the surface of the exposed active region 102 between the word lines W / L ₁ , W / L ₂ ,..., W / L _n spaced at predetermined intervals.

A plurality of memory cell arrays arranged in the XY direction by an arrangement of the active region 101 extending in the Y axis and the word lines W / L ₁ , W / L ₂ ,..., W / L _n extending in the X axis. When forming a, a string select line (SSL) and a ground select line (GSL), which are select transistors, are respectively disposed outside the first word line (W / L ₁ ) and the nth word line (W / L _n ). Form a "string" as the memory unit of. In the string, n memory cell transistors are connected in series while sharing a source / drain.

Gates of the memory cell transistor and the selection transistor according to the present invention have the following structure. That is, the first blocking layer 108 is formed on the semiconductor substrate 100 in which the plurality of floating gates 106 are arranged in a checker pattern, in which a subsequent etching process is provided as an etch stop layer. An interlayer insulating layer 110 and a second blocking layer 112 provided as an abrasive blocking layer in a subsequent chemical mechanical polishing (CMP) process are sequentially formed on the first blocking layer 108. A plurality of trenches 114 for control gate patterning are formed through the first blocking layer 108, the interlayer insulating layer 110, and the second blocking layer 112 on the floating gate 106. A dielectric film 116 is formed on the inner wall and the bottom surface of the trenches 110 and is planarized with the surface of the second blocking layer 112 to control the plurality of control gates 120 in the trenches 110. ) Is formed.

As described above, according to the present invention, since the control gate 120 is formed using the damascene process, the control gate 120 should be formed of a single layer of polysilicon. Therefore, after the control gate 120 is formed to reduce the gate resistance to implement a high speed operation, the control gate is formed by a metal silicidation reaction using the second blocking layer 112 as a silicide blocking layer. The metal silicide film 124 is formed only on the upper surface of the 120.

Select transistors constituting the string select line SSL and the ground select line GSL may have a floating gate 106 in the field region 102 between each input / output I / O to prevent signal delay caused by a resistor. ) And a butting contact hole (reference numeral 113 of FIG. 7) for connecting the control gate 120. Thus, the select transistors operate as MOS transistors having electrically one gate. According to the present invention, since the butting contact hole is simultaneously formed when the trench 114 for patterning the control gate is formed, the photolithography process for forming the butting contact hole can be omitted.

One bit line contact hole 150 is provided between the string selection lines SSL adjacent to each other, and the two strings share one bit line contact hole 150 in the form of a mirror image. K bit lines repeated along the X axis while extending in the Y axis so as to be orthogonal to the word line through at least one interlayer insulating film on the word lines W / L ₁ , W / L ₂ ,..., W / L _n . (B / L _k , B / L _k-1 , B / L _k-2 ,...) Are formed.

The outer side of the "string" is provided with a common source line (CSL) 122 extending in the X-axis direction between the ground selection line (GSL) adjacent to each other, a plurality of on the common source line 122 One metal contact hole 160 is formed for each bit line. The common source line 122 may expose the second blocking layer 112, the interlayer insulating layer 110, and the first blocking layer to expose the active region between the floating gates 106 of the ground selection line GSL adjacent to each other. It is formed in the contact hole 118 penetrating the film 108. Therefore, according to the present invention, since the height of the common source line 112 and the gate height of the transistor are the same, the step difference between the gate and the common source line 112 can be eliminated to increase the margin of a subsequent photolithography process. .

4A through 11 are cross-sectional views and perspective views illustrating a method of manufacturing a flash memory device along the lines A-A 'and B-B' of FIG. 2.

4A and 4B, by forming a plurality of field oxide films extending in a first direction and repeating in a second direction on a semiconductor substrate 100 through a shallow trench isolation (STI) process. The semiconductor substrate 100 is divided into an active region 101 and a field region 102.

Subsequently, a tunnel oxide film (ie, a gate oxide film) 104 is formed on the active region 101 in a thickness of about 30 to 100 kPa by a thermal oxidation process. Alternatively, the gate oxide layer may be grown on the substrate 100 to have a different thickness of the gate oxide layer of the select transistor and the cell transistor, and then the gate oxide layer of the cell transistor region may be removed by a wet etching process using a photolithography process. 104 may be formed.

Subsequently, a polysilicon film doped with impurities on the gate oxide film 104 and the semiconductor substrate 100 is deposited to a thickness of about 1000 GPa or more to form a floating gate layer 105.

5A and 5B, the floating gate layer 105 is patterned by a photolithography process so that a plurality of floating gates 106 are disposed over an edge portion of the active region 101 and the field regions 102 on both sides thereof. To form. The floating gates 106 are arranged in a checkerboard shape.

Referring to FIG. 6, first blocking layers 108 may be formed on the floating gates 106 and the semiconductor substrate 100 to serve as an etch stop layer during a subsequent etching process. Preferably, the first blocking film 108 is formed by depositing a nitride film to a thickness of about 300 to 500 kPa by a low pressure chemical vapor deposition (LPCVD) method.

An oxide film is deposited on the first blocking layer 108 to a thickness of about 2000 GPa or more to form an interlayer insulating layer 110.

A second blocking layer 112 is formed on the interlayer insulating layer 110 to serve as an abrasive blocking layer in a subsequent chemical mechanical polishing (CMP) process. Preferably, the second blocking film 112 is formed by depositing a nitride film to a thickness of about 300 GPa or more by low pressure chemical vapor deposition (LPCVD).

Referring to FIG. 7, the second blocking layer 112, the interlayer insulating layer 110, and the first blocking layer 108 are partially etched by a photolithography process to expose a portion of the upper surface of the floating gate 106. Multiple trenches 114 are formed. At the same time, a butting contact hole 113 for connecting the floating gate 106 and the control gate to be formed in a subsequent process is formed in a predetermined region of the semiconductor substrate 100.

Referring to FIG. 8, a dielectric layer 116 such as ONO is formed on the trenches 114 and the second blocking layer 112 to have a thickness of about 100 to about 300 μm. The dielectric layer 116 maintains charge characteristics charged in the floating gate 106 and transfers the voltage of the control gate to the floating gate 106.

Referring to FIG. 9, a ground select line GSL adjacent to each other by partially etching the dielectric layer 116, the second blocking layer 112, the interlayer insulating layer 110, and the first blocking layer 108 by a photolithography process. A contact hole 118 exposing the active region between the electrodes is formed.

Referring to FIG. 10, the conductive layer 119 is thick enough to sufficiently fill the trench 114 and the contact hole 118 in the contact hole 118, the trench 114, and the dielectric layer 116. For example, a polysilicon film doped with impurities is deposited.

Referring to FIG. 11, the conductive layer 119 is removed until the surface of the second blocking layer 112 is exposed by a chemical mechanical polishing (CMP) process. Then, the control gate 120 made of the conductive layer is formed in the trench 114. At the same time, a common source line 112 made of the conductive layer is formed in the contact hole 118. Thus, since the gates of the memory cell transistor and the selection transistor and the common source line 112 are formed at the same height, the step difference between them can be eliminated to increase the margin of the subsequent photolithography process. In addition, since the second blocking layer 112 made of nitride acts as an abrasive blocking layer during the CMP process, the open area of the conductive layer 119 becomes uniform.

Subsequently, after performing RF plasma etching to remove the native oxide layer or the like, a metal layer on the control gate 120, the common source line 112, and the second blocking layer 112 may be formed in-situ. Not shown), for example a cobalt (Co) layer is deposited by a sputtering method. Subsequently, the metal silicide film 124 is formed only on the surfaces of the control gate 120 and the common source line 112 exposed by performing two heat treatments using Rapid Thermal Annealing (RTA) or a furnace. For example, a cobalt disilicide (CoSi ₂ ) film is formed. In this case, the second blocking layer 112 serves as a silicidation blocking layer.

As described above, according to the present invention, the following effects can be obtained.

In the prior art, since a multi-step etching process is required to form gates of a memory cell transistor and a selection transistor, particles and defects are very likely to occur during the etching process. In contrast, in the present invention, since the control gate is formed using the damascene process, only one etching process is performed until the control gate is formed after the floating gate is formed. Therefore, the possibility of particle and defect generation by the etching process can be eliminated.

② Conventionally, since a hard mask made of oxide is used for gate patterning, when the thickness of the hard mask is increased, an aspect ratio becomes large when the floating gate layer made of polysilicon is etched to cause a profile defect. On the contrary, in the present invention, since the floating gate is first formed, and then the interlayer insulating film made of oxide is deposited only by the height of the control gate, etching of the oxide film excellent in anisotropic etching characteristics as well as a small aspect ratio when etching the interlayer insulating film. Therefore, a good gate profile can be obtained.

In the prior art, since the butting contact process is performed after the gates of the memory cell transistor and the selection transistor are formed, a photolithography process is added. On the contrary, in the present invention, since a butting contact hole for connecting the floating gate and the control gate is formed together when the trench for the control gate patterning is formed, a separate photolithography process for the butting contact is not necessary, thereby simplifying the process. have.

④ Conventionally, since the height of the common source line is higher than the gate height, there is a problem in that the margin of the subsequent photolithography process is reduced due to the step between the gate and the common source line. In contrast, in the present invention, when the control gate is formed inside the trench, the common source line is formed together, so that the height of the gate and the common source line are the same, thereby eliminating the step.

⑤ Conventionally, when the interlayer insulating film is planarized by the CMP process to form a metal silicide film on the surface of the polysilicon control gate, a poor selectivity between the oxide film and the polysilicon film for the CMP process causes a failure of the metal silicide. In contrast, in the present invention, when the control gate is formed by performing the CMP process on the polysilicon film, the open area of the control gate made of the polysilicon film becomes uniform because the second blocking film made of nitride acts as the polishing blocking layer. . Thus, the metal silicidation process for the polysilicon control gate can proceed well.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (13)

A semiconductor substrate divided into an active region and a field region; A plurality of floating gates formed on the semiconductor substrate; A first blocking layer formed on the floating gates and the semiconductor substrate; An interlayer insulating film and a second blocking film sequentially stacked on the first blocking film and having a plurality of trenches penetrating a portion of the first blocking film over each floating gate to partially expose an upper surface of each floating gate. ; A dielectric film formed on inner walls and bottom surfaces of the trenches; And And a plurality of control gates planarized with a surface of the second blocking layer to fill the trenches. 2. The active device of claim 1, further comprising a contact hole formed over the first blocking layer, the interlayer insulating layer, and the second blocking layer over the active region between the floating gate and the floating gate. Further includes a common source line, And the common source line is formed at the same height as the control gate. The nonvolatile memory device of claim 1, wherein the first and second blocking layers are formed of nitride. The nonvolatile memory device of claim 1, wherein the control gate is formed of polysilicon doped with impurities. The nonvolatile memory device of claim 4, further comprising a metal silicide layer formed by a silicide reaction on an upper surface of the control gate. Dividing the semiconductor substrate into an active region and a field region; Forming a plurality of floating gates on the semiconductor substrate; Sequentially forming a first blocking film, an interlayer insulating film, and a second blocking film on the floating gates and the semiconductor substrate; Partially etching the second blocking layer, the interlayer insulating film, and the first blocking film to form a plurality of trenches exposing the top surface of each floating gate; Forming a dielectric layer on the trenches and the second stop layer; Depositing a conductive layer on the dielectric layer to completely fill the trenches; And Removing the conductive layer to the surface of the second stop layer by chemical mechanical polishing to form a plurality of control gates in the trenches. The method of claim 6, wherein the forming of the plurality of floating gates comprises: Forming a gate oxide film on the semiconductor substrate; Depositing a floating gate layer on the gate oxide film and the semiconductor substrate; And patterning the floating gate layer to form a plurality of floating gates arranged in a checkerboard shape. The method of claim 6, wherein the forming of the plurality of trenches simultaneously forms a butting contact hole that partially exposes an upper surface of the floating gate to connect the floating gate and the control gate in a predetermined region of the semiconductor substrate. A method of manufacturing a nonvolatile memory device, characterized in that. The contact hole of claim 6, further comprising partially etching the dielectric layer, the second blocking layer, the interlayer insulating layer, and the first blocking layer to expose the active region between the floating gate and the floating gate before depositing the conductive layer. And forming a non-volatile memory device. The method of claim 9, wherein the forming of the plurality of control gates simultaneously forms a common source line formed of the conductive layer in the contact hole. 7. The method of claim 6, wherein the first and second blocking films are formed of nitride. The method of claim 6, wherein the conductive layer is formed of polysilicon doped with impurities. The method of claim 12, after forming the plurality of control gates: Depositing a metal layer on the entire surface of the resultant product in which the control gates are formed; And And silicating a metal of the metal layer and silicon of the control gate to form metal silicide layers on surfaces of the control gates.