JP4786610B2 - Thin film transistor and liquid crystal display device - Google Patents

Description

  The present invention relates to a thin film transistor and a liquid crystal display device.

  In recent years, a technique for forming a wiring by an ink jet method without using photolithography has been proposed. In this technique, for example, as disclosed in JP-A-11-204529 (published July 30, 1999), an affinity region having affinity for a wiring forming material on a substrate on which wiring is formed; A non-affinity region having non-affinity with respect to the wiring forming material is formed, and a wiring is formed by dropping (attaching) a droplet of the wiring material to the affinity region by an ink jet method (hereinafter, referred to as a wiring region). The term “dropping” includes both “dropping” and “flying”).

  In addition, US Patent Application Publication No. US2003 / 0003231A1 corresponds to Japanese Patent Application Laid-Open No. 11-204529.

  Similarly, Japanese Patent Laid-Open No. 2000-353594 (published on Dec. 19, 2000) discloses that both sides of a wiring formation region are suppressed in order to suppress the protrusion of the wiring material from the wiring formation region in the wiring formation technique using the inkjet method. It is disclosed that a bank is formed, the upper part of the bank is made non-lyophilic (liquid repellency), and the wiring formation region is made lyophilic.

  Note that Japanese Patent Application Laid-Open No. 2000-353594 corresponds to European Patent Application EP0987778 A1.

  SID 01 DIGEST, pages 40-43, 6.1: Invited Paper: All-Polymer Thin Film Transistors Fabricated by High-Resolution Ink-jet Printing A technique for forming a TFT using a material as a material is disclosed.

In this technique, after a polyimide strip is formed on the TFT channel portion by photolithography, a conductive polymer electrode material is printed on both sides of the channel portion by an ink jet printer. It has been reported that since the polyimide strip has liquid repellency, the source / drain electrodes could be formed on both sides of the channel portion without the electrode material riding on the strip.
Japanese Patent Laid-Open No. 11-204529 (published July 30, 1999) JP 2000-353594 A (published on December 19, 2000) Pages 40-43 of SID 01 DIGEST, 6.1: Invited Paper: All-Polymer Thin Film Transistors Fabricated by High-Resolution Ink-jet Printing (Author Takeo Kawase et al.)

  Problems to be solved by the present invention will be described below.

  When the above-described forming technique such as wiring by the ink jet method is used for manufacturing a thin film transistor, the number of necessary masks is reduced and the number of manufacturing steps is reduced as compared with the case of using photolithography. In addition, a large-scale processing apparatus for forming wiring and the like is not necessary, and the equipment cost is reduced. As a result, the cost can be reduced.

  Therefore, since such advantages can be enjoyed, it is effective to use a technique for forming wiring or the like by an ink jet method for forming a thin film transistor.

  However, when the electrodes are formed by simply dropping droplets of the electrode material onto the source electrode or drain electrode formation region of the thin film transistor by the inkjet method, the droplets of the dropped droplet adhere to the channel portion of the thin film transistor. There is a risk that it will remain in that position.

  In this case, leakage occurs between the source and drain electrodes due to the splash in the channel portion, or a residue of the n + layer is generated by using the splash as a mask when the n + layer is processed. Leak current flows, and a desired TFT characteristic cannot be obtained.

  The present invention has been made to solve the above-described problems, and its main object is to provide a thin film transistor having an electrode configuration in which droplets of electrode material do not adhere to the channel portion of the thin film transistor. There is.

In order to achieve the above object, the thin film transistor of the present invention comprises: (i) a semiconductor layer facing a gate electrode through a gate insulating layer; and (ii) a source electrode and a drain electrically connected to the semiconductor layer. A thin film transistor including an electrode and (iii) a channel portion formed in the semiconductor layer between the source electrode and the drain electrode, wherein the source electrode is continuous with a source wiring through a source transition portion, and The drain electrode is continuous with the drain wiring through the drain transition portion, and the source transition portion and the drain transition portion are provided at positions outside the region of the semiconductor layer, and the electrode width in the source transition portion is the source width The electrode width at the drain transition portion is gradually extended from the wiring to the semiconductor layer region, and / or It is characterized by gradually spreading toward the layer area .

According to the above structure, since the provided source transition part and the drain transition part and the position of the outer region (region semiconductor layer is disposed) of the semiconductor layer of the drain electrode of the source electrode, the source electrode and the drain electrode , The source transition portion and the drain transition portion, which are outside the region of the semiconductor layer, can be set as a dropping position when a droplet of the liquid electrode material is dropped.

  Thereby, when the source electrode and the drain electrode are formed, it is possible to prevent the droplets from adhering to the channel portion between the two electrodes. Therefore, it is possible to avoid a situation in which a residue of the n + layer is generated by using the above-mentioned splash as a mask, a leak current flows between the source and the drain, and a desired TFT characteristic cannot be obtained.

  In addition, according to the above configuration, the dropped droplet can easily flow in the direction in which the electrode width is increased, so that the dropping position can be separated from the channel portion, and the dropping portion can be reliably extended to the semiconductor portion. Electrode material can be flowed to the region.

  The liquid crystal display device of the present invention is configured to include the thin film transistor of the present invention.

  Other objects, features, and advantages of the present invention will be fully understood from the following description. The advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

[ Reference form 1]
One embodiment of the present invention will be described below with reference to the drawings.
The liquid crystal display device according to an embodiment of the reference of the present invention has the pixel shown in FIG. 2 (a). The figure is a plan view showing a schematic configuration of one pixel in the TFT array substrate of the liquid crystal display device. Further, FIG. 2B shows a cross-sectional view taken along line AA in FIG.

  As shown in FIGS. 2A and 2B, in the TFT array substrate 11, the gate electrode 13 (gate wiring) and the source electrode 17 (source wiring) are provided in a matrix on the glass substrate 12, and are adjacent to each other. An auxiliary capacitance electrode 14 (auxiliary capacitance wiring) is provided between the gate electrodes 13 (gate wiring).

  As shown in FIG. 2B, the TFT array substrate 11 has a gate electrode 13 and an auxiliary capacitance electrode 14 on a glass substrate 12 at positions from the TFT portion 22 to the auxiliary capacitance portion 23. The gate insulating layer 15 is provided.

  A semiconductor layer 16 having an a-Si layer is formed on the gate electrode 13 via the gate insulating layer 15, and ends of the source electrode 17 and the drain electrode 18 are formed thereon. The other end of the drain electrode 18 reaches a position on the auxiliary capacitance electrode 14 through the gate insulating layer 15, and a contact hole 24 is formed at this position. A protective film 19 is formed on the source electrode 17 and the drain electrode 18, and a photosensitive acrylic resin layer 20 and a pixel electrode 21 are sequentially formed thereon.

  The above-described configuration of the TFT section 22 is called a bottom gate structure, but the present invention is not limited to the bottom gate structure, and the gate electrode 13 is formed on the semiconductor layer 16 via the gate insulating layer 15. The present invention can also be applied to a top gate structure in which is formed.

  Therefore, in the TFT portion 22 of the present invention, the semiconductor layer 16 is formed so as to face the gate electrode 13 with the gate insulating layer 15 interposed therebetween, and the source electrode 17 and the drain electrically connected to the semiconductor layer 16 are also provided. It is sufficient if the electrode 18 is formed.

In the present reference, the production of the TFT array substrate 11, for example, by an inkjet method, the pattern forming apparatus is used for discharging or dropping the material forming layers. As shown in FIG. 3, the pattern forming apparatus includes a mounting table 32 on which a substrate 31 (corresponding to the glass substrate 12) is mounted, and includes, for example, a wiring material on the substrate 31 on the mounting table 32. Ink jet head 33 as a droplet discharge means for discharging fluid ink (droplet or fluid material), X direction drive unit 34 for moving inkjet head 33 in the X direction, and Y direction drive unit for moving in the Y direction 35 is provided.

  The X and Y directions are directions parallel to the X and Y axes of two-dimensional orthogonal coordinates with respect to the plane including the substrate 31.

  The pattern forming apparatus performs various controls such as an ink supply system 36 that supplies ink to the ink jet head 33, ejection control of the ink jet head 33, and drive control of the X direction drive unit 34 and the Y direction drive unit 35. A control unit 37 is provided. From the control unit 37, application position information is output to the X and Y direction drive units 34 and 35, and ejection information is output to a head driver (not shown) of the inkjet head 33. As a result, the inkjet head 33 operates in conjunction with the X and Y direction drive units 34 and 35, and a target amount of droplets is supplied to a target position on the substrate 31.

  The inkjet head 33 may be a piezo type using a piezo actuator, a bubble type having a heater in the head, or another type. The amount of ink discharged from the inkjet head 33 can be controlled by controlling the applied voltage. The droplet discharge means may be of any type as long as it can supply droplets, such as a method of simply dropping droplets, instead of the inkjet head 33.

Next, a method for manufacturing the TFT array substrate 11 in the liquid crystal display device will be described.
In the present reference, TFT array substrate 11, as shown in FIG. 4, a gate preprocessing step 41, a gate line applying forming step 42, a gate insulating layer forming, the semiconductor layer forming step 43, a semiconductor layer formation step 44 Source / drain line pretreatment step 45, source / drain line coating formation step 46, channel portion processing step 47, protective film formation step 48, protective film processing step 49, and pixel electrode formation step 50.

(Gate pretreatment step 41)
In this gate pretreatment step 41, pretreatment for the gate line coating formation step 42 is performed. In the next gate line coating formation step 42, a gate line is formed by dropping a liquid wiring material using a pattern forming apparatus. Therefore, here, processing for appropriately applying the liquid wiring material to the gate line forming region 61 shown in FIG. 5A by discharging (dropping) the liquid wiring material from the pattern forming apparatus is performed. FIG. 5A is a plan view of the glass substrate 12 included in the TFT array substrate 11.

  This processing is roughly as follows. In the first treatment, the substrate (glass substrate 12) is given a property that the substrate is easily wetted or repelled with respect to the liquid wiring material, and a hydrophilic region (lyophilic region) as the gate line forming region 61 is provided. And a water repellent treatment (liquid repellent treatment) for patterning a water repellent region (liquid repellent region) as a gate line non-formation region. The second process is a process of forming a guide for regulating the liquid flow, that is, a guide along the gate line formation region 61.

  In the former, a hydrophilic / hydrophobic treatment with a photocatalyst using titanium oxide is representative. In the latter, a resist material is used and guide formation is performed by photolithography. Further, in order to impart repellency to the guide or the substrate surface, there are cases in which they are exposed to CF4 or O2 gas in plasma. The resist is removed after the wiring is formed.

  Here, the photocatalytic treatment using titanium oxide was performed as follows. That is, a glass substrate 12 of the TFT array substrate 11 was coated with a mixture (water repellent material) of ZONYL FSN (trade name: manufactured by DuPont), which is a fluorine-based nonionic surfactant, mixed with isopropyl alcohol. Further, a titanium dioxide fine particle dispersion and a mixture of ethanol were applied as a photocatalyst layer to the gate wiring pattern mask by spin coating and baked at 150 ° C. Then, using the mask, the glass substrate 12 was exposed to UV light. As the exposure conditions, 365 nm ultraviolet light was used, and irradiation was performed at an intensity of 70 mW / cm 2 for 2 minutes.

  More specific description will be given below with reference to FIGS. 12 (a) to 12 (d). First, as shown in FIG. 12A, the wettability changing layer 2 is formed by applying the water-repellent material on the glass substrate 12 using a spin coat method or the like and drying it. A silane coupling agent may be used as the water repellent material.

  Next, as shown in FIG. 12B, UV exposure is performed under the above exposure conditions through a photomask 3 in which a mask pattern 4 made of chromium or the like and a photocatalyst layer 5 made of titanium oxide or the like are previously formed.

  As a result, as shown in FIGS. 12C and 12D, only the UV-exposed portion has improved wettability, and the hydrophilic pattern 6 corresponding to the gate line formation region 61 can be formed.

(Gate line coating formation process 42)
This gate line coating formation step 42 is shown in FIGS. FIG. 5B is a plan view of the glass substrate 12 in a state in which the gate electrode 13 and the auxiliary capacitance electrode 14 are formed between the adjacent gate electrodes 13, and FIG. FIG.

  As shown in FIG. 5B, the portion protruding from one gate electrode 13 toward the adjacent auxiliary capacitance electrode 14 is finally the TFT portion as shown in FIG. 1 and FIG. The gate electrode 66 is formed. However, the gate electrode 13 depicted on the upper side of the gate electrode 13 shown in FIG. 5 is omitted for the sake of simplicity.

  In this step, a wiring material is applied to the gate line formation region 61 on the glass substrate 12 as shown in FIGS. As the wiring material, a material obtained by dispersing Ag fine particles coated with an organic film as a surface coating layer in an organic solvent was used. The wiring width was about 50 μm, and the amount of wiring material discharged from the inkjet head 33 was set to 80 pl.

  Since the wiring material discharged from the inkjet head 33 spreads along the gate line formation region 61 on the surface subjected to the hydrophilic / water-repellent treatment, the discharge interval on the gate line formation region 61 is set to be approximately 500 μm. After coating, baking was performed at 350 ° C. for 1 hour, and wirings for the gate electrode 13 and the auxiliary capacitance electrode 14 were formed.

  The reason why the baking temperature is set to 350 ° C. is that processing heat of about 300 ° C. is applied in the semiconductor layer forming step 44 in the next stage. Therefore, the firing temperature is not limited to this temperature. For example, when forming an organic semiconductor, the annealing temperature may be set to 100 to 200 ° C. In such a case, the firing temperature can be lowered to 200 to 250 ° C.

  Further, as the wiring material, in addition to Ag, use may be made of a simple substance such as Ag—Pd, Ag—Au, Ag—Cu, Cu, Cu—Ni or the like containing fine particles of an alloy material or a paste material in an organic solvent. Is possible. Furthermore, for the wiring material, the surface coating layer that protects the fine particles and the dissociation temperature of the organic material contained in the organic solvent are controlled in accordance with the necessary firing temperature, and the desired resistance value and surface state are set. It is possible to obtain. The dissociation temperature is a temperature at which the surface coat layer and the organic solvent evaporate.

(Gate insulation layer deposition / semiconductor layer deposition step 43)
FIG. 6A shows this gate insulating layer deposition / semiconductor layer deposition step 43.
In this process, three layers of the gate insulating layer 15, the a-Si film formation layer 64, and the n + film formation layer 65 were continuously formed on the glass substrate 12 that had undergone the gate line coating formation step 42 by CVD. The gate insulating layer 15, the a-Si layer 64, and the n + layer 65 were formed to have a thickness of 0.3 μm, 0.15 μm, and 0.05 μm, respectively, without breaking the vacuum (while maintaining the vacuum state). The film forming temperature was 300 ° C.

(Semiconductor layer forming step 44)
This semiconductor layer forming step 44 is shown in FIGS. 6B to 6E. 6E is a plan view showing the glass substrate 12 that has undergone the semiconductor layer forming step 44, FIG. 6D is a cross-sectional view taken along the line CC in FIG. 6E, and FIGS. (C) is a longitudinal cross-sectional view in the position shown in FIG.6 (d) which shows each process of the semiconductor layer formation process 44. FIG.

  In this step 44, a resist material is applied on the n + film forming layer 65, and this resist material is processed by a photolithography process and an etching process, so that the shape of the semiconductor layer 16 is formed as shown in FIG. The resist layer 67 is formed.

  Next, using gas (for example, SF6 + HCl), as shown in FIG. 6C, the n + film formation layer 65 and the a-Si film formation layer 64 are dry-etched to form the n + layer 69 and the a-Si layer. 68 was formed. Thereafter, the glass substrate 12 was washed with an organic solvent, and the resist layer 67 was peeled and removed as shown in FIG.

(Source / drain line pretreatment step 45)
In this source / drain line pretreatment step 45, a wiring guide is formed along the contour of the region (source / drain formation region) where the source electrode 17 and the drain electrode 18 shown in FIG.

  Here, the source electrode 17 and the drain electrode 18 corresponding to the grid-like source wiring and drain wiring shown in FIG. 2A and the source electrode 17 and the drain electrode 18 in the TFT portion 22 are formed simultaneously. Therefore, the source / drain formation region includes a source wiring and a drain wiring formation region.

  The wiring guide was formed using a photoresist material. That is, a photoresist was applied on the glass substrate 12 that had undergone the semiconductor layer forming step 44, pre-baked, exposed and developed using a photomask, and then post-baked to form a wiring guide. The width of the wiring guide formed here was about 10 μm, and the width of the groove formed by the wiring guide (width of the wiring formation region) was about 10 μm.

  The SiNx surface (upper surface of the gate insulating layer 15) is subjected to a hydrophilic treatment with oxygen plasma so that the wiring material applied by the pattern forming apparatus is well adapted to the surface to be the base surface, and the wiring guide is plasma. Water repellent treatment may be performed by flowing CF 4 gas into the inside.

  The above-described hydrophilic / water-repellent treatment is basically the same as the hydrophilic / water-repellent treatment disclosed in Japanese Patent Application Laid-Open No. 2000-353594 (European Patent Application EP0987778 A1). The wiring guide has water repellency because the surface layer of the photoresist material (organic resin) is modified with F (fluorine). SF6 gas may be used in place of the CF4 gas.

  Further, instead of forming the wiring guide, the hydrophilic / hydrophobic treatment according to the wiring electrode pattern (the hydrophilic region as the source / drain line forming region) by the photocatalytic hydrophilic / hydrophobic treatment method used for forming the gate electrode. And a process of forming a water-repellent region as a source / drain line non-forming region in accordance with a desired pattern).

(Source / drain line coating formation process 46)
In this source / drain line coating formation step 46, the source electrode 17 and the drain electrode 18 were formed by applying a wiring material to the source / drain formation region formed by the wiring guide using a pattern forming apparatus. Here, the discharge amount of the wiring material from the inkjet head 33 is set to 2 pl. Further, an Ag fine particle material was used as the wiring material, and the formed film thickness was 0.3 μm. The firing temperature was 200 ° C. After firing, the wiring guide was removed with an organic solvent.

  Note that although the same wiring material as that used for the gate electrode 13 can be used as the wiring material, since the formation of a-Si is performed at about 300 ° C., the firing temperature is 300 ° C. or lower. There is a need to do.

(Channel part processing step 47)
Here, the TFT channel portion 72 is processed. First, the wiring guide was removed with an organic solvent. Or the wiring guide of the channel part 72 was removed by ashing. Next, the n + layer 69 was oxidized by ashing or laser oxidation to make it nonconductive.

(Protective film forming step 48, protective film processing step 49)
Here, first, an SiO 2 film to be the protective film 19 (FIG. 2B) was formed by CVD on the glass substrate 12 on which the source and drain electrodes were formed. Next, an acrylic resist material to be the photosensitive acrylic resin layer 20 was applied on the SiO2 film, and a pixel electrode formation pattern and a terminal processing pattern were formed on the resist layer.

  In the formation of the pattern, a part for removing the resist layer after development and a part for removing about half in thickness were formed on the mask. The latter is an area for halftone exposure having a transmittance of about 50%.

  That is, the protective film 19 and the photosensitive acrylic resin layer 20 are etched to remove all the resist layer in the portion where the terminal surface of the contact hole 24 is formed, while the photosensitive acrylic resin is removed in the portion where the pixel electrode 21 is formed. The thickness of the resist layer was adjusted to half of the coating thickness so that the periphery of the pixel electrode formation pattern in the layer 20 became a guide shown in FIG.

  Next, using the resist layer as a mask, first, the protective film 19 and the photosensitive acrylic resin layer 20 in the terminal portion were removed by dry etching.

(Pixel electrode forming step 50)
On the pixel electrode formation pattern of the photosensitive acrylic resin layer 20, an ITO fine particle material as a pixel electrode material was applied by a pattern formation apparatus, and baked at 200 ° C. to form the pixel electrode 21. Thereby, a TFT array substrate 11 was obtained.

  As described above, in the manufacturing method of the TFT array substrate 11, the number of masks can be reduced as compared with a conventional manufacturing method that does not use an ink-jet pattern forming device. It can be greatly reduced. Thereby, the amount of capital investment can also be reduced significantly.

  The TFT array substrate 11 having the bottom gate TFT portion 22 can be manufactured by the manufacturing process described above. However, when manufacturing the TFT array substrate 11 having the top gate structure, the manufacturing process is as shown in FIG. It changes like the flow shown in.

  Each process 121-132 shown in FIG. 18 is appended with the number of the corresponding process among the processes 41-50 shown in FIG.

  In the manufacturing process of the top gate structure, the gate electrode 13 is formed after the source electrode 17 and the drain electrode 18 and the semiconductor layer 16 are formed. It is basically the same as the contents of 50.

  However, the gate insulating layer formation / semiconductor layer formation step 43 includes a semiconductor n + layer formation step 123, a semiconductor n + layer formation (processing) step 124, a semiconductor layer (a-Si layer) formation step 125, The process is separated into a semiconductor layer forming (processing) step 126 and a gate insulating layer forming step 127.

  In each of the semiconductor n + layer formation (processing) step 124 and the semiconductor layer formation (processing) step 126, as described in the formation of the semiconductor layer 16, the resist formed by the photolithography step and the etching step is used as a mask. Dry etching may be performed.

  Next, a method for forming the source electrode 17 and the drain electrode 18 in the TFT portion 22 will be described in detail.

  As shown in FIGS. 1 and 2A, the source electrode 17 and the drain electrode 18 are formed so as to cross the TFT portion gate electrode 66. In the configuration shown in FIG. 1, the source electrode 17 and the drain electrode 18 are branched into a plurality of lines in the TFT portion 22. That is, the source electrode 17 includes a plurality of branch electrode portions 17a, and the drain electrode 18 includes a plurality of branch electrode portions 18b. The branch electrode portions 17a of the source electrode 17 and the branch electrode portions 18b of the drain electrode 18 are alternately arranged, and a channel portion 72 is formed between the adjacent branch electrode portions 17a and 18b. The width of the branch electrode portions 17a and 18b is, for example, 10 μm, and the width of the channel portion 72 (the distance between the branch electrode portions 17a and 18b) is, for example, 10 μm.

  When the source electrode 17 and the drain electrode 18 of the TFT section 22 are formed by dropping the electrode material from the pattern forming apparatus, a fine droplet of the wiring material is applied to each electrode, or the droplet of the wiring material is applied. Apply over multiple wires.

  Here, the wiring width is usually several μm, and in order to realize a droplet having a diameter of several μm, it is necessary to realize a discharge amount far below 1 pl in the pattern forming apparatus. However, it is difficult to realize such a droplet diameter. Moreover, even if it is realized, the liquid droplets are applied to the 2 to 3 million TFT portions 22 of the liquid crystal panel in order to apply the fine droplets in terms of the life of the inkjet head 33 in terms of time. It is also difficult. Therefore, a droplet having a diameter larger than several μm is dropped.

  In this case, when droplets are directly dropped on the electrodes (branch electrode portions 17a and 18a) of the channel portion 72, the droplets of the wiring material may adhere to the channel portion 72 or a residue of the wiring material may be generated.

  When the wiring material remains in the channel portion 72 in this way, when the n + layer 69 of the channel portion 72 is etched, the remaining wiring material serves as a mask and the n + layer 69 remains. For this reason, a leak occurs between the source electrode 17 and the drain electrode 18.

  In order to clarify the reason why this leak occurs, processing of the channel portion 72 will be described. FIG. 14A shows a state before the source / drain electrodes are formed in the E-E ′ cross section of FIG. 13. After the semiconductor layer 16 composed of the a-Si layer 68 and the n + layer 69 is formed, a guide 200 for separating the source electrode 17 and the drain electrode 18 on the channel portion 72 is formed.

  In this cross-sectional view, the upper part is shown from the gate insulating layer 15 where the semiconductor layer 16 is formed, and the gate electrode 66 is omitted.

  Next, FIG. 14B shows a state where the materials for the source electrode 17 and the drain electrode 18 are applied and baked, and FIG. 14C shows a state where the guide 200 is removed by an organic solvent or ashing. In this state, the n + layer 69 still exists on the semiconductor layer 16, and in this state, current easily flows when a voltage is applied to the source electrode 17 and the drain electrode 18 by the carriers of the n + layer 69.

  Therefore, it is necessary to remove the n + layer 69. For the removal of the n + layer 69, dry etching using a gas such as SF 6 + HCl can be employed. Further, instead of removing the n + layer 69, the n + layer 69 may be made nonconductive by ashing or laser oxidation.

  FIG. 14D shows a state in which the n + layer 69 is removed. Thus, the processing of the channel portion 72 is completed.

  At this time, if the electrode material remains on the guide 200 of the channel portion 72, the removal or non-conducting of the n + layer 69 becomes insufficient.

  For example, FIG. 13 shows the case where the electrode material remains in a part of the channel portion 72 on the source electrode 17 side, and FIG. 14E shows the E-E ′ cross section. As shown in FIG. 14E, when the residue (Q) of the electrode material remains on the guide 200, as shown in FIG. 14F, in the step of removing the guide 200, the residue (Q) becomes a mask. Therefore, a part of the guide 200 may remain. This occurs in the same manner in both processing using an organic solvent and peeling by ashing.

  As shown in FIG. 14 (f), when a part of the guide 200 remains in the channel portion 72, as shown in FIG. 14 (g), in the removal of the n + layer 69 in the next step, the residue ( Q) It is impossible to completely remove the n + layer 69 in a certain portion. Similarly, in the process of making the n + layer 69 non-conductive by ashing or laser oxidation, it becomes impossible to make the n + layer 69 where the residue (Q) is present non-conductive.

  As described above, the n + layer 69 remains in the channel portion 72 due to the residue (Q). Therefore, when the residue (Q) straddles the source / drain electrodes 17 and 18 as shown in FIG. A leak current flows between the source / drain electrodes 17 and 18 due to the residue (Q). Naturally, since the n + layer 69 remains in this portion, even if the residue (Q) is removed after the processing of the n + layer 69, the current flows through the n + layer 69 between the source and drain electrodes 17 and 18. Flows. For this reason, a leak occurs between the source / drain electrodes 17 and 18.

  As described above, it is important that no residue (Q) is generated when the source / drain electrodes 17 and 18 are formed.

  Therefore, when the source electrode 17 and the drain electrode 18 are formed in the TFT portion 22, the position where the channel portion 72 (semiconductor layer 16) is removed from the region where the source electrode 17 and the drain electrode 18 are formed is the liquid of the wiring material. It is set as a drop dropping position. Specifically, when the source electrode 17 and the drain electrode 18 have the branch electrode portion 17a and the branch electrode portion 18b as described above, as shown in FIG. 1, the branch start end portion 17b of each of the branch electrode portions 17a and 18a. , 18b is a dropping position 81.

  The dropping position 81 is determined in consideration of the droplet dropping accuracy in the pattern forming apparatus, and the branch start end portions 17b and 18b are arranged at the dropping position 81 determined as described above.

  In the pattern forming apparatus, the droplet dropping accuracy, that is, the deviation amount of the actually dropped position from the target dropping position is determined by the processing error of the ink jet head 33, the adhesion state of the droplet at the head nozzle, the droplet amount. It depends on variations, repeat drive position accuracy in the X direction drive unit 34 and the Y direction drive unit 35, thermal expansion of the inkjet head 33, the moving speed of the inkjet head 33 during ejection, and the like. The dropping accuracy in the pattern forming apparatus is, for example, ± 3 to ± 5 μm when one nozzle discharges in a stationary state, while it is, for example, ± 10 to ± 15 μm in the case of a multi-nozzle.

In this reference embodiment, the head life and tact time are taken into consideration, and a plurality of wirings are formed with one droplet, or an electrode having a droplet diameter larger than the electrode width and a line width of 10 μm is formed. In consideration of this, the amount of one droplet was set to 4 pl. With this drop volume, the drop diameter when dropped (when landed) was about 20 μm. Therefore, it is preferable that the ratio between the electrode width of the branch electrode portions 17a and 18a and the droplet diameter when dropped is approximately 1: 2.

  In consideration of such conditions, the dropping position 81 is set to 30 μm from the end of the semiconductor layer 16 (a-Si layer 68) as shown in FIG. In the figure, reference numeral 82 denotes a dropping center at the dropping position 81, and 83 denotes a dropping center error range 83 of ± 15 μm from the dropping center 82. Reference numeral 84 denotes a dropping position (droplet diameter: 20 μm) when a droplet is dropped at a position deviated by 15 μm from the dropping position 81 (dropping center 82) toward the channel portion 72.

  As described above, droplets are dropped at the dropping position 81 away from the channel portion 72 to form the source electrode 17 and the drain electrode 18, so that droplets of the wiring material adhere to the TFT, that is, the channel portion 72. No leakage occurs between the source and drain electrodes. Therefore, stable TFT characteristics can be obtained when the source electrode 17 and the drain electrode 18 are formed by dropping the droplets of the wiring material.

[ Reference form 2]
Another embodiment of the present invention will be described below with reference to the drawings.
In the present reference, TFT 22 of the TFT array substrate 11 (FIG. 2 (a)) has a structure shown in FIG. In the TFT portion 22, a source electrode 91 and a drain electrode 92 are provided in place of the source electrode 17 and the drain electrode 18. In addition, the semiconductor layer 93 in place of the semiconductor layer 16 has a substantially circular shape that is a droplet dropping shape.

  Similarly to the source electrode 17 and the drain electrode 18, the source electrode 91 and the drain electrode 92 have branch electrode portions 91a and 92a, respectively. The branch electrode portions 91a and 92a are bifurcated from the branch start end portions 91b and 92b, respectively. It is branched to. The number of branches can be set as appropriate.

  As already described, in the configuration shown in FIG. 1, the branch electrode portions 17a and 18a of the source electrode 17 and the drain electrode 18 first protrude from the gate electrode 13 from the TFT gate electrode 66 from the branch start end portions 17b and 18b. It extends in a direction parallel to the direction (two directions opposite to each other), and then extends on the TFT portion gate electrode 66 in a direction perpendicular to the direction in which the TFT portion gate electrode 66 protrudes.

  On the other hand, in the configuration shown in FIG. 8, the branch electrode portions 91 a and 92 a of the source electrode 91 and the drain electrode 92 are first formed between the branch electrode portions 91 a from the branch start end portions 91 b and 92 b toward the TFT portion gate electrode 66. It extends in an oblique direction (two directions) so that the interval or the interval between the branch electrode portions 92a is widened, and then extends in a direction perpendicular to the direction in which the TFT portion gate electrode 66 protrudes on the TFT portion gate electrode 66. ing.

  That is, in the branch electrode portions 91a and 92a, portions on the semiconductor layer 93 are arranged in parallel, and portions between these parallel portions and the branch start end portions 91b and 92b are formed in a straight line.

Further, in the present reference, the semiconductor layer 93, as described above, has a generally circular which is dropping the droplet shape. A method for manufacturing the TFT array substrate 11 in this case will be described below.

In this manufacturing method, from the gate pretreatment step 41 to the gate insulating layer formation / semiconductor layer formation step 43 (FIG. 9A) and the source / drain line pretreatment step 45 after the semiconductor layer formation step 44 to the pixel. The electrode forming step 50 is the same as in the case of the reference embodiment 1, and the semiconductor layer forming step 44 is performed as follows.

  This semiconductor layer forming step 44 is shown in FIGS. 9B to 9E. 9E is a plan view showing the glass substrate 12 that has undergone the semiconductor layer forming step 44, FIG. 9D is a cross-sectional view taken along the line DD in FIG. 9E, and FIGS. (C) is a longitudinal cross-sectional view in the position shown in FIG.9 (d) which shows each process.

  In this step, as shown in FIG. 9B, a thermosetting resin as a resist material is formed on the n + layer 65 on the TFT portion gate electrode (branch electrode) 66 branched from the gate electrode 13 by a pattern forming apparatus. The resist layer 94 formed thereby was used as a processing pattern. The discharge amount of the resist material was, for example, one droplet of 10 pl, and a circular pattern with a diameter of approximately 30 μm was obtained at a predetermined position on the TFT portion gate electrode 66. This was baked at 150 ° C. As the thermosetting resin of the resist layer 94, a resist TEF series manufactured by Tokyo Ohka Kogyo Co., Ltd. was used by adjusting the viscosity for inkjet.

  As a material for the resist layer 94, UV resin or photoresist can be used in addition to the above-mentioned thermosetting resin. The resist layer 94 does not need to be transparent, but if it is transparent, the formation position can be easily confirmed. Further, it is desirable that the resist layer 94 has a resistance to dry etching heat, a resistance to dry etching gas, and an etching selectivity with a material to be etched.

  Next, using gas (for example, SF6 + HCl), as shown in FIG. 9C, the n + film formation layer 65 and the a-Si film formation layer 64 are dry-etched to form the n + layer 69 and the a-Si layer. 68 was formed. Thereafter, the glass substrate 12 was washed with an organic solvent, and the resist layer 94 was peeled and removed as shown in FIG.

  As described above, in the semiconductor layer forming step 44, the shape of the semiconductor layer 93 composed of the n + layer 69 and the a-Si layer 68 is used without changing the resin pattern (the pattern of the resist layer 94) discharged by the pattern forming apparatus. It is reflected in. Therefore, the semiconductor layer 93 is formed in a pattern having a circular shape or a curve close to a circular shape as it is when a droplet of the material of the resist layer 94 is dropped on the glass substrate 12 from the inkjet head 33.

  When the semiconductor layer 93 has a shape that protrudes outside the region of the TFT portion gate electrode 66 as described above, the tip end portions of the branch electrode portions 91a and 92a do not protrude outside the region of the TFT portion gate electrode 66 (TFT In the region of the partial gate electrode 66).

  8 differs from the TFT portion gate electrode 66 and the semiconductor layer 16 in FIG. 7 in that the semiconductor layer 93 extends outward from the end portion of the TFT portion gate electrode 66. For this reason, it is desirable that the tips of the branch electrode portions 91 a and 92 a in FIG. 8 are inside the end face line of the TFT portion gate electrode 66, that is, on the TFT portion gate electrode 66. This is because when the source / drain electrodes 17 and 18 extend outside the TFT portion gate electrode 66, the leakage current increases and the TFT characteristics deteriorate.

  Here, the generation mechanism of the leakage current shown in the source / drain line coating formation step 46 will be described in detail with reference to FIGS. 16 (a), 16 (b) and FIGS. 17 (a), 17 (b).

  FIG. 16A is a plan view of the TFT portion when the source electrode 17 is on the TFT portion gate electrode 66 inside the end line of the TFT portion gate electrode 66, and FIG. FIG. On the other hand, FIG. 17A is a plan view of the TFT portion when the source electrode 17 is outside the line at the end of the TFT portion gate electrode 66, that is, when the source electrode 17 extends outside the TFT portion gate electrode 66. FIG. 17B is a cross-sectional view taken along line HH.

  16A and 17A show a case where a negative potential is applied to the TFT portion gate electrode 66. FIG. As shown in FIGS. 16B and 17B, the TFT portion gate electrode 66 faces the a-Si layer 68 with the gate insulating layer 15 interposed therebetween. Here, the n + layer 69 is a layer for injecting carriers into the a-Si layer 68, and is a layer in an overelectron state doped with phosphorus (P) or the like.

  In the TFTs of FIGS. 16A, 16B, and 17A, 17B, the leakage current between the source and drain electrodes 17, 18 when a voltage of, for example, −4 V is applied to the TFT portion gate electrode 66. It was measured. As a result, the leakage current was about 1 pA when the source / drain electrodes 17 and 18 were on the TFT portion gate electrode 66. On the other hand, in a state where the source / drain electrodes 17 and 18 extend outside the TFT portion gate electrode 66, the leakage current increased to 20 to 30 pA.

  As a result, it was found that the TFT characteristics deteriorated when the source / drain electrodes 17 and 18 extended outward. In addition, the reason why this result occurs can be explained as follows.

  First, a case where a negative potential is applied to the TFT portion gate electrode 66 will be described. When the TFT portion gate electrode 66 has a negative potential, electrons as carriers are present away from the TFT portion gate electrode 66 due to repulsion between negative charges as shown in FIG. Therefore, electrons exist in the periphery of the semiconductor region, and hardly exist in the a-Si layer 68 on the TFT portion gate electrode 66. For this reason, the TFT is in an OFF state.

  Even if electrons try to flow between the gate / drain electrodes 17, 18, they must flow over the portion (P) that is negatively pulled on the TFT portion gate electrode 66. Since it is a negative potential, electrons cannot flow beyond the TFT portion gate electrode 66 due to repulsion of charges. For this reason, it is considered that the leakage current is small.

  On the other hand, in the case of FIG. 17A, since the source / drain electrodes 17 and 18 are outside from the outer edge of the TFT portion gate electrode 66 even if the TFT portion gate electrode 66 is at a negative potential, The gate electrode 66 can move along the outer peripheral portion of the a-Si layer 68 without exceeding the negatively pulled portion (P). For this reason, it is considered that the leakage current easily flows.

  As can be understood from the above description, in the TFT portion, the source / drain electrodes 17 and 18 are preferably located on the inner side of the outer edge of the TFT portion gate electrode 66 (on the TFT portion gate electrode 66).

  Next, a case where a positive potential is applied to the TFT portion gate electrode 66 will be described. When the TFT portion gate electrode 66 has a positive potential, electrons in the n + layer 69 are attracted to the potential of the TFT portion gate electrode 66, and carriers exist in the channel portion. Therefore, a current easily flows between the source / drain electrodes 17 and 18, and the TFT is turned on. For example, when 10 V is applied to the TFT portion gate electrode 66, a current of about 1 μA flows between the source / drain electrodes 17 and 18. The applied voltage between the source / drain electrodes 17 and 18 at this time was 10V. When the TFT is ON, electrons try to flow between the source / drain electrodes 17 and 18 at the shortest distance, so that the source / drain electrodes 17 and 18 are out of the outer edge of the TFT portion gate electrode 66. There is no effect.

  In addition, although the formation of the resist layer 94 is performed by dropping one droplet from the inkjet head 33, it may be performed by dropping a plurality of droplets. However, in the case where the resist layer 94 is formed by making droplets infinitely fine and finely discharging such fine liquids, it takes a long time to form one semiconductor layer 93. As the number of dots (number of ejections) increases, the life of the inkjet head 33 is shortened.

  An important point in each process using the inkjet head 33 is that when a layer (film) is formed in a desired area by dropping droplets, an appropriate amount of liquid is used and the number of shots (discharge number) is as small as possible. To drop a drop. By doing so, it is possible to realize the maximum number of processes within the usage limit of the ink jet head 33, and thus it is possible to minimize the apparatus cost.

  Further, the semiconductor layer forming step 44 is also characterized in that it is not necessary to perform a special process on the surface that receives the liquid droplets ejected by the ink jet head 33. That is, in a state in which the surface on which the droplet is dropped is extremely wet, unless the surface is patterned, the discharged droplet spreads indefinitely and the film forming process is not established. However, the a-Si film formation layer 64 (the surface thereof) has many Si terminations, so that the surface of the a-Si film formation layer 64 is basically water-repellent, and the droplets are a-Si film formation layers. 64 has a large contact angle to some extent, and is close to a circle. Therefore, it is not necessary to treat the substrate side (a-Si film formation layer 64) specially.

  In addition, the substrate surface that has been subjected to baking, treatment in gas (dry etching), or the like is likely to have a short molecule attached thereto, which is a case where a semiconductor other than a-Si, for example, an organic semiconductor is used. However, the ejected liquid droplets often exist with a certain large contact angle.

  Conventionally, in order to pattern a semiconductor layer, a mask or a photolithography process has been required. On the other hand, in the semiconductor layer forming step 44, a droplet is dropped from the inkjet head 33 and a pattern (resist layer 94) serving as a mask is directly drawn. Is no longer necessary. Therefore, a significant cost reduction can be realized.

  In addition, as a method of forming the semiconductor layer 93 having a droplet dropping shape, the semiconductor layer 93 may be formed in addition to the method of forming the semiconductor layer 93 using the resist layer 94 as a mask by dropping the droplet as described above. A method of directly dropping the material to be 93 by a pattern forming apparatus is also possible. As the semiconductor material in this case, an organic semiconductor material typified by polyvinyl carbazole (PVK) or polyphenylene vinylene (PPV) can be used.

  As described above, the branch electrode portions 91a and 92a are formed so that the portions on the branch start end portions 91b and 92b side are inclined with respect to the direction in which the TFT portion gate electrode 66 protrudes. This is mainly due to the following reason.

  The semiconductor layer 93 formed in a droplet dropping shape may be larger than the semiconductor layer 16. In such a case, the positions of the branch start end portions 91b and 92b, which are the dropping positions 81, are arranged on the TFT portion gate electrode 66 more than in the case of the configuration of FIG. 1 in order to avoid the deposition of the electrode material on the channel portion 72. It needs to be further away from the location. On the other hand, the electrode material dripped at the position corresponding to the branch start end portions 91b and 92b (dropping position 81) needs to be surely distributed to the end portions of the branch electrode portions 91a and 92a. Accordingly, if the branch electrode end portions 91b and 92b side portions of the branch electrode portions 91a and 92a are formed obliquely, the branch start end portions 91b and 92b are further away from the position of the TFT portion gate electrode 66, and the branch start end portions 91b and 92b. It is possible to suppress the length of the branch electrode portions 91a and 92a from the tip to the tip.

  Further, even when a droplet dropped from the pattern forming apparatus is dropped at a position (dropping position 84) that is shifted from the desired dropping position 81 toward the channel portion 72, the branch start ends of the branch electrode portions 91a and 92a. Since the portions on the 91b, 92b side are formed obliquely, for example, the interval between the branch electrode portions 91a at the dropping position is narrower than the interval between the branch electrode portions 17a shown in FIG. As a result, compared to the case of the configuration shown in FIG. 1, the dropped liquid droplets can be easily dropped on the branch electrode portions 91a and 92a. Therefore, an allowable range of error with respect to the target dropping position 81 of the electrode material is widened.

[Embodiment 1 ]
An embodiment of the present invention will be described below with reference to FIGS. 10 (a) and 10 (b).
In the present embodiment, the TFT portion 22 of the TFT array substrate 11 has a configuration shown in FIG. In the TFT portion 22, a source electrode 101 and a drain electrode 102 are provided instead of the source electrode 17 and the drain electrode 18, for example, the semiconductor layer 16 is provided. The TFT array substrate 11 can be manufactured by the same method as that described in Reference Embodiment 1.

  The source electrode 101 has a large area on the branch start end portion 101 b side in the branch electrode portion 101 a extending on the semiconductor layer 16. In other words, the branch electrode portion 101a protrudes from the source electrode 101 into a trapezoidal shape, and the lower base of the trapezoidal shape is the branch start end portion 101b.

  For this purpose, the source electrode 101 has an electrode width that gradually increases toward both side portions of the branch electrode portion 101 a connected to the main line of the source electrode 101. In other words, the electrode width gradually decreases from the two bottom corners of the trapezoid shape (both side portions of the branch electrode portion 101a) toward the upper side portion of the trapezoid shape, and the upper side portion of the trapezoid shape extends onto the semiconductor layer 16. Yes. In other words, if the two bottom corners are referred to as a source transition portion that mediates between the main line (source wiring) of the source electrode 101 and the source electrode 101 in the TFT portion 22, each source The electrode width at the transition portion (bottom corner portion) gradually increases from the source wiring toward the formation region of the semiconductor layer 16.

  Therefore, in such a source electrode 101, both side portions (the two source transition portions) of the branch start end portion 101b in the branch electrode portion 101a allow droplets of electrode material to flow outside the region of the channel portion 72 (semiconductor layer 16). This is the dropping position 81 for dripping.

  On the other hand, the electrode width of the drain electrode 102 gradually increases from the position near the channel portion 72 toward the channel portion 72. In other words, if the vicinity position is referred to as a drain transition portion that mediates between the drain electrode 102 in the TFT portion 22 and the wiring (drain wiring) of the drain electrode 102, the electrode width in the drain transition portion is the drain width. It gradually spreads from the wiring toward the formation region of the semiconductor layer 16. The electrode width expansion start end portion 102 a (that is, the drain transition portion) that is the vicinity position is the dropping position 81.

  Here, the electrode material dropped in the electrode formation region formed by the convex guide or the hydrophilic / hydrophobic treatment in the above-described source / drain line pretreatment step 45 is affected by the contact angle θ shown in FIG. Thus, the electrode is pulled in the wide direction in the electrode formation region and flows in that direction (spontaneously). Therefore, even when the dropping position 81 is set outside the region of the channel portion 72 (semiconductor layer 16), the dropped electrode material can easily reach the tip position on the channel portion 72 side of the source electrode 101 and the drain electrode 102. The source electrode 101 and the drain electrode 102 can be reliably formed in the TFT portion 22 by dropping the wiring material.

  In this way, when wiring such as electrodes is formed by dropping droplets using a pattern forming device, the flow direction of the dropped droplets is controlled by changing the wiring width (width of the wiring formation region). can do.

In this embodiment, there is shown an example of the TFT composed of one channel section 72, in the electrode portion of the TFT shown in Reference Embodiment 1, 2 and will be described later in Reference Embodiment 3, Needless to say, the wiring width may be appropriately changed.

[ Reference form 3]
Still another embodiment of the present invention will be described below with reference to FIG.

In the present reference, TFT 22 of the TFT array substrate 11 has a structure shown in FIG. 11. In the TFT portion 22, a source electrode 111 and a drain electrode 112 are provided instead of the source electrode 17 and the drain electrode 18, for example, the semiconductor layer 93 is provided. The semiconductor layer 93 has a substantially circular shape, and is locally formed on the straight gate wiring (the main line of the gate electrode 13) via the gate insulating layer 15 (FIG. 9). This TFT array substrate 11 can be manufactured by the same method as the method shown in Reference Embodiment 2.

  In the configuration shown in FIG. 1 and FIG. 8, a wide channel portion 72 is formed by forming a plurality of electrodes in the TFT portion 22, that is, by forming the branch electrode portions 17a and 18a and the branch electrode portions 91a and 92a. This is effective when the charge transfer is large, such as when driving a large pixel. Further, the pattern of the TFT part gate electrode 66 and the pattern of the source electrodes 17 and 91 (branch electrode parts 17a and 91a) and the drain electrodes 18 and 92 (branch electrode parts 18b and 92b) are in the extending direction of the TFT part gate electrode 66. Even if it is deviated, in particular, the configuration of FIG. 1 has a feature that it is easy to obtain stable characteristics even if it deviates in a direction perpendicular to the direction in which the TFT portion gate electrode 66 extends.

In the configuration of this reference forms shown in Figure 11, the channel portion 72 side of the branch electrode portion 111a and the drain electrode 112 extending over the semiconductor layer 93 is branched from the main line of the source electrode 111 portion and is TFT section gate electrode 66 It is arranged in the extending direction and is provided in the region of the TFT portion gate electrode 66.

  In other words, the branch electrode portion 111a extends from the source wiring intersecting the gate wiring onto the semiconductor layer 93 along the gate wiring, and from the drain wiring crossing the extending direction of the gate wiring along the gate wiring. Thus, the drain electrode 112 extends onto the semiconductor layer 93. A portion where the branch electrode portion 111a starts to extend from the source wiring is called a source transition portion, and a portion where the drain electrode 112 starts to extend from the drain wiring is called a drain transition portion.

  With such a configuration, the TFT portion 22 is relatively small, which is advantageous for realizing a high aperture ratio.

  In the above configuration, the dropping position 81 outside the region of the channel portion 72 (semiconductor layer 93) is set to a position corresponding to the branch start end portion 111b (that is, the source transition portion) of the branch electrode portion 111a on the source electrode 111 side. ing. On the drain electrode 112 side, the drain electrode 112 is set at a position corresponding to a portion bent toward the channel portion 72 side (that is, a drain transition portion). As a result, it is possible to prevent the electrode material droplets dropped from the pattern forming apparatus from adhering to the channel portion 72.

The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope shown in the claims, and the present invention can be obtained by appropriately combining technical means disclosed in different embodiments and reference embodiments. Such embodiments are also included in the technical scope of the present invention.

  The thin film transistor includes: (i) a semiconductor layer facing the gate electrode through the gate insulating layer; (ii) a source electrode and a drain electrode electrically connected to the semiconductor layer; and (iii) the source electrode and A thin film transistor including a channel portion between drain electrodes, wherein the source electrode and the drain electrode are formed by dropping droplets of an electrode material, and the source electrode and the drain electrode are at least the semiconductor The portion in the layer region is a branch electrode portion branched into a plurality of branches, the branch electrode portions of both electrodes are alternately arranged, and the branch start end portion of the branch electrode portion is located outside the region of the semiconductor layer. May be provided.

  According to the above configuration, since the branch start end portion of the branch electrode portion between the source electrode and the drain electrode is provided at a position outside the region of the semiconductor layer (region where the semiconductor layer is disposed), the branch electrode portion is provided. When the source electrode and the drain electrode are formed, the branch start end portion outside the region of the semiconductor layer can be set as a dropping position for dropping a droplet of the electrode material.

  Thereby, when the source electrode and the drain electrode are formed, it is possible to prevent the droplets from adhering to the channel portion between the two electrodes. Therefore, it is possible to avoid a situation in which a residue of the n + layer is generated by using the above-mentioned splash as a mask, a leak current flows between the source and the drain, and a desired TFT characteristic cannot be obtained.

  Further, since a wide channel portion is formed between the alternately arranged branch electrode portions, it is effective when the charge transfer is large as in the case of driving a large pixel.

  Further, with the branch start end portion as the droplet dropping position of the electrode material, the branch start end is positioned at a position where no droplet is dropped onto the channel portion based on an error in the drop position when forming the branch electrode portion. A part may be provided.

  Further, the plurality of branch electrode portions may be parallel portions arranged in parallel with each other in the region of the semiconductor layer, and a portion between the parallel portion and the branch start end portion may be formed linearly. .

  Further, at least one of the source electrode and the drain electrode may be provided with a portion where the electrode width is gradually increased toward the end portion on the semiconductor side.

  The portion where the electrode width is gradually enlarged may be provided between the branch start end and the end on the semiconductor side.

  The channel portion may be formed such that the width of the channel portion is within the range of the length of the branch electrode portion.

  Further, the branch electrode portion of the source electrode or the branch electrode portion of the drain electrode may be formed so that the interval between the adjacent branch electrode portions increases from the branch start end portion toward the channel portion.

  The semiconductor layer may be formed in a substantially circular pattern having a diameter larger than the width of the gate electrode in the channel portion.

  The semiconductor layer may be formed in a substantially circular pattern having a diameter larger than the width of the gate electrode in the channel portion, and each end of the branch electrode portion may be located within the width of the gate electrode.

  In the thin film transistor, a substantially circular semiconductor layer is locally formed on a straight gate wiring via a gate insulating layer, and a source electrode and a drain electrode are formed on the semiconductor layer. A channel part is formed between the electrodes, the source electrode is continuous with the source wiring through the source transition part, and the drain electrode is continuous with the drain wiring through the drain transition part. The part may be provided at a position outside the region of the semiconductor layer.

  In the above-described thin film transistor, the branch start end portion is based on a droplet drop position error when the branch start end portion is set as a droplet drop position of the electrode material when forming the branch electrode portion. It is good also as a structure provided in the position where a droplet is not dripped at the said channel part.

  According to said structure, when forming a source electrode and a drain electrode by dripping the droplet of an electrode material, the situation where the droplet of the said droplet adheres to the channel part between both electrodes can be prevented further reliably. .

  In the above thin film transistor, the plurality of branch electrode portions are configured such that portions on the semiconductor layer are arranged in parallel to each other, and a portion between the parallel portion and the branch start end portion is formed in a straight line. Also good.

  According to said structure, in order to avoid the situation where the droplet of the electrode material droplets adhere to the channel portion, the branch start end portion is reliably moved away from the channel portion, and the branch electrode from the branch start end portion to the tip end portion The situation where the length of a part becomes long can be suppressed.

  The thin film transistor may have a configuration in which at least one of the source electrode and the drain electrode is provided with a portion where the electrode width is gradually increased toward the end portion on the semiconductor side.

  According to the above configuration, the dropped droplets easily flow in the direction in which the electrode width is increased, so that the dropping position can be separated from the channel portion, and to the region that reliably extends from the dropping position to the semiconductor portion. Electrode material can be flowed.

  The specific embodiments or examples made in the section of the detailed description of the invention are merely to clarify the technical contents of the present invention, and the present invention is limited only to such specific examples. The present invention should not be interpreted in a narrow sense, and various modifications can be made within the spirit of the present invention and the scope of the claims described below.

  A thin film transistor including an electrode structure in which splashes do not adhere to a channel portion of the thin film transistor, and a liquid crystal display device can be provided.

Figure 1 is a plan view showing the structure of a TFT section of a TFT array substrate according to an embodiment of the reference of the present invention. 2 (a) is a plan view showing a schematic configuration of one pixel of the TFT array substrate according to an embodiment the liquid crystal display device of the reference of the present invention. FIG. 2B is a cross-sectional view taken along line AA in FIG. Figure 3 is a perspective view schematically showing a pattern forming apparatus of an ink jet method used in the preparation of the liquid crystal display device according to an embodiment of the reference of the present invention. FIG. 4 is a flowchart showing a manufacturing process of the TFT array substrate shown in FIGS. 2 (a) and 2 (b). FIG. 5A is a plan view of the TFT array substrate for explaining the gate pretreatment process shown in FIG. FIG. 5B is a plan view of the TFT array substrate for explaining the gate line coating formation process. FIG.5 (c) is a BB arrow directional cross-sectional view in FIG.5 (b). 6A is a cross-sectional view of a portion corresponding to the cross section taken along line BB in FIG. 5B, and shows the gate insulating layer film formation / semiconductor layer film formation process shown in FIG. And it is CC sectional view taken on the line in FIG.6 (e). 6B is a cross-sectional view of a portion corresponding to the cross section taken along the line BB in FIG. 5B, and after the gate insulating layer and the semiconductor layer are formed in the semiconductor layer forming step shown in FIG. FIG. 7 shows a state where the photolithography process is finished, and is a cross-sectional view taken along the line CC in FIG. 6 (e). FIG. 6C is a cross-sectional view of a portion corresponding to the cross section taken along the line BB in FIG. 5B, and shows the etching process of the a-Si film-forming layer and the n + film-forming layer in the same step. FIG. 7 is a cross-sectional view taken along the line CC in FIG. FIG. 6D shows a resist removal process in the same step, and is a cross-sectional view taken along the line CC in FIG. FIG. 6E is a plan view of the TFT array substrate that has undergone the semiconductor layer forming step. FIG. 7 is a plan view showing the size of each part of the TFT part shown in FIG. 1 and the range of error from a desired dropping position. Figure 8 is a plan view showing the structure of a TFT section of a TFT array substrate according to another embodiment of the reference of the present invention. 9A is a cross-sectional view of a portion corresponding to the cross section taken along line BB in FIG. 5B, and FIG. 4 shows a case where a TFT array substrate having the TFT portion shown in FIG. FIG. 10 is a sectional view taken along line DD in FIG. 9E, showing the gate insulating layer film forming / semiconductor layer forming process shown. FIG. 9B is a cross-sectional view of a portion corresponding to the cross section taken along line BB in FIG. 5B, and after the gate insulating layer and the semiconductor layer are formed in the semiconductor layer forming step shown in FIG. FIG. 10 shows a state after the photolithography process, and is a cross-sectional view taken along line DD in FIG. 9E. FIG. 9C is a cross-sectional view of a portion corresponding to the cross section taken along the line BB in FIG. 5B, and shows the etching process of the a-Si film-forming layer and the n + film-forming layer in the same step. FIG. 10 is a cross-sectional view taken along line DD in FIG. FIG. 9D shows a resist removal process in the same process, and is a cross-sectional view taken along line DD in FIG. 9E. FIG. 9E is a plan view of the TFT array substrate that has undergone the semiconductor layer forming step. FIG. 10A is a plan view showing the configuration of the TFT portion of the TFT array substrate in the embodiment of the present invention. FIG. 10B is a cross-sectional view of a portion corresponding to the cross section taken along the line EE in FIG. 10A before the source electrode and the drain electrode are formed. Figure 11 is a plan view showing the structure of a TFT section of a TFT array substrate according to another embodiment of the reference of the present invention. FIG. 12A is an explanatory diagram showing a process of forming a hydrophilic pattern in the water repellent region by a hydrophilic treatment of the substrate using a photocatalyst. FIG. 12B is an explanatory diagram showing a process of forming a hydrophilic pattern in the water-repellent region by hydrophilic treatment of the substrate using a photocatalyst. FIG. 12C is an explanatory diagram showing a process of forming a hydrophilic pattern in the water-repellent region by hydrophilic treatment of the substrate using a photocatalyst. FIG. 12D is an explanatory diagram showing a process of forming a hydrophilic pattern in the water-repellent region by hydrophilic treatment of the substrate using a photocatalyst. FIG. 13 is a plan view showing a state in which droplets of the electrode material remain in a part of the channel portion on the source electrode side. FIG. 14A is a schematic cross-sectional view showing a processing step of the channel portion in the TFT portion. FIG. 14B is a schematic cross-sectional view showing the processing step of the channel portion in the TFT portion. FIG. 14C is a schematic cross-sectional view showing the processing step of the channel portion in the TFT portion. FIG. 14D is a schematic cross-sectional view showing a processing step of the channel portion in the TFT portion. FIG. 14E is a schematic cross-sectional view showing a processing step of the channel portion in the case where splashes of the electrode material remain in the channel portion, by a cross-section taken along the line E-E ′ of FIG. 13. FIG. 14F is a schematic cross-sectional view showing a processing step of the channel portion in the case where droplets of the electrode material remain in the channel portion, by a cross-section taken along the line E-E ′ in FIG. 13. FIG. 14G is a schematic cross-sectional view showing a processing step of the channel portion in the case where splashes of the electrode material remain in the channel portion, by a cross-sectional view taken along line E-E ′ of FIG. 13. FIG. 15 is a plan view showing a state in which splashes of the electrode material remain so as to cover the channel portion between the source electrode and the drain electrode. FIG. 16A is a plan view showing a configuration in which a leak current hardly occurs between the source and drain electrodes when the shape of the semiconductor layer protrudes outside the region of the TFT portion gate electrode. FIG. 16B is a cross-sectional view taken along line G-G ′ of FIG. FIG. 17A is a plan view showing a configuration in which a leak current is likely to be generated between the source and drain electrodes when the shape of the semiconductor layer protrudes outside the region of the TFT portion gate electrode. FIG. 17B is a cross-sectional view taken along the line H-H ′ of FIG. FIG. 18 is a flowchart showing a manufacturing process of a TFT array substrate having a top gate structure.

Claims (3)

(i) a semiconductor layer facing the gate electrode through the gate insulating layer, (ii) a source electrode and a drain electrode electrically connected to the semiconductor layer, and (iii) between the source electrode and the drain electrode, A thin film transistor including a channel portion formed in the semiconductor layer,
The source electrode is continuous with the source wiring through the source transition portion, and the drain electrode is continuous with the drain wiring through the drain transition portion,
The source electrode, the source transition portion and the source wiring, and the drain electrode, the drain transition portion and the drain wiring are respectively formed in a source formation region and a drain formation region formed by providing a convex guide along the contour. After dropping the electrode material droplets and firing, it is formed by removing the guide,
The source transition portion and the drain transition portion are provided at positions outside the region of the semiconductor layer, and are dropping positions for dropping droplets of the electrode material,
The electrode width in the source transition portion gradually increases from the source wiring toward the semiconductor layer region, and / or the electrode width in the drain transition portion gradually increases from the drain wiring toward the semiconductor layer region. Spreading thin film transistor. (i) a semiconductor layer facing the gate electrode through the gate insulating layer, (ii) a source electrode and a drain electrode electrically connected to the semiconductor layer, and (iii) between the source electrode and the drain electrode, A thin film transistor including a channel portion formed in the semiconductor layer,
The source electrode is continuous with the source wiring through the source transition portion, and the drain electrode is continuous with the drain wiring through the drain transition portion,
The source electrode , the source transition portion, and the source wiring, and the drain electrode, the drain transition portion, and the drain wiring are formed of a droplet of an electrode material in each of the source formation region and the drain formation region that are formed by the hydrophilic / hydrophobic treatment. Formed by dripping and firing,
The source transition portion and the drain transition portion are provided at positions outside the region of the semiconductor layer, and are dropping positions for dropping droplets of the electrode material,
The electrode width in the source transition portion gradually increases from the source wiring toward the semiconductor layer region, and / or the electrode width in the drain transition portion gradually increases from the drain wiring toward the semiconductor layer region. Spreading thin film transistor.   A liquid crystal display device comprising the thin film transistor according to claim 1.

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