JP4786223B2 - Epitaxial silicon carbide single crystal substrate and manufacturing method thereof - Google Patents
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 48
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 47
- 239000000758 substrate Substances 0.000 title claims description 47
- 239000013078 crystal Substances 0.000 title claims description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000007547 defect Effects 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 13
- 230000003746 surface roughness Effects 0.000 claims description 10
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000003763 carbonization Methods 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 39
- 238000005498 polishing Methods 0.000 description 14
- 229910003460 diamond Inorganic materials 0.000 description 9
- 239000010432 diamond Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 6
- 239000002245 particle Substances 0.000 description 6
- 239000006061 abrasive grain Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000879 optical micrograph Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000000089 atomic force micrograph Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000002484 cyclic voltammetry Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Description
本発明は、エピタキシャル炭化珪素（ＳｉＣ）単結晶基板及びその製造方法に関するものである。 The present invention relates to an epitaxial silicon carbide (SiC) single crystal substrate and a method for manufacturing the same.
炭化珪素（ＳｉＣ）は、耐熱性及び機械的強度に優れ、物理的、化学的に安定なことから、耐環境性半導体材料として注目されている。また、近年、高周波高耐圧電子デバイス等の基板としてＳｉＣ単結晶基板の需要が高まっている。 Silicon carbide (SiC) has attracted attention as an environmentally resistant semiconductor material because it is excellent in heat resistance and mechanical strength and is physically and chemically stable. In recent years, the demand for SiC single crystal substrates as substrates for high-frequency, high-voltage electronic devices has increased.
ＳｉＣ単結晶基板を用いて、電力デバイス、高周波デバイス等を作製する場合には、通常、基板上に熱ＣＶＤ法（熱化学蒸着法）と呼ばれる方法を用いてＳｉＣ薄膜をエピタキシャル成長させたり、イオン注入法により直接ドーパントを打ち込んだりするのが一般的であるが、後者の場合には、注入後に高温でのアニールが必要となるため、エピタキシャル成長による薄膜形成が多用されている。 When manufacturing a power device, a high-frequency device, etc. using a SiC single crystal substrate, a SiC thin film is epitaxially grown on the substrate by a method called thermal CVD (thermochemical vapor deposition) or ion implantation is usually performed. In general, a dopant is directly implanted by a method, but in the latter case, annealing at a high temperature is required after implantation, and therefore thin film formation by epitaxial growth is frequently used.
ＳｉＣには、ｃ軸方向に反転位置関係にある（０００１）面（Ｓｉ面）と（０００−１）面（Ｃ面）が存在し、結晶学的には極性面と呼ばれる。エピタキシャル成長を行う場合、通常はＳｉ面が用いられているが、これはｓｉｔｅ−ｃｏｍｐｅｔｉｔｉｏｎ技術と言われる、原料ガスにおけるＣとＳｉの原子数の比（Ｃ／Ｓｉ比）を上げることによって、エピタキシャル膜中のｎ型残留不純物密度を下げることがＣ面に比べて容易にでき、また、ＭＯＳ界面におけるキャリア移動度もＳｉ面の方が大きいためである。しかし、近年、減圧下で成長することによりＣ面でもｓｉｔｅ−ｃｏｍｐｅｔｉｔｉｏｎ技術が適用でき、ある程度Ｓｉ面に匹敵するレベルにまで膜中のｎ型残留不純物密度を低減できる可能性のあることが明らかになってきており、さらに、アニール方法の改善でＭＯＳ界面の品質も向上することが報告されている（非特許文献１）。 SiC has a (0001) plane (Si plane) and a (000-1) plane (C plane) that are in a reverse positional relationship in the c-axis direction, and is called a polar plane crystallographically. When epitaxial growth is performed, the Si surface is usually used. This is called a site-compression technique, and the epitaxial film is formed by increasing the ratio of the number of C and Si atoms in the source gas (C / Si ratio). This is because the n-type residual impurity density can be easily reduced as compared with the C-plane, and the carrier mobility at the MOS interface is larger on the Si-plane. However, in recent years, it is clear that the site-compression technology can be applied to the C plane by growing under reduced pressure, and the n-type residual impurity density in the film may be reduced to a level comparable to the Si plane to some extent. Furthermore, it has been reported that the quality of the MOS interface is improved by improving the annealing method (Non-Patent Document 1).
さらに、Ｃ面は、酸化速度がＳｉ面に比べ約１桁大きいため、ＭＯＳ構造の作製においては有利であり、加えて、エピタキシャル成長面の平坦性にも優れていることから、上記近年の特性改善と相まってＣ面上のエピタキシャル成長層のデバイス応用への関心が高まっている。 Furthermore, since the oxidation rate of the C plane is about an order of magnitude higher than that of the Si plane, it is advantageous in the fabrication of a MOS structure, and in addition, the flatness of the epitaxial growth plane is excellent, so that the above-mentioned characteristics have been improved recently In conjunction with this, there is a growing interest in device applications of epitaxially grown layers on the C-plane.
Ｋｏｊｉｍａらは、４Ｈ−ＳｉＣのＣ面上で減圧下におけるエピタキシャル成長の条件を変化させた場合の成長膜の表面モホロジーについて報告している（非特許文献２、３）。それによると、欠陥のない平坦な表面を得るためには、成長温度が１６００℃、原料ガス（ＳｉＨ４とＣ３Ｈ８）におけるＣ／Ｓｉ比は１．５以下であることが必要としているが、膜中のｎ型残留不純物密度は、Ｃ／Ｓｉ比が１．５以下の時、２×１０１５ｃｍ−３以上の値を示しており、デバイス応用に必要な１×１０１５ｃｍ−３以下が達成されていない。また、Ｃ／Ｓｉ比が３．０の時には０．７〜１×１０１５ ｃｍ−３となっているが、この場合にはｈｉｌｌｏｃｋ(ヒロック)と呼ばれるエピタキシャル欠陥が多数発生し、平坦な表面が得られていない。即ち、現状技術では、Ｃ面上のエピタキシャル成長において、ｓｉｔｅ−ｃｏｍｐｅｔｉｔｉｏｎ効果を利用してＣ／Ｓｉ比を上げ、低いｎ型残留不純物密度を得ようとすると、表面モホロジーが悪化し、逆に、表面モホロジーを改善するためには、Ｃ／Ｓｉ比を下げなければならないため、膜中のｎ型残留不純物密度が増加するという、相反する状況が発生し、良好な表面モホロジーと低いｎ型残留不純物密度を両立させることが困難である。一方、膜中のｎ型残留不純物密度を下げるための他の方法として、ｓｉｔｅ−ｃｏｍｐｅｔｉｔｉｏｎ効果を利用する以外に、成長温度を下げて、成長炉からの不純物がエピタキシャル膜中に取り込まれないようにすることも有効である。即ち、成長温度を下げることができれば、良好な表面モホロジーが得られるとされるＣ／Ｓｉ比が１．５程度でも、１×１０１５ｃｍ−３以下のｎ型残留不純物密度が得られると考えられ、両立が期待できる。しかし、成長温度の低下は、エピタキシャル成長のために必要なエネルギーを低減することになるため、正常な成長が阻害され高品質のエピタキシャル膜を得ることは困難である。 Kojima et al. Have reported the surface morphology of the growth film when changing the conditions of epitaxial growth under reduced pressure on the C-plane of 4H-SiC (Non-Patent Documents 2 and 3). According to this, in order to obtain a flat surface without defects, it is necessary that the growth temperature is 1600 ° C. and the C / Si ratio in the source gas (SiH 4 and C 3 H 8 ) is 1.5 or less. However, the n-type residual impurity density in the film shows a value of 2 × 10 15 cm −3 or more when the C / Si ratio is 1.5 or less, and is 1 × 10 15 cm − necessary for device application. Less than 3 has not been achieved. In addition, when the C / Si ratio is 3.0, it is 0.7 to 1 × 10 15 cm −3 , but in this case, many epitaxial defects called hillocks occur and a flat surface is formed. Not obtained. That is, in the current state of technology, in the epitaxial growth on the C-plane, when the C / Si ratio is increased by using the site-competition effect to obtain a low n-type residual impurity density, the surface morphology deteriorates. In order to improve the morphology, the C / Si ratio must be lowered, resulting in a conflicting situation in which the n-type residual impurity density in the film increases, resulting in a good surface morphology and a low n-type residual impurity density. It is difficult to achieve both. On the other hand, as another method for reducing the n-type residual impurity density in the film, besides using the site-competition effect, the growth temperature is lowered so that impurities from the growth furnace are not taken into the epitaxial film. It is also effective to do. In other words, if the growth temperature can be lowered, an n-type residual impurity density of 1 × 10 15 cm −3 or less can be obtained even if the C / Si ratio is about 1.5, at which good surface morphology is obtained. Can be expected. However, lowering the growth temperature reduces the energy required for epitaxial growth, so that normal growth is hindered and it is difficult to obtain a high-quality epitaxial film.
したがって、今後デバイスへの応用が期待されるＣ面上へのエピタキシャル成長であるが、現状技術では、欠陥のない平坦な成長面と低いｎ型残留不純物密度を同時に得ることは困難である。これらを両立させるためには、成長温度を下げることが有効であるが、エピタキシャル成長そのものが阻害されるため、デバイス作成に必要な高品質エピタキシャル膜を得ることは難しかった。
本発明は、上記Ｃ面上へのエピタキシャル成長において、欠陥のない平坦な成長面を持ち、かつ、残留不純物が低減された高品質エピタキシャル膜を有するＳｉＣ単結晶基板、及びその製造方法を提供するものである。 The present invention provides a SiC single crystal substrate having a high-quality epitaxial film having a flat growth surface free from defects and having reduced residual impurities in the epitaxial growth on the C-plane, and a method for manufacturing the same. It is.
本発明は、エピタキシャル成長前の基板表面の平坦度と成長条件との関係に注目することにより、上記課題を解決できることを見出し、完成したものである。即ち、本発明は、
（１） 表面粗さ（Ｒａ）が１．０ｎｍ以下である炭化珪素単結晶基板の（０００−１）面上に、三角形状欠陥とピット状欠陥の合計の表面欠陥密度が５０個／ｃｍ２以下の炭化珪素単結晶薄膜を有することを特徴とするエピタキシャル炭化珪素単結晶基板、
（２） 前記炭化珪素単結晶薄膜のｎ型残留不純物濃度が１×１０１５ｃｍ−３以下である（１）記載のエピタキシャル炭化珪素単結晶基板、
（３） 前記炭化珪素単結晶薄膜の表面粗さ（Ｒａ）が０．５ｎｍ以下である（１）記載のエピタキシャル炭化珪素単結晶基板、
（４） 前記炭化珪素単結晶薄膜の膜厚が５０μｍ以下である（１）記載のエピタキシャル炭化珪素単結晶基板、
（５） 表面粗さ（Ｒａ）が１．０ｎｍ以下である炭化珪素単結晶基板の（０００−１）面に炭化珪素単結晶薄膜をエピタキシャル成長することを特徴とするエピタキシャル炭化珪素単結晶基板の製造方法、
（６） 前記エピタキシャル成長が、熱化学蒸着法（ＣＶＤ法）を用いる（５）記載のエピタキシャル炭化珪素単結晶基板の製造方法、
（７） 前記エピタキシャル成長の成長温度が１５００℃以下である（５）又は（６）に記載のエピタキシャル炭化珪素単結晶基板の製造方法、
（８） （１）〜（４）のいずれか一つに記載のエピタキシャル炭化珪素単結晶基板を用いてなるデバイス、
である。
The present invention has been completed by finding that the above-mentioned problems can be solved by paying attention to the relationship between the flatness of the substrate surface before the epitaxial growth and the growth conditions. That is, the present invention
(1) On the (000-1) plane of a silicon carbide single crystal substrate having a surface roughness (Ra) of 1.0 nm or less, the total surface defect density of triangular defects and pit defects is 50 / cm 2. An epitaxial silicon carbide single crystal substrate comprising the following silicon carbide single crystal thin film,
(2) The epitaxial silicon carbide single crystal substrate according to (1), wherein the silicon carbide single crystal thin film has an n-type residual impurity concentration of 1 × 10 15 cm −3 or less,
(3) The epitaxial silicon carbide single crystal substrate according to (1), wherein the silicon carbide single crystal thin film has a surface roughness (Ra) of 0.5 nm or less,
(4) The epitaxial silicon carbide single crystal substrate according to (1), wherein the silicon carbide single crystal thin film has a thickness of 50 μm or less,
(5) Production of an epitaxial silicon carbide single crystal substrate, wherein a silicon carbide single crystal thin film is epitaxially grown on a (000-1) plane of a silicon carbide single crystal substrate having a surface roughness (Ra) of 1.0 nm or less. Method,
(6) The method for producing an epitaxial silicon carbide single crystal substrate according to (5), wherein the epitaxial growth uses a thermal chemical vapor deposition method (CVD method),
(7) The method for producing an epitaxial silicon carbide single crystal substrate according to (5) or (6), wherein a growth temperature of the epitaxial growth is 1500 ° C. or less,
(8) A device using the epitaxial silicon carbide single crystal substrate according to any one of (1) to (4),
It is.
本発明によれば、Ｃ面上へのエピタキシャル成長をしたＳｉＣ単結晶基板であっても、欠陥のない平坦な成長面を持ち、ｎ型残留不純物が低減された高品質エピタキシャル膜を有するＳｉＣ単結晶基板を提供することが可能である。 According to the present invention, even if the SiC single crystal substrate is epitaxially grown on the C plane, the SiC single crystal has a high quality epitaxial film having a flat growth surface without defects and reduced n-type residual impurities. It is possible to provide a substrate.
また、本発明の製造方法は、１５００℃以下の成長温度でＣＶＤを行うものであるが、エピタキシャル成長としては比較的低い温度で成長を行うため、装置に与える熱ダメージが低減され、装置自体の信頼性が向上する。加えて、ＣＶＤ法であるため、装置構成が容易で制御性にも優れ、均一性、再現性の高いエピタキシャル膜が得られる。 Further, although the manufacturing method of the present invention performs CVD at a growth temperature of 1500 ° C. or less, since epitaxial growth is performed at a relatively low temperature, thermal damage given to the device is reduced, and the reliability of the device itself is reduced. Improves. In addition, since the CVD method is used, an epitaxial film with an easy apparatus configuration, excellent controllability, and high uniformity and reproducibility can be obtained.
さらに、本発明のエピタキシャルＳｉＣ単結晶基板を用いたデバイスは、欠陥のない平坦な成長面を持ち、ｎ型残留不純物が低減された高品質エピタキシャル膜上に形成されるため、その特性及び歩留りが向上する。 Furthermore, since the device using the epitaxial SiC single crystal substrate of the present invention is formed on a high-quality epitaxial film having a flat growth surface without defects and reduced n-type residual impurities, its characteristics and yield are improves.
本発明は、Ｃ面上へのエピタキシャル成長に関するものである。従来、Ｃ面上のエピタキシャル膜は、Ｓｉ面上の膜に比べて、膜中のｎ型残留不純物密度を下げることが難しく、また、ＭＯＳ界面におけるキャリア移動度もＳｉ面上の膜に比べて劣っていた。しかし、近年の研究により、Ｃ面でもｓｉｔｅ−ｃｏｍｐｅｔｉｔｉｏｎ技術が適用できて、ある程度Ｓｉ面に匹敵するレベルにまで膜中のｎ型残留不純物密度を低減できる可能性のあることが明らかになってきており、さらに、アニ−ル方法の改善でＭＯＳ界面の品質も向上することが報告されるようになった。また、Ｃ面は、酸化速度がＳｉ面に比べ約１桁大きいため、ＭＯＳ構造の作製においては有利であり、加えて、エピタキシャル成長面の平坦性にも優れていることから、上記近年の特性改善と相まってＣ面上のエピタキシャル成長層のデバイス応用への関心が高まっている。そこで、本発明では、Ｃ面上へのエピタキシャル成長において、成長前の基板表面の平坦度と成長条件との関係に注目し、基板表面の平坦度を上げることで、成長温度を下げても欠陥が少なく、かつ、ｎ型残留不純物密度が低減された高品質エピタキシャル膜（炭化珪素単結晶薄膜）が得られることを示したものである。 The present invention relates to epitaxial growth on a C-plane. Conventionally, it is difficult for the epitaxial film on the C plane to lower the n-type residual impurity density in the film compared to the film on the Si plane, and the carrier mobility at the MOS interface is also lower than that on the Si plane. It was inferior. However, recent research has revealed that the site-completion technique can be applied to the C plane, and the n-type residual impurity density in the film may be reduced to a level comparable to the Si plane to some extent. Furthermore, it has been reported that improvement of the annealing method improves the quality of the MOS interface. In addition, since the oxidation rate of the C plane is about an order of magnitude higher than that of the Si plane, it is advantageous in the fabrication of the MOS structure. In addition, since the flatness of the epitaxial growth plane is also excellent, the above-described recent characteristics improvement In conjunction with this, there is a growing interest in device applications of epitaxially grown layers on the C-plane. Therefore, in the present invention, in epitaxial growth on the C-plane, attention is paid to the relationship between the flatness of the substrate surface before growth and the growth conditions, and defects are not detected even when the growth temperature is lowered by increasing the flatness of the substrate surface. This shows that a high quality epitaxial film (silicon carbide single crystal thin film) with a small n-type residual impurity density is obtained.
本発明の具体的な内容について述べる。まず、ＳｉＣ基板の作成方法については、ＳｉＣ単結晶のインゴットを作製した後、それをスライスしてウェハ状の基板に切り出し、所定の厚さまで粗削りを行い、その後、研磨工程に入り、基板の両面を平坦かつ鏡面に仕上げて基板とする。通常は、この研磨工程において、使用するダイヤモンド砥粒の粒径を徐々に小さくし、最終的には平均粒径が１μｍのダイヤモンド砥粒を使用するが、本発明においては、平均粒径が０．５μｍあるいは０．２５μｍの砥粒を最終研磨に使用し、研磨面のキズ等を減らし、平坦度を上げてからエピタキシャル成長を行うことを試みた。これは、特に成長温度を下げた場合、成長前の基板表面のキズや細かい凹凸がエピタキシャル成長を阻害し、その部分が核となって欠陥が形成され、成長後の表面状態を劣化させると考えたためである。 The specific contents of the present invention will be described. First, about the production method of a SiC substrate, after producing a SiC single crystal ingot, it is sliced and cut into a wafer-like substrate, roughed to a predetermined thickness, and then enters a polishing step. Is finished to a flat mirror surface. Usually, in this polishing step, the grain size of the diamond abrasive grains to be used is gradually reduced, and finally, diamond abrasive grains having an average grain diameter of 1 μm are used. An attempt was made to use epitaxial grains of 0.5 μm or 0.25 μm for final polishing, reduce scratches on the polished surface, etc., and increase the flatness before epitaxial growth. This is because, especially when the growth temperature is lowered, scratches and fine irregularities on the substrate surface before growth inhibits epitaxial growth, and that part forms nuclei and defects are formed, deteriorating the surface state after growth. It is.
実際にエピタキシャル成長に用いた装置は、横形のＣＶＤ装置である。ＣＶＤ法は装置構成が簡単であり、ガスのｏｎ／ｏｆｆで成長を制御できるため、エピタキシャル膜の制御性、再現性に優れた成長方法である。成長条件としては、原料ガスであるＳｉＨ４とＣ３Ｈ８について、ＳｉＨ４流量は毎分２〜３ｃｍ３、Ｃ３Ｈ８流量は毎分０．５〜３ｃｍ３である。これらの流量は、良好な表面状態を保ちつつ、適当な成長速度（毎時３〜４μｍ）が得られると言う観点から決められた。成長温度は、従来技術との関連から、デバイス応用に必要なｎ型残留不純物密度を得るためには１５００℃以下が必要と判断したが、成長温度を下げ過ぎるとエピタキシャル成長が行われなくなることから、下限は１４００℃とすることが好ましい。また、成長時の圧力は１×１０４〜３×１０４Ｐａ、さらに、原料ガスと共に流す水素のキャリアガスの流量は、毎分１０〜２０Ｌである。このような条件の下、最終研磨に使用するダイヤモンド砥粒の平均粒径を０．５μｍあるいは０．２５μｍと従来よりも小さくして平坦度を上げたＣ面を用いて、エピタキシャル成長を行ったところ、１５００℃という、従来よりも低い成長温度でも、高品質なエピタキシャル膜を得ることができた。エピタキシャル膜の品質を評価する指標としては、欠陥密度、ｎ型残留不純物密度、及び表面粗さ等がある。Ｃ面上のエピタキシャル欠陥としては、通常ｈｉｌｌｏｃｋ(ヒロック)と呼ばれる三角形状の欠陥、あるいはピット状の窪みが観察されるが、デバイス応用からはその密度は５０個／ｃｍ２以下である。また、ｎ型残留不純物密度は、通常デバイス応用で用いられるドーピング密度の下限が５×１０１５ｃｍ−３程度であることから、その値以下、例えば１×１０１５ｃｍ−３以下が望ましい。エピタキシャル膜の表面粗さは、デバイスを微細化した際に、パターン欠陥を起こさないために重要であるが、通常１０μｍ×１０μｍの領域内で表面粗さＲａが１ｎｍ以下、好ましくは０．５ｎｍ以下であることが求められている。エピタキシャル膜のＲａは、成長前の基板表面のＲａに比べ、同等あるいは小さくなることが一般的であるが、それを考慮すると成長前の基板表面のＲａは１ｎｍ以下に抑えておくことが必要であり、１５００℃と言う比較的低い成長温度でエピタキシャル成長が行われるためにも、Ｒａが１ｎｍ以下の平坦度の高い基板を用いることは必須と判断した。また、エピタキシャル膜の膜厚は、デバイスの耐圧等を考慮した場合、５０μｍ以下が望ましい。 The apparatus actually used for epitaxial growth is a horizontal CVD apparatus. Since the CVD method has a simple apparatus configuration and can control growth by turning gas on / off, it is a growth method with excellent controllability and reproducibility of the epitaxial film. As growth conditions, the SiH 4 flow rate is 2 to 3 cm 3 per minute and the C 3 H 8 flow rate is 0.5 to 3 cm 3 per minute for SiH 4 and C 3 H 8 which are source gases. These flow rates were determined from the viewpoint that an appropriate growth rate (3 to 4 μm / hour) can be obtained while maintaining a good surface state. The growth temperature is determined to be 1500 ° C. or lower in order to obtain the n-type residual impurity density necessary for device application in relation to the conventional technology, but if the growth temperature is too low, epitaxial growth cannot be performed. The lower limit is preferably 1400 ° C. The growth pressure is 1 × 10 4 to 3 × 10 4 Pa, and the flow rate of the hydrogen carrier gas that flows along with the raw material gas is 10 to 20 L / min. Under such conditions, the epitaxial growth was carried out using the C-plane with the average particle size of the diamond abrasive grains used for the final polishing being 0.5 μm or 0.25 μm, which was smaller than the conventional one to increase the flatness. A high quality epitaxial film could be obtained even at a growth temperature of 1500 ° C., which is lower than the conventional growth temperature. As indices for evaluating the quality of the epitaxial film, there are a defect density, an n-type residual impurity density, a surface roughness, and the like. The epitaxial defects on the C-plane, triangular defects commonly referred to as hillock (hillocks), or is a pit-like recess is observed, from device applications that density is 5 0 / cm 2 or less. Moreover, since the lower limit of the doping density normally used for device application is about 5 × 10 15 cm −3 , the n-type residual impurity density is preferably less than that value, for example, 1 × 10 15 cm −3 or less. The surface roughness of the epitaxial film is important in order to prevent pattern defects when the device is miniaturized, but the surface roughness Ra is usually 1 nm or less, preferably 0.5 nm or less in a region of 10 μm × 10 μm. It is required to be. The Ra of the epitaxial film is generally equal to or smaller than the Ra on the substrate surface before the growth, but considering this, it is necessary to keep the Ra on the substrate surface before the growth to 1 nm or less. In order to perform epitaxial growth at a relatively low growth temperature of 1500 ° C., it was determined that it was essential to use a substrate having a high flatness with an Ra of 1 nm or less. Further, the film thickness of the epitaxial film is desirably 50 μm or less in consideration of the breakdown voltage of the device.
（実施例１）
２インチ（５０ｍｍ）ウェハ用ＳｉＣ単結晶インゴットから、約４００μｍの厚さでスライスし、粗削りを行った後、平均粒径が１μｍのダイヤモンド砥粒による通常研磨を実施した、４Ｈ型のポリタイプを有するＣ面に、平均粒径が０．２５μｍのダイヤモンド砥粒を用いて最終研磨を行った。表面ＡＦＭ像の観察から、研磨後の基板表面のＲａ値は０．３５ｎｍであった。その後、表面の研磨ダメージ層を除去するためにリアクティブイオンエッチングを行った後、エピタキシャル成長を実施した。具体的なエピタキシャル成長条件の例としては、原料ガスであるＳｉＨ４とＣ３Ｈ８について、ＳｉＨ４流量：毎分２ｃｍ３、Ｃ３Ｈ８流量：毎分１ｃｍ３であり、Ｃ／Ｓｉ比は１．５である。また、成長温度：１５００℃、成長時の圧力：１．６×１０４Ｐａ、さらに、水素キャリアガスの流量：毎分１６Ｌである。得られたエピタキシャル膜の膜厚は約３．５μｍであった。
Example 1
A 4H-type polytype was obtained by slicing a rough single chip from a SiC single crystal ingot for a 2 inch (50 mm) wafer with a thickness of about 400 μm and then performing normal polishing with diamond grains having an average particle diameter of 1 μm. Final polishing was performed on the C surface having diamond abrasive grains having an average particle diameter of 0.25 μm. From the observation of the surface AFM image, the Ra value of the polished substrate surface was 0.35 nm. Thereafter, reactive ion etching was performed to remove the polishing damage layer on the surface, and then epitaxial growth was performed. As an example of specific epitaxial growth conditions, for SiH 4 and C 3 H 8 which are source gases, SiH 4 flow rate: 2 cm 3 / min, C 3 H 8 flow rate: 1 cm 3 / min, and C / Si ratio is 1.5. The growth temperature is 1500 ° C., the growth pressure is 1.6 × 10 4 Pa, and the flow rate of the hydrogen carrier gas is 16 L / min. The film thickness of the obtained epitaxial film was about 3.5 μm.
エピタキシャル成長後の表面の光学顕微鏡写真を図１に示す。成長面は鏡面であり、欠陥等も見られず、良好な成長面が得られていることが分かる。欠陥密度としては、三角形あるいはピット状の欠陥密度が３０個／ｃｍ２以下であった。図２には、成長後の表面のＡＦＭ像を示す。図２からＲａ値は０．２１ｎｍであり、平坦性の高い表面となっている。また、このエピタキシャル膜表面に、Ｎｉ電極を形成して、Ｃ−Ｖ測定により残留不純物密度を求めたところ、ｎ型残留不純物密度の平均値は９．５×１０１４ｃｍ−３であり、デバイス応用に必要な値が得られていることが確かめられた。これらの結果より、エピタキシャル成長前の基板表面の平坦度を上げることで、成長温度を下げても欠陥密度の小さい成長面が得られ、かつ低いｎ型残留不純物密度も達成されていることが明らかになった。 An optical micrograph of the surface after epitaxial growth is shown in FIG. It can be seen that the growth surface is a mirror surface, no defects or the like are observed, and a good growth surface is obtained. As the defect density, the triangular or pit-shaped defect density was 30 pieces / cm 2 or less. FIG. 2 shows an AFM image of the surface after growth. From FIG. 2, the Ra value is 0.21 nm, which is a highly flat surface. Further, when an Ni electrode was formed on the surface of the epitaxial film and the residual impurity density was determined by CV measurement, the average value of the n-type residual impurity density was 9.5 × 10 14 cm −3 , and the device It was confirmed that the values required for application were obtained. From these results, it is clear that by increasing the flatness of the substrate surface before epitaxial growth, a growth surface with a low defect density can be obtained even when the growth temperature is lowered, and a low n-type residual impurity density is also achieved. became.
（実施例２）
実施例１と同様にスライス、粗削り、通常研磨を行った、４Ｈ型のポリタイプを有する２インチ（５０ｍｍ）のＣ面ウェハに、粒径が０．５μｍのダイヤモンド研磨剤を用いて最終研磨を行い、エピタキシャル成長を実施した。研磨後の基板表面のＲａ値は０．４７ｎｍであり、リアクティブイオンエッチングやエピタキシャル成長の条件は実施例１と同様である。エピタキシャル膜の膜厚は約３．５μｍであり、成長面は鏡面で、三角形あるいはピット状の欠陥密度は５０個／ｃｍ２以下であった。実施例１に比べ欠陥密度が増加しているのは、粒径の大きいダイヤモンド研磨剤を使ったため、研磨後の表面粗さが大きいことによるものであるが、この値でも通常市販されているＳｉ面上エピタキシャル基板と同等ないしそれ以下のレベルである。また、ｎ型残留不純物密度の平均値は９．５×１０１４ｃｍ−３であり、エピタキシャル膜のＲａは０．３０ｎｍであった。
(Example 2)
The final polishing was performed on a 2 inch (50 mm) C-plane wafer having a 4H-type polytype using a diamond abrasive having a particle size of 0.5 μm, as in Example 1. And epitaxial growth was performed. The Ra value of the substrate surface after polishing is 0.47 nm, and the conditions for reactive ion etching and epitaxial growth are the same as in Example 1. The film thickness of the epitaxial film was about 3.5 μm, the growth surface was a mirror surface, and the defect density of triangles or pits was 50 / cm 2 or less. The reason why the defect density is increased compared to Example 1 is that a diamond abrasive having a large particle size is used, and thus the surface roughness after polishing is large. The level is equivalent to or lower than that of the epitaxial substrate on the surface. The average value of the n-type residual impurity density was 9.5 × 10 14 cm −3 , and the Ra of the epitaxial film was 0.30 nm.
（比較例）
比較例として、実施例１と同様のスライス、粗削り、平均粒径が１μｍのダイヤモンド砥粒を使用する通常研磨のみを行った、４Ｈ型のポリタイプを有する２インチ（５０ｍｍ）のＣ面ウェハに、エピタキシャル成長を実施した。研磨後の基板表面のＲａ値は１．５ｎｍであり、リアクティブイオンエッチングやエピタキシャル成長の条件は実施例１と同様である。エピタキシャル膜の膜厚は約３．５μｍである。成長後の表面の光学顕微鏡写真を図３に示す。図３より三角形あるいはピット状の欠陥の密度が５×１０３個／ｃｍ２以上発生しており、成長前の基板表面の平坦度が、成長後の状態に大きく影響していることが分かる。このエピタキシャル膜表面に、Ｎｉ電極を形成して、Ｃ−Ｖ測定により残留不純物密度を求めようとしたところ、欠陥によるリーク電流のため、評価は行えなかった。また、欠陥による凸凹が大き過ぎるため、ＡＦＭ測定も行えず、エピタキシャル膜のＲａを求めることはできなかった。
(Comparative example)
As a comparative example, a 2 inch (50 mm) C-plane wafer having a 4H-type polytype was obtained by performing only normal polishing using the same slice, rough cutting, and diamond abrasive grains having an average particle diameter of 1 μm as in Example 1. Epitaxial growth was performed. The Ra value of the substrate surface after polishing is 1.5 nm, and the conditions for reactive ion etching and epitaxial growth are the same as in Example 1. The film thickness of the epitaxial film is about 3.5 μm. An optical micrograph of the surface after growth is shown in FIG. FIG. 3 shows that the density of triangular or pit-like defects is 5 × 10 3 pieces / cm 2 or more, and the flatness of the substrate surface before growth greatly affects the state after growth. When an Ni electrode was formed on the surface of the epitaxial film and the residual impurity density was determined by CV measurement, evaluation could not be performed due to a leakage current due to defects. Moreover, since the unevenness due to the defect is too large, AFM measurement cannot be performed, and Ra of the epitaxial film cannot be obtained.
この発明によれば、Ｃ面上へのエピタキシャル成長において、欠陥のない平坦な成長面を持ち、かつ残留不純物が低減された高品質エピタキシャル膜を有するＳｉＣ単結晶基板を作成することが可能である。そのため、このような基板上に電子デバイスを形成すればデバイスの特性が向上することが期待できる。本実施例においては最終研磨にダイヤモンド研磨剤を用いた研磨面を使用しているが、コロイダルシリカ等を用いるメカノケミカル研磨による研磨面についても同様である。 According to the present invention, it is possible to produce a SiC single crystal substrate having a high-quality epitaxial film having a flat growth surface without defects and having reduced residual impurities in epitaxial growth on the C-plane. Therefore, if an electronic device is formed on such a substrate, it can be expected that the characteristics of the device are improved. In this embodiment, a polished surface using a diamond abrasive is used for final polishing, but the same applies to a polished surface by mechanochemical polishing using colloidal silica or the like.
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| JP3915252B2 (en) * | 1998-06-09 | 2007-05-16 | 富士電機デバイステクノロジー株式会社 | Method for manufacturing silicon carbide semiconductor substrate |
| JP5285202B2 (en) * | 2004-03-26 | 2013-09-11 | 一般財団法人電力中央研究所 | Bipolar semiconductor device and manufacturing method thereof |
| JP4539140B2 (en) * | 2004-03-29 | 2010-09-08 | 住友電気工業株式会社 | Silicon carbide substrate and method for manufacturing the same |
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