JP4786155B2 - Semiconductor device and semiconductor device refresh processing method - Google Patents

Description

  The present invention relates to a semiconductor device having a volatile memory, and more particularly to a configuration of a volatile memory that suppresses an increase in power consumption accompanying an increase in memory capacity.

  In recent years, electronic devices that handle images, such as digital cameras, digital video cameras, and camera-equipped mobile phones, tend to increase the number of CCD pixels year by year and increase the data capacity to be processed. For this purpose, a DRAM (Dynamic RAM) is generally used. There is another SRAM (Static RAM) as a volatile memory other than DRAM, but it is expensive, requires a large circuit scale of the device, requires large power consumption, and has a large capacity such as image data. Not suitable for data recording. Therefore, the DRAM is more suitable as a volatile memory for image processing than the SRAM.

  When a DRAM is used, a refresh process is performed to periodically reproduce and rewrite information in order to record and hold the recorded data. Here, the current consumption required for the refresh process increases in proportion to the data capacity. If the refresh process period and access to the volatile memory are performed within the same time and the process conflicts, access to the volatile memory is waited and the access speed is reduced, so the number of refreshes is efficiently reduced. There is also a need.

As an example of reducing the number of times the volatile memory is refreshed, for example, there is an example of a semiconductor memory device that uses information of a FAT (File Allocation Table). That is, the DRAM has a self-refresh mode, a memory for FAT, a register group attached to the FAT, a value stored in a first register associated with the FAT, and a self-refresh operation mode signal Thus, the value of the register group is rewritten, and the self-refresh of the memory area indicated by the FAT is stopped. (For example, refer to Patent Document 1).
JP-A-9-128965 (FIG. 1)

  However, the technique described in Patent Document 1 requires a FAT information management memory in addition to the volatile memory for storing data. The cost of the FAT information management memory is high and the power consumption is increased. Was. In particular, since data is managed in units of FAT, the number of data areas is large, and a large-capacity management memory is used to manage whether it is in use or unused in units of clusters, which are FAT information units, whether refresh is necessary, etc. Is required separately. Further, in the FAT information, since it is necessary to fix and manage data in units of clusters, there has been a situation in which refreshing must be performed on a memory area that is larger than the originally required data capacity.

  The present invention has been made to solve such problems, and provides a semiconductor device that can efficiently reduce the power consumption by minimizing the refresh period of a memory area that does not require data retention. The purpose is to do.

A semiconductor device according to the present invention includes a volatile memory that stores data for each of a plurality of divided areas, and a refresh controller unit that refreshes each of the plurality of areas of the volatile memory. A refresh stop control is performed for each region of the volatile memory with respect to the refresh controller unit based on the set number of readings.
With such a configuration, it is possible to efficiently minimize the refresh period of the memory area that does not require data retention and to reduce power consumption.

A semiconductor device according to the present invention includes a volatile memory that stores data for each of a plurality of divided areas, a refresh controller that refreshes each of the plurality of areas of the volatile memory, and each of the plurality of areas of the volatile memory. A register for setting the number of times of reading is possible for each of the plurality of areas of the volatile memory, and a plurality of the volatile memories respectively provided for each of the plurality of areas of the volatile memory. A counter for counting the number of times read from each of the areas is provided corresponding to each of the plurality of areas of the volatile memory, and the readability set in the register for each of the plurality of areas of the volatile memory is provided. Comparing the number of times and the number of readings counted by the counter, according to the comparison result of this comparator, To serial refresh controller unit, and is characterized in that the refresh stop control for each region of the volatile memory.
With such a configuration, it is possible to efficiently minimize the refresh period of the memory area that does not require data retention and to reduce power consumption.

  In addition, the comparator may perform refresh stop control for each area of the volatile memory with respect to the refresh controller unit when the number of readings counted by the counter reaches the number of possible readings set in the register.

  Further, the plurality of areas of the volatile memory may be divided by addresses.

  Further, a holding unit for recording and holding the comparison result of the comparator is provided, and the refresh controller unit is controlled to stop refreshing for each area of the volatile memory according to the comparison result recorded and held in the holding unit. You may do it.

  Further, in place of the register, the counter, and the comparator, the refresh controller unit may be controlled to stop refreshing during a period from when writing to the volatile memory is performed until reading is performed. .

  In addition, the register, counter, and comparator are provided only for a part of the plurality of areas of the volatile memory, and the area other than the part of the area is written from when writing occurs. The refresh controller may be controlled to stop refreshing for a period until reading.

The refresh processing method for a semiconductor device according to the present invention is a refresh processing method for refreshing a volatile memory storing data for each of a plurality of divided areas, and can be read from each of the plurality of areas of the volatile memory. Set the number of times, count the number of times read from each of the plurality of areas of the volatile memory, compare the number of times that can be read and the number of times of reading for each of the plurality of areas of the volatile memory, the comparison result Accordingly, refresh stop control is performed for each area of the volatile memory.
By such a method, the refresh period of the memory area that does not need to hold data efficiently can be minimized and power consumption can be reduced.

  According to the present invention, it is possible to provide a semiconductor device that can efficiently reduce the power consumption by minimizing the refresh period of a memory area that does not require data retention.

Embodiment 1 of the Invention
Embodiment 1 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention.
FIG. 2 is a diagram showing an internal configuration of the access monitoring circuit unit shown in FIG.

In FIG. 1, an access monitoring circuit unit 1 includes an address (Address (RAS / CAS)) signal Signal (hereinafter referred to as S) 1, a write signal (Write Enable) S2, a read signal (Read Enable) S3, and a preset value. In response to the read count setting signal S4 for each area of the memory cell 3, the refresh stop signal S5 is output to the refresh controller unit 2.
The refresh controller unit 2 performs a RAS (Row Address Strobe) control 4 and a CAS (Column Address Strobe) control 5 described later in accordance with a refresh stop signal S5 from the access monitoring circuit unit 1 and a refresh request (Refresh_Req) signal S6 from a CPU (not shown). Then, the specified address of the memory cell 2 is refreshed.

The memory cell 3 is a DRAM which is a volatile memory, and has a 16-bit address space in the description of this embodiment. The memory cell 3 is configured to be accessed by designating a row address and a column address. The row address is input by the RAS control unit 4 and the column address is input by the CAS control unit 5.
The CPU (not shown) uses the RAS control 4 and CAS control 5 to address the memory cell 2 in accordance with the address signal S1, the write signal S2, the read signal S3, the refresh request signal S6 from the refresh controller unit 2, and the refresh stop signal S5. The area is specified by the above, and writing, reading, or refreshing is performed on the specified area.

Next, the internal configuration of the access monitoring circuit unit 1 in FIG. 1 will be described with reference to FIG.
In FIG. 2, the access detection unit 10 accesses the memory, that is, detects an address signal S1, a write signal S2, and a read signal S3, and uses these signals S1, S2, and S3 as a memory management unit (area 1) 101 described later. To (region n) 10n.
The memory management unit (area 1) 101 manages the area 1 that is one of a plurality of divided areas of the memory cell 3. The memory management unit (area 1) 101 includes a counter 111, a setting register 121, a comparator 131, and a status 141. A memory management unit 10n (n = 1, 2,...) Is provided for each area specified by an address, and each of the memory management units 10n (n = 1, 2, 3,...) Has a counter 11n. (N = 1, 2, 3,...), Setting register 12n (n = 1, 2, 3,...), Comparator 13n (n = 1, 2, 3,...), Status 14n. (N = 1, 2, 3,...).

The setting register 121 is provided for each of the plurality of regions of the memory cell 3 and sets the number of times that data can be read.
The counter 111 is provided for each of the plurality of regions of the memory cell 3 and counts the number of times of reading from the read signal S2 input from the access detection unit 10.
The comparator 131 is provided for each of the plurality of regions of the memory cell 3, compares the number of reads that can be read set in the setting register 121 and the number of reads counted by the counter 111, and outputs the comparison result to the status 141.
The status 141 holds an identification signal for recognizing the necessity of refreshing the area 1 of the memory cell 3. For example, when “0” is held in the status 141, a refresh stop signal S 5 is output to the refresh controller unit 2, and self refresh is controlled to be stopped / suppressed for the region 1 of the memory cell 3.

Next, the operation of the semiconductor device according to the first embodiment of the present invention will be described.
FIG. 3 is an initial setting flowchart of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is an operation flowchart of the semiconductor device according to the first embodiment of the present invention.
First, the semiconductor device is initialized. In FIG. 3, initial setting by the access monitoring circuit unit 1 is started by an instruction by an address signal S1 from a CPU (not shown) (ST301), and the access detection unit 10 performs area setting for the memory management unit 10n (ST302). ). Here, a case where there is a region setting for the region 1 of the memory cell 3 will be described. First, the start address of region 1 (for example, address 0x0000 when a 16-bit address space is used for memory cell 3) is set (ST303), and then the end address of region 1 (for example, 0x0FFF) is set (ST304). Next, the number of readings corresponding to the region 1 of the memory cell 3 is set to, for example, N times in the setting register 121 of the memory management unit (region 1) 101 (ST305). Similarly, in accordance with an instruction from a CPU (not shown), area setting is repeated for other areas (ST302 to ST305), and after the area setting is completed (ST302), the initial setting is completed (ST306).

Next, the operation of the semiconductor device according to the present invention will be described.
The access detection unit 10 always detects the presence / absence of the write signal S2 and the read signal S3 for each region of the memory cell 3 initialized in FIG.
In FIG. 4, for example, when a CPU (not shown) outputs a write signal S2 for the address 0x0000 of the memory cell 3, the access detection unit 10 of the access monitoring circuit unit 1 detects the write signal S2 and performs self-refresh. Each setting operation is started (ST401).

Next, the access detection unit 10 detects whether the start address (address 0x0000) of the area 1 of the memory cell 3 has been written (ST402). If the start address is written as a result of the detection (ST402), the number of readings of the counter 111 is initialized to 0, and the status 141 identification signal is set to "1" (ST403). If the start address of area 1 of memory cell 3 is not written (ST402), the number of readings of counter 111 is not initialized to 0, and the identification signal of status 141 is not rewritten.
Next, the access detection unit 10 detects whether the end address (address 0x0FFF) of the area 1 of the memory cell 3 has been read (ST404). If the end address is read as a result of the detection (ST404), the counter 111 of the memory management unit (area 1) 101 is incremented by 1 (ST405). Next, the comparator 131 compares the number of possible reads N set in the setting register 121 and the number of reads counted by the counter 111 (ST406). If both values are the same, the comparator 131 identifies the status 141. The signal is converted from “1” to “0” (ST407), and the processing of each setting operation for self-refresh is completed. On the other hand, if both numerical values are not the same in ST406, the processing of each setting operation for self-refresh is terminated without converting the identification signal of status 141 (ST408).

  When the status 141 holds the identification signal “0”, the refresh stop signal S5 is output to the refresh controller unit 2. When the refresh request signal S6 is output from the CPU (not shown) to the refresh controller unit 2 at regular time intervals, the refresh controller unit 2 displays the statuses 141, 142,... Of each memory management unit 101, 102,. Self-refresh is not performed for the region where the identification signal of 14n is “0”, and self-refresh of the memory cell 3 is performed via the RAS control 4 and CAS control 5 for the region where the identification signal is “1”. Do.

  With such a configuration, it is possible to provide a semiconductor device that can efficiently reduce the power consumption by minimizing the refresh period of a memory area that does not require data retention. That is, since the area setting is directly performed on the physical address of the memory cell 3, it is necessary to use a FAT-adapted system (for example, a file system) as in the technique of Patent Document 1 shown in the related art. There is no need to newly provide a FAT management memory as a data management area. In addition, since the number of areas and the area size can be freely set, it is not necessary to increase the number of divisions of the data area of the memory cell as in the technique described in Patent Document 1 shown in the related art, For all these divided units, a memory for holding the state of necessity of refresh is not required, and further, the number of areas can be optimized and controlled, so the load on the CPU (not shown) can be reduced. The power consumption of the entire semiconductor device can be reduced. Furthermore, since the memory management unit can freely set the necessary data area, it is not necessary to manage the data in a fixed size in units of clusters as in the technique described in Patent Document 1 of the prior art. There is no problem of refreshing a region having a size larger than the amount. Since refresh is performed in accordance with the number of readings for each region, it is possible to perform necessary processing only during an optimum period, and power consumption of the semiconductor device can be reduced to a minimum.

Next, an example in which the semiconductor device according to the present invention is applied to a digital camera will be described.
FIG. 5 is a diagram for explaining a processing system of a digital camera.
In FIG. 5, a CCD 200 is a camera that images a subject. The capturing unit 300 captures the subject image captured by the CCD 200 into an image sensor, converts it into image data, and writes the image data to the large-scale DRAM 400. Large scale DRAM 400 corresponds to memory cell 3 having the configuration shown in FIG. The image quality adjustment unit 500 performs image quality adjustment such as brightness, saturation, display balance, and the like on the imaging data written in the DRAM 400. The JPEG processing unit 600 compresses the image data written in the large-scale DRAM 400 using the JPEG method. The external data recording unit 700 records imaging data on a recording medium such as a card. The resizing unit 900 converts the image data to a size that can be displayed on a display unit 1000 such as an LCD. The display control unit 1100 performs display control on the display unit of the LCD 1000 or the like. A CPU 1200 controls the entire digital camera. These are also signal-connected via the main bus 1200.

Next, a process for recording image data captured by the CCD 200 on a card or the like 800 will be described.
FIG. 6 is a diagram showing an operation flow of the processing system of the digital camera.
In FIG. 6, first, the CCD 200 images a subject (ST601). Next, capturing unit 300 captures the subject imaged by CCD 200 as imaging data (ST602). Next, capturing unit 300 records image data in large-scale DRAM 400 (ST603). At this time, for example, it is designated to be recorded in a specific area (area 1) of the large-scale DRAM 400. Next, the image quality adjustment unit 500 reads the image data recorded in the area 1 from the area 1 of the large-scale DRAM 400 (ST604), adjusts the image quality (ST605), and then again returns to the specific area (area 2) of the large-scale DRAM 400. (ST606). Next, the image data after image quality adjustment recorded in the area 2 of the large-scale DRAM 400 is read by the JPEG processing unit 600 (ST607), compressed and converted into the JPEG method (ST608), and then the specific area (area) of the large-scale DRAM 400 again. Write back to 3) (ST609). Next, the external data recording unit 700 reads the image data recorded in the area 3 of the large-scale DRAM 400 and JPEG-converted (ST610), and records and saves it on the card or the like 800 (ST611).

Next, the process in which the CCD 200 displays image data on the LCD 1000 will be described.
ST601 to ST606 are the same as the process of recording on the card 800 or the like.
The image quality adjustment unit 500 reads the image data recorded in the area 1 from the large-scale DRAM 400, adjusts the image quality, and then writes it back to the specific area (area 2) of the large-scale DRAM 400 again (ST606). However, after the image data after image quality adjustment recorded in the area 2 of the large-scale DRAM 400 is read (ST612), the image data is resized so as to be displayed on the LCD 1000 (ST613), and again in the specific area (area 4) of the large-scale DRAM 400. Write back (ST614). Next, the display control unit 1100 reads the resized image data from the area 4 of the large-scale DRAM 400 (ST615) and displays it on the LCD 1000 or the like (ST616).

Usually, a user of a digital camera records image data captured by the CCD 200 on a card or the like 800, and after recording the image data on the card or the like 800, displays it on the LCD or the like 1000 to check the contents of imaging.
Here, when the number of times of reading to the large-scale DRAM 400 is confirmed, ST604 is once entered into the area 1, ST607 is twice entered into the area 2, ST612 is entered once into the area 3, ST610 is entered once into the area 4, and ST615 is entered into the area 4 once. Times.
Accordingly, the setting register 121 of the memory management unit (area 1) 101 in FIG. 2 is set once, the setting register 122 of the memory management section (area 2) 102 is set twice, and the setting register of the memory management section (area 3) 103 is set. If once is set in 123 and once in the setting register 124 of the memory management unit (area 4) 104, a necessary minimum image data holding period is secured, and the large-scale DRAM 400 (memory cell 3) Self-refresh can be performed.

  Incidentally, the large-scale DRAM 400 may be used as an operation area of the CPU 1200 or the like. In this case, an infinite number of readings, that is, constant self-refreshing may be set for a specific area during operation. On the other hand, for areas other than the specific area that is currently in operation, it may be set so that 0 reading, that is, self-refreshing is not always performed. By doing so, it is possible to efficiently reduce the power consumption of the semiconductor device.

In FIG. 5, when the display control such as the image compression rate and the contrast is fixed in advance, or when these processes are performed by the CPU 1200 or the like, the resizing unit 900 and the display control unit 1100 are omitted. It can also be configured.
At this time, the reading process for area 2 in ST612 and the reading process for area 4 in ST615 are not required. In this case, if the setting is made once for all the setting registers 121 to 124 of the memory management units (areas 1 to 4) 101 to 104 in FIG. The DRAM 400 (memory cell 3) can be self-refreshed. As described above, when each setting register can be set once, the refresh is performed when the memory cell 3 as the volatile memory is read in place of the setting register 121, the counter 111, and the comparator 131. The controller unit 2 is controlled to stop self-refresh. Therefore, each counter, each setting register and each comparator are not required, the number of components of the semiconductor device can be reduced, and more efficient power reduction can be realized even during self-refresh.
The setting register 121, the counter 111, and the comparator 131 may be provided only for a part of the plurality of areas of the volatile memory. In this case, for the areas other than the part of the areas, When reading is performed, the refresh controller 2 is controlled to stop self-refresh.

  Furthermore, the memory cell 3 area can be set to an appropriate number of read count setting areas and impossible area areas, thereby efficiently minimizing the refresh period of memory areas that do not require data retention and reducing power consumption. To reduce.

It is a figure which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 1 is a diagram showing an internal configuration of the access monitoring circuit unit. It is an initial setting flowchart of the semiconductor device concerning Embodiment 1 of the present invention. FIG. 6 is an operation flowchart of the semiconductor device according to the first embodiment of the present invention. It is a figure explaining the processing system of a digital camera. It is a figure which shows the operation | movement flow of the processing system of a digital camera.

Explanation of symbols

  1 access monitoring circuit unit, 2 refresh controller unit, 3 memory cell, 4 RAS control, 5 CAS control, 10 access detection unit, 10n address management unit (region n), 11n counter, 12n setting register, 13n comparator, 14n status 200 CCD, 300 capture unit, 400 large scale DRAM, 500 image quality adjustment unit, 600 JPEG processing unit, 700 external data recording unit, 800 card, 900 resize unit, 1000 LCD, 1100 display control unit, 1200 CPU, etc.

Claims (6)

Volatile memory that stores data for each of the divided areas,
A refresh controller for refreshing each of the plurality of areas of the volatile memory;
A register that is provided corresponding to each of the plurality of areas of the volatile memory, and sets a readable count for each of the plurality of areas of the volatile memory;
A counter provided corresponding to each of the plurality of areas of the volatile memory, and counting the number of times read from each of the plurality of areas of the volatile memory;
A comparator provided corresponding to each of the plurality of areas of the volatile memory, and for comparing each of the plurality of areas of the volatile memory with the number of readable times set in the register and the number of reads counted by the counter With
The refresh controller unit is refreshed for each area of the volatile memory in accordance with the comparison result of the comparator when the number of possible reads set in the register is equal to the number of reads counted by the counter. The semiconductor device is characterized in that stop control is performed.   The comparator performs refresh stop control for each area of the volatile memory with respect to the refresh controller unit when the number of readings counted by the counter reaches the number of possible readings set in the register. A volatile memory according to 1 is a semiconductor device.   2. The semiconductor device according to claim 1, wherein the plurality of areas of the volatile memory are divided by addresses.   A holding unit for recording and holding the comparison result of the comparator is provided, and the refresh controller unit is controlled to stop refreshing for each area of the volatile memory according to the comparison result recorded and held in the holding unit. The semiconductor device according to claim 1.   Registers, counters, and comparators are provided only for some of the plurality of regions of the volatile memory,
  2. The semiconductor device according to claim 1, wherein when a read operation is performed on a region other than the partial region, refresh stop control is performed on the refresh controller unit. 3.   A refresh processing method for refreshing a volatile memory storing data for each of a plurality of divided areas,
  Set the number of readable times for each of the multiple areas of volatile memory,
  Count the number of reads from each of the plurality of areas of the volatile memory,
  For each of the plurality of areas of the volatile memory, compare the number of possible reads and the number of reads,
  A refresh processing method for a semiconductor device, characterized in that refresh stop control is performed for each area of the volatile memory in accordance with a comparison result when the number of possible reads and the number of reads are equal.

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