JP4775016B2 - Switching power supply control circuit - Google Patents

Description

  The present invention relates to a switching power supply control circuit in which a switch element is connected to a primary winding of a transformer, and a predetermined output power is supplied from a secondary winding of the transformer to a load, and is particularly applied to both ends of the switch element. The present invention relates to a quasi-resonant switching power supply control circuit that turns on a switch element in accordance with a feedback signal from a load at a timing when the lowest voltage point is detected.

  Conventionally, a current discontinuous mode flyback resonance circuit as shown in Patent Document 1 has been used for the purpose of reducing switching loss of a switching power supply. This utilizes the voltage resonance phenomenon caused by the inductance of the primary winding and the resonance capacitor after the secondary current becomes zero.

FIG. 4 is a block diagram showing a control circuit of a conventional quasi-resonant switching power supply.
In the control circuit 10, a bottom detection circuit (Valley Detection) 11 is connected to an input terminal ZCD for zero current detection. The bottom detection circuit 11 is a comparator that compares the voltage applied to the input terminal ZCD with a reference voltage (threshold) having a voltage level close to 0 V. The output terminal of the bottom detection circuit 11 is one input terminal of the AND circuit 12. To the one-shot circuit 13 via the AND circuit 12. A voltage controlled oscillator (VCO) 14 is connected to the other input terminal of the AND circuit 12. The voltage controlled oscillator 14 is an oscillator that changes an output frequency depending on the magnitude of a voltage (VCO voltage) input thereto, and includes a voltage signal input terminal VCO and a reset signal input terminal Reset. In the voltage controlled oscillator 14, the input terminal of the VCO voltage is connected to the feedback signal input terminal FB, and the input terminal of the reset signal Reset is connected to the output terminal of the one-shot circuit 13.

  The feedback signal detection input terminal FB is connected to the inverting input terminal (−) of the comparator 15. The comparator 15 has its non-inverting input terminal (+) grounded via a reference power supply E 1 of 0.5 V, and outputs a disable signal Disable from the output terminal to the inverter circuit 16. The output of the inverter circuit 16 is connected to the clear terminal (CLR) of the one-shot circuit 13. The input terminal FB is connected to a 5V power source E2 through a series circuit of a resistor R and a diode D, and determines the FB terminal voltage.

  A current comparator 17 is connected to the current sense input terminal IS, and a current sense signal is supplied to the non-inverting input terminal (+) of the four input terminals of the current comparator 17. The remaining three inverting input terminals (−) are connected to a feedback signal input terminal FB, a 1V reference power supply E3, and a soft start circuit 18, respectively. The output terminal of the current comparator 17 is connected to the reset terminal R of the flip-flop circuit 19. The output terminal of the one-shot circuit 13 is connected to the set terminal S of the flip-flop circuit 19. The Q output of the flip-flop circuit 19 is connected to the output terminal OUT via the AND circuit 20, and the output signal Q is switched to a switching element Q1 such as a power MOSFET externally connected to the output terminal OUT (see FIG. 5 described later). Output as a signal. The soft start circuit 18 generates a soft start signal that limits the turn-on period of the switch element Q1 when the switching power supply is activated.

  In the overload detection comparator 21, the inverting input terminal (−) is connected to the feedback signal input terminal FB, and the non-inverting input terminal (+) is grounded via the 3.3V reference power supply E4. . The output terminal of the comparator 21 is connected to the reset terminal Reset of the timer circuit 22. The timer circuit 22 is for setting two delay times. The first output signal (low) is output to the AND circuit 20 100 ms after the comparator 21 detects the overload state, and the switch The switching signal to the element Q1 is forcibly stopped. The second output signal is output 800 ms after the overload state is detected, and is supplied as a reset signal to a startup circuit (not shown).

  In the switching power supply control circuit 10 described above, as shown in Patent Document 1, the voltage applied to the switch element Q1 at the time of zero cross detection becomes the minimum point of the resonance waveform, and the switch element Q1 is turned on at this timing. Thus, the next switching cycle is started, which is generally called a pseudo-resonance type or partial resonance type switching power supply control method.

  In this switching power supply control method, when the drain current of the switch element Q1 is zero and the drain voltage is low (at or near the minimum point), the switch element Q1 is switched from OFF to ON, and the ON current flows to cause self-excited oscillation. Switching operation by Therefore, compared with a PWM (Pulse Width Modulation) method based on a switching operation at a fixed frequency using an ordinary oscillator, that is, a so-called hard switching control method, the change in the drain voltage can be reduced in the quasi-resonant switching power supply control. Therefore, switching noise can be reduced, and energy loss by soft switching can be reduced, so that a highly efficient power source can be configured by reducing power consumption.

  Further, the switching power supply device described in Patent Document 2 alternately repeats the oscillation operation period and the oscillation stop period in order to reduce the standby switching loss. The lighter the load, the shorter the oscillation period. It is configured to perform burst switching operation so as to be long. According to such a configuration of the switching power supply device, there is an effect that it is possible to improve power conversion efficiency and to save power by performing a burst switching operation during standby.

Next, a configuration example of an AC / DC switching power supply circuit using the control circuit 10 described above and a PWM control operation thereof will be described.
FIG. 5 is a block diagram illustrating an example of an AC / DC switching power supply circuit.

  4 corresponds to the integrated circuit IC in the AC / DC switching power supply circuit in FIG. 5. The control circuit 10 in FIG. 4 includes an input terminal ZCD for zero current detection, a feedback signal, and the like. Only the input terminal FB, the current sense signal input terminal IS, and the output terminal OUT for outputting a control signal to the switch element Q1 such as a power MOSFET are shown. However, in the package of the 8-pin integrated circuit IC, a ground terminal GND for supplying a reference voltage to each part of the integrated circuit, a power supply terminal VCC for supplying power of the integrated circuit, a VH terminal for supplying start-up current, and an unconnected A pin having a terminal function such as an NC terminal is provided.

In FIG. 5, the AC input of the AC power supply AC is rectified by the diode bridge D1 to become a DC input voltage V _IN . The transformer T1 includes an inductance (Lp) of the primary winding Lp and a capacitance of a resonance capacitor Cr connected in parallel to the switch element Q1 (this can be configured only by a parasitic capacitance of the switch element Q1). An LC resonance circuit is provided. The input voltage V _IN is supplied to one end of the smoothing capacitor C1 and the primary winding Lp of the transformer T1, and the other end of the primary winding Lp is connected to the drain of the switch element Q1. The source of the switch element Q1 is connected to the other end of the smoothing capacitor C1 through the resistor R1, and the gate is connected to the output terminal OUT of the integrated circuit IC through the resistor R2.

  The primary winding Lp, the secondary winding Ls, and the auxiliary winding Lb of the transformer T1 are all wound around the same core of the transformer T1. Note that the inductance of the secondary winding Ls is Ls, and the inductance of the auxiliary winding Lb is Lb. The resonance capacitor Cr is connected in parallel to the series circuit of the switch element Q1 and the resistor R1, but the same effect can be obtained even if it is mounted in parallel with the primary winding Lp. The auxiliary winding Lb is connected to a rectifying diode D2 and a smoothing capacitor C2 for producing a power source for the integrated circuit IC. R3 is a resistor that supplies the voltage at the connection point between the switch element Q1 and the resistor R1 to the current sense signal input terminal IS, and R4 is directly input to the input terminal ZCD of the integrated circuit IC without rectifying the voltage of the auxiliary winding Lb. It is resistance to do.

  The secondary winding Ls of the transformer T1 is provided with a diode D3 and a smoothing capacitor C3 for rectifying the voltage generated in the secondary winding Ls. The anode of the diode D3 is connected to one end of the secondary winding Ls, and the cathode is connected to the power output terminal Vout and one end of the smoothing capacitor C3. The other end of the smoothing capacitor C3 is connected to the other end of the secondary winding Ls and to the ground terminal Gnd.

  The integrated circuit IC changes the potential of the output terminal OUT to a high / low level, drives the gate of the switch element Q1, and turns on / off the switch element Q1 to turn on the secondary of the transformer T1. A DC voltage smoothed on the winding Ls side is generated between the power output terminal Vout and the ground terminal Gnd. At this time, since a drain current flows through the switching element Q1 during the ON period, a current flows to the secondary winding Ls side by the back electromotive force in the transformer T1 connected thereto, and energy is stored. The switch element Q1 is then turned off, but current stored in the transformer T1 causes a current to flow through the smoothing capacitor C3 through the diode D3 on the secondary winding Ls side of the transformer T1 during the off period of the switch element Q1. Thus, a DC voltage smoothed on the secondary winding Ls side of the transformer T1 is generated between the power supply output terminal Vout and the ground terminal Gnd.

  Between the power supply output terminal Vout and the ground terminal Gnd, an output detection circuit including a series circuit of resistors R5 and R6 and a resistor R7, a photodiode PD, a capacitor C4, and a shunt regulator D4 is configured. Here, a current corresponding to the output voltage flows through the photodiode PD, and a feedback signal is supplied to the phototransistor PT connected between the auxiliary winding Lb and the feedback signal input terminal FB of the integrated circuit IC. Electric power corresponding to load fluctuations (not shown) can be supplied.

  In the circuit of FIG. 5, when the switch element Q1 is turned off, the energy stored in the transformer T1 is released to the smoothing circuit on the secondary winding Ls side. This is simply referred to as the drain voltage.) Vds drops from the high level, and oscillation starts in the LC resonance circuit of the transformer T1. Note that the timing chart of FIG. 7 to be described later shows the oscillation waveform of the drain voltage Vds of the switch element Q1 generated at the timing of heavy load, medium load, and light load, respectively.

  At this time, a voltage waveform corresponding to the drain voltage Vds having an amplitude proportional to the number of windings appears in the auxiliary winding Lb of the transformer T1. The drain voltage Vds of the switch element Q1 oscillates around the DC voltage generated between the terminals of the smoothing capacitor C1 when the AC input of the AC power supply AC is rectified. On the other hand, the input terminal ZCD for zero current detection is connected to the auxiliary winding Lb having a polarity opposite to that of the primary winding Lp of the transformer T1, and therefore has a vibration waveform centered on 0V. A zero current detection signal appears.

  In the integrated circuit IC, the zero detection of the zero current detection signal applied to the input terminal ZCD is performed in the bottom detection circuit 11. The output signal of the bottom detection circuit 11 is adjusted for a delay of ¼ period of resonance vibration from the zero cross timing, and is supplied to the one-shot circuit 13 via the AND circuit 12 (that is, the bottom detection circuit 11 detects the bottom). Instead of detecting directly, the bottom is detected indirectly from the zero cross). A switching signal is output from the flip-flop circuit 19 to the output terminal OUT via the AND circuit 20 at the timing when the drain voltage Vds of the switch element Q1 becomes the lowest voltage (bottom). As a result, a switching operation in a state where the current flowing through the transformer T1 is zero (voltage and current are shifted by ¼ period in the resonance circuit), that is, soft switching can be realized.

FIG. 6 is a characteristic diagram showing the relationship between the switching frequency (fsw) and the output power (Po).
If the electronic device or the like is in a standby state, the output load connected to the output terminal of the power supply becomes a light load. In this case, less power is supplied to the load such as a microcomputer than in the normal operation state. The problem here is that when the load is light, the switching frequency rises significantly, the switching loss in the switching element Q1 increases, and the heat generation causes damage to the switching element Q1, or the noise regulation is 150 kHz or higher. Entering the lap deduction zone, the product standard cannot be cleared.

  Therefore, as shown in FIG. 6, the switching control is performed by limiting the maximum switching frequency so as not to exceed a certain level. In FIG. 6, when the upper limit of the maximum switching frequency is set to 130 kHz and a trigger signal for the next switching is input to the input terminal ZCD for zero current detection during that period (within one period), the trigger signal is By invalidating and skipping one cycle of resonance (bottom skip), the increase in frequency is suppressed (refer to Patent Document 1 for details of bottom skip). In FIG. 6, trigger skipping may or may not occur at the change of the switching frequency, so that the switching frequency fluctuates is indicated by double vertical lines.

FIG. 7 is a timing chart showing a steady operation in the control circuit of FIG.
4A to 4D show the drain voltage Vds of the switching element Q1, the output waveform of the voltage controlled oscillator 14 (corresponding to the period of the maximum blanking frequency fsw), the bottom detection signal of the bottom detection circuit 11, and the output. Output pulses output from the terminal OUT are shown respectively. When the output of the voltage controlled oscillator 14 is high, bottom detection of the drain voltage Vds is invalid (the corresponding input of the AND circuit 12 is negative logic), and the output of the voltage controlled oscillator 14 becomes low (Low). When the first bottom is detected, an output pulse is output from the output terminal OUT. In the case of a partial resonance power supply, in general, when the heaviest load is set, the maximum peak current Ids flows through the switching element Q1 such as a power MOSFET, and the switching element Q1 has an output pulse as shown in FIG. The on width is maximized. At this time, the period during which flyback energy is supplied to the secondary winding Ls side is also maximized, so that the switching frequency is lowest. As the load becomes lighter from this state, the switching frequency of the switching element Q1 gradually increases due to the narrowing of the ON width.

  When the load becomes lighter, the period for disabling the switching trigger by the maximum blanking frequency fsw (the high output period of the voltage controlled oscillator 14 corresponds to the period) is extended, and the connected load is The switching loss can be reduced by further reducing the number of times of switching by reducing the set value of the maximum switching frequency by the voltage controlled oscillator 14 according to the fluctuation. At this time, the fluctuation of the load can be detected by determining a decrease in the FB terminal voltage at the input terminal FB to which the voltage signal of the secondary side circuit of the transformer T1 is fed back or a decrease in the ON width of the switch element Q1.

  In relation to the output power (Po) and the switching frequency (fsw), as shown in FIG. 6, if the number of times of switching is forcibly reduced in a light load state, the switching loss in the switch element Q1 can be reduced. It is. This is a method in which the maximum switching frequency described above is linearly reduced in accordance with the load state detected as the FB terminal voltage at the input terminal FB of the feedback signal. In the conventional circuit of FIG. 4, the output time (Max fsw Blanking) for determining the maximum switching frequency of the voltage controlled oscillator 14 is switched by the FB terminal voltage of the input terminal FB so that the blanking time becomes longer as the load becomes lighter. The switching frequency of the switching element Q1 is reduced by linearly lowering the switching frequency.

Therefore, this quasi-resonant switching power supply control method sets a reference level at the feedback signal input terminal FB and stops the switching operation when the voltage drops below that voltage value, while the reference level is exceeded. Compared with the burst switching type in which the switching operation is continued at a constant frequency, the switching operation can be evenly distributed and the output ripple can be minimized.
Japanese Patent No. 3116338 Japanese Patent Laying-Open No. 2003-33017 (paragraph numbers [0002] to [0012] and FIG. 9)

  Here, the next trigger is supplied to the input terminal ZCD for zero current detection during the period in which the oscillation of the drain voltage Vds continues while being attenuated, and the switching frequency is captured at the bottom of the resonance operation, and the next switching element Q1. There is no problem as long as it can be turned on. However, if the switching power supply can handle a lower standby power load, the switching frequency becomes extremely slow. For example, when the switching power supply becomes several kHz, the resonance operation of the drain voltage Vds is attenuated and stopped. The trigger signal is generated and the switching operation is resumed.

In such a case, since the drain voltage Vds is turned on from a state where it is substantially equal to the input voltage V _IN after the DC conversion, soft switching at the low drain voltage Vds originally intended for the partial resonance power supply is not performed. In both cases, the switching operation at light load is hard switching from a high voltage. Therefore, the quasi-resonant switching power supply has a problem that the efficiency at light load cannot be improved, for example, switching noise increases or switching loss increases as compared with the conventional burst switching system.

  The present invention has been made in view of these points, and an object of the present invention is to provide a switching power supply control circuit that improves the power efficiency when the switching frequency becomes low at light loads.

  Another object of the present invention is to provide a switching power supply control circuit that is configured to reduce the circuit scale by sharing circuit components that function during light loads with circuit components that function during normal operation or startup. It is to be.

  In the present invention, in order to solve the above-described problem, a switching power supply control circuit that supplies a predetermined output power from a secondary winding of the transformer to a load, the switching element being connected to the primary winding of the transformer, In a quasi-resonant switching power supply control circuit that turns on at a timing that becomes the lowest point of the voltage applied to both ends of the switch element and controls the switching operation of the switch element according to a feedback signal from the load, A signal generating means for generating a switching command signal to the switch element, an oscillation means having a fixed cycle for defining an upper limit frequency when the switch element is turned on by the switching command signal, and the switching element is continuously connected by the switching command signal And turn it on for N preset times. Counting means for counting the number of turn-on so as to stop the switching command signal when turned on, and when the load is a light load, the switching element is turned on N times continuously and paused, A switching power supply control circuit configured as described above is provided.

  According to the present invention, even when the switching frequency (period) becomes very slow, hard switching is performed once at first, but soft switching of partial resonance operation is performed from the second time to the preset Nth time. it can. Therefore, it is possible to prevent a decrease in efficiency at a low switching frequency.

  In addition, by setting the number of continuous switching N to an appropriate number according to the application of the switching power supply, optimal switching is achieved with regard to suppressing ripples that are a trade-off relationship in partial resonant power supplies and increasing efficiency at light loads. It can be set to the operating state.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a switching power supply control circuit according to the first embodiment.

  This switching power supply control circuit is configured such that when the load is a light load, the switching element is continuously turned on N times (N is an appropriate positive integer value) and is intermittently operated. It is what. Here, the basic configuration of the quasi-resonant switching power supply control circuit is the same as that of the conventional circuit shown in FIG. Omitted.

  The configuration relating to the frequency linear reduction function at light load is different from the conventional circuit of FIG. 4 in the following points. That is, a pulse counter circuit 23 is added between the one-shot circuit 13 that generates the on-trigger of the switch element Q1 and the comparator 15 that stops the switching operation when the FB terminal voltage drops below 0.5V. This is the point that the switching pulses output from the circuit 19 are counted. Another difference is that a timer circuit 24 having a fixed period (for example, 130 kHz) is used instead of the voltage-controlled oscillator 14 in the conventional circuit of FIG. 4 that changes the switching frequency according to the signal voltage at the feedback signal input terminal FB.

  Therefore, when the feedback signal voltage exceeds 0.5 V, which is the threshold voltage (Vth) of the comparator 15, a reset signal is input to the reset terminal Reset of the pulse counter circuit 23, and Low (Low) is output from the output terminal. While the high-level signal is supplied from the inverter circuit 16 to the clear terminal CLR of the one-shot circuit 13, the one-shot circuit 13 operates continuously (the clear terminal CLR is negative logic).

  On the contrary, when the signal voltage at the feedback signal input terminal FB becomes 0.5 V or less, the reset signal of the pulse counter circuit 23 is released. Assuming that 16 is set as the reference pulse number N in the pulse counter circuit 23, the switching pulse output from the flip-flop circuit 19 is supplied to the clock terminal clk. At that time, the output signal of the pulse counter circuit 23 is switched to the high level, and at this time, the pulse output from the one-shot circuit 13 is stopped.

  FIG. 2 is a timing chart showing the relationship between the feedback signal and the switching operation in the switching power supply control circuit of FIG. When the FB terminal voltage exceeds 0.5V, the output pulse is continuously output. However, when the load is light, the output voltage on the secondary side of the transformer T1 rises and the FB terminal voltage decreases, and the FB terminal When the voltage falls below 0.5 V, 16 switching pulses are output continuously from the output terminal OUT to stop the output pulse. As a result, the output voltage from the secondary side of the transformer T1 rises, and the switching operation is stopped while the feedback signal voltage is reduced to an undershoot level.

  Thereafter, since the output voltage on the secondary side of the transformer T1 decreases, the switching operation is resumed when the FB terminal voltage rises and exceeds 0.5 V, and energy is transferred to the secondary side circuit of the transformer T1. Is supplied. Again, as above, output pulses are continuously output while the FB terminal voltage exceeds 0.5V, and 16 switching pulses are output continuously when the FB terminal voltage falls below 0.5V. To stop. In FIG. 2, the continuous pulse while the FB terminal voltage exceeds 0.5V is omitted. Thus, every time the FB terminal voltage is lowered to 0.5 V or less by the feedback signal, the switching power supply performs an intermittent operation by repeating the cycle of performing the switching operation at least 16 times and then stopping. The feedback signal automatically changes as the FB terminal voltage in accordance with the magnitude of the load supplied from the secondary side circuit of the transformer T1, and the magnitude of the intermittent period is determined. In this case, a certain amount of ripple is generated in the secondary side output, but the ripple and the switching loss are optimally set by appropriately setting the minimum number of switching times according to the reference pulse number N of the pulse counter circuit 23. Can be adjusted.

  In the first embodiment, a one-shot circuit 13 that generates a switching command signal to the switch element Q1, a timer circuit 24 having a fixed cycle that defines an upper limit frequency when the switch element Q1 is turned on by the switching command signal, When the switch element Q1 is continuously turned on by the command signal, the pulse counter circuit 23 counts the number of turn-on so that the switching command signal is stopped at the preset N turn-on, thereby reducing the load. Even when the switching frequency becomes extremely slow due to a load (the time from the switching operation to the next switching operation becomes long), the pulse counter circuit 23 is used to continue the switching frequency in the normal operation state without frequency reduction. Set the number of triggers In order to prevent the switching operation based on the switching command signal from becoming hard switching, for example, 16 consecutive switchings are handled as a minimum unit, and switching is performed with the 16 times as one unit according to the load. did. As a result, even when the switching frequency becomes very low and one cycle (the time from one unit of switching to the next unit of switching) becomes long, the first one is hard switching, but from the second Soft switching of partial resonance operation can be performed up to the 16th time. Therefore, a reduction in efficiency at a low frequency that has occurred in the conventional circuit is prevented. In addition, since the number of continuous switching is set to a fixed number appropriately for the power supply application, it is possible to set the optimum state for ripple and light load efficiency that are in a trade-off relationship with the partial resonance power supply.

(Embodiment 2)
FIG. 3 is a circuit diagram showing a switching power supply control circuit according to the second embodiment.
In the switching power supply control circuit of the second embodiment, the voltage controlled oscillator 25 is connected to the trigger terminal (Enable trg) of the pulse counter circuit 23, and the frequency is controlled from the voltage controlled oscillator 25 according to the magnitude of the FB terminal voltage. The trigger signal is generated to trigger the pulse counter circuit 23. Here, when the load is light, not only is the intermittent operation in which the switching element is continuously turned on N times (N is an appropriate positive integer value) and paused, but also the trigger signal of the voltage controlled oscillator 25 Thus, the operation of the pulse counter circuit 23 is started to control the stop period in the intermittent operation of the switch element. Since the basic configuration of the quasi-resonant switching power supply control circuit is the same as that of the conventional circuit shown in FIG. 4, the same components as those of the conventional circuit are denoted by the same reference numerals, and description thereof is omitted. To do.

  The configuration relating to the frequency linear reduction function at light load is different from the conventional circuit of FIG. 4 in the following points. That is, the switching period is controlled by the timer circuit 24 having a fixed period of 130 kHz, and the voltage control oscillator 25 that is variable frequency controlled by the FB terminal voltage is added to enable the pulse counter circuit 23 from the enable trigger ( Enable trg) signal is output, and the switching operation is continuously performed by the reference pulse number N set in the pulse counter circuit 23.

  Here, if the energy sent to the secondary circuit is excessive, the FB terminal voltage is lowered and the oscillation frequency of the voltage controlled oscillator 25 is lowered. Conversely, if the energy is insufficient, the oscillation frequency is increased. Since the voltage controlled oscillator 25 operates, the voltage generated in the secondary circuit can be stabilized. Further, the pseudo-resonance operation can be maintained by treating the switching operation that is continuous for the number of times set by the pulse counter circuit 23 as one unit.

  Further, since the function required for the voltage controlled oscillator 25 is merely to issue an enable trigger signal, a charge / discharge circuit including a current source whose current value varies depending on the built-in capacitance of the integrated circuit IC and the magnitude of the FB terminal voltage, and a counter It is also possible to configure the voltage controlled oscillator 25 with a circuit. The feedback signal input terminal FB is set as a VCO voltage to the voltage controlled oscillator 25, and this is input to the current source of the charge / discharge circuit so that the oscillation frequency is first made analog variable from about 100 kHz to about 1 kHz, and then the counter is used. If the frequency is divided down to about 1/100, the trigger signal frequency can be set in the range of 1 kHz to 10 Hz.

  Further, by inputting the output of the comparator 15 to the NAND circuit 26, when the energy supply to the secondary side is excessive even when the oscillation frequency is lowered to the minimum, the FB terminal voltage is set to a predetermined level (here, When the voltage drops below 0.5V), the output of the NAND circuit 26 is inverted and fixed to high, and the switching operation is forcibly stopped. Therefore, when there is no secondary load, etc. In addition, the secondary circuit voltage can be prevented from rising.

  Note that the control circuit 10 of the switching power supply described above has an overload protection function similar to that of the conventional circuit as protection when the load on the secondary side is too heavy. This is because a state in which the FB terminal voltage has increased to 3.3 V or more (Overload) is detected by the comparator 21 as an overload, and when this state continues for 100 ms or more, the timer circuit 22 causes the switching command signal at the output terminal OUT to be Is to stop. At this time, the delay time of 100 ms is set because the same state occurs when the power supply is started, and the start-up state is completed until the stabilization capacitor is charged, and usually ends within 100 ms. This is for distinguishing between such an activated state and an overloaded state.

  After the time of 100 ms elapses, the switching operation is temporarily stopped. In general, when restarting a stopped switching operation, a restart recommendation is made after waiting for about 800 ms. This is because, assuming a secondary-side short circuit, if the starting cycle is too short, the heat generation state becomes long and damages the switch element.

  The timer circuit 22 that realizes such an overload protection function requires an oscillator and a counter having a long period for counting time such as 100 ms and 800 ms. Therefore, if these oscillators and counters are configured to share the oscillator (charge / discharge circuit) and frequency divider (counter) of the voltage controlled oscillator 25 shown in FIG. 3, the increase in circuit scale can be suppressed. it can. For this purpose, when the FB terminal voltage is below a certain level (for example, 1V), the voltage controlled oscillator 25 and the pulse counter circuit 23 are used as circuit components at a light load, and when the voltage is above a certain level (for example, 3.3V). In this case, the voltage controlled oscillator 25 may be used as a component of the overload protection circuit by switching the setting values of the clock and the count number.

  Further, the voltage controlled oscillator 25 is used in common with the soft start circuit 18, thereby having the same effect that suppresses an increase in circuit scale. That is, the soft start circuit 18 is a function that limits the turn-on period of the switch element to prevent the pulse width from suddenly reaching the maximum state when the power is turned on, and gradually widens the turn-on period. In terms of time, it is necessary to generate a pulse having a rising waveform of 1 ms or more. Therefore, if the voltage controlled oscillator 25 is configured to output an oscillation pulse having a rising waveform with a slow cycle and input it to the PWM comparator, the two circuits can be shared.

1 is a circuit diagram showing a switching power supply control circuit according to a first embodiment. 2 is a timing chart showing a relationship between a feedback signal and a switching operation in the switching power supply control circuit of FIG. 1. FIG. 6 is a circuit diagram showing a switching power supply control circuit according to a second embodiment. It is a block diagram which shows the control circuit of the conventional quasi-resonant type switching power supply. It is a block diagram which shows an example of an AC / DC switching power supply circuit. It is a characteristic view which shows the relationship between switching frequency (fsw) and output electric power (Po). It is a timing chart which shows the steady operation in the control circuit of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Control circuit 11 Bottom detection circuit 12, 20 AND circuit 13 One-shot circuit 14 Voltage control oscillator 15 Comparator 16 Inverter circuit 17 Current comparator 18 Soft start circuit 19 Flip-flop circuit 21 Comparator for overload detection (Overload) 22, 24 Timer Circuit 23 Pulse counter circuit 25 Voltage controlled oscillator 26 NAND circuit Q1 Switch element IC Integrated circuit ZCD Zero current detection input terminal FB Feedback signal input terminal IS Current sense signal input terminal OUT Output terminal T1 Transformer

Claims (4)

A switching power supply control circuit, wherein a switching element is connected to a primary winding of a transformer and supplies a predetermined output power from a secondary winding of the transformer to a load, and a voltage applied to both ends of the switching element is the lowest In a quasi-resonant switching power supply control circuit that turns on at a point timing and controls the switching operation of the switch element according to a feedback signal from the load,
Signal generating means for generating a switching command signal to the switch element;
A fixed-cycle oscillating means for defining an upper limit frequency when the switch element is turned on by the switching command signal;
Counting means for counting the number of turn-on so as to stop the switching command signal at a preset N turn-on when the switch element is continuously turned on by the switching command signal;
With
When the load is a light load, the switching power supply control circuit is configured to perform an intermittent operation in which the switch element is continuously turned on N times and stopped.   The overload protection circuit that determines the timing until the switching operation of the switch element is stopped and the timing of restart when the load is not a light load is configured by sharing the counting means. The switching power supply control circuit according to 1. The counting means includes a voltage controlled oscillator that generates a trigger signal at a timing according to the magnitude of the signal voltage of the feedback signal, and a pulse counter connected to the voltage controlled oscillator,
2. The switching power supply control according to claim 1, wherein when the load is a light load, a stop period in the intermittent operation of the switch element is controlled by the pulse counter which starts counting by the voltage controlled oscillator. circuit. 4. The switching according to claim 3, wherein a soft start circuit for generating a soft start signal for limiting a turn-on period of the switch element when the switching power supply is started is configured by sharing the voltage controlled oscillator. Power supply control circuit.

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