JP4772878B2 - Game machine - Google Patents

Description

  The present invention is capable of playing a predetermined game using a game medium, and a game machine such as a pachinko game machine or a slot machine that pays out a prize game medium as a prize based on the fact that a payout condition is established by the game. About.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. In other words, or a condition for winning a prize ball is easily established.

  In a pachinko gaming machine, a combination of a predetermined display mode with a display result of a variable display unit that displays a special symbol is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, in the variable display device, the symbols other than the symbol that becomes the final stop symbol (for example, the middle symbol of the left and right middle symbols) are stopped, swung, and enlarged / reduced in a state in which the symbols continuously match the specific display mode for a predetermined time. Or, the possibility of big hits continues before the final result is displayed due to the deformed state, multiple symbols changing synchronously with the same symbol, or the position of the display symbol changing. An effect that is performed in a state where these are in progress (hereinafter, these states are referred to as reach states) is referred to as reach effect. A variable display including a reach effect is referred to as a reach variable display. In the reach state, the interest of the game is enhanced by making the variation pattern different from the variation pattern in the normal state. Then, when the display result of the symbols variably displayed on the variable display device does not satisfy the condition for reaching the reach state, the state is “missed” and the variable display state is terminated. A player plays a game while enjoying how to generate a big hit.

  The game progress in the gaming machine is controlled by game control means such as a microcomputer. When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game is performed by the game control means mounted on the main board. Since it is controlled, the number of winning balls based on winning is determined by the game control means and transmitted to the payout control board. On the other hand, the rental of game media is irrelevant to the progress of the game, and is generally controlled by the payout control means without going through the game control means.

  As described above, the gaming machine is equipped with control means in addition to the game control means. The game control means for controlling the progress of the game transmits a control signal indicating an operation instruction or the like according to the game situation to each control means mounted on another control board other than the main board. Hereinafter, the game control means and other control means may be referred to as electrical component control means, and the board on which the electrical component control means is mounted may be referred to as an electrical component control board.

  As described above, the number of winning balls based on winning is determined by the game control means, and a control signal indicating the number of winning balls is transmitted to the payout control means. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control signal from the game control means.

  However, since the communication of the control signal indicating the number of prize balls exchanged between the game control means and the payout control means was executed regardless of the completion of the payout, the number based on winning due to the signal being missed or misrecognized. May not be paid out correctly. Therefore, there is a risk that the game value obtained by the player will be lost.

  Accordingly, an object of the present invention is to provide a gaming machine capable of transmitting and receiving control signals in a communication mode in which game media is paid out accurately.

The gaming machine according to the present invention can play a predetermined game using a game medium, and can pay out a prize game medium as a prize based on the winning of the game medium in a prize area in the game area. And a variable display unit that variably displays a plurality of types of identification information that can be distinguished from each other, and is advantageous to the player when the display result of the identification information in the variable display unit is a predetermined specific display result. A game machine that controls to a specific gaming state, having a variation data storage unit that stores variation data generated when the control is performed, and a game control unit that controls the progress of the game (for example, a game control including a CPU 56) means, and game control means 561) shown in FIG. 43, which can power supply to the gaming machine to the stored contents of the variation data storage means be stopped is maintained for a predetermined period of time serial The content holding unit, by detecting a voltage drop of a predetermined power supply voltage, and a power supply monitoring means for outputting a detection signal upon detecting the occurrence of power failure, an operation means for outputting an operation signal in accordance with the operation, the prize game A payout means (for example, a ball payout device 97, a payout means 97a shown in FIG. 43) for paying out the medium, a payout control means (for example, a payout control means including a payout control CPU 371), a payout shown in FIG. A control means 371a), a winning detection means for detecting that a game medium has been won in the winning area and outputting a winning detection signal; and detecting a prize game medium paid out by the paying means and outputting a payout detection signal. game medium detection (e.g. payout count switch 301, game medium detecting unit 501 shown in FIG. 43) and means, the game control means, the input of the detection signal from the power supply monitoring means Then, when the power supply stop process for saving the storage contents of the fluctuation data storage means is executed and the operation signal from the operation means is not input when the power supply is started, the fluctuation data Execute state return control to restore the control state to the state when the power supply stop process was started based on the storage content stored in the fluctuation data storage unit when the storage content of the storage unit was stored, When an operation signal is input from the operation means, the main contents of the variable data storage means are initialized, a predetermined process is repeatedly executed, and a timer interrupt generated every predetermined time is selected. A specific game state determination for executing an interrupt process activated by interrupting the process and updating a specific game state determination value for determining whether or not to enter a specific game state in the interrupt process Numerical value updating process and an initial value setting process for setting an initial value numerical value as an initial value for updating the specific gaming state determining numerical value, and updating the initial value numerical value as a predetermined process in the main process Execute the initial value update process, set the interrupt processing by the timer interrupt to be disabled before starting the initial value update process in the main process, and set the timer interrupt after the initial value update process is completed. A payout command signal (for example, the number of payouts) that can specify the number of payouts of the prize game medium to the payout control means based on the fact that the payout detection means outputs a winning detection signal. signals and REQ signal, and outputs a payout command signal) shown in FIG. 43, the payout control means payout process of prize game medium by controlling the dispensing means based on the payout command signal (e.g. FIG. 36 and Prize balls control process shown in 37, then executes a payout process) in step S757a shown in FIG. 43, payout detection signal from the game medium detection means is input to the payout control means, the payout control means, the game medium detection means The number-of-payout determination signal (for example, CPU 371 for payout control) is determined by monitoring the input state of the payout detection signal and determining whether or not the prize game medium having the number of payouts specified by the payout command signal has been paid out (eg, step S547). The payout control means includes the payout number determination means 371b) shown in FIG. 43, and the payout processing is completed when it is determined by the payout number determination means that the number of payout game media specified by the payout command signal has been paid out. A payout completion signal (for example, a prize ball payout completion signal output by lowering the BUSY signal from a high level to a low level) indicating to the game control means Forces payout completion signal output unit (e.g., dispensing control means including a dispensing control CPU 371, a payout completion signal transmitter 371c shown in FIG. 43) and a gaming control means is inputted operation signal from the operation means It is characterized by determining whether there is a detection determination period shorter than the winning detection determination period in which the winning detection signal output from the winning detection means is determined to be valid .

According to the first aspect of the invention, the game control means, and outputting a possible payout command signal specifying the payout of the prize game media against payout control means based on the satisfied payout condition, payout control means, Based on the payout command signal, the payout means is controlled to execute payout processing of the prize game medium. The payout detection signal from the game medium detection means is input to the payout control means, and the payout control means is sent from the game medium detection means. The payout detection signal is used to monitor the input state of the payout detection signal to determine whether or not the number of payout game media specified by the payout command signal has been paid out, and the payout command signal is specified by the payout number determination means. characterized in including that a payout completion signal output means for outputting a payout completion signal indicating that the payout process is completed with respect to the game control means if has been paid out number of the prize game media is determined to have been paid out Toss Because, an effect that possibility of recognition errors may occur related to the payout between game control means and the dispensing control means is reduced.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is a disassembled perspective view which shows the structural example of a ball dispensing apparatus. It is a front view which shows the exposed part of the power supply board installed in the game board. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a power supply board. It is a block diagram which shows the example of 1 structure around CPU. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows an example of the relationship between a backup flag and whether to perform a game state restoration process. It is a flowchart which shows a game state restoration process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows an unmaskable interruption process (process at the time of an electric power supply stop). It is a flowchart which shows an unmaskable interruption process (process at the time of an electric power supply stop). It is a timing diagram which shows the mode of the power supply fall and NMI signal at the time of the electric power supply stop to a game machine. It is explanatory drawing which shows the example of formation of the switch timer in RAM. It is a flowchart which shows an example of a switch process. It is a flowchart which shows an example of a switch check process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows an example of a prize ball process. It is a flowchart which shows a switch-on check process. It is explanatory drawing which shows the structural example of an input determination value table. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a flowchart which shows an example of a prize ball payout completion confirmation process. It is a flowchart which shows the main process which CPU in a payout control board performs. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows the example of 1 structure of RAM in the payout control means. It is a flowchart which shows the example of a switch process. It is a flowchart which shows the example of a payment prohibition state setting process. It is a flowchart which shows the example of a prepaid card unit control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a prize ball control process. It is a flowchart which shows the example of a prize ball control process. It is a timing chart which shows the example of the output state of a control signal. It is a timing chart which shows the example of the output state of a control signal. It is a timing chart which shows the example of the output state of a control signal. It is a timing chart which shows the example of the output state of a control signal. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a block diagram which shows the structure of a gaming machine.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to, for example, an image-type gaming machine or a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Every time there is a valid start prize, the start storage display area is changed by one (for example, the display color is changed from blue display to red display). Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, the symbol display area and the start memory display area are provided separately, so that the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. In this case, the start memory number display may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9, but a display (special symbol start memory display) for displaying the start memory number is provided separately from the variable display device 9. It may be.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The gaming board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of the game balls to the winning holes 29, 30, 33 is detected by winning hole switches 29a, 30a, 33a, 39a, respectively. The Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning port 14 that accepts game media and allows winnings, and the big winning port also constitute a winning area. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided on the outer periphery of the game area 7. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on in the vicinity of the top frame lamp 28a when the supply ball is cut. A cut lamp 52 is provided. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 includes a use indicator lamp 151 that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator 153 that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp 154 indicating that a card is inserted into the unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the card.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When the game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, a game control board (main board) 31 on which a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control microcomputer, and the like are mounted. Is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decoration LEDs provided on the game board 6, normal symbol start memory display 41, decoration lamp 25, top frame lamp 28a provided on the frame side, left frame lamp 28b, right frame lamp 28c, prize ball There are also provided a lamp control board 35 on which lamp control means for controlling the lighting of the lamp 51 and the bulb break lamp 52 and a sound control board 70 on which sound control means for controlling sound generation from the speaker 27 are mounted. In addition, a power supply board 910 and a launch control board 91 on which a power supply circuit for generating DC30V, DC21V, DC12V and DC5V is mounted are provided.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board (information output board) 34 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG. 4, reach the ball payout device covered with the prize ball case 40A through the curve rod 186. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  A large number of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full, and finally game balls are paid out after the game balls reach the contact port 45. The game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the drive of the launching device also stops.

  As shown in FIG. 4, a ball removal passage 191 is formed on the side of the ball payout device from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is an exploded perspective view showing a configuration example of the ball dispensing device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, 142 as the prize ball case 40A. The upper portions of the cases 140 and 141 are provided with holes 170 and 171 communicating with the lower ball passage of the ball break switch 187, and the game balls flow into the ball dispensing device 97 through the holes 170 and 171.

  The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a drive source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted to the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

  In this embodiment, the ball passage 293 is commonly used both when paying out a prize ball and lending a ball. Accordingly, the game ball flows down through the ball passage 293 both when the prize ball is paid out and when the ball is lent. The payout motor 289 is controlled by a payout control CPU mounted on the payout control board 37. Further, the payout control CPU controls the payout motor 289 in accordance with a command from the game control CPU mounted on the main board 31.

  A payout sensor (payout count switch) 301 for detecting a game ball paid out by the ball payout device is provided below the flow path of the game balls. The payout count switch 301 detects both game balls paid out as prize balls and game balls paid out as rental balls. That is, in this example, the paid-out prize balls and the paid-out lending balls are detected by a common payout sensor. The detection signal of the payout count switch 301 is input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on these detection signals. In this embodiment, the detection signal of the payout count switch 301 is not input to the CPU of the main board 31. Power is supplied from the power supply board 910 to the payout count switch 301 via the payout control board 37. A plurality of payout sensors may be provided.

  A protrusion 295 that forms a payout motor position sensor is formed on the periphery of the gear 291. The protrusion 295 transmits or blocks light from the light emitter (not shown) to the light receiving part (not shown) of the payout motor position sensor as the gear 291 rotates, that is, the payout motor 289 rotates. Or The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

  Further, the ball payout device may be configured to perform both the prize ball payout and the ball lending, but the ball payout device that performs the prize ball payout and the ball payout device that performs the ball lending are provided separately. Also good. Further, for example, the sprocket rotation direction may be changed to separate the award ball payout and the ball lending, or the ball payout device having any structure other than the ball payout device 97 illustrated in the present embodiment. Even if is used, the present invention can be applied.

  FIG. 6 is a front view showing an exposed portion of the power supply board 910 installed on the game board 6. As shown in FIG. 6, most of the power supply substrate 910 overlaps with the main substrate 31, but there is an exposed portion that is exposed to the outside without overlapping with the main substrate 31. The exposed portion includes a power switch 914 as a power supply permission means for executing or shutting off power supply to each electrical component control board and each electrical component of the gaming machine 1, and storage contents stored in the main board 31. A clear switch 921 is provided as an operation means for clearing backup data stored in a means (for example, a backup RAM capable of retaining the contents even when power supply is stopped). In this manner, since the power switch 914 and the clear switch 921 are arranged close to each other, the operation of the clear switch 921 related to starting to supply power to the gaming machine by the power switch 914 is facilitated.

  FIG. 7 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 7 also shows the payout control board 37 and the effect control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 29a, 30a, 33a, 39a and a clear A basic circuit includes a switch circuit 58 that supplies a signal from the switch 921 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball apparatus 15, a solenoid 21 that opens and closes the opening and closing plate 20, and a solenoid 21A that switches a path in the special winning opening. A solenoid circuit 59 that is driven in accordance with a command from 53 is mounted.

  Although not shown in FIG. 7, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name is not limited as long as it is a means capable of detecting a game ball. In particular, each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a that perform winning detection is also a winning detection means. Note that the winning detection means may be configured to collectively detect the respective game balls that have won separately a plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is paid out, a game ball entering the passing gate becomes a win, and a switch (for example, a switch provided in the passing gate) The gate switch 32a) becomes a winning detection means.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (means for storing variation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  A RAM 55 (may be a CPU built-in RAM) 55 is a backup RAM that is partially or entirely backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the launch control board 91 is controlled so that the game ball is launched at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the effect control means mounted on the effect control board 80 controls the display of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board, and on the frame side. Display control of the provided top frame lamp 28a, left frame lamp 28b, and right frame lamp 28c is performed. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays special symbols and the normal symbol display 10 that variably displays normal symbols.

  FIG. 8 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full switch 48 is input to the I / O port 372 b of the payout control board 37 via the relay board 72. The detection signal from the ball break switch 187 is also input to the I / O port 372 b of the payout control board 37 via the relay board 72.

  The payout control CPU 371 of the payout control board 37 pays off the ball when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop processing.

  When there is a win, the output circuit 67 of the main board 31 outputs a REQ signal (prize ball request signal) for making a payout request for a prize ball and a payout number signal indicating the number of prize balls to be paid out. The payout number signal is composed of 4-bit data and is output by four signal lines. The payout number signal is input to the I / O port 372a via the input circuit 373A. When a REQ signal and a payout number signal are input from the I / O port 372a, the payout control CPU 371 performs control for driving the ball payout device 97 to pay out the number of game balls indicated by the payout number signal. A power supply confirmation signal is also output from the output circuit 67 of the main board 31. In addition, when the payout control board 37 is executing the payout process of the winning ball, the main board 31 outputs a BUSY signal indicating that the payout process is being output via the output circuit 373B of the payout control board 37. (Prize ball paying out signal) is input. The output form of each signal will be described in detail later. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  The payout control CPU 371 receives, via the output port 372c, a prize ball payout number signal indicating the number of payout balls and a ball lending number signal indicating the number of payout balls, for the terminal board (frame external terminal board and board). Including the external terminal board). A door opening information switch 161 is connected to the terminal board 160 (frame external terminal board). In addition, an error signal is output to the error display LED 374 via the output port 372d. Further, a signal for instructing lighting / extinguishing of the lamp is output to the winning ball lamp 51 and the ball-out lamp 52 via the output port 372f. A detection signal from the error release switch 375 for releasing the error state is input to the input port 372d of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a detection signal from the payout motor position sensor for detecting the rotational position of the payout count switch 301 and the payout motor 289 is input to the input port 372 b of the payout control board 37 via the relay board 72. The payout count switch 301 is provided in the payout mechanism portion of the ball payout device 97, and detects the game balls (prize balls and rental balls) actually paid out. A drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

  The card unit 50 is equipped with a card unit control microcomputer. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The interface board 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372b and the output port 372e. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is exchanged between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in the AC 24V power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. I'm trying not to be.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 9 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the effect control board 80, and the payout control board 37, and generates voltages used by the electric component control boards and the mechanical parts in the gaming machine. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. Further, a capacitor 916 serving as a backup power source, that is, a memory holding means, is charged from a line of power source for driving DC + 5V, that is, an IC on each substrate. Note that VSL is generated by rectifying and boosting AC24V with a rectifier element in the rectifier circuit 912. VSL is a solenoid driving power source.

  The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 has one or a plurality of converter ICs 920 (only one is shown in FIG. 9), generates + 21V, + 12V, and + 5V based on VSL and outputs the generated voltages to the connector 915. A relatively large capacitor 923 is connected to the input side of the converter IC 920. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as + 30V, + 12V, + 5V, etc., decreases relatively slowly. A relatively large capacitor 924 is also connected to the input side of the connector 915. Therefore, the + 30V DC voltage output to the connector 915 is more gradually reduced than the other DC voltages. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board. FIG. 9 shows one connector 915 as a representative, but the connector is provided for each electrical component control board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 has a storage state with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is stopped (a RAM that is backed up by power, that is, a backup storage unit that can be in a storage content holding state even when the power supply is stopped) It becomes a backup power supply that supplies power so that it can be maintained. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line. In this embodiment, + 5V for backup is supplied to the main board 31.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time. Instead of the capacitors 923 and 924, a battery that can be charged from a + 30V power source may be used. When a battery is used instead of the capacitor 923, a rechargeable battery that can supply power to the payout count switch 301 is used for a period longer than the payout confirmation period described later. In addition, said battery does not need to have a charging function, For example, batteries, such as a nickel cadmium battery, an alkaline battery, and a manganese battery, can also be used.

  As shown in FIG. 9, a pushbutton structured clear switch 921 is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 via the connector 915. If the clear switch 921 is not pressed, a high level (off state) signal is output. In this embodiment, when the clear signal in the on state is output, the operation signal is output from the clear switch 921 as the operation means. Note that the clear switch 921 may have a configuration other than the push button structure.

  In this embodiment, since the clear switch 921 is mounted on the power supply board 910, even if the power board 910 is used as it is for the replaced game board 6 in the case of replacement of the game board 6 or the like, In the game board 6, the game state restoration process or the like can be executed as it is. That is, the power supply board 910 can be reused. Note that the clear switch 921 may be mounted not on the power supply board 910 but on another board such as a switch board.

  FIG. 10 is a block diagram illustrating a configuration example around the CPU 56 in the main board 31. As shown in FIG. 10, a power monitoring IC 902 as a power monitoring circuit is mounted on the main board 31. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage from the power supply board 910 and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output (specifically, it is set to the low level) because the power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used.

  A power-off signal from the power monitoring IC 902 is input to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. As described above, the power supply monitoring circuit is a circuit that detects a power supply voltage drop by monitoring the voltage of any of the various DC power supplies used by the gaming machine. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value falls below a predetermined value, a low-level power cut-off signal is generated. VSL is the largest DC voltage in the gaming machine, and is +30 V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt process.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed.

  Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. In other words, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. When the voltage of the + 12V power supply decreases, the switch output becomes on. However, if the + 30V power supply voltage, which decreases faster than + 12V, is monitored and the stop of the power supply is recognized, the power supply is turned on before the switch output shows the on state. It is possible to enter a state of waiting for recovery and not detect switch output.

  In this embodiment, a system reset circuit 65 is mounted on the main board 31 as shown in FIG. A reset signal from the system reset circuit 65 is input to a reset terminal (reset signal input unit) of the CPU 56.

  The reset IC 651 in the system reset circuit 65 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor when the power is turned on, and sets the output to the high level when the predetermined time elapses. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the same as the power supply voltage monitored by the power supply monitoring circuit, and the voltage value is lower than a predetermined value (the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). When the value is less than or equal to, the output is set to low level. Therefore, the CPU 56 performs a predetermined power supply stop process in response to a power-off signal from the power supply monitoring circuit, and then resets the system (that is, returns to the initial state of the system).

  As shown in FIG. 10, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the power supply monitoring circuit (power supply monitoring IC 902) (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to low level is set to + 9V. In such a configuration, since the power supply monitoring circuit and the system reset circuit 65 monitor the voltage of the same power supply VSL, the timing at which the voltage monitoring circuit outputs a power-off signal and the system reset circuit 65 reset the system. It is possible to reliably set the difference in timing for outputting the signal within a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop process in response to the power-off signal from the power supply monitoring circuit until the completion of the power supply stop process. The power supply voltage monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM 55 is backed up by the backup power source supplied from the power supply board 910, and the content remains even if power supply to the gaming machine is stopped. Saved. When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the gaming state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

  In the configuration shown in FIG. 10, two reset signals (low level signals) are given to the reset terminal of the CPU 56 when the power is turned on, but the reset is reliably released even if the reset signal rises only once. When the CPU is used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  Next, the operation of the gaming machine will be described. FIG. 11 is a flowchart showing the main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts main processing after step S1. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set in an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. In this example, as shown in FIG. 12, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, there is no backup (OFF). State).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped (step S10). ). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  As described above, when “backup exists” is not confirmed according to the status of the backup flag, the initialization process described later is performed without performing the gaming state recovery process described later, and therefore there is no backup data. However, it is possible to prevent the gaming state restoration process from being executed, and the control state can be returned to the initial state by the initialization process.

  In addition, when the check result using the check data is not normal, the initialization process described later is performed without performing the gaming state recovery process described later, so that the contents differ from those at the time of stopping the power supply. It is possible to prevent the gaming state recovery process from being executed based on the backup data that has been made, and the control state can be returned to the initial state by the initialization process.

  The CPU 56 uses the backup flag and check data such as a checksum to check whether data in the backup RAM area is stored. That is, when the power supply is restored, a plurality of recovery conditions for determining whether or not to restore the control state before the power supply is stopped (in this example, the backup flag was normally stored) When all of the checksums are normal), a recovery process for recovering the control state based on the stored contents stored in the variable data storage means is executed, and at least one of the plurality of recovery conditions When the condition is not satisfied, an initialization process for initializing the storage contents of the variation data storage means can be executed. By using a plurality of recovery conditions, the gaming state can be accurately returned to the state when the power supply is stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. If an operation signal is output from the operation means, initialization processing is executed regardless of a plurality of recovery conditions (step S7). In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the state recovery process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S11). Note that the entire area of the RAM may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total winning ball number storage buffer, a special symbol process flag, a winning ball flag, a ball running flag Then, a work area setting process for setting an initial value to a flag for selectively performing processing according to the control state such as a payout stop flag is performed (step S12).

  Further, the CPU 56 executes a process of transmitting an initialization command for initializing the effect control board 80 to the effect control board 80 (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S15). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  When the execution of the initialization process (steps S11 to S15) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process described later, and thus conflicts with the process in the timer interrupt process. This is to avoid that. That is, if the timer interrupt is generated during the process of step S17 and the counter value for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  FIG. 13 is a flowchart illustrating an example of the game state restoration process. In the game state restoration process, the CPU 56 first performs a stack pointer restoration process (step S80). The value of the stack pointer is saved in a predetermined RAM area (stack pointer save buffer in the work area backed up by power) in the power supply stop process described in detail later. Therefore, in step S81, the RAM area value is set in the stack pointer to return. Note that the register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

  Next, the CPU 56 transmits an effect control command for restoring the display state according to the display state of the special symbol in the variable display device 9 when the power supply is stopped (step S84).

  Thereafter, the CPU 56 clears the backup flag (step S88), that is, resets a flag indicating that a predetermined storage protection process has been executed when the previous power supply was stopped. Therefore, unnecessary information can be prevented from remaining after the control state is restored. Also, the saved values of various registers are read from the stack area and set in various registers (IX register, HL register, DE register, BC register) (step S89). That is, register restoration processing is performed. Each time each register is restored, the value of the stack pointer is decreased. In other words, the value of the stack pointer is updated to point to the previous address in the stack area. If the parity flag is not turned on, an interrupt permission state is set (steps S90 and S91). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S92).

  Then, the RET instruction is executed. When the RET instruction is executed, the CPU 56 realizes a program return operation by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state restoration process. This is because the stack pointer restoration process is performed in step S81, and after the register restoration process is completed in step S89, the stack pointer indicating the stack area is executed when the power supply stop process by the NMI is started. Indicates the area where the program address is saved. That is, the return address stored in the stack area pointed to by the returned stack pointer is the address where the NMI occurred when the power supply was last stopped in the program. Therefore, the next RET command in step S92 returns to the address where the NMI occurred when the power supply was stopped. That is, in this embodiment, recovery control is executed based on the address data (program address data) saved in the stack area.

  When the timer interrupt occurs, the CPU 56 performs the register saving process (step S20), and then executes the game control process of steps S21 to S32 shown in FIG. In the game control process, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a through the switch circuit 58. These state determinations are performed (switch processing: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S28). Further, a process for setting the effect control command related to the normal symbol in a predetermined area of the RAM 55 and sending the effect control command is performed (normal symbol command control process: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21, and 21A in response to a drive command in order to open or close the variable winning ball device 15 or the opening / closing plate 20, or to switch the game ball passage in the special winning opening. To do.

  Then, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals from the winning opening switches 29a, 30a, 33a, 39a (step S32). Specifically, a control signal such as a payout number signal indicating the number of winning balls is output to the payout control board 37 in response to detection of winning based on the winning opening switch 29a, 30a, 33a, 39a being turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a control signal such as a payout number signal indicating the number of prize balls. Thereafter, the contents of the register are restored (step S33), and the interrupt permission state is set (step S34).

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 15 and FIG. 16 are flowcharts showing a processing example of a non-maskable interrupt process (power supply stop process) executed in response to the power-off signal from the power supply board 910. The non-maskable interrupt process means a process that cannot be prohibited from being interrupted. When a non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 sets the address of the program executed when the non-maskable interrupt occurs (specifically, the next address after completion of execution) as a stack pointer. Is saved in the stack area pointed to by and the value of the stack pointer is increased. That is, the stack pointer value is updated to point to the next address in the stack area.

  In the power supply stop process, the CPU 56 saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Further, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the backup RAM area (steps S454 to S458). When the power is restored, the register contents are restored based on the saved contents, and the interrupt permission / prohibition state is internally set according to the contents of the parity flag.

  Next, the CPU 56 sets clear data (00) in an appropriate register (step S459), and sets the number of processes (in this example, “7”) in another register (step S460). Further, the address of the output port 0 is set in the IO pointer (step S461). Another register is used as the IO pointer.

  Then, clear data is set at the address indicated by the IO pointer (step S462), the value of the IO pointer is incremented by 1 (step S463), and the value of the processing number is subtracted by 1 (step S464). The processes of steps S462 to S464 are repeated until the value of the number of processes becomes 0 (step S465). As a result, clear data is set for all output ports 0-6. In this example, “1” is in the on state and “00”, which is the clear data, is set in each output port, so all the output ports are in the off state.

  As described above, since each output port is turned off, it is reliably prevented that a situation inconsistent with the saved gaming state occurs. In other words, in a gaming machine having a variable winning ball device such as a pachinko gaming machine, the position of the variable winning hole in the variable winning ball device and the installation position of the winning port switch for detecting a winning are determined due to mounting. It must be separated to some extent. If the output port, in particular the output port that outputs the signal for opening the variable winning ball device, is not turned off immediately, the power supply will stop when the power supply is stopped, even though the variable prize opening has been won. There may be a situation in which the execution of the process is started and the winning opening switch is not detected. In that case, it is not stored that there was a winning in the variable winning opening. In other words, the gaming state that is actually occurring (the winning has been) does not match the saved gaming state. However, in this embodiment, since the output port is cleared and the variable winning ball device is closed, it is reliably prevented that a situation inconsistent with the saved gaming state occurs.

  In addition, since the output port can be cleared in the process of stopping power supply that is executed before the electric component can be driven, before the electric component can be driven. Each electric component controlled by the game control means can be put into an appropriate operation stop state. For example, the operation of the electrical component is stopped after the operation of the electrical component is stopped, such as closing the open large winning opening and closing the open variable winning ball device 15. be able to. Therefore, it is possible to wait for the power supply to be restored in an appropriate stop state.

  Further, since the electric components are stopped during the power supply stop process, power is not consumed to drive the electric components, and the current used for signal output from the output port Is cut off, so that power consumption can be suppressed although it is in a small amount.

  When all the output ports are turned off (step S465), the CPU 56 stores the backup specified value (“55H” in this example) in the backup flag (step S487). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S488 to S497). That is, first, the clear data (00) is set in the checksum data area (step S488), and the checksum calculation start address is set in the pointer (step S489). Also, the number of checksum calculations is set (step S490).

  Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S491). The calculation result is stored in the checksum data area (step S492), the pointer value is incremented by 1 (step S493), and the value of the checksum calculation count is decremented by 1 (step S494). The processes in steps S491 to S494 are repeated until the value of the checksum calculation count becomes 0 (step S495).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S496). Then, the inverted data is stored in the checksum data area (step S497). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S498). Thereafter, the built-in RAM 55 cannot be accessed.

  When the access prohibition value is set in the RAM access register, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  In this embodiment, all RAM areas in which data used in the game control process are stored are backed up. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the gaming state.

  In this embodiment, the power supply stop process is executed according to the NMI. However, the power supply stop signal is connected to the maskable terminal of the CPU 56 and the power supply stop process is executed by the maskable interrupt process. May be. Alternatively, a power-off signal may be input to the input port and the power supply stop process may be executed according to the input port check result.

  In this embodiment, the register saving process is performed at the beginning of the process activated in response to the power-off signal. However, after the switch detection process is executed, that is, the backup flag is set and the checksum is calculated. Register saving processing can be performed before processing. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Further, even if some registers are used, register saving processing can be performed on the unused registers before setting the backup flag and calculating the checksum.

  FIG. 17 is a timing diagram showing the state of the power supply voltage drop and the NMI signal (= power supply cut-off signal: power supply stop signal) when power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of the monitoring voltage (the voltage input to the power supply monitoring IC 902) in the VSL that is the highest DC power supply voltage gradually decreases. In this example, when the voltage drops to +22 V, a power cut-off signal is output from the power monitoring IC 902 mounted on the main board 31 (becomes a low level).

  The power-off signal is input to the NMI terminal of the CPU 56. The CPU 56 executes a predetermined power supply stop process by the NMI process.

  When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the system reset circuit 65 mounted on the main board 31 becomes low level, and the CPU 56 enters a system reset state. Note that the CPU 56 has completed the power supply stop process before entering the system reset state.

  When the voltage value of VSL is further decreased to be lower than a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot be operated on each substrate. However, at least the main board 31 executes the power supply stop process, and the CPU 56 is in a system reset state.

  As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, and the voltage drops when the voltage of the power supply falls below a predetermined value. Generates a signal (power failure detection signal). As shown in FIG. 17, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stop process.

  Here, the power supply monitoring circuit monitors the voltage branched from the highest power supply VSL among the DC voltages used in the gaming machine, but the timing of generating the power-off signal operates with the IC drive voltage. The monitoring target voltage may not be the highest voltage of the power supply VSL as long as the operation time for the electrical component control means to perform the predetermined power supply stop process is ensured. In other words, if at least a voltage higher than the driving voltage of the IC or solenoid is monitored, the power-off signal is generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stop process is secured. be able to. In this example, a voltage branched from the power source VSL is used as a drive voltage for a solenoid or the like. Unlike a line to which a monitoring target voltage is supplied, a large-capacitance capacitor 924 is provided on a line for supplying a drive voltage to a solenoid or the like. Since it is connected, the power-off signal can be generated at a timing when a predetermined period during which the supply of the drive voltage to the solenoid or the like can be continued is secured.

  When a voltage other than the highest power supply VSL is used as the monitoring target voltage, as described above, the monitoring target voltage is preferably a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped. That is, since the voltage supplied to the various switches of the gaming machine (switch voltage: for example, the drive voltage of the payout count switch 301) is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. . Therefore, it is preferable to monitor a voltage higher than at least the switch voltage.

  Next, a specific example of the switch process (step S21) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. A switch timer is used to measure the predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates an ON state. As shown in FIG. 18, the switch timers are provided by the number N of detection signals. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports.

  FIG. 19 is a flowchart illustrating a processing example of the switch processing in step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch process, the CPU 56 first inputs data input to the input port 0 (step S101). Next, “8” is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

  FIG. 20 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets port input data, in this case, input data from the input port 0, as a “comparison value” (step S121). Further, clear data (00) is set (step S122). Then, the switch timer pointed to by the pointer (switch timer address is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S124). Data of input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 33a is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S125), that is, if the detection signal of the winning opening switch 33a is on, the switch timer value is incremented by 1 (step S127). If the value after addition is not 0, the addition value is returned to the switch timer (steps S128 and S129). When the value after addition becomes 0, the addition value is not returned to the switch timer. That is, when the value of the switch timer has already reached the maximum value (255), the value is not increased further.

  If the value of the carry flag is “0”, that is, if the detection signal of the winning opening switch 33a is in the OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

  Thereafter, the CPU 56 adds 1 to the pointer (switch timer address) (step S130) and subtracts 1 from the number of processes (step S131). If the number of processes is not 0, the process returns to step S122. Then, the processes of steps S122 to S132 are repeated.

  The processes in steps S122 to S132 are repeated for the number of processes, that is, eight times, and during that time, the detection signal of the switch input to the 8 bits of the input port 0 is sequentially checked to determine whether it is on or off. If it is ON, the value of the corresponding switch timer is incremented by one.

  The CPU 56 inputs the data input to the input port 1 in step S105 of the switch process. Next, “4” is set as the processing number (step S106), and the address of the switch timer for the count switch 23 is set in the pointer (step S107). Then, a switch check processing subroutine is called (step S108).

  In the switch check processing subroutine, since the above-described processing is executed, the processing in steps S122 to S132 is repeated for the number of processing, that is, four times, and the detection signal of the switch input to the 4 bits of the input port 1 during that time. Then, a check process is sequentially performed to determine whether the state is on or off. If the state is on, the value of the corresponding switch timer is incremented by one.

  In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

  FIG. 21 and FIG. 22 are flowcharts showing an example of the prize ball process in step S32 in the game control process. In this embodiment, in the prize ball processing, it is determined whether or not the prize opening switches 33a, 39a, 29a, 30a, the count switch 23, and the start opening switch 14a to be paid out are surely turned on. When turned on, processing such as control is performed so that a REQ signal (prize ball request signal) for making a prize ball payout request and a payout number signal indicating the number of prize balls are output to the payout control board 37.

  In the prize ball processing, the CPU 56 sets “0” as the offset of the input determination value table (step S169), and sets “0” as the offset of the address of the switch timer (step S170). The offset “0” in the input determination value table means that the first data in the input determination value table is used. In this example, the offset “0” of the address of the switch timer means that the switch timer corresponding to the winning opening switch 33a is designated. Also, “4” is set as the number of repetitions (step S171). Then, a switch-on check routine is called (step S172).

  The input determination value table is a ROM area in which a determination value for determining that the switch has been turned on when it is detected how many times it is continuously turned on is set for each switch. A configuration example of the input determination value table is shown in FIG. As shown in FIG. 24, determination values “2”, “250”, and “1” are set in the input determination value table in order from the top, that is, in order from the area with the smallest address value. In the switch-on check routine, the judgment value set at the address determined by the head address and the offset value in the input judgment value table is compared with the value of the switch timer determined by the head address and the offset value of the switch timer. If they match, for example, a switch-on flag is set.

  An example of a switch-on check routine is shown in FIG. In the switch-on check routine, the CPU 56 sets the head address of the input determination value table (see FIG. 24) (step S281). Then, an offset is added to the address (step S282), and a switch-on determination value is loaded from the address after the addition (step S283).

  Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the address after the addition (step S286). Since each switch timer is arranged in the same order as the bit order of the input port, the value of the switch timer corresponding to the switch is loaded.

  Then, the CPU 56 compares the loaded switch timer value with the switch-on determination value (step S287). If they match, a switch-on flag is set (step 228).

  In this case, in the switch-on check routine, the switch-on flag is set if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value “2” (step S173). Then, the switch check-on routine is executed for the number of repetitions initially set (step S176, S177) while the offset of the switch timer address is updated (step S178). For 39a, 29a, 30a, the corresponding switch timer value is compared with the switch-on determination value “2”.

  When the switch-on flag is set, 10 is added to the stored value (unpaid-out number data) of the total winning ball number storage buffer (step S175). The total winning ball number storage buffer is a buffer for storing a cumulative value of the number of winning balls instructed to the payout control means (however, subtracted when paying out), and is formed in the backup RAM.

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S179), and sets “5” as the offset of the switch timer address (step S180). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input ports, the offset “5” of the switch timer address means that the switch timer corresponding to the start port switch 14a is designated. Then, a switch-on check routine is called (step S181).

  In the switch-on check routine, if the value of the switch timer corresponding to the start port switch 14a matches the switch-on determination value “2”, the switch-on flag is set (step S182). When the switch-on flag is set, 5 is added to the stored value of the total winning ball number storage buffer (step S184).

  Next, the CPU 56 sets “0” as the offset of the input determination value table (step S185), and sets “6” as the offset of the switch timer address (step S186). The offset “0” in the input determination value table means that the first data in the input determination value table is used. Since the switch timers are arranged in the same order as the bit order of the input ports, the offset “6” of the switch timer address means that the switch timer corresponding to the count switch 23 is designated. Then, a switch-on check routine is called (step S187).

  In the switch-on check routine, if the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S188). When the switch-on flag is set, 15 is added to the stored value of the total winning ball number storage buffer (step S190).

  If the REQ signal is at a low level (ON state) (step S191), the CPU 56 monitors the number of prize balls actually paid out from the ball payout device 97 and stores the value stored in the total prize ball number storage buffer. A prize ball payout completion confirmation process to be subtracted is performed (step S192).

  If the REQ signal is at a high level (off state) (step S191), if the total prize ball number storage buffer is not 0, that is, if there is a prize ball remaining (step S193), the CPU 56 The payout request signal is output with the REQ signal at a low level, and the payout number signal is output (steps S194 and S195). In this example, the payout number signal indicates any number from 1 to 15. In this example, in step S195, if the content of the total prize ball number storage buffer is less than 15, a payout number signal indicating the number is output, and if it is 15 or more, a payout number signal indicating 15 is output. Is done. Then, the number indicated by the number-of-payout signal set in the output state in step S195 (that is, the number requested to be paid out to the payout control board 37) is stored in the requested number buffer (step S196). The requested number buffer is a storage area that is provided, for example, in an area where the power of the RAM 55 is backed up, and stores the number of prize balls requested to be paid out to the payout control board 37.

  FIG. 25 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are exchanged between the main board 31 and the payout control board 37 in order to perform various controls relating to the payout control and the like. As shown in FIG. 25, the power supply confirmation signal is set to a high level output state when the main board 31 rises (for example, the output state is set in the initialization process or the game state restoration process), and is sent to the payout control board 37. It is a signal for notifying that the main board 31 has risen. Further, the power confirmation signal is set to the low level output state when the power interruption is detected, and is also used as a signal for notifying the dispensing control board 37 that the main board 31 has detected the power interruption. The REQ signal (prize ball request signal) is set to a low-level output state at the time of a prize ball payout request, and is a signal (payout request signal: trigger signal for a prize ball payout request) for requesting execution of a prize ball payout process. It is used as In addition, the REQ signal is set to a high level output state when a payout completion notice is received from the payout control board 37, and is also used as a signal (payout completion acceptance signal) for notifying that a payout completion notice has been accepted. The payout number signal is a signal that is output to designate the number of game balls (1 to 15) that make a payout request. In this embodiment, the payout request signal and the payout quantity signal (an example of the payout command signal) are not a one-shot signal that transmits specific information by a change in signal level, but from the payout control board 37. The output state is continuously maintained until a prize ball payout completion signal, which will be described later, is received, and specific information is transmitted according to the signal level. The BUSY signal is a signal used by the main board 31 to confirm the operation state on the payout control board 37. This BUSY signal is set to a high level output state at the start of the prize ball payout process, and is used as a signal for notifying that the prize ball payout process is in progress (a prize ball payout signal). The BUSY signal is a low-level output state when the prize ball payout process is completed, and is a signal for notifying that the number of prize balls payout process according to the request from the main board 31 has been completed. Also used as (Prize ball payout completion signal). Each control signal only needs to have a configuration in which the output state and the stop state can be distinguished, and the above logic may be reversed.

  FIG. 26 is a block diagram showing signal lines used for transmission / reception of each control signal shown in FIG. As shown in FIG. 26, the power confirmation signal, the REQ signal, and the payout number signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. The BUSY signal is output via the output circuit 373B by the payout control CPU 371 and input to the CPU 56 via the input circuit 68. The power supply confirmation signal, the REQ signal, and the BUSY signal are each set as 1-bit data and are transmitted through one signal line. In the present example, 1 to 15 payout number signals are designated, so that the number of payout number signals is 4-bit data and is transmitted through four signal lines.

  FIG. 27 is a flowchart illustrating an example of a prize ball payout completion confirmation process. In the prize ball payout completion confirmation process, the CPU 56 first checks whether or not a prize ball payout completion signal has been received (step S381). Specifically, it is confirmed whether or not the BUSY signal is lowered from the high level to the low level. When receiving the winning ball payout completion signal, the CPU 56 loads the stored value of the total winning ball number storage buffer and the stored value of the requested number buffer (step S382), and requests from the stored value of the total winning ball number storage buffer. The stored value in the number buffer is subtracted (step S383). That is, the number of prize balls that have been paid out is subtracted from the stored value in the total prize ball number storage buffer. Then, the stored value in the request number buffer is cleared (for example, “0” is stored as the initial value) (step S384).

  Then, the CPU 56 sets the output of the REQ signal to a high level off state and outputs a payout completion acceptance signal (step S385), and sets the payout number signal output to a low level stop state (step S386).

Next, the operation of the payout control means will be described.
FIG. 28 is a flowchart showing the main processing of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM). In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a payout control process is executed.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Used as Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, the CH3 register is set to a value corresponding to 2 ms as an initial value.

  Next, the payout control CPU 371 executes normal initialization processing (steps S711 to S713). In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S711). In addition, initial values are set in flags and counters in the RAM area. Then, the CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically generated every 2 ms (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited in step S701 of the initial setting process, the interruption is permitted before the initialization process is finished (step S713).

  In this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, a timer interrupt flag indicating that a timer interrupt has occurred is set as shown in FIG. 29 (step S792). If it is detected in the main process that the timer interrupt flag is set (step S751), the timer interrupt flag is reset (step S752), and the payout control process (steps S752 to S760) is executed. The

  In the timer interrupt, as shown in FIG. 29, the interrupt permission state is first set (step S791). Therefore, the interrupt is permitted during the timer interrupt process, and the payout control command receiving process based on the input of the INT signal can be preferentially executed.

  In the payout control process, the payout control CPU 371 first determines whether or not a switch such as the payout count switch 301 input to the input port 372b is turned on (switch process: step S753).

  Next, the payout control CPU 371 sets the payout prohibition state if the ball break switch 187 or the full tank switch 48 is on, and the ball break switch 187 and the full tank switch 48 are turned off so that the payout prohibition condition is not satisfied. Then, the payout prohibition state is canceled (payout prohibition state setting process: step S754). Note that the ball-out lamp 52 is turned on / off in response to turning on / off of the ball-out switch 187. Then, a prepaid card unit control process is performed (step S755).

  Next, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756).

  Further, the payout control CPU 371 performs a prize ball control process for paying out the number of prize balls indicated by the payout quantity signal from the main board (step S757). Then, a drive signal is output to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of rotations is performed. (Step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control them. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). In addition, processing for outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

  FIG. 30 is an explanatory diagram showing a usage example of the RAM built in the payout control CPU 371. In this example, a total number memory (for example, 2 bytes) and a lending ball number memory are formed in the RAM area. The total number storage stores the number of prize balls that have not been paid out of the number of prize balls that have been instructed from the main board 31 side. The rented ball number storage stores the number of balls that have not been paid out. The RAM area is not limited to an area for storing information related to the number of game balls described above. For example, various flags such as a flag indicating an error state such as a payout stop flag and a payout path error flag described later are stored. And an area for storing various buffers such as a reception command buffer.

  Then, when the payout control CPU 371 receives, for example, a prize ball number signal indicating the number of prize balls from the game control means in the prize ball control process (step S757), the content is increased in the total number memory by the designated number. To do. In addition, in the ball lending control process (step S756), every time a ball lending request signal is received from the card unit 50, the content is increased in the lending ball number storage by the number of one unit (for example, 25). Further, when the payout count switch 301 detects one prize ball payout in the prize ball control process, the payout control CPU 371 decrements the value of the total number memory by 1, and in the ball lending control process, the payout count switch 301 lends one. When the ball payout is detected, the value of the lending ball number memory is decreased by one. Therefore, the number of unpaid prize balls and the number of lent balls are stored in the RAM area.

  FIG. 31 is a flowchart illustrating an example of the switch processing in step S753. In the switch process, the payout control CPU 371 checks whether or not the payout count switch 301 indicates an on state (step S753a). If the ON state is indicated, the payout control CPU 371 increments the payout count switch ON counter by 1 (step S753b). The payout count switch on counter is a counter for counting the number of times that the on state of the payout count switch 301 is detected.

  Then, the value of the payout count switch on counter is checked (step S753c). If the value is 2, it is determined that one game ball has been paid out. Next, the payout control CPU 371 checks whether one game ball that has been paid out is a prize ball or a lending ball. In this example, it is confirmed whether or not a ball lending process flag, which will be described later, is on (step S753d). If it is on, it is determined that one lending ball has been paid out. It is determined that a prize ball has been paid out. When it is determined that one lending ball has been paid out, the payout control CPU 371 decrements the lending ball unpaid-out number counter (the number of lending balls stored in the lending ball number storage) (step S753e). ). On the other hand, when it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout number counter (the number of prize balls stored in the total number memory) by -1 (step). S753f). In step S753d, the award ball processing flag may be confirmed to identify whether a ball rental or a prize ball is paid out.

  When it is determined that one lending ball has been paid out, the payout control CPU 371 increments the value of the lending ball information counter by 1 (step S753g). If the value of the lending ball information counter is 25 or more (step S753h), the value of the lending ball information output counter is incremented by 1 (step S753i), and the value of the lending ball information counter is decremented by -25 (step S753j). The value of the lending ball information output counter is referred to in the output process (step S760) in the payout control process shown in FIG. 28. If the value is 1 or more, 1 pulse is output as the lending number signal. The Therefore, in this embodiment, every time 25 game balls are paid out as rental balls, one ball rental number signal is output to the outside of the gaming machine.

  If it is determined that one prize ball has been paid out, the payout control CPU 371 increments the value of the prize ball information counter by 1 (step S753k). If the value of the prize ball information counter is 10 or more (step S7531), the value of the prize ball information output counter is incremented by 1 (step S753m), and the value of the prize ball information counter is incremented by -10 (step S753n). The value of the prize ball information output counter is referred to in the output process (step S760) in the payout control process shown in FIG. 28. If the value is 1 or more, one pulse is output as the prize ball payout number signal. Is done. Therefore, in this embodiment, every time 10 game balls are paid out as prize balls, one prize ball payout quantity signal is output to the outside of the gaming machine.

  When it is confirmed in step S753a that the payout count switch 301 is not in the on state, the payout control CPU 371 clears the payout count switch on counter (step S753o).

  FIG. 32 is a flowchart illustrating an example of the payout prohibition state setting process in step S754. In the payout prohibition state setting process, the payout control CPU 371 checks whether or not the full switch 48 indicates the on state (step S754a). If the on state is indicated, the payout control CPU 371 increments the full switch on counter by 1 (step S754b). The full tank switch on counter is a counter for counting the number of times that the on state of the full tank switch 48 is detected.

  Then, the value of the full tank switch-on counter is checked (step S754c). If the value is 50, it is determined that the lower pan is full. If it is determined that the lower pan is full, the payout control CPU 371 sets the payout prohibited state (step S754d).

  When it is confirmed in step S754a that the full tank switch 48 is not on, the payout control CPU 371 clears the full tank switch on counter (step S754e).

  Next, the payout control CPU 371 checks whether or not the ball break switch 187 indicates an on state (step S754f). If the on state is indicated, the payout control CPU 371 increments the ball break switch on counter by 1 (step S754i). The out-of-ball switch on counter is a counter for counting the number of times the on-state of the out-of-ball switch 187 is detected.

  Then, the value of the ball break switch-on counter is checked (step S754j). If the value is 250, it is determined that the ball has run out. If it is determined that the ball is out of play, the payout control CPU 371 sets the payout prohibited state (step S754k).

  If it is confirmed in step S754f that the ball break switch 187 is not in the on state, the payout control CPU 371 clears the ball break switch on counter (step S754g), and if it is in the payout prohibition state, the payout prohibition state. Is released (step S754h). Accordingly, when it is confirmed that neither the full tank switch 48 nor the ball break switch 187 is in the on state when the payout prohibition state is set, the payout prohibition state is canceled.

  When setting the payout prohibited state, for example, the driving of the payout motor 289 is stopped and an internal flag (payout stop flag) indicating that payout is stopped is set. Further, when releasing the payout prohibition state, the drive of the payout motor 289 is resumed and the payout stop flag is reset. That is, in steps S754d and S754k, a process of storing data indicating that the payout is prohibited (set payout stop flag) in a predetermined storage area is executed. In step S754h, a payout is performed. Is stored in a predetermined storage area, indicating that the data is in a permitted state (reset payout suspension flag).

  The payout suspension flag is stored, for example, in the RAM area. The payout suspension flag has a 1-byte structure composed of bits D0 to D7, for example. In this case, for example, if D0 is “1”, it indicates a state in which the payout prohibition state is set, and if D1 is “1”, it indicates a state in which the payout prohibition state is cancelled. D2 is used, for example, to indicate a return waiting state after the payout prohibition state is canceled. D3 to D7 are unused areas.

  Here, the state of the payout suspension flag in the processing of FIG. 32 will be specifically described. In the processing of steps S754d and S754k, the payout control CPU 371 sets the payout stop flag D0 to “0” and sets D1 to “1”. In the process of step S754h, the payout control CPU 371 sets the payout stop flag D0 to “1”, sets D1 to “0”, and sets D2 to “1”. The payout control CPU 371 sets D2 to “0” after a predetermined period (for example, 1 [s]) when D2 is set to “1”. In this embodiment, the payout suspension flag indicates that payout is prohibited when D0 is “0” and D1 is “1”. Further, when D0 is “1” and D1 is “0”, it indicates that the payout is permitted (the state where the payout prohibition state is released). The payout suspension flag may have a configuration other than the 1-byte configuration, and each bit may be used in another manner (for example, only D0 is used and D0 is set to “ If it is “0”, it indicates a payout prohibition state, and if D0 is “1”, it indicates a payout permission state).

  When the payout prohibition state is set, the payout motor 289 may be stopped immediately. However, the payout motor 289 may be stopped at a place where the cut is good instead of being controlled as such. For example, the payout of the game ball is executed in a requested unit from the main board 31 or the card unit 50 (for example, any one of 5, 10, 15, or 25), and when the payout of one unit is completed, the payout motor While 289 is stopped, the internal state may be set to the payout prohibited state. As described above, the ball break switch 187 is installed at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage. Even if detected, at least 25 payouts are possible from that point. Accordingly, there is no problem even if the payout is prohibited when the payout of one unit is completed. Further, if the payout is prohibited in units of one unit, it becomes easy to control when payout is resumed.

  FIG. 33 is a flowchart showing an example of the prepaid card unit control process in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not a VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Also, the payout control CPU 371 checks whether or not the value of the VL signal non-detection counter is 125 in this embodiment (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CPU 371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S755d).

  If the VL signal is detected to be off 125 times (2 ms × 125 = 250 ms) continuously by the above processing, the ball firing prohibited state is set.

  If the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the discharge control CPU 371 stops outputting the firing control signal (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to enable the drive motor 94 (step S755g). .

  34 and 35 are flowcharts showing an example of the ball lending control process in step S756. In this embodiment, the maximum value of the continuous payout number is set as one unit (for example, 25) of the lending ball, but the maximum value of the continuous payout number may be another number.

  In the ball lending control process, the payout control CPU 371 checks whether or not the ball lending is stopped (step S510). If it is stopped, the process is terminated. Note that whether or not the ball lending is stopped is confirmed by whether or not the payout suspension flag set in the payout prohibition state setting process or the like shown in FIG. 32 is turned on.

  If the ball lending is not stopped, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S511). If the ball lending is being paid out, the process proceeds to the ball lending process shown in FIG. To do. Whether or not the lending ball is being paid out is determined by the state of a ball lending process flag which will be described later. If the rental ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout, the payout control CPU 371 checks whether or not a ball lending request has been received from the card unit 50 (step S513). If requested, the ball lending process flag is turned on (step S514), and 25 (number of ball lending units: 100 yen here) is set in the lending ball number storage in the RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the payout control CPU 371 sets a motor rotation time for paying out 25 game balls, or determines the number of output pulses corresponding to the motor rotation time. Then, the payout motor 289 is turned on (step S518), and the process proceeds to the ball lending process shown in FIG.

  Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized acceptance. In addition, the ball lending process flag is set in the RAM area.

  FIG. 35 is a flowchart showing a ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch processing of step S752, it is confirmed whether or not the lending ball has been paid out by the detection signal of the payout count switch 301, etc., so that the lending ball number storage subtraction is performed in the ball lending control processing. Is not done.

  In the ball lending control process, the payout control CPU 371 checks whether or not it is during the lending ball passage waiting time (step S519). If it is not during the lending ball passage waiting time, the lending ball is paid out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be finished (whether the payout operation of one unit has been finished) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522) and sets the lending ball passage waiting time (step S523).

  If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 checks whether or not the lending ball passage waiting time has ended (step S524). The lending ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout count switch 301. When confirming the end of the lending ball passage waiting time, all lending balls of one unit have been paid out, so that the card unit 50 can accept the next lending request. The EXS signal is turned off (step S525). Also, the ball lending process flag is turned off (step S527). If the last payout ball does not pass the payout count switch 301 before the lending ball passage waiting time elapses, a payout path error is determined. In this embodiment, the winning ball and the lending are performed by the same payout device.

  After turning off the EXS signal indicating acceptance of a ball lending request, if the BRQ signal, which is a ball lending request signal, is turned on again within a predetermined period, the ball lending process is continued without turning off the payout motor. Also good. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be executed continuously.

  FIG. 36 and FIG. 37 are flowcharts showing an example of the prize ball control process in step S757. In the winning ball control process, the payout control CPU 371 first checks whether or not the winning ball is stopped (step S530). If it is stopped, the process is terminated. Whether or not the prize ball is stopped is confirmed by whether or not the payout stop flag set in the payout prohibition state setting process or the like shown in FIG. 32 is turned on.

  If the winning ball is not stopped, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S531), and if the lending ball is being paid out, the processing is terminated. Whether or not the lending ball is being paid out is determined based on the state of the lending ball processing flag. If the lending ball is not being paid out, it is confirmed whether or not the winning ball payout process has already been started, that is, whether or not the winning ball is being drawn (step S532). If it is during the winning ball, the process proceeds to the processing during the winning ball shown in FIG. Whether or not a prize ball is in progress is determined by the state of a prize ball processing flag to be described later.

  If the winning ball is not being paid out, the payout control CPU 371 checks whether or not the REQ signal is input (step S534). If the REQ signal is input, the payout control CPU 371 determines that a prize ball payout request has been made from the main board 31, and turns on the prize ball processing flag (step S535). The prize ball processing flag is set in the RAM area.

  Next, the payout control CPU 371 sets the number (for example, 5, 10, 15) indicated by the payout number signal from the main board 31 as the number of unpaid award balls in the total number memory (step S536). In addition, the payout control CPU 371 instructs the payout motor 289 to rotate the payout motor 289 until paying out the number of game balls indicated by the payout quantity signal (for example, 5 pieces, 10 pieces, and 15 pieces). In order to output a drive signal, the number of payout operations indicated by the payout number signal is set (step S537). Specifically, the motor rotation time for paying out the number of game balls indicated by the payout number signal is set, or the number of output pulses corresponding to the motor rotation time is determined. Then, the payout control CPU 371 outputs a BUSY signal (prize ball paying out signal) for notifying the main board 31 that the prize ball payout operation is being executed. Also, the payout control CPU 371 turns on the payout motor 289 (step S539). Then, the process proceeds to a process during payout of prize balls in the prize ball control process shown in FIG.

  FIG. 37 is a flowchart showing an example of a process during a prize ball in the payout control process by the payout control CPU 371. In the winning ball control process, if the payout motor 289 is not turned on, it is turned on.

  In the processing during the winning ball, the payout control CPU 371 checks whether or not it is during the waiting time for winning ball passing (step S540). If it is not during the award ball passing waiting time, a prize ball is paid out (step S541), and it is confirmed whether or not the driving of the payout motor 289 should be finished (whether the number of payout operations indicated by the number-of-payout signal has been finished). (Step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543) and sets the award ball passage waiting time (step S545). The award ball waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout count switch 301.

  If it is during the prize ball passage waiting time in step S540, the payout control CPU 371 checks whether or not the prize ball passage waiting time has ended (step S546). When the winning ball passing waiting time ends, all the winning balls paid out by the payout operation set in step S536 are detected by the payout count switch 301. In this example, if the waiting time for award ball passing has ended, the payout control CPU 371 confirms whether or not the payout of the number of prize balls requested for payout from the main board 31 has been completed. It is confirmed whether or not the storage content of the number storage is 0 (step S547). If the storage content of the total number storage is not 0, the payout control CPU 371 determines that the number of game balls indicated by the payout number signal from the main board 31 has not been completely paid out, and the predetermined correction number In order to output a drive signal to the payout motor 289 so as to rotate the payout motor 289 until the game ball is paid out, one payout operation is set in this example (step S548). And the process after step S538 is performed.

  As described above, in this example, if the stored content of the total number storage is not 0 in step S547, a process of paying out one game ball as the correction number (correction process) is executed. That is, game balls are paid out one by one until it is confirmed in step S547 that the stored contents of the total number storage are zero. However, in this embodiment, although not shown in FIG. 36 and FIG. 37, in spite of the processing for paying out a predetermined number (for example, 3) of game balls by the correction processing, If it is not confirmed by confirmation that the stored contents of the total number storage is 0, a payout path error is assumed.

  When it is confirmed in step S547 that the storage content of the total number storage is 0, the payout control CPU 371 determines that the payout of the number of prize balls indicated by the payout number signal from the main board 31 has been completed. The BUSY signal is stopped (step S549), and the prize ball processing flag is turned off (step S550).

  In this embodiment, the ball lending is prioritized over the winning ball processing according to the determinations in steps S511 and S531, but the winning ball processing may be prioritized over the ball lending.

  In the above embodiment, the RAM is used as the fluctuation data storage means. However, as the fluctuation data storage means, a storage means other than the RAM may be used as long as it is an electrically rewritable storage means. Good.

  Further, in the above embodiment, the power supply monitoring means and the circuit for generating a signal for system reset are provided on the main board 31, but one or both of them are provided on the power supply board 910. Also good.

  Next, the output state of control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 38 is a timing chart showing an example of the output state of the control signal. Here, 15 winnings are detected after 5 winnings are detected by the switches for detecting winnings (for example, winning port switches 33a, 39a, 29a, 30a, start port switch 14a, count switch 23). The case will be described.

  As shown in FIG. 38, when five winnings are detected, the CPU 56 sets the REQ signal to the low level on state and sets the payout number signal indicating five to the high level on state. Upon receiving the REQ signal, the payout control CPU 371 sets 5 in the total number memory based on the payout number signal, sets the BUSY signal indicating that a prize ball is being paid out, and outputs the payout motor. The payout processing of five prize balls indicated by the payout number signal is driven. Upon confirming that five prize balls have been paid out based on the detection signal from the payout count switch 301, the payout control CPU 371 lowers the BUSY signal to a low level and outputs a prize ball payout completion signal. . The CPU 56 confirms that the payout process has been completed by receiving the prize ball payout completion signal, raises the REQ signal to a high level, outputs a payout completion acceptance signal, and turns off the payout number signal.

  When it is confirmed that the payout process based on the five winnings is completed, the CPU 56 turns on the REQ signal and turns on the payout number signal indicating fifteen. Upon receiving the REQ signal, the payout control CPU 371 sets 15 in the total number memory based on the payout number signal, sets the BUSY signal indicating that a prize ball is being paid out, and outputs the payout motor. It drives to execute the payout processing of 15 prize balls indicated by the payout number signal. Upon confirming that 15 prize balls have been paid out based on the detection signal from the payout count switch 301, the payout control CPU 371 lowers the BUSY signal to a low level and outputs a prize ball payout completion signal. . The CPU 56 confirms that the payout process has been completed by receiving the prize ball payout completion signal, raises the REQ signal to a high level, outputs a payout completion acceptance signal, and turns off the payout number signal.

  In this example, as shown in FIG. 38, the payout process based on 15 winnings is in a waiting state until the payout process based on 5 winnings is completed. In other words, in this example, when a plurality of winnings are continuously generated, the CPU 56 is based on the subsequent winning until the paying of the winning ball based on the previous winning is confirmed by the reception of the winning ball payout completion signal. It waits for a prize ball payout request.

  FIG. 39 is a timing chart showing an example of the output state of the control signal when there is a prize ball payout request during execution of the ball lending process. As shown in FIG. 39, when 15 winnings are detected, the CPU 56 sets the REQ signal to the low level on state and sets the payout number signal indicating 15 to the high level on state. Even if the REQ signal is output, the payout control CPU 371 does not accept the award ball payout request because the ball lending process is being executed (specifically, the process in step S534 is performed according to the determination in step S531 described above). The BUSY signal is not output until the ball lending process is completed. When the ball lending process is completed, the payout control CPU 371 sets 15 in the total number memory based on the payout number signal, sets the BUSY signal to the output state, and drives the payout motor 289 to output the payout number signal. The payout process of 15 prize balls shown in FIG. Upon confirming that 15 prize balls have been paid out based on the detection signal from the payout count switch 301, the payout control CPU 371 lowers the BUSY signal to a low level and outputs a prize ball payout completion signal. . The CPU 56 confirms that the payout process has been completed by receiving the prize ball payout completion signal, raises the REQ signal to a high level, outputs a payout completion acceptance signal, and turns off the payout number signal.

  As described above, in this example, when there is a prize ball payout request during execution of the ball lending process, the payout control CPU 371 accepts the payout request after the ball lending process is completed.

  FIG. 40 shows that the number of requested balls from the main board 31 is ended in the dispensing control board 37 even though the operation of the dispensing motor 289 for dispensing the required number of prize balls from the main board 31 is completed. It is a timing chart which shows the example of the output state of a control signal in case the payout count switch 301 has not detected the payout of the winning ball (when the total number memory is not 0). As shown in FIG. 40, when 15 winnings are detected, the CPU 56 turns on the REQ signal at the low level and turns on the payout number signal indicating 15 at the high level. Upon receipt of the REQ signal, the payout control CPU 371 sets 15 in the total number memory based on the payout number signal, sets the BUSY signal to the output state, and pays out 15 prize balls indicated by the payout number signal. Therefore, the payout motor 289 is driven. When driving of the payout motor 289 for paying out 15 prize balls is completed, the payout control CPU 371 determines whether or not 15 prize balls have been paid out based on the detection signal from the payout count switch 301. (Confirm whether or not the total number storage is 0). Here, as shown in FIG. 40, the payout control CPU 371 has confirmed the payout of 14 prize balls, but has not yet confirmed the payout of 15 prize balls.

  However, when it is not confirmed by the detection signal from the payout count switch 301 that 15 prize balls have been paid out (when the total number memory does not become 0 even after the prize ball passing waiting time is finished: step S547). For reference), the payout control CPU 371 drives the payout motor 289 to pay out one prize ball as a correction process (see step S548). When it is confirmed by the detection signal from the payout count switch 301 based on this one payout that 15 prize balls have been paid out (when the total number memory becomes 0), the payout control CPU 371. Lowers the BUSY signal to a low level and outputs a winning ball payout completion signal. The CPU 56 confirms that the payout process has been completed by receiving the prize ball payout completion signal, raises the REQ signal to a high level, outputs a payout completion acceptance signal, and turns off the payout number signal.

  As described above, in the present example, the payout control board 37 starts from the main board 31 despite the operation of the payout motor 289 for paying out the required number of prize balls from the main board 31. When the payout count switch 301 has not detected payout of the requested number of prize balls, a correction process for adding one game ball and paying out is executed so that an appropriate number of prize balls is paid out. Is done. If the discrepancy in recognition is not resolved even if one game ball is added and paid out, a correction process for adding and paying out one game ball is further performed. Further, when a predetermined number (for example, three) of game balls are paid out by the correction process, the payout count switch 301 does not detect the payout of the required number of prize balls from the main board 31. Is a payout route error.

  Note that the cause of the above-described recognition shift may be, for example, an abnormality in the payout motor 289, an abnormality in the payout count switch 301, or an abnormality in the payout control board 37.

  FIG. 41 is a timing chart showing an example of the output state of the control signal when the power interruption occurs during the payout of the prize ball. As shown in FIG. 41, when 15 winnings are detected, the CPU 56 sets the REQ signal to the low level on state and sets the payout number signal indicating 15 to the high level on state. Upon receipt of the REQ signal, the payout control CPU 371 sets 15 in the total number memory based on the payout number signal, sets the BUSY signal to the output state, and pays out 15 prize balls indicated by the payout number signal. Therefore, the payout motor 289 is driven. When detecting power-off, the CPU 56 executes a process of turning off the power confirmation signal. At this time, the CPU 56 also stops the payout number signal.

  When it is confirmed that the power supply confirmation signal is turned off during the payout process for paying out the prize ball, the payout control CPU 371 performs a process of stopping the BUSY signal and forcibly stopping the drive of the payout motor 289. Execute.

  As described above, in this example, when a power failure occurs during execution of a prize ball payout process, the prize ball payout process is forcibly terminated.

  Next, error processing will be described. FIG. 42 is an explanatory diagram showing the relationship between the type of error and the display of the error display LED 374 (see FIG. 8). In this embodiment, when each error shown in FIG. 42 occurs, in this example, the payout stop flag is set and the payout prohibited state is set. In this example, it is determined that a ball shortage error has occurred when the ball shortage switch 187 is turned on, and it is determined that a lower pan full tank error has occurred when the full tank switch 48 is on.

  Further, it is determined that an in-unit ball biting error has occurred when a motor sensor output abnormality is detected, and a dispensing unit error has occurred when an abnormality has occurred in the dispensing unit in which the dispensing device 97 is mounted. Determined. The motor sensor output abnormality is detected when the motor position sensor is turned on for a predetermined period or longer or is turned off for a predetermined period or longer in, for example, ball lending control processing or prize ball control processing. In this case, it is considered that a game ball, a foreign object, or the like is sandwiched between the sprockets 292. An abnormality in the payout unit corresponds to an abnormality in the payout count switch 301 or the like. The payout unit error includes a payout path error.

  Further, when the VL-off detection flag is set, it is determined that a prepaid card unit unconnected error has occurred, and a prepaid card unit communication error has occurred when communication with the card unit 50 is executed at an irregular timing. Determined. The VL off detection flag is set in step S755d shown in FIG.

  In this example, if it is determined in the error process of step S759 that a ball break error has occurred, the payout control CPU 371 displays “0” on the error display LED 374. Further, when it is determined that a lower pan full error has occurred, “1” is displayed on the error display LED 374, and when it is determined that an in-unit ball biting error has occurred, “2” is displayed on the error display LED 374. ”Is displayed,“ 3 ”is displayed on the error display LED 374 when it is determined that a payout unit error has occurred, and the error display LED 374 when it is determined that a prepaid card unit unconnected error has occurred. “4” is displayed, and if it is determined that a prepaid card unit communication error has occurred, “5” is displayed on the error display LED 374.

  In this example, when an in-unit ball biting error occurs, when the error release switch 375 is pressed after the abnormality is released, the payout stop flag is reset and the error display LED 374 is displayed. It is erased and the error condition is cleared. Even when a payout unit error occurs, if the error release switch 375 is pressed, the payout stop flag is reset and the display of the error display LED 374 is erased, and the error state is resolved.

  FIG. 43 is a block diagram showing a configuration of a characteristic portion in the gaming machine of the present example described above. As shown in FIG. 43, the gaming machine of this example can play a predetermined game using a game medium, and pays out a prize game medium as a prize based on the fact that a payout condition is satisfied by the game. A gaming machine, which is paid out by a game control means 561 for controlling the progress of the game, a payout means 97a for paying out premium game media, a payout control means 371a for controlling the payout means 97a, and a payout means 97a. Game medium detecting means 501 for detecting a prize game medium, and the game control means 561 continuously issues a payout command signal for designating a payout number of the prize game medium to the payout control means 371a based on the establishment of the payout condition. The payout control means 371a controls the payout means 97a based on the payout command signal to execute the payout process of the prize game medium (the payout process in step S757). The detection signal from the game medium detection means 501 is input to the payout control means 371a, and the payout control means 371a monitors the input state of the detection signal from the game medium detection means 501 and is designated by the payout command signal. The number-of-payout determination means 371b for determining whether or not the number-of-payout prize game medium has been paid out, and the number-of-payout prize determining means 371b determine that the quantity of the prize game medium designated by the payout command signal has been paid out. A payout completion signal transmitting means 371c for outputting a payout completion signal indicating that the payout process has been completed to the game control means 561. The game control means 561 continues based on the receipt of the payout completion signal. The payout command signal stop means 562 for stopping the output of the payout command signal that is output in an automatic manner is included.

  As described above, the game control means is configured to output the payout number signal indicating the payout number of the premium game medium and the REQ signal for making a payout request based on the establishment of the payout condition. Can start payout processing based on the REQ signal and pay out the number of prize balls indicated by the payout number signal.

  Further, as described above, the payout control means monitors the input state of the detection signal from the payout count switch 301 to confirm whether or not the number of prize balls indicated by the payout number signal has been paid out, and the payout number signal indicates Since it is configured to output a prize ball payout completion signal when it is confirmed that the number of prize balls has been paid out, the game control means can recognize that the prize ball has been paid out correctly. This can reduce the possibility of a recognition error relating to the number of payouts between the game control means and the payout control means. As described above, since the control signal is transmitted and received in a communication mode in which the payout of the prize ball is accurately executed, it is possible to prevent the game value obtained by the player from being lost.

  Regardless of whether or not the payout has ended, if the REQ signal is stopped when a predetermined period has elapsed from the start of output, the REQ signal may be stopped even if the payout has not ended. However, in the above-described embodiment, the REQ signal is stopped when the prize ball payout completion signal confirms that the number of prize balls indicated by the payout quantity signal has been paid out. There is no such evil.

  Further, as described above, after the payout control means finishes the payout operation for paying out the number of prize balls indicated by the payout quantity signal, the storage content of the total number memory is confirmed, and the number of prize balls to be paid out remains. In such a case, since the correction payout operation for paying out one prize ball is performed (see FIG. 40), the correction payout operation is performed when there is a discrepancy in recognition in the payout control means. The number of prize balls indicated by the payout quantity signal can be reliably paid out. As described above, since the control signal is transmitted and received in a communication mode in which the payout of the prize ball is accurately executed, it is possible to prevent the game value obtained by the player from being lost. Note that the number of game balls to be paid out by the correction operation may not be one, such as the number set in the total number memory.

  In the embodiment described above, the payout control means performs the corrected payout operation in accordance with the stored contents of the total number storage, so that the game control means manages the remaining payout and manages the shortage with respect to the payout control means. There is no need to newly transmit a control signal indicating the number of payouts. Therefore, the control burden on the game control means is reduced. Further, since the payout control means is configured to execute the corrected payout operation based on the information managed by itself (stored contents of the total number memory), the payout control means independently manages the payout quantity. be able to.

  Further, as described above, the corrected payout operation for paying out one prize ball is configured to be repeatedly executed unless the stored content of the total number memory becomes 0. The number of prize balls indicated by the signal can be paid out more reliably.

  In addition, as described above, if the stored contents of the total number memory does not become 0 even when the corrected payout operation for paying out one prize ball is repeatedly executed a predetermined number of times (for example, 3 times), an error state occurs. Therefore, the player or game clerk can recognize that the number of prize balls indicated by the payout number signal is not paid out correctly. When the above error state occurs, the payout stop flag is set and the payout prohibition state is set. Therefore, it is possible to prevent the payout process from being continuously performed when the number of award balls indicated by the payout quantity signal is not accurately paid out. The number of repetitions determined as an error state may be any number of times, for example, the same number of times as the number of payouts indicated by the payout number signal (for example, 15 times for 15 payouts).

  Further, as described above, the payout control means sends to the game control means a control signal indicating that the payout processing of the number of prize balls indicated by the number-of-payout signal has been completed (a prize ball payout completion signal due to the fall of the BUSY signal). The game control means can recognize that the payout process of the payout control means has been completed.

  Further, as described above, the payout control means is configured to output to the game control means a control signal (BUSY signal) indicating that the payout process based on the REQ signal is being executed. The game control means can recognize that the process is being executed.

  Further, as described above, the game control means generates a power interruption in response to the input of the power interruption signal from the power monitoring means (power monitoring IC 902) (specifically, the detection condition of the power monitoring IC 902 is satisfied). The control signal (power supply confirmation signal) indicating that the power supply has been turned off is output (the power supply confirmation signal is turned off), so that the payout control means can recognize that a power supply interruption has occurred.

  As described above, since the power supply monitoring means (power supply monitoring IC 902) is mounted on the main board 31, the power supply monitoring means can be installed near the CPU 56 to which the power-off signal is input. The game control means can quickly recognize the supply stop.

  Further, as described above, the game control means outputs a control signal (power supply confirmation signal) indicating that power supply to the gaming machine has started to the payout control means when the power supply is started (power supply confirmation signal is output). The payout control means can recognize that the power supply has started.

  Further, as described above, since the payout prohibition state is canceled based on the operation of the error cancel switch 375, it is possible to easily cancel the payout prohibition state and activate the payout process.

  In the above-described embodiment, the payout device 97 is configured to pay out the lending balls and the winning balls, so that the number of parts can be reduced.

  In the above-described embodiment, the payout game ball is identified as a rental ball or a prize ball and the remaining payout is updated. Therefore, the rental ball and the prize ball are identified. Can manage the remaining payout. In addition, it is configured to check whether the paid-out game balls are rental balls or prize balls, and to output the number of paid-out rental balls and the number of paid-out prize balls separately to the outside. Therefore, it is possible to distinguish and grasp the number of lending balls paid out and the number of winning balls from the outside.

  In the above-described embodiment, the payout completion signal and the payout processing signal are both constituted by the BUSY signal, and the payout completion signal and the payout processing signal are identified by changing the output mode of the BUSY signal. Thus, the signal line between the game control means and the payout control means can be reduced.

  In the embodiment described above, the payout control means prohibits the game medium payout process when a prohibition condition for prohibiting the payout of the game ball is satisfied (for example, a ball is out of play, the lower plate is full). Although the processing for setting the payout prohibition state (for example, setting of the payout suspension flag) is performed, not only the payout prohibition state is set, but also a control signal (payout prohibition signal) indicating that the payout prohibition condition is satisfied. You may make it output with respect to a game control means. If comprised in this way, it can make a game control means recognize that it is a payment prohibition state.

  In the above-described embodiment, the RAM provided on the payout control board 37 is assumed to have no power-backed-up area. However, a part or all of the power may be backed up like the main board 31. .

  Further, in the above-described embodiment, the detection signal of the payout count switch 301 is input to the payout control board 37. However, the detection signal of the payout count switch 301 is input to the main board 31 to detect it. A control signal indicating that there is a problem may be output from the main board 31 to the payout control board 37.

  In the above-described embodiment, the payout request is made by the REQ signal and the payout number is designated by the payout number signal. However, the payout request and the payout number may be designated by the payout number signal. Good. In this case, the payout control means may determine that a payout request is made at the same time when the payout number signal outputs a signal designating the payout number. With this configuration, it is not necessary to use the REQ signal, and signal lines can be reduced.

  In the above-described embodiment, the BUSY signal is output during the award ball payout process. However, the BUSY signal may be output during the lending ball payout process. If comprised in this way, it can recognize that the game control means is in the ball lending process. Therefore, the game control means can determine that an error has occurred when it is recognized that the ball lending process is continuously executed for a predetermined period or longer based on the output state of the BUSY signal.

  In the above-described embodiment, the payout control means determines that the prize ball payout is ended when it detects that the payout motor 289 has rotated by the planned payout number. However, the number of detections by the payout motor position sensor becomes the expected payout number. If it reaches, it may be determined that the prize ball payout has ended. That is, the payout control means is configured to determine whether or not the payout has been completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 289 or the number of detections by the payout motor position sensor). May be.

  Although not particularly mentioned in the above-described embodiment, the payout control means detects the operation amount of the drive means (for example, the payout motor 289, the gear 291 and the sprocket 292) of the payout means, and based on the detection. It may be configured to determine whether or not an abnormality (payout unit error) related to payout has occurred. If comprised in this way, the abnormality which concerns on payout can be detected reliably.

  Further, in the above embodiment, the ball payout device 97 pays out winning balls and rental balls. However, a payout device for paying out a winning ball and a payout device for lending a ball may be provided separately. In the above embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent, The invention can be applied.

  Further, in the above-described embodiment, it has been described that the payout prohibition state is set when the ball is out of play or the lower pan is full. However, when it is not preferable to perform other payouts or payouts may be performed. Even when it is impossible, the payout prohibition state is set. For example, when the glass door frame 2 is in an open state and a detection signal is output from the door opening switch 161, the payout prohibited state is set in the above embodiment.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (prepaid card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. The IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can be read at least by the recording medium processing device such as an identification code that can identify the recording information It may be something that can be recorded on. Further, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to a card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  The pachinko gaming machine of each of the above embodiments mainly gives a player a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display unit 9 based on the start winning is a combination of the predetermined symbols. It was a first type pachinko game machine that can be used, but if there is a prize in a predetermined area of an electric game that is released based on a start prize, a second type pachinko game that can give a predetermined game value to a player 3rd type pachinko game where a predetermined right is generated or continued when there is a prize for a predetermined electric game that is released when the stop symbol of the pattern variably displayed based on the machine or the start winning combination becomes a combination of the predetermined pattern The present invention can be applied even to a machine.

  Furthermore, the present invention can be applied to a slot machine or the like provided with an electrical component for paying out the game medium, not limited to a pachinko game machine in which the game medium is a game ball.

  In addition, the payout means can execute the payout of the premium game medium and the rental game medium to be lent to the player based on the loan request. When it is configured to detect a medium, the number of parts can be reduced.

  The number of prize game media that indicates whether the detection signal from the game medium detection means is based on detection of a prize game medium or a rental game medium based on the determination by the payout type determination means, and indicates the number of prize game media paid out When the external information signal output process is performed to output a signal or a gaming medium number signal indicating the number of gaming media that has been paid out to the outside of the gaming machine, It is possible to reliably distinguish whether the played game medium is a prize game medium or a rental game medium.

  If the payout control means is configured to output to the game control means a payout processing signal indicating that a prize game medium payout process is being executed based on the payout command signal, The game control means can recognize that the game is being executed.

  When the payout completion signal and the payout processing signal are configured so that the payout completion signal and the payout processing signal are identified by a change in the output form of the same signal, the game control means and the payout control means The signal line between them can be reduced.

  When the payout control means is configured to determine the end of the payout process based on the detection of the operation amount detecting means for detecting the operation amount of the drive unit of the payout means, the payout control means performs the payout by the payout means. It is possible to reliably recognize the end of the operation.

  Power supply monitoring means for monitoring the state of a predetermined power source used in the gaming machine and outputting a detection signal based on the establishment of a detection condition relating to the stoppage of power supply to the gaming machine, and the game control means includes power supply monitoring When the supply stop detection signal indicating that the detection condition is satisfied is output to the payout control means in response to the input of the detection signal from the means, the supply of power to the gaming machine is stopped. The payout control means can grasp that the detection condition related to is established.

  When the power supply monitoring means is configured to be mounted on a game control board provided with the game control means, and the power supply monitoring means is mounted on a board on which the detection signal of the power supply monitoring means is used, the game control means stops power supply. Can be recognized quickly.

  When the game control means is configured to output a power supply start signal indicating that the control operation of the game control means has started to the payout control means at the start of power supply, the game control means The payout control means can recognize that the control operation has started.

  Based on the establishment of the prohibition condition for prohibiting the payout of the prize game medium, the payout control means performs a process for setting the payout prohibition state for prohibiting the payout process of the prize game medium, and causes the setting of the payout prohibition state. When the prohibition condition is a specific prohibition condition, the withdrawal prohibition state is immediately released if the withdrawal prohibition state is canceled based on the operation of a predetermined operation means. be able to.

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
65 System reset circuit (power supply monitoring means)
97 Ball dispenser 371 Dispensing control CPU
902 IC for power monitoring (power monitoring means)

Claims (1)

It is possible to play a predetermined game using game media, and it is possible to pay out premium game media as prizes based on the winning of game media in the prize area in the game area , and each can be identified A variable display unit that variably displays a plurality of types of identification information, and when the display result of the identification information on the variable display unit is a predetermined specific display result, control to a specific gaming state advantageous to the player A gaming machine that
Game control means for controlling the progress of the game, having fluctuation data storage means for storing fluctuation data generated when performing the control,
Storage content holding means capable of holding the storage content of the variation data storage means for a predetermined period even when power supply to the gaming machine is stopped;
Power supply monitoring means for detecting a voltage drop of a predetermined power supply voltage and outputting a detection signal when the occurrence of power supply interruption is detected;
An operation means for outputting an operation signal in response to an operation;
And dispensing means pays out Jing products game media,
A payout control means for controlling the payout means;
Winning detection means for detecting that a game medium has won in the winning area and outputting a winning detection signal;
A game medium detecting means for detecting a prize game medium paid out by the payout means and outputting a payout detection signal ;
The game control means includes
In response to an input of the detection signal from the power supply monitoring unit, a power supply stop process for saving the storage content of the variation data storage unit is executed.
If the operation signal from the operation means is not input when power supply is started, the stored contents of the variable data storage means are stored in the variable data storage means when stored. When the operation signal from the operation means is input, the state return control is executed to restore the control state to the state when the power supply stop process is started based on the stored contents. Initialize the storage contents of the data storage means,
A main process that repeatedly executes a predetermined process, and an interrupt process that is started by interrupting the main process according to a timer interrupt that occurs every predetermined time,
In the interrupt process, a specific gaming state determination numerical value update process for updating a specific gaming state determination numerical value for determining whether or not to enter the specific gaming state, and an initial update of the specific gaming state determination numerical value Execute the initial value setting process to set the numerical value for the initial value as the value,
In the main process, as the predetermined process, an initial value numerical value update process for updating the initial value numerical value is executed,
Before starting the initial value updating process in the main process, the interrupt processing by the timer interrupt is set to a prohibited state, and after the initial value updating process, the interrupt by the timer interrupt is completed. Set the status to allow
Based on the fact that the winning detection means has output the winning detection signal, the payout control means outputs a payout command signal that can specify the payout number of the prize game medium,
The payout control means controls the payout means based on the payout command signal to execute a payout process of the prize game medium,
The payout detection signal from the game medium detection means is input to the payout control means,
The payout control means includes
A payout number determination means for monitoring an input state of the payout detection signal from the game medium detection means and determining whether or not a prize game medium of the payout number specified by the payout command signal has been paid out;
Outputs a payout completion signal indicating that the payout process is completed when the prize game medium payout number specified in the payout command signal is determined to have been paid out by the payout amount determination means to the player control means A payout completion signal output means,
The game control means detects whether or not the operation signal from the operation means is input, and the detection determination is shorter than a winning detection determination period in which the winning detection signal output from the winning detection means is determined to be valid. A gaming machine that is characterized by a period .

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