JP4771838B2 - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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JP4771838B2
JP4771838B2 JP2006062092A JP2006062092A JP4771838B2 JP 4771838 B2 JP4771838 B2 JP 4771838B2 JP 2006062092 A JP2006062092 A JP 2006062092A JP 2006062092 A JP2006062092 A JP 2006062092A JP 4771838 B2 JP4771838 B2 JP 4771838B2
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internal electrode
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JP2007242827A (en
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政浩 西垣
裕章 三野
英之 大鈴
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Kyocera Corp
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この発明は積層セラミックコンデンサに関し、特に、微粒のチタン酸バリウム系結晶粒子により形成された誘電体層を具備する小型高容量の積層セラミックコンデンサに関する。   The present invention relates to a multilayer ceramic capacitor, and more particularly to a small-sized and high-capacity multilayer ceramic capacitor having a dielectric layer formed of fine barium titanate crystal grains.

近年、積層セラミックコンデンサは小型高容量化のために、それを構成する誘電体層および内部電極層の薄層化ならびに多層化が図られており、積層数は200層を越え、また、誘電体層の厚みは3μm以下となり、その誘電体層を構成する結晶粒子の平均粒径は0.8μm以下となっている(特許文献1参照、特許文献2参照)。
特開2003−17356号公報 特開2005−347509号公報
In recent years, in order to reduce the size and increase the capacity of multilayer ceramic capacitors, the dielectric layers and internal electrode layers constituting the multilayer ceramic capacitors have been made thinner and multilayered. The number of laminated layers exceeds 200 layers. The thickness of the layer is 3 μm or less, and the average particle size of the crystal particles constituting the dielectric layer is 0.8 μm or less (see Patent Document 1 and Patent Document 2).
JP 2003-17356 A JP 2005-347509 A

このような積層セラミックコンデンサでは、誘電体層の薄層化および多層化に伴い、誘電体層間に形成される内部電極層の厚みが大きく影響するようになり、内部電極層が形成されている部分と形成されていない部分との間で内部電極層の厚みによる段差が累積し、内部電極層の無い周囲の誘電体層に変形がおこり、内部電極層の端部領域では誘電体層が本来の厚みよりも部分的に薄くなり、絶縁性が低下したり、高温負荷寿命が低下するという問題があった。   In such a multilayer ceramic capacitor, the thickness of the internal electrode layer formed between the dielectric layers is greatly influenced by the thinning and multilayering of the dielectric layer, and the portion where the internal electrode layer is formed Steps due to the thickness of the internal electrode layer accumulate between the part where the internal electrode layer is not formed and the surrounding dielectric layer without the internal electrode layer is deformed. There is a problem that the thickness is partially thinner than the thickness, resulting in a decrease in insulation and a decrease in high-temperature load life.

従って本発明は、誘電体層の厚みを薄層化しても絶縁性に優れ、高温負荷寿命の信頼性に優れた積層セラミックコンデンサを提供することを目的とする。   Accordingly, an object of the present invention is to provide a multilayer ceramic capacitor that is excellent in insulation even when the thickness of the dielectric layer is reduced, and that is excellent in reliability of high-temperature load life.

本発明の積層セラミックコンデンサは、(1)複数の結晶粒子からなる誘電体層および
内部電極層が交互に積層されたコンデンサ本体と、該コンデンサ本体の前記内部電極層が導出された対向する端面にそれぞれ設けられた一対の外部電極とを具備する積層セラミックコンデンサにおいて、
内部電極パターンを形成し、
該内部電極パターンの周囲の同一面に第1セラミックパターンを形成し、
前記内部電極パターンの端部付近および前記第1セラミックパターン上に、含まれるセラミック粉末の平均粒径D が前記第1セラミックパターンに含まれるセラミック粉末の平均粒径D よりも小さい第2セラミックパターンを形成し、
前記内部電極パターン上における前記第2セラミックパターンの内側の同一面に、含まれるセラミック粉末の平均粒径D が前記第2セラミックパターンに含まれるセラミック粉末の平均粒径D よりも大きい第3セラミックパターンを形成してパターンシートを形成し、
該パターンシートを積層して焼成することによって、
前記外部電極が形成された端面に平行な前記コンデンサ本体の断面における前記内部電極層間の前記誘電体層について、前記内部電極層の平面方向の端部において前記内部電極層の積層方向に引いた直線上に存在する前記結晶粒子数が、前記内部電極層の平面方向の中央部において、これも前記内部電極層の積層方向に引いた直線上に存在する前記結晶粒子数よりも多いとともに、前記内部電極層と同一面の外周における前記誘電体層を構成する結晶粒子の平均粒径が、前記内部電極層間の誘電体層における前記内部電極層の平面方向の端部を構成する前記結晶粒子の平均粒径よりも大きいことを特徴とする。
The multilayer ceramic capacitor of the present invention includes (1) a capacitor main body in which dielectric layers and internal electrode layers made of a plurality of crystal particles are alternately stacked, and opposite end surfaces of the capacitor main body from which the internal electrode layers are derived. In a multilayer ceramic capacitor having a pair of external electrodes provided respectively,
Forming an internal electrode pattern,
Forming a first ceramic pattern on the same surface around the internal electrode pattern;
The inner electrode near the end of the pattern and the first ceramic pattern on the second ceramic average particle diameter D 2 of the ceramic powder is smaller than the average particle diameter D 1 of the ceramic powder contained in the first ceramic pattern included Forming a pattern,
On the same surface of the inner side of the second ceramic pattern in the internal electrode pattern, the third average particle diameter D 3 of the ceramic powder is greater than the average particle diameter D 2 of the ceramic powder contained in the second ceramic pattern included Form a ceramic sheet to form a pattern sheet,
By laminating and baking the pattern sheet,
A straight line drawn in the laminating direction of the internal electrode layer at the end in the planar direction of the internal electrode layer with respect to the dielectric layer between the internal electrode layers in the cross section of the capacitor body parallel to the end surface on which the external electrode is formed said number crystal grains present in the above, in the central portion in the planar direction of the internal electrode layer, with more than the number of crystal grains which is also present on a line drawn in the stacking direction of the internal electrode layers, the internal The average particle diameter of the crystal particles constituting the dielectric layer on the outer periphery of the same surface as the electrode layer is the average of the crystal grains constituting the end portion of the dielectric layer between the internal electrode layers in the planar direction of the internal electrode layer. It is characterized by being larger than the particle size .

また上記積層セラミックコンデンサでは、(2)前記結晶粒子がジルコニアを含有し、前記内部電極層の端部における前記誘電体層の前記結晶粒子のジルコニアの含有量は前記内部電極層の中央部における前記誘電体層の前記結晶粒子のジルコニアの含有量よりも多いことが望ましい。   In the multilayer ceramic capacitor, (2) the crystal particles contain zirconia, and the zirconia content of the crystal particles of the dielectric layer at the end of the internal electrode layer is the center of the internal electrode layer. It is desirable that the content of zirconia in the crystal particles of the dielectric layer is larger.

ここで、直線の太さは結晶粒子の最小径よりも小さいものとする。また、内部電極層の平面方向の端部とはコンデンサ本体の上記断面に露出した内部電極層の平面方向の終端付近の位置のことである。この内部電極層の端部は上下層の内部電極層の端部同士を積層方向(内部電極層の平面方向に対して垂直な方向)に直線で結ぶことのできる箇所である。また、内部電極層の平面方向の中央部とは上記断面に露出した内部電極層の平面方向の終端間の中央の位置のことである。   Here, the thickness of the straight line is smaller than the minimum diameter of the crystal particles. Further, the end in the planar direction of the internal electrode layer is a position near the end in the planar direction of the internal electrode layer exposed in the cross section of the capacitor body. The ends of the internal electrode layers are places where the ends of the upper and lower internal electrode layers can be connected in a straight line in the stacking direction (a direction perpendicular to the plane direction of the internal electrode layers). Further, the central portion of the internal electrode layer in the planar direction is the central position between the terminal ends of the internal electrode layer exposed in the cross section in the planar direction.

通常、誘電体層の厚みを薄層化して多層化した場合、内部電極層が形成されている部分と形成されていない部分との間で内部電極層の厚みによる段差の影響が大きくなり、内部電極層の無い周囲の誘電体層が変形しやすくなるが、本発明の積層セラミックコンデンサによれば、誘電体層の変形により内部電極層の端部における誘電体層の厚みが内部電極層の中央部における誘電体層の厚みよりも部分的に薄くなっても、内部電極層の端部における誘電体層中の結晶粒子数を内部電極層の中央部における誘電体層中の結晶粒子数よりも多くしたことにより、誘電体層の絶縁性を高めることができ、積層セラミックコンデンサの高温負荷寿命の信頼性を向上できる。   Normally, when the thickness of the dielectric layer is reduced to a multilayer, the effect of the step due to the thickness of the internal electrode layer increases between the portion where the internal electrode layer is formed and the portion where the internal electrode layer is not formed. Although the surrounding dielectric layer without the electrode layer is easily deformed, according to the multilayer ceramic capacitor of the present invention, due to the deformation of the dielectric layer, the thickness of the dielectric layer at the end of the internal electrode layer is the center of the internal electrode layer. The number of crystal particles in the dielectric layer at the end of the internal electrode layer is smaller than the number of crystal particles in the dielectric layer at the center of the internal electrode layer As a result of the increase, the insulation of the dielectric layer can be improved, and the reliability of the multilayer ceramic capacitor at the high temperature load life can be improved.

図1は本発明の積層セラミックコンデンサの斜視図である。図2はコンデンサ本体内部の誘電体層上に形成された内部電極層を示す平面図であり、内部電極層の面内における図1に示したA−A断面の端部および中央部の位置を示すものである。   FIG. 1 is a perspective view of the multilayer ceramic capacitor of the present invention. FIG. 2 is a plan view showing the internal electrode layer formed on the dielectric layer inside the capacitor body. The positions of the end and center of the AA cross section shown in FIG. 1 in the plane of the internal electrode layer are shown. It is shown.

図3(a)は図1のA−A断面図であり、(b)は図1(a)の中央部と端部における誘電体層を構成する結晶粒子を表す模式図である。本発明の積層セラミックコンデンサはコンデンサ本体1の対向する端面に一対の外部電極3a、3bが形成されている。コンデンサ本体1は誘電体層5および内部電極層7が交互に積層され構成されている。外部電極3a、3bはコンデンサ本体1の内部電極層7が導出された端面に接続されている(図1のB−B方向)。ここで積層セラミックコンデンサの積層数は300層以上が高容量化のために好ましい。 3A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 3B is a schematic diagram showing crystal grains constituting the dielectric layer at the center and the end of FIG. In the multilayer ceramic capacitor of the present invention, a pair of external electrodes 3 a and 3 b are formed on opposite end surfaces of the capacitor body 1. The capacitor body 1 is configured by alternately laminating dielectric layers 5 and internal electrode layers 7. The external electrodes 3a and 3b are connected to the end face from which the internal electrode layer 7 of the capacitor body 1 is led out (direction BB in FIG. 1). Here, the number of laminated ceramic capacitors is preferably 300 or more for high capacity.

また、誘電体層5の厚みは2μm以下が望ましく、特に、1〜1、5μmが好ましい。誘電体層5の厚みが1μm以上であれば高絶縁性となり、2μm以下であれば高容量化できる。   The thickness of the dielectric layer 5 is desirably 2 μm or less, and particularly preferably 1 to 1 and 5 μm. If the thickness of the dielectric layer 5 is 1 μm or more, it becomes highly insulating, and if it is 2 μm or less, the capacity can be increased.

一方、内部電極層7の厚みは0.5〜1.5μmが好ましい。内部電極層7の厚みが0.5μm以上であれば焼成後の途切れが抑えられて有効面積を大きくでき静電容量を高められる。内部電極層7の厚みが1.5μm以下であれば積層コンデンサの薄層化に好適であり、また内部電極層7の段差を抑えられる。   On the other hand, the thickness of the internal electrode layer 7 is preferably 0.5 to 1.5 μm. If the thickness of the internal electrode layer 7 is 0.5 μm or more, discontinuity after firing is suppressed, the effective area can be increased, and the capacitance can be increased. If the thickness of the internal electrode layer 7 is 1.5 μm or less, it is suitable for reducing the thickness of the multilayer capacitor, and the step of the internal electrode layer 7 can be suppressed.

本発明の積層セラミックコンデンサは誘電体層5がチタン酸バリウムを主成分とする複数の結晶粒子9からなるものである。そして、本発明では、この結晶粒子9について以下の特徴を有する。即ち、本発明の積層セラミックコンデンサでは、外部電極3a、3bが形成された端面に平行な前記コンデンサ本体1の断面における前記内部電極層7間の誘電体層5について、前記内部電極層7の平面方向の端部7aにおいて内部電極層7の積層方向に引いた直線13上に存在する結晶粒子9数が、内部電極層7の平面方向の中央部7bにおいて、これも内部電極層7の積層方向に引いた直線13上に存在する結晶粒子9数よりも多いことが重要である。内部電極層7の端部7a付近の誘電体層5の結晶粒子の数をn1、内部電極層7の中央部7bの誘電体層5の結晶粒子9の数をn2としたときに、n1/n2=1.8〜2の範囲が好ましい。n1/n2=1.8以上であると絶縁抵抗および高温負荷寿命が高まり、一方、n1/n2が2以下では静電容量を高く維持できるという効果がある。つまり、内部電極層7の端部7aの誘電体層5を形成する結晶粒子9の平均粒径D1が内部電極層7の中央部7bの誘電体層5を形成する結晶粒子9の平均粒径D2よりも小さいものである。誘電体層5の厚みが2μm以下の場合の結晶粒子9の平均粒径D1、D2については、内部電極層7の端部7aの誘電体層5を形成する結晶粒子9の平均粒径D1が0.1〜0.4μmであることが望ましく、一方、内部電極層7の中央部7bの誘電体層5を形成する結晶粒子9の平均粒径D2は0.3〜0.5μmであることが望ましい。誘電体層5の厚みが2μm以下の場合に、上記のような結晶粒子の粒径差を有することにより、小型高容量の積層セラミックコンデンサにおいて誘電体層5が薄層化され変形が起こっても高絶縁性化が可能となる。   In the multilayer ceramic capacitor of the present invention, the dielectric layer 5 is composed of a plurality of crystal grains 9 whose main component is barium titanate. In the present invention, the crystal grain 9 has the following characteristics. That is, in the multilayer ceramic capacitor of the present invention, the dielectric layer 5 between the internal electrode layers 7 in the cross section of the capacitor body 1 parallel to the end surface on which the external electrodes 3a and 3b are formed is the plane of the internal electrode layer 7. The number of crystal grains 9 existing on the straight line 13 drawn in the laminating direction of the internal electrode layer 7 at the end portion 7 a in the direction is also in the laminating direction of the internal electrode layer 7 at the central portion 7 b in the planar direction of the internal electrode layer 7. It is important that the number is larger than the number of crystal grains 9 existing on the straight line 13 drawn. When the number of crystal grains in the dielectric layer 5 near the end 7a of the internal electrode layer 7 is n1, and the number of crystal grains 9 in the dielectric layer 5 in the central part 7b of the internal electrode layer 7 is n2, n1 / The range of n2 = 1.8-2 is preferable. When n1 / n2 = 1.8 or more, the insulation resistance and the high temperature load life are increased. On the other hand, when n1 / n2 is 2 or less, the capacitance can be maintained high. That is, the average particle diameter D1 of the crystal particles 9 forming the dielectric layer 5 at the end portion 7a of the internal electrode layer 7 is equal to the average particle diameter of the crystal particles 9 forming the dielectric layer 5 at the central portion 7b of the internal electrode layer 7. It is smaller than D2. Regarding the average particle diameters D1 and D2 of the crystal particles 9 when the thickness of the dielectric layer 5 is 2 μm or less, the average particle diameter D1 of the crystal particles 9 forming the dielectric layer 5 at the end 7a of the internal electrode layer 7 is Desirably, the average particle diameter D2 of the crystal particles 9 forming the dielectric layer 5 of the central portion 7b of the internal electrode layer 7 is 0.3 to 0.5 μm. Is desirable. When the thickness of the dielectric layer 5 is 2 μm or less, the dielectric layer 5 is thinned and deformed in a small-sized and high-capacity multilayer ceramic capacitor by having the above-mentioned crystal grain size difference. High insulation can be achieved.

また、本発明によれば誘電体層5を形成する結晶粒子9の粒径は内部電極層7の中央部7bから内部電極層の端部7aにかけて次第に微粒化していることが望ましい。このような粒径の変化は後述の工程図に示すように、内部電極パターンの端部から全幅の10〜30%程度の領域に中央部よりも細かい粉末を付与することにより形成できる。内部電極パターンの端部から全幅の10%より少ないと絶縁性が低下しやすい。一方、30%より多いと静電容量が低下する。   Further, according to the present invention, it is desirable that the grain size of the crystal particles 9 forming the dielectric layer 5 is gradually atomized from the central portion 7b of the internal electrode layer 7 to the end portion 7a of the internal electrode layer. Such a change in particle size can be formed by applying a finer powder than the center portion to an area of about 10 to 30% of the entire width from the end portion of the internal electrode pattern, as shown in a process drawing described later. If it is less than 10% of the total width from the end of the internal electrode pattern, the insulating property tends to be lowered. On the other hand, if it exceeds 30%, the capacitance decreases.

本発明の積層セラミックコンデンサにおいて誘電体層5は希土類元素の酸化物、MgOおよびやMnOを含有することが望ましく、結晶粒子9に含まれる希土類元素の酸化物、MgOおよびMnOの含有量はBaTiOを主体とする結晶粒子100モル部に対して、希土類元素の酸化物およびMgOが0.5〜2モル部、MnO=0.2〜0.5モル部であれば、静電容量の温度特性を安定化できるとともに絶縁性が高まり高温負荷試験での信頼性が優れたものとなる。 In the multilayer ceramic capacitor of the present invention, the dielectric layer 5 preferably contains rare earth element oxides, MgO and MnO, and the contents of rare earth element oxides, MgO and MnO contained in the crystal grains 9 are BaTiO 3. If the rare earth element oxide and MgO are 0.5 to 2 mol parts and MnO = 0.2 to 0.5 mol parts with respect to 100 mol parts of the crystal grains mainly composed of, the temperature characteristics of capacitance As a result, the insulation is increased and the reliability in the high temperature load test is excellent.

また、係る誘電体層5は内部電極層7の端部7aの誘電体層5を形成する結晶粒子9のジルコニアの含有量が内部電極層7の中央部7bの誘電体層5を形成する結晶粒子9のジルコニア(ZrO)の含有量よりも多いことが好ましい。BaTiOを主体とする結晶粒子9にジルコニアの成分を固溶させることにより結晶粒子9の焼成時の粒成長を抑制できる。また、結晶粒子9にジルコニアを含有させて、内部電極層7の端部7aにおける結晶粒子9のジルコニアの含有量を内部電極層7の中央部7bにおける結晶粒子9のジルコニアの含有量よりも多くしたものは高温負荷信頼性が向上する。この場合、ジルコニアの含有量は原料粉末全体で0.4〜2モル部含有することが望ましい。また、本発明に係る結晶粒子9はBaTi1−xZr(x=0.005〜0.2)のように最初から固溶させたものを用いることもできる。 The dielectric layer 5 is a crystal in which the content of zirconia in the crystal particles 9 forming the dielectric layer 5 at the end 7 a of the internal electrode layer 7 forms the dielectric layer 5 in the central portion 7 b of the internal electrode layer 7. The content is preferably larger than the content of zirconia (ZrO 2 ) in the particles 9. By causing the zirconia component to be dissolved in the crystal particles 9 mainly composed of BaTiO 3 , grain growth at the time of firing the crystal particles 9 can be suppressed. Further, zirconia is contained in the crystal particles 9 so that the zirconia content of the crystal particles 9 at the end 7 a of the internal electrode layer 7 is larger than the zirconia content of the crystal particles 9 in the central portion 7 b of the internal electrode layer 7. This improves the high temperature load reliability. In this case, the content of zirconia is desirably 0.4 to 2 mole parts in the whole raw material powder. Further, the crystal grains 9 of the present invention can also be used in which a solid solution from the start as BaTi 1-x Zr x O 3 (x = 0.005~0.2).

内部電極層7は高積層化しても製造コストを抑制できるという部で、ニッケル(Ni)またはニッケル合金などの卑金属が望ましく、特に、係る誘電体層5との同時焼成が図れるという部でニッケル(Ni)がより望ましい。   The internal electrode layer 7 is preferably a base metal such as nickel (Ni) or a nickel alloy in that the manufacturing cost can be suppressed even if the internal electrode layer 7 is highly laminated, and in particular, the nickel (Ni Ni) is more desirable.

図4は、本発明における交流インピーダンス測定を用いた誘電体層中の粒界の抵抗の評価手法を示す模式図である。図4において、20aは試料である積層セラミックコンデンサを装着して温度制御を行う恒温槽、20bは試料に直流電圧を印加するHALT測定装置、20cは交流電源を有するインピーダンス測定装置である。図5は、(a)本発明の交流インピーダンス測定を用いた誘電体層中の粒界の抵抗評価結果の代表例であり、(b)は積層セラミックコンデンサを構成する誘電体層を構成するコア(中心部)、シェル(外周部)、粒界相11および内部電極層7と誘電体層5との界面の4つの成分を等価回路で表したものである。   FIG. 4 is a schematic diagram showing a method for evaluating the resistance of a grain boundary in a dielectric layer using AC impedance measurement in the present invention. In FIG. 4, reference numeral 20a denotes a thermostatic chamber in which a multilayer ceramic capacitor as a sample is attached to perform temperature control, 20b denotes a HALT measuring device that applies a DC voltage to the sample, and 20c denotes an impedance measuring device having an AC power source. FIG. 5 is a typical example of (a) the resistance evaluation result of the grain boundary in the dielectric layer using the AC impedance measurement of the present invention, and (b) is the core constituting the dielectric layer constituting the multilayer ceramic capacitor. (Center part), shell (outer peripheral part), grain boundary phase 11, and four components of the interface between the internal electrode layer 7 and the dielectric layer 5 are represented by an equivalent circuit.

この場合、積層セラミックコンデンサを、誘電体層5を構成するチタン酸バリウムを主成分とする結晶粒子9が示すキュリー温度よりも高い温度、および、積層セラミックコンデンサの定格電圧の1/3以上の電圧の高温負荷雰囲気中に放置する。そして、上記の条件の高温負荷雰囲気に放置する前後において、同じ条件にて交流インピーダンス測定での誘電体層5中の粒界の抵抗減少率を測定する。図5には本発明の積層セラミックコンデンサにおける結晶粒子9のコア(中心部)、シェル(外周部)、粒界および内部電極と誘電体層との界面におけるインピーダンス変化のグラフ(コールコールプロット)の例を示している。この評価では誘電体層5を図の等価回路のように、コア(中心部)、シェル(外周部)、粒界相11および内部電極層7と誘電体層5との界面の4つの成分に区別する。グラフの横軸はインピーダンス信号の実部、縦軸は虚部を示す。インピーダンスの変化を示すグラフは加速寿命試験(HALT)の前と後との違い、およびシミュレーションによるフィッティングである。本発明では、特に、粒界における抵抗変化に着目するものであり、その実部の変化率が1%/min以下であることが望ましい。この評価は、例えば、加速寿命試験(HALT)前後の図5のコールコールプロットを専用ソフトによって、上記4つの成分に分けて求めることができる。ここで、試験温度としてはキュリー温度の1.5倍、電圧としては定格電圧の2/5V以上が好ましい。試験条件を上記のように設定すると高温負荷雰囲気処理前後での誘電体層5中のイオンの拡散や電子の移動が大きくなり粒界相11の抵抗減少率を顕著に見ることができるという利点がある。   In this case, the multilayer ceramic capacitor has a temperature higher than the Curie temperature indicated by the crystal particles 9 mainly composed of barium titanate constituting the dielectric layer 5 and a voltage equal to or higher than 1/3 of the rated voltage of the multilayer ceramic capacitor. Leave in a high temperature load atmosphere. And before and after leaving to stand in the high temperature load atmosphere of said conditions, the resistance reduction rate of the grain boundary in the dielectric material layer 5 in an alternating current impedance measurement is measured on the same conditions. FIG. 5 shows a graph (Cole-Cole plot) of impedance change at the core (center part), shell (outer peripheral part), grain boundary, and interface between the internal electrode and the dielectric layer of the crystal grain 9 in the multilayer ceramic capacitor of the present invention. An example is shown. In this evaluation, the dielectric layer 5 is divided into four components, ie, the core (center portion), the shell (outer peripheral portion), the grain boundary phase 11 and the interface between the internal electrode layer 7 and the dielectric layer 5 as shown in the equivalent circuit of FIG. Distinguish. The horizontal axis of the graph indicates the real part of the impedance signal, and the vertical axis indicates the imaginary part. The graph showing the change in impedance is the difference between before and after the accelerated life test (HALT), and fitting by simulation. In the present invention, attention is particularly paid to the resistance change at the grain boundary, and the rate of change of the real part is preferably 1% / min or less. This evaluation can be obtained, for example, by dividing the Cole-Cole plot of FIG. 5 before and after the accelerated life test (HALT) into the above four components by using dedicated software. Here, the test temperature is preferably 1.5 times the Curie temperature, and the voltage is preferably 2/5 V or more of the rated voltage. When the test conditions are set as described above, there is an advantage that the diffusion rate of ions and the movement of electrons in the dielectric layer 5 before and after the high-temperature load atmosphere treatment are increased, and the resistance reduction rate of the grain boundary phase 11 can be seen remarkably. is there.

次に、本発明の積層セラミックコンデンサの製法について詳細に説明する。図6は本発明の積層セラミックコンデンサの製法を示す工程図である(サイドマージン方向(A−A))。図7は本発明の積層セラミックコンデンサの製法を示す工程図である(エンドマージン方向(B−B))。   Next, a method for producing the multilayer ceramic capacitor of the present invention will be described in detail. FIG. 6 is a process diagram showing the method for producing the multilayer ceramic capacitor of the present invention (side margin direction (AA)). FIG. 7 is a process diagram showing the method for producing the multilayer ceramic capacitor of the present invention (end margin direction (BB)).

(a)工程において、基材31上に長方形状の内部電極パターン33を形成する。内部電極パターン33となる導体ペーストは、Niもしくはこれらの合金粉末を主成分金属とし、これに共材としてのセラミック粉末を混合し、有機バインダ、溶剤および分散剤を添加して調製する。セラミック粉末としては後述のBT粉末が好ましいが、導体ペーストにセラミックス粉末を含有させることで、内部電極層7を貫通して上下の誘電体層5を接続するように柱状のセラミックスが形成される。これにより誘電体層5と内部電極層7間の剥離を防止できる。   In the step (a), a rectangular internal electrode pattern 33 is formed on the substrate 31. The conductor paste to be the internal electrode pattern 33 is prepared by mixing Ni or an alloy powder thereof as a main component metal, mixing ceramic powder as a co-material with this, and adding an organic binder, a solvent and a dispersant. As the ceramic powder, BT powder described later is preferable. However, by including ceramic powder in the conductor paste, columnar ceramic is formed so as to penetrate the internal electrode layer 7 and connect the upper and lower dielectric layers 5. Thereby, peeling between the dielectric layer 5 and the internal electrode layer 7 can be prevented.

次に、(b)工程において、内部電極パターン33の周囲に内部電極パターン33と同一面になるように第1セラミックパターン35を形成する。次に、(c)工程において、内部電極パターン33の端部付近33aおよび第1セラミックパターン35上に第2セラミックパターン37を形成する。次に、(d)工程において(図7のエンドマージン方向(B−B)についての(d)工程は省略)、内部電極パターン33上における第2セラミックパターン37の内側に第2セラミックパターン37と同一面になるように第3セラミックパターン39を形成して基材31上にパターンシート40を形成する。この場合、第1セラミックパターン35に含まれるセラミック粉末の平均粒径D1と第3セラミックパターン39に含まれるセラミック粉末の平均粒径D3は同等であることが好ましい。一方、内部電極パターン33の端部33aに形成する第2セラミックパターン35に含まれるセラミック粉末の平均粒径D2は上記第1および第3セラミックパターンに含まれるセラミック粉末の平均粒径D1、D3よりも小さいことが重要である。つまり、D1>D2、D3>D2、D1=D3の関係より好ましい。ここで内部電極パターン33の厚みが0.5μm以上2μm以下が好ましく、一方、第2セラミックパターン35の厚みは1μm以上3μm以下が好ましい。次に、基材からパターンシート39を剥離する。次に、(e)工程において、パターンシート39を長方形状の内部電極パターン33の短辺が揃い、かつ長辺が半パターンずれるように所望の枚数積層し、この上下面に保護層シート41としてセラミックグリーンシートを積層し母体積層体43を形成する。次に、母体積層体43を切断線45に沿って切断して、両端に内部電極パターン33の端面が積層方向に交互に露出するコンデンサ本体成形体を形成する。次に、コンデンサ本体成形体を焼成してコンデンサ本体1を形成する。次に、コンデンサ本体1の内部電極層7が露出する端面にCuなどに卑金属を主成分とする外部電極3を形成する。上記工程において用いる原料粉末は、第1〜3セラミックパターン35、37、39についてはBaTiO粉末に対して上述した希土類元素、MgO、MnOなどの添加剤とともにガラス粉末を添加する。ガラス粉末はBaTiO粉末100質量部に対して0.5〜2質量部であることが低温焼結できるという点で好ましい。第2セラミックパターン37に含まれるセラミック粉末の平均粒径は0.1〜0.2μm、一方、第1および第3セラミックパターン35、39に含まれるセラミック粉末の平均粒径は0.15〜0.35μmであることが望ましい。また、第2セラミックパターン37に含まれるセラミック粉末として、BaTiOを主体とする原料粉末中にジルコニア(ZrO)粉末を0.5〜1モル%添加することが望ましい。さらには、BaTi1−xZr(x=0.005〜0.2)を用いることによっても同様の効果がある。 Next, in step (b), a first ceramic pattern 35 is formed around the internal electrode pattern 33 so as to be flush with the internal electrode pattern 33. Next, in step (c), the second ceramic pattern 37 is formed on the vicinity 33 a of the internal electrode pattern 33 and on the first ceramic pattern 35. Next, in the step (d) (the step (d) in the end margin direction (BB) in FIG. 7 is omitted), the second ceramic pattern 37 and the second ceramic pattern 37 on the internal electrode pattern 33 are arranged inside the second ceramic pattern 37. The third ceramic pattern 39 is formed so as to be on the same surface, and the pattern sheet 40 is formed on the substrate 31. In this case, it is preferable that the average particle diameter D1 of the ceramic powder included in the first ceramic pattern 35 and the average particle diameter D3 of the ceramic powder included in the third ceramic pattern 39 are equal. On the other hand, the average particle diameter D2 of the ceramic powder included in the second ceramic pattern 35 formed at the end 33a of the internal electrode pattern 33 is based on the average particle diameters D1 and D3 of the ceramic powder included in the first and third ceramic patterns. It is important to be small. That is, it is more preferable than the relationship of D1> D2, D3> D2, and D1 = D3. Here, the thickness of the internal electrode pattern 33 is preferably 0.5 μm or more and 2 μm or less, while the thickness of the second ceramic pattern 35 is preferably 1 μm or more and 3 μm or less. Next, the pattern sheet 39 is peeled from the substrate. Next, in step (e), a desired number of pattern sheets 39 are stacked so that the short sides of the rectangular internal electrode pattern 33 are aligned and the long sides are shifted by a half pattern, and the protective layer sheet 41 is formed on the upper and lower surfaces. The green body 43 is formed by laminating ceramic green sheets. Next, the base laminate 43 is cut along the cutting line 45 to form a capacitor body molded body in which the end faces of the internal electrode pattern 33 are alternately exposed at both ends in the stacking direction. Next, the capacitor body 1 is formed by firing the capacitor body molded body. Next, the external electrode 3 mainly composed of a base metal such as Cu is formed on the end surface of the capacitor body 1 where the internal electrode layer 7 is exposed. For the first to third ceramic patterns 35, 37, and 39, the glass powder is added to the BaTiO 3 powder together with the above-described additives such as rare earth elements, MgO, and MnO as the raw material powder used in the above process. The glass powder is preferably 0.5 to 2 parts by mass with respect to 100 parts by mass of the BaTiO 3 powder because it can be sintered at a low temperature. The average particle size of the ceramic powder included in the second ceramic pattern 37 is 0.1 to 0.2 μm, while the average particle size of the ceramic powder included in the first and third ceramic patterns 35 and 39 is 0.15 to 0. .35 μm is desirable. Moreover, as a ceramic powder contained in the second ceramic pattern 37, it is desirable to add 0.5 to 1 mol% of zirconia (ZrO 2 ) powder in a raw material powder mainly composed of BaTiO 3 . Furthermore, the same effect also by using BaTi 1-x Zr x O 3 (x = 0.005~0.2).

また、内部電極パターン33の端部33aに形成する第2セラミックパターン37に用いるセラミック粉末として、2個以上のセラミック粉末が結合したネッキング粉末を用いると、セラミックパターン中においてセラミック粉末を配向したものにでき、誘電体層5の厚み方向に多くの界面数を形成できる。ネッキング粉末のアスペクト比は長寸/短寸比が1.5以上が好ましく、短寸の平均径が0.3μm以下にするという理由から長寸/短寸比3以下が好ましい。   Further, when a necking powder in which two or more ceramic powders are combined is used as the ceramic powder used for the second ceramic pattern 37 formed on the end 33a of the internal electrode pattern 33, the ceramic powder is oriented in the ceramic pattern. It is possible to form a large number of interfaces in the thickness direction of the dielectric layer 5. The aspect ratio of the necking powder is preferably a long dimension / short dimension ratio of 1.5 or more, and a long dimension / short dimension ratio of 3 or less is preferable because the average diameter of the short dimension is 0.3 μm or less.

内部電極パターン33に用いる金属粉末としてはNiまたはCu、あるいはこれらの合金粉末が好ましく、これらの金属粉末の平均粒径は0.1〜0.2μmであることが過焼結を抑制しつつ段差を低減できるという部で好ましい。上述した本発明の積層セラミックコンデンサの製法によれば、内部電極パターン33の中央部と端部との間で異なる粒径のセラミック粉末を有するセラミックパターンを形成する手法を採用することにより、上記のように内部電極層7の端部7aの誘電体層5を形成する結晶粒子9の平均粒径を内部電極層7の中央部7bの誘電体層5を形成する結晶粒子9の平均粒径よりも小さくして、端部7a側の結晶粒子9の数を中央部7bの誘電体層5を形成する結晶粒子9の数を多くした誘電体層5を具備する積層セラミックコンデンサを容易に形成できる。   The metal powder used for the internal electrode pattern 33 is preferably Ni or Cu, or an alloy powder thereof, and the average particle diameter of these metal powders is 0.1 to 0.2 μm while suppressing oversintering. It is preferable in the part which can reduce. According to the manufacturing method of the multilayer ceramic capacitor of the present invention described above, by adopting a method of forming a ceramic pattern having ceramic powders having different particle sizes between the central portion and the end portion of the internal electrode pattern 33, Thus, the average particle size of the crystal particles 9 forming the dielectric layer 5 at the end 7a of the internal electrode layer 7 is larger than the average particle size of the crystal particles 9 forming the dielectric layer 5 at the central portion 7b of the internal electrode layer 7. Therefore, it is possible to easily form a multilayer ceramic capacitor including the dielectric layer 5 in which the number of crystal grains 9 on the end portion 7a side is larger than the number of crystal grains 9 forming the dielectric layer 5 in the central portion 7b. .

本発明の積層セラミックコンデンサを以下のようにして作製した。第1および第3セラミックパターンに用いるセラミック粉末として平均粒径0.3μm、粉末の平均アスペクト比1.1、BaとTiのモル比が1.003のものを用いた。主成分粉末であるチタン酸バリウム(BaTiO)粉末に対する添加剤量はBaTiO100モル部に対して、MgOを0.5モル部、Yを0.5モル部およびMnOをMnCOとして0.3モル部添加した。焼結助剤としてSiOが50モル%、LiOが10モル%、BaOが20モル%、CaOが20モル%で構成されたガラス粉末をチタン酸バリウム粉末100質量部に対して1.2質量部添加した。ガラス粉末の平均粒径は0.5μmとした。第2セラミックパターンに用いるセラミック粉末は表1に示した。添加剤とその添加量は上記第1および第3セラミックパターンと同じとした。上記各粉末の混合粉末を直径5mmのジルコニアボールを用いて、溶媒としてトルエンとアルコールとの混合溶媒を添加し湿式混合し、それぞれ第1、第2および第3セラミックパターン用のスラリを調製した。次に、平均粒径が0.2μmのNi粉末を含む導体ペーストを調製した。次に、基材であるポリエステルフィルム上に厚み1μmの内部電極パターンを所定の配置に複数形成した。内部電極パターンの面積は長辺を1.6mm、短辺を0.8mmとした。次に、内部電極パターンの周囲に第1セラミックパターンを実質的に同一厚みになるように形成した。次に、内部電極パターンの中央部を除く領域に第2セラミックパターンを形成した。第2セラミックパターンは内部電極パターンの端部からそれぞれ長辺、短辺の全幅の20%の領域の幅に形成した。次に、第2セラミックパターンを付与していない内部電極パターンの上面に第1セラミックパターンと同じセラミックスラリを用いて第3セラミックパターンを形成しパターンシートを形成した。第2セラミックパターンと第3セラミックパターンとは実質的に同じ厚みになるように形成した。次に、ポリエステルフィルムとパターンシートとを剥離し、パターンシートを、長方形状の内部電極パターンの短辺が揃い、かつ長辺が半パターンずれるように所望の枚数積層し母体積層体を形成した。内部電極パターンの積層数は360層とし、その上下面に第1セラミックパターンのセラミックスラリから形成した厚み5μmのセラミックグリーンシートを上下20層ずつ積層した。プレス条件は温度60℃、圧力10Pa、時間10分の条件とした。次に、母体積層体を切断して、両端に内部電極パターンの端面が積層方向に交互に露出するコンデンサ本体成形体を形成した。次に、コンデンサ本体成形体を焼成してコンデンサ本体を形成した。焼成は大気中で300℃/hにて脱バインダ処理を行い、1170℃(酸素分圧10−6Pa)で2時間焼成し、続いて、窒素雰囲気中1000℃で7.5時間再酸化処理をした。次に、コンデンサ本体の内部電極層が露出する端面にCuの外部電極を焼き付けて、次いで、この外部電極の表面に、順にNiメッキ及びSnメッキを行い、積層セラミックコンデンサを作製した。コンデンサ本体の寸法は内部電極層に平行な面が1mm×0.5mm、厚みが1mmであった。内部電極層の面積は0.7mm×0.3mmであった。誘電体層の厚みは平均で2μmであった。 The multilayer ceramic capacitor of the present invention was produced as follows. As the ceramic powder used for the first and third ceramic patterns, one having an average particle size of 0.3 μm, an average aspect ratio of the powder of 1.1, and a molar ratio of Ba and Ti of 1.003 was used. Barium titanate as the main component powder (BaTiO 3) additive amount for powder for BaTiO 3 100 molar parts, 0.5 mole part MgO, Y 2 O 3 and MnCO 3 0.5 mole part and MnO As a result, 0.3 mol part was added. A glass powder composed of 50 mol% of SiO 2, 10 mol% of Li 2 O, 20 mol% of BaO, and 20 mol% of CaO as a sintering aid is 1. added to 100 parts by mass of barium titanate powder. 2 parts by mass were added. The average particle size of the glass powder was 0.5 μm. The ceramic powder used for the second ceramic pattern is shown in Table 1. The additive and the amount added were the same as those of the first and third ceramic patterns. Using a zirconia ball having a diameter of 5 mm, a mixed solvent of toluene and alcohol as a solvent was added to the mixed powder of the above powders and wet mixed to prepare slurry for the first, second and third ceramic patterns, respectively. Next, a conductor paste containing Ni powder having an average particle size of 0.2 μm was prepared. Next, a plurality of internal electrode patterns having a thickness of 1 μm were formed in a predetermined arrangement on a polyester film as a base material. The area of the internal electrode pattern was 1.6 mm for the long side and 0.8 mm for the short side. Next, the first ceramic pattern was formed to have substantially the same thickness around the internal electrode pattern. Next, a second ceramic pattern was formed in a region excluding the central portion of the internal electrode pattern. The second ceramic pattern was formed to have a width of 20% of the entire width of the long side and the short side from the end of the internal electrode pattern. Next, a third ceramic pattern was formed on the upper surface of the internal electrode pattern not provided with the second ceramic pattern by using the same ceramic slurry as the first ceramic pattern to form a pattern sheet. The second ceramic pattern and the third ceramic pattern were formed to have substantially the same thickness. Next, the polyester film and the pattern sheet were peeled off, and a desired number of layers were laminated so that the short sides of the rectangular internal electrode pattern were aligned and the long sides were shifted by a half pattern to form a base laminate. The number of laminated internal electrode patterns was 360 layers, and upper and lower ceramic green sheets having a thickness of 5 μm formed from the ceramic slurry of the first ceramic pattern were laminated on the upper and lower surfaces. The pressing conditions were a temperature of 60 ° C., a pressure of 10 7 Pa, and a time of 10 minutes. Next, the base laminate was cut to form a capacitor body molded body in which the end faces of the internal electrode pattern were alternately exposed at both ends in the stacking direction. Next, the capacitor body was fired to form a capacitor body. Firing is performed by removing the binder at 300 ° C./h in the atmosphere, firing at 1170 ° C. (oxygen partial pressure 10 −6 Pa) for 2 hours, and then reoxidation treatment at 1000 ° C. in a nitrogen atmosphere for 7.5 hours. Did. Next, a Cu external electrode was baked on the end surface of the capacitor main body where the internal electrode layer was exposed, and then Ni plating and Sn plating were sequentially performed on the surface of the external electrode to produce a multilayer ceramic capacitor. As for the dimensions of the capacitor body, the surface parallel to the internal electrode layer was 1 mm × 0.5 mm, and the thickness was 1 mm. The area of the internal electrode layer was 0.7 mm × 0.3 mm. The average thickness of the dielectric layer was 2 μm.

得られた積層セラミックコンデンサを以下のように評価した。誘電体層間に存在する結晶粒子数を評価した。この場合、誘電体層の1層あたりの結晶粒子数が多いものが結晶粒子の平均粒径が小さいものとなる。結晶粒子数の算出は下記の手法を用いて行った。まず、積層セラミックコンデンサの外部電極面を下にして樹脂に埋め、研磨紙を用いて磁器の中央部まで研磨した。次に溶液(HCl=0.09%、HF=0.04%)を用いてケミカルエッチングを25℃で5秒間行い粒界を露出させた。粒界の露出した研磨面の内部電極層に上下挟まれた誘電体層の中央部および端部(内部電極層の端部から約0.1μmほど内側)をそれぞれ電子顕微鏡(SEM)を用いて写真の中央に誘電体層が入るように50000倍で撮影した。この後、撮影した写真の両端にある誘電体層と内部電極層との界面を直線で結び、その直線から誘電体層の厚み方向に垂線を引き、その線上に存在する結晶粒子について、内部電極層との界面から対面の内部電極層との界面までの間にある結晶粒子の個数を評価した。積層セラミックコンデンサの試料数は10個とした。静電容量はLCRメータを用いて、20℃の温度で、AC1V、測定周波数1kHzの条件で測定した。試料数は各100個とした。絶縁抵抗は絶縁抵抗計を用いて、温度25℃において電圧2V、印加時間1分後の値を測定した。試料数は各100個とした。高温負荷処理前後の抵抗減少率は、高温負荷試験を簡易的に短時間で評価できる上述の方法を用いた。この場合の高温負荷条件としては、温度250℃、積層セラミックコンデンサの外部電極に印加する電圧は3Vとした。測定時の電圧は0.1V、周波数は10mHz〜10kHzの間、その処理前後における交流インピーダンスを試料数30個について評価した。HALT(高温高電圧加速信頼性)試験は、125℃および135℃で直流電圧を22V印可した状態で行い、漏れ電流が10mAを超えた時間を故障時間とした。測定終了後、DC=9.45Vにおける換算を行い(L2/L1=(V1/V2)(例えば、L2は9.45Vでの故障時間、L1は22Vでの故障時間、V1は22V、V1は9.45V、n=5)、0.3%累積故障1000時間での判定を行い、1000時間以上を良品とした。結果を表1、2に示した。

Figure 0004771838
The obtained multilayer ceramic capacitor was evaluated as follows. The number of crystal grains existing between the dielectric layers was evaluated. In this case, those having a larger number of crystal particles per dielectric layer have a smaller average particle size. The number of crystal grains was calculated using the following method. First, the external electrode surface of the multilayer ceramic capacitor was buried in a resin and polished to the center of the porcelain using abrasive paper. Next, chemical etching was performed using a solution (HCl = 0.09%, HF = 0.04%) at 25 ° C. for 5 seconds to expose the grain boundaries. Using an electron microscope (SEM), the center and the end (about 0.1 μm from the end of the internal electrode layer) of the dielectric layer sandwiched between the internal electrode layers on the polished surface where the grain boundaries are exposed are respectively used. The photo was taken at 50000x so that the dielectric layer was in the center of the photo. After that, the interface between the dielectric layer and the internal electrode layer at both ends of the photograph taken is connected with a straight line, a perpendicular line is drawn from the straight line in the thickness direction of the dielectric layer, and the crystal electrode existing on the line is connected to the internal electrode. The number of crystal grains between the interface with the layer and the interface with the facing internal electrode layer was evaluated. The number of samples of the multilayer ceramic capacitor was ten. The capacitance was measured using an LCR meter at a temperature of 20 ° C. under the conditions of AC 1 V and measurement frequency 1 kHz. The number of samples was 100 each. The insulation resistance was measured using an insulation resistance meter at a voltage of 2 V and an application time of 1 minute at a temperature of 25 ° C. The number of samples was 100 each. For the resistance reduction rate before and after the high temperature load treatment, the above-described method capable of simply and quickly evaluating the high temperature load test was used. As high temperature load conditions in this case, the temperature was 250 ° C., and the voltage applied to the external electrode of the multilayer ceramic capacitor was 3V. The voltage during measurement was 0.1 V, the frequency was 10 mHz to 10 kHz, and the AC impedance before and after the treatment was evaluated for 30 samples. The HALT (high temperature high voltage acceleration reliability) test was performed with a DC voltage of 22 V applied at 125 ° C. and 135 ° C., and the time when the leakage current exceeded 10 mA was defined as the failure time. After the measurement is completed, conversion is performed at DC = 9.45V (L2 / L1 = (V1 / V2) n (for example, L2 is a failure time at 9.45V, L1 is a failure time at 22V, V1 is 22V, V1 Was 9.45V, n = 5), 0.3% cumulative failure was determined at 1000 hours, and 1000 hours or more was determined to be non-defective, and the results are shown in Tables 1 and 2.
Figure 0004771838

Figure 0004771838
Figure 0004771838

表1、2の結果から明らかなように、第1および第3セラミックパターンに用いたセラミック粉末の平均粒径に対して平均粒径の小さいセラミック粉末を第2セラミックパターンに用いた本発明の試料No.2〜12では、誘電体層間における内部電極層の端部の結晶粒子数が中央部の結晶粒子数よりも多く、内部電極層上における端部の誘電体層厚み当たりの結晶粒子の平均粒径が中央部よりも小さくなったことにより、静電容量が0.79μF〜0.96μFと、比較例である試料No.1に比較してわずかに低下したものの、絶縁抵抗が200MΩ〜260MΩ、高温負荷処理前後での抵抗減少率が1%/min以下となり、高絶縁性かつ高温負荷信頼性(HALT)が得られた。特に、内部電極層の端部の結晶粒子にジルコニアを含有させて、内部電極層の端部における結晶粒子のジルコニアの含有量を内部電極層の中央部における結晶粒子のジルコニアの含有量よりも多くした試料No.3〜5、8〜10では高温負荷処理前後での抵抗減少率が0.7%/min以下であり高い高温負荷信頼性を示した。これに対して、第1〜第3セラミックパターンに同じ平均粒径のセラミック粉末を用いた試料No.1では静電容量は1.03μFと高いものの、絶縁抵抗が180MΩ、高温負荷処理前後での抵抗減少率が1.2%/minと大きかった。   As is clear from the results of Tables 1 and 2, the sample of the present invention in which the ceramic powder having a smaller average particle size than the average particle size of the ceramic powder used in the first and third ceramic patterns was used in the second ceramic pattern. No. 2 to 12, the number of crystal particles at the end of the internal electrode layer between the dielectric layers is larger than the number of crystal particles at the center, and the average particle size of the crystal particles per thickness of the dielectric layer on the internal electrode layer Is smaller than the central portion, and the capacitance is 0.79 μF to 0.96 μF. Although the insulation resistance was slightly lower than 1, the insulation resistance was 200 MΩ to 260 MΩ, and the resistance reduction rate before and after the high temperature load treatment was 1% / min or less, and high insulation and high temperature load reliability (HALT) were obtained. . In particular, zirconia is contained in the end portion of the internal electrode layer so that the content of zirconia in the end portion of the internal electrode layer is larger than the content of zirconia in the center portion of the internal electrode layer. Sample No. In 3-5 and 8-10, the resistance reduction rate before and after the high temperature load treatment was 0.7% / min or less, indicating high high temperature load reliability. On the other hand, sample No. 1 using ceramic powder having the same average particle diameter for the first to third ceramic patterns. 1, the capacitance was as high as 1.03 μF, but the insulation resistance was 180 MΩ, and the resistance reduction rate before and after the high temperature load treatment was as large as 1.2% / min.

本発明の積層セラミックコンデンサの斜視図である。1 is a perspective view of a multilayer ceramic capacitor of the present invention. 本発明の積層セラミックコンデンサのコンデンサ本体内部の誘電体層上に形成された内部電極層を示す平面図であり、内部電極層の面内における図1に示したA−A断面の端部および中央部の位置を示すものである。It is a top view which shows the internal electrode layer formed on the dielectric material layer inside the capacitor | condenser main body of the multilayer ceramic capacitor of this invention, and the edge part and center of the AA cross section shown in FIG. 1 in the surface of an internal electrode layer This indicates the position of the part. (a)は図1のA−A断面図であり、(b)は図1(a)の中央部と端部における誘電体層を構成する結晶粒子を表す模式図である。(A) is AA sectional drawing of FIG. 1, (b) is a schematic diagram showing the crystal grain which comprises the dielectric material layer in the center part and edge part of Fig.1 (a). 本発明における交流インピーダンス測定を用いた誘電体層中の粒界の抵抗の評価手法を示す模式図である。It is a schematic diagram which shows the evaluation method of the resistance of the grain boundary in the dielectric material layer using the alternating current impedance measurement in this invention. (a)本発明の交流インピーダンス測定を用いた誘電体層中の粒界の抵抗評価結果の代表例であり、(b)は積層セラミックコンデンサを構成する誘電体層を構成するコア(中心部)、シェル(外周部)、粒界相および内部電極層と誘電体層との界面の4つの成分を等価回路で表したものである。(A) It is a typical example of the resistance evaluation result of the grain boundary in the dielectric layer using the alternating current impedance measurement of this invention, (b) is the core (center part) which comprises the dielectric material layer which comprises a multilayer ceramic capacitor The four components of the shell (outer peripheral portion), the grain boundary phase, and the interface between the internal electrode layer and the dielectric layer are represented by an equivalent circuit. 本発明の積層セラミックコンデンサの製法を示す工程図である(サイドマージン方向(A−A))。It is process drawing which shows the manufacturing method of the multilayer ceramic capacitor of this invention (side margin direction (AA)). 本発明の積層セラミックコンデンサの製法を示す工程図である(エンドマージン方向(B−B))。It is process drawing which shows the manufacturing method of the multilayer ceramic capacitor of this invention (end margin direction (BB)).

符号の説明Explanation of symbols

1 コンデンサ本体
3 外部電極
5 誘電体層
7 内部電極層
7a 端部
7b 中央部
9 結晶粒子
DESCRIPTION OF SYMBOLS 1 Capacitor body 3 External electrode 5 Dielectric layer 7 Internal electrode layer 7a End part 7b Center part 9 Crystal grain

Claims (2)

複数の結晶粒子からなる誘電体層および内部電極層が交互に積層されたコンデンサ本体と、該コンデンサ本体の前記内部電極層が導出された対向する端面にそれぞれ設けられた一対の外部電極とを具備する積層セラミックコンデンサにおいて、
内部電極パターンを形成し、
該内部電極パターンの周囲の同一面に第1セラミックパターンを形成し、
前記内部電極パターンの端部付近および前記第1セラミックパターン上に、含まれるセラミック粉末の平均粒径D が前記第1セラミックパターンに含まれるセラミック粉末の平均粒径D よりも小さい第2セラミックパターンを形成し、
前記内部電極パターン上における前記第2セラミックパターンの内側の同一面に、含まれるセラミック粉末の平均粒径D が前記第2セラミックパターンに含まれるセラミック粉末の平均粒径D よりも大きい第3セラミックパターンを形成してパターンシートを形成し、
該パターンシートを積層して焼成することによって、
前記外部電極が形成された端面に平行な前記コンデンサ本体の断面における前記内部電極層間の前記誘電体層について、前記内部電極層の平面方向の端部において前記内部電極層の積層方向に引いた直線上に存在する前記結晶粒子数が、前記内部電極層の平面方向の中央部において、これも前記内部電極層の積層方向に引いた直線上に存在する前記結晶粒子数よりも多いとともに、前記内部電極層と同一面の外周における前記誘電体層を構成する結晶粒子の平均粒径が、前記内部電極層間の誘電体層における前記内部電極層の平面方向の端部を構成する前記結晶粒子の平均粒径よりも大きいことを特徴とする積層セラミックコンデンサ。
A capacitor body in which dielectric layers and internal electrode layers made of a plurality of crystal particles are alternately laminated, and a pair of external electrodes provided on opposing end surfaces from which the internal electrode layers of the capacitor body are led out, respectively. In the multilayer ceramic capacitor
Forming an internal electrode pattern,
Forming a first ceramic pattern on the same surface around the internal electrode pattern;
The inner electrode near the end of the pattern and the first ceramic pattern on the second ceramic average particle diameter D 2 of the ceramic powder is smaller than the average particle diameter D 1 of the ceramic powder contained in the first ceramic pattern included Forming a pattern,
On the same surface of the inner side of the second ceramic pattern in the internal electrode pattern, the third average particle diameter D 3 of the ceramic powder is greater than the average particle diameter D 2 of the ceramic powder contained in the second ceramic pattern included Form a ceramic sheet to form a pattern sheet,
By laminating and baking the pattern sheet,
A straight line drawn in the laminating direction of the internal electrode layer at the end in the planar direction of the internal electrode layer with respect to the dielectric layer between the internal electrode layers in the cross section of the capacitor body parallel to the end surface on which the external electrode is formed said number crystal grains present in the above, in the central portion in the planar direction of the internal electrode layer, with more than the number of crystal grains which is also present on a line drawn in the stacking direction of the internal electrode layers, the internal The average particle diameter of the crystal particles constituting the dielectric layer on the outer periphery of the same surface as the electrode layer is the average of the crystal grains constituting the end portion of the dielectric layer between the internal electrode layers in the planar direction of the internal electrode layer. A multilayer ceramic capacitor characterized by being larger than the particle size .
前記結晶粒子がジルコニアを含有し、前記内部電極層の端部における前記誘電体層の前記結晶粒子のジルコニアの含有量は前記内部電極層の中央部における前記誘電体層の前記結晶粒子のジルコニアの含有量よりも多い請求項1に記載の積層セラミックコンデンサ。   The crystal particles contain zirconia, and the zirconia content of the crystal particles of the dielectric layer at the end of the internal electrode layer is the zirconia of the crystal particles of the dielectric layer at the center of the internal electrode layer. The multilayer ceramic capacitor according to claim 1, wherein the content is larger than the content.
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