JP4764682B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

The present invention relates to a manufacturing method of the solid-state imaging equipment, in particular, it relates to manufacturing methods of a solid-state imaging equipment having a MOS transistor as a transfer transistor.

  As one of solid-state imaging devices, an amplification-type solid-state imaging device having an amplification MOS transistor in a pixel cell (unit cell) has been proposed. The amplification type solid-state imaging device includes a photodiode, a transfer transistor, and an amplification MOS transistor in each pixel cell. The signal charge generated by the photodiode is transferred to the amplification transistor by the transfer transistor, and the amplification transistor generates an image signal having a predetermined potential that is amplified according to the charge amount of the signal charge. Thereby, imaging can be performed with high sensitivity.

  Here, a conventional solid-state imaging device will be described with reference to the drawings, taking an amplification type solid-state imaging device as an example. FIG. 7 is a conceptual circuit diagram showing an equivalent circuit of a conventional solid-state imaging device. The solid-state imaging device shown in FIG. 7 includes a pixel unit 1 in which M × N pixel cells 10 that generate image signals are arranged in a matrix of M rows and N columns, and readout of image signals from the pixel unit 1. A vertical selection circuit unit 2 that controls image data in units of rows, a row signal holding circuit unit 3 that holds image signals from each pixel cell 10 in the same row selected by the vertical selection circuit unit 2, and a row signal holding circuit unit 3 A horizontal selection circuit unit 4 that controls reading of a plurality of image signals held in the memory and a load transistor group 5.

  The pixel cell 10 generates a signal charge by photoelectric conversion and accumulates the generated signal charge, a transfer transistor 12 that controls transfer of the signal charge accumulated in the photodiode 11, and a transfer transistor 12 An amplifying transistor 13 for amplifying the signal charge transferred by the pixel cell 10 to generate an image signal, a selection transistor 14 for controlling reading of the image signal to the outside of the pixel cell 10, a drain of the transfer transistor 12, and a gate of the amplifying transistor 13. And a reset transistor 15 for resetting the potential.

  The gate of the transfer transistor 12 is connected to the vertical selection circuit unit 2 via the transfer signal line 21. The transfer transistor 12 transfers the signal charge generated by the photodiode 11 to the gate of the amplification transistor 13 in response to the transfer control signal from the vertical selection circuit unit 2.

  The gate of the amplification transistor 13 is connected to the drain of the transfer transistor 12. The source of the amplification transistor 13 is connected to the drain of the selection transistor 14. The drain of the amplification transistor 13 is connected to a pixel power source (not shown) via the drain line 22. The amplification transistor 13 generates an image signal having a predetermined potential according to the signal charge from the transfer transistor 12 input to the gate of the amplification transistor 13, and sends the generated image signal to the selection transistor 14. Since the amplification transistor 13 is used as a source follower circuit, the image signal sent to the drain of the selection transistor 14 varies depending on the gate potential (amount of signal charge) of the amplification transistor 13. It is amplified by.

  The gate of the selection transistor 14 is connected to the vertical selection circuit unit 2 via a row selection signal line 24. The source of the selection transistor 14 is connected to the load transistor group 5 and the row signal holding circuit unit 3 via the vertical signal line 23. The drain of the selection transistor 14 is connected to the source of the amplification transistor 13. The selection transistor 14 sends an image signal to the vertical signal line 23 in accordance with the row selection signal from the vertical selection circuit unit 2.

  The gate of the reset transistor 15 is connected to the vertical selection circuit unit 2 via the reset signal line 25. The source of the reset transistor 15 is connected to both the drain of the transfer transistor 12 and the gate of the amplification transistor 13. The drain of the reset transistor 15 is connected to the pixel power supply via the drain line 22. The reset transistor 15 resets the potential of the drain of the transfer transistor 12 and the gate of the amplification transistor 13 to a predetermined initial value in response to a reset signal from the vertical selection circuit unit 2.

  Here, a driving method of the conventional solid-state imaging device shown in FIG. 7 will be described. FIG. 8 is a timing chart for explaining an example of the operation of the conventional solid-state imaging device. The description will be made with reference to FIGS. 7 and 8 simultaneously. Hereinafter, the pixel cell located in the i-th row and the j-th column is abbreviated as “(i, j) pixel cell”.

  When the solid-state imaging device is driven, the pixel power supply is changed from the L level (OFF state) to the high potential H level (ON state), and during the driving, the H level is always maintained as shown in FIG.

  In all the pixel cells 10, the vertical selection circuit unit 2 applies only to the row selection signal line 24 of the first row under the condition that the transfer transistor 12, the amplification transistor 13, the selection transistor 14, and the reset transistor 15 are all OFF. The first row selection signal S1 is sent out as shown in FIG. As a result, in each pixel cell 10 ((1, 1) pixel cell to (1, n) pixel cell) in the first row, the selection transistor 14 is turned on during the period in which the first row selection signal S1 is at the H level. The amplifier transistor 13 and the load transistor group 5 constitute a source follower circuit.

  The vertical selection circuit unit 2 sends the first reset signal S2 only to the reset signal line 25 in the first row as shown in FIG. 8 within the period in which the first row selection signal S1 is at the H level. . As a result, in each pixel cell 10 in the first row, the reset transistor 15 is turned on while the first reset signal S2 is at the H level, and the potentials of the drain of the transfer transistor 12 and the gate of the amplification transistor 13 are predetermined. To the initial value of.

  After the initialization by the first reset signal, the vertical selection circuit unit 2 is shown in FIG. 8 in the transfer signal line 21 of the first row within the period in which the first row selection signal S1 is at the H level. As described above, the first transfer signal S3 is transmitted. As a result, in each pixel cell 10 in the first row, the transfer transistor 12 is turned on during the period in which the first transfer signal S3 is at the H level, and the signal charge is transferred to the gate of the amplification transistor 13. The potential of the gate of the amplification transistor 13 is a potential corresponding to the amount of signal charges. At this time, in each pixel cell 10 in the first row, since the selection transistor 14 is in the ON state, it is amplified according to the potential of the gate of the amplification transistor 13 via the selection transistor 14 and the vertical signal line 23. An image signal is sent to the row signal holding unit 3. The image signal of each pixel cell in the first row is held in the row signal holding unit 3. In each pixel cell 10 in the first row, after the image signal is transmitted, the first row selection signal S1 is set to the L level, and the vertical selection transistor 14 is turned off.

  After the first row selection signal S1 becomes L level, the horizontal selection circuit unit 4 sends the first column selection signal S10 to the row signal holding unit 3 via the column selection signal line 26 as shown in FIG. To send. As a result, the image signal of the pixel cell ((1, 1) pixel cell) in the first column held in the row signal holding unit 3 is extracted as a part of the output signal S13. Subsequently, as in the case of the pixel cell 10 in the first column, the horizontal selection circuit unit 4 sequentially supplies column selection signals (second column selection signal S11 to Nth column selection signal S12) to the row signal holding unit 3. By sending the image signal, the image signal of each pixel cell ((1,2) pixel cell to (1, N) pixel cell) from the second column to the Nth column is extracted as a part of the output signal S13. Through the above process, an output (first row output) corresponding to each pixel cell 10 in the first row in the output signal S13 is sent to the outside of the solid-state imaging device.

  Similarly to the case of the first row, as shown in FIG. 8, the second row selection signal S4, the second reset signal S5, the second transfer signal S6, the first column selection signals S10 to Nth. In response to the column selection signal S12, image signals corresponding to all the pixel cells 10 in the second row are extracted as part of the output signal S13 (second row output). Thereafter, similarly, image signals corresponding to all the pixel cells included in the third row to the (M−1) th row are output. Finally, as shown in FIG. 8, the Mth row selection signal S4, the Mth reset signal S5, the Mth transfer signal S6, the first column selection signal S10 to the Nth column selection signal S12 Image signals corresponding to all the pixel cells 10 in the row are extracted as part of the output signal S13 (M-th row output). Thereby, the imaging of one image (still image) is completed. In the case of a moving image, a plurality of images are continuously captured.

  In reading the signal charge accumulated in the photodiode 11, it is preferable that the signal charge is completely transferred. “Complete transfer” means that all signal charges are transferred from the photodiode 11 and the signal charges remaining in the photodiode 11 after transfer are zero. When the driving voltage of the pixel power supply is large exceeding 10V (volt), substantially complete transfer can be realized. However, in recent years, MOS transistors such as the transfer transistor 12 have been miniaturized, and the drive voltage has decreased with the miniaturization. Actually, the drive voltage is reduced to about 2.5V, and complete transfer becomes difficult when the drive voltage is small as described above.

  The reason why complete transfer becomes difficult as the drive voltage decreases will be described below. FIG. 9 is a schematic cross-sectional view showing an example of the structure in the vicinity of a transfer transistor of a conventional solid-state imaging device.

  As shown in FIG. 9, the gate (hereinafter referred to as “transfer gate electrode”) 106 of the transfer transistor 12 (see FIG. 7) is formed on the p-type semiconductor substrate 100 via the gate insulating film 105. In addition, a gate (hereinafter referred to as “reset gate electrode”) 108 of the reset transistor 15 (see FIG. 7) is formed via the gate insulating film 107.

  In the p-type semiconductor substrate 100, a deep photodiode diffusion layer 102 containing an n-type impurity and a shallow photodiode diffusion layer 103 shallower than the deep photodiode diffusion layer 102 and containing a p-type impurity are formed. . The conductivity type of the deep photodiode diffusion layer 103 is n-type, and the conductivity type of the shallow photodiode diffusion layer 103 is p-type. Here, the diffusion layer means a region containing p-type impurities or n-type impurities. Further, the conductivity type of the diffusion layer means the conductivity type of the main part for expressing a specific function. Strictly speaking, in the diffusion layer, the conductivity type may be different in a portion overlapping with another diffusion layer having a different conductivity type or in the vicinity of the boundary between the overlapping portions.

  The p-type semiconductor substrate 100, the deep photodiode diffusion layer 102, and the shallow photodiode diffusion layer 103 constitute an embedded pnp-photodiode 11 (see FIG. 7). Specifically, a pn junction interface is formed in the vicinity of the boundary between the p-type semiconductor substrate 100 and the deep photodiode diffusion layer 102. A pn junction interface is formed in the vicinity of the boundary between the deep photodiode diffusion layer 102 and the shallow photodiode diffusion layer 103.

  The end of the shallow photodiode diffusion layer 103 on the transfer gate electrode 106 side (the right end of the shallow photodiode diffusion layer 103 in FIG. 9) is on the left side of the right end of the deep photodiode diffusion layer 102 so as to be away from the transfer gate electrode 106. positioned. The deep photodiode diffusion layer 102 is not only a part of the pnp-photodiode but also the drain of the transfer transistor.

  A threshold diffusion layer 404 that controls the threshold voltage (channel potential) of the transfer transistor is formed in a region under the transfer gate electrode 106 in the p-type semiconductor substrate 100. The conductivity type of the threshold diffusion layer 404 is p-type. Note that the threshold diffusion layer 404 shown in FIG. 9 is formed in a deep region in order to suppress punch through together with the threshold voltage.

  The manufacturing process of the solid-state imaging device includes a process of heating the semiconductor substrate, such as a heat treatment for activating impurities implanted in each diffusion layer such as the deep photodiode diffusion layer 102 and the threshold diffusion layer 404. . Through these heating steps, impurities are diffused, and the formation region of each diffusion layer is expanded.

  A floating diffusion layer 109 is formed in a region between the transfer gate electrode 106 and the reset gate electrode 108 in the p-type semiconductor substrate 100. The conductivity type of the floating diffusion layer 109 is p-type. The floating diffusion layer 109 constitutes a wiring connecting the drain of the transfer transistor, the source of the reset transistor, and the gate of the amplification transistor 13 (see FIG. 7).

  A power supply diffusion layer 110 to which a drive voltage of a pixel power supply (not shown) is applied is formed in a region adjacent to the region where the reset gate electrode 108 is formed in the p-type semiconductor substrate 100. The conductivity type of power supply diffusion layer 110 is p-type. The power source diffusion layer 110 constitutes the drain of the reset transistor, the drain of the amplification transistor, and the wiring that connects them to the pixel power source.

  When a driving voltage is applied to the power diffusion layer 110 and the transfer transistor is in an OFF state, when a predetermined voltage is applied to the reset gate electrode 108 to turn the reset transistor ON, the floating diffusion layer 109 is The voltage is reset to substantially the same voltage as the driving voltage. Thereafter, the reset transistor is turned off to make the floating diffusion layer 109 electrically floating. Thereafter, when a predetermined voltage is applied to the transfer gate electrode 106 to turn on the transfer transistor, the signal charge accumulated in the deep photodiode diffusion layer 102 is transferred to the floating diffusion layer 109, and the potential of the floating diffusion layer 109 is Becomes a signal potential corresponding to the signal charge. Thereafter, the transfer of the signal charge from the deep photodiode diffusion layer 102 to the floating diffusion layer 109 is completed by turning off the transfer transistor.

  The broken line arrows in FIG. 9 represent the main transfer path of signal charges and the transfer direction of signal charges. The “main transfer path” means a path through which signal charges mainly pass among transfer paths of signal charges, and is the most in the potential distribution in the vertical direction of the semiconductor substrate within a range through which the signal charges pass during transfer. It means a path in which high potential parts are connected along the horizontal direction. The “transfer direction” means a direction in which signal charges move in the vicinity under the transfer gate electrode 106.

  Here, the potential distribution along the main transfer path of the signal charge immediately after the start of the transfer of the signal charge will be described. 10A and 10B are explanatory diagrams for explaining an example of the potential distribution along the main transfer path in the signal charge transfer of the conventional solid-state imaging device. FIG. 10A shows a case where the drive voltage is a high voltage (for example, 10 V), and FIG. 10B shows a case where the drive voltage is a low voltage (for example, 2.8 V to 3.3 V). Represents. In the following, the potential distribution along the main transfer path is simply abbreviated as potential distribution.

  As shown in FIG. 10A, the potential distribution is such that when the driving voltage of the pixel power supply (voltage applied to the power supply diffusion layer) is 10 V or more, the threshold diffusion layer from the deep photodiode diffusion layer 102 side is obtained. A distribution monotonously decreasing toward the 404 side is shown. Note that “monotonically decreasing” means that there is no portion that increases, and that there may be portions that do not change.

  However, when the drive voltage is reduced to about 5 V, there is no distribution that monotonously decreases from the deep photodiode diffusion layer 102 side toward the threshold diffusion layer 404 side. Furthermore, it is known that when the driving voltage is reduced to about 2.8V to 3.3V, a distribution having three irregularities is shown as shown in FIG. 10B (for example, Patent Document 1). Moreover, if the drive voltage is less than 2.8 V, the drop between the three irregularities is further increased. If the potential distribution is uneven, it is likely to be trapped during signal charge transfer. In FIG. 10B, in order to clarify the characteristics of the potential distribution, the concave portion is represented as a square-shaped well and the convex portion is represented as a square-shaped wall. However, the potential distribution is actually smooth. It is represented by a curved surface.

  As described above, since the signal charge to be trapped increases as the power supply voltage decreases, complete transfer becomes difficult. In the following, the concave portion on the deep side in the potential distribution is referred to as a “potential pocket on the deep side”, and the concave portion on the surface side is referred to as a “potential pocket on the front surface side”. The convex portion is referred to as a “potential barrier”.

  In the solid-state imaging device having a general structure, as shown in FIG. 9, the portion A where the deep potential pocket is formed is in the vicinity of the boundary of the threshold diffusion layer 404 inside the deep photodiode diffusion layer 102. Thus, it is located at a depth of about 0.7 μm from the surface of the p-type semiconductor substrate 100. The portion C where the surface side potential pocket is formed is in the vicinity of the pn junction interface formed by the deep photodiode diffusion layer 102 and the p-type threshold diffusion layer 404, and the surface of the p-type semiconductor substrate 100. To a depth of about 0.2 μm. The portion B where the potential barrier is formed is a region between the portion A and the portion C, and is located at a depth of about 0.4 μm from the surface of the p-type semiconductor substrate 100.

  Thus, in recent years, a solid-state imaging device has been proposed that can perform complete transfer even when the drive voltage is low by controlling the potential distribution along the main transfer path (see, for example, Patent Document 1). Here, a method for controlling the potential distribution along the main transfer path will be described. FIG. 11 is a schematic cross-sectional view showing another example of the structure in the vicinity of the transfer transistor in the conventional solid-state imaging device. FIG. 12 is an explanatory diagram for explaining another example of the potential distribution along the main transfer path in the signal charge transfer of the conventional solid-state imaging device.

  As shown in FIG. 11, the diffusion layer corresponding to the threshold diffusion layer 404 shown in FIG. 9 is divided into three diffusion layers having different depths (a deep diffusion layer 414, an intermediate diffusion layer 424, and a shallow diffusion layer). 434). The deep diffusion layer 414, the intermediate diffusion layer 424, and the shallow diffusion layer 434 have a portion A where a potential pocket on the deep side may be formed, a portion B where a potential barrier may be formed, and a surface side, respectively. It is formed in accordance with the depth of the portion C where the potential pocket may be formed.

  The concentration of the p-type impurity (p-type impurity for the deep diffusion layer) for forming the deep diffusion layer 414 is adjusted so as not to generate a potential pocket on the deep side. In the vicinity of the portion A, the concentration of the p-type impurity for the deep diffusion layer is higher than the concentration of the p-type impurity (p-type impurity for the threshold diffusion layer) for forming the conventional threshold diffusion layer 404 (see FIG. 9). If the voltage is also increased, the potential at the bottom of the potential pocket on the deep side increases. Therefore, by appropriately controlling the concentration distribution of the p-type impurity for the deep diffusion layer, the generation of the potential pocket on the deep side in the vicinity of the portion A can be suppressed as shown in FIG.

  The concentration of the p-type impurity (p-type impurity for the intermediate diffusion layer) or the n-type impurity (n-type impurity for the intermediate diffusion layer) for forming the intermediate diffusion layer 424 is adjusted so as not to generate a potential barrier. Yes. If the concentration of the p-type impurity for the intermediate diffusion layer is substantially decreased from the concentration of the p-type impurity for the conventional threshold diffusion layer in the vicinity of the portion B, the potential at the top of the potential barrier is lowered. Therefore, by appropriately controlling the impurity concentration distribution in the intermediate diffusion layer, the generation of a potential barrier in the vicinity of the portion B can be suppressed as shown in FIG. Here, substantially reducing the concentration of the p-type impurity in the vicinity of the portion B means that the concentration of the hole carrier only needs to be decreased, and the concentration of the p-type impurity may be decreased. The n-type impurity concentration may be increased.

  The concentration of the p-type impurity (shallow diffusion layer impurity) for forming the shallow diffusion layer 434 is adjusted so as not to generate a potential pocket on the surface side. As in the case of the deep diffusion layer 414, by appropriately controlling the concentration distribution of the p-type impurity for the shallow diffusion layer, as shown in FIG. Can be suppressed.

  As described above, the potential distribution monotonously decreases from the deep photodiode diffusion layer 102 side toward the shallow diffusion layer 434 side by suppressing the generation of the potential pocket on the deep side, the potential barrier, and the potential pocket on the surface side. Can be made. Thereby, complete transfer of signal charges can be realized.

  By the way, in order to improve the imaging performance of a solid-state imaging device, a technique for reducing dark current is generally known. Hereinafter, a solid-state imaging device with reduced dark current will be described. FIG. 13 is a schematic cross-sectional view partially showing another structural example in the vicinity of the transfer transistor in the conventional solid-state imaging device. The solid-state imaging device shown in FIG. 13 further includes a p-type surface boron layer 413 formed on the surface side of the p-type semiconductor substrate 100 so as to cover the n-type deep photodiode diffusion layer 102. With such a configuration, dark current is reduced. In general, a mask for forming the n-type deep photodiode diffusion layer 102 is also used as a mask for forming the p-type surface boron layer 413. Therefore, as shown in FIG. 13, the n-type deep photodiode diffusion layer 102 and the p-type surface boron layer 413 are formed in different depths in substantially the same region.

Further, for example, Patent Document 2 discloses a solid-state imaging device that improves the sensitivity of a photodiode and realizes complete transfer at a low voltage. This conventional solid-state imaging device further includes a p-type diffusion layer formed in a region in the semiconductor substrate from below the floating diffusion layer to below the n-type deep photodiode diffusion layer. In this conventional solid-state imaging device, the sensitivity of the photodiode is improved and the transfer efficiency at a low voltage is improved by improving the transfer efficiency of the signal charge generated in the deep part of the n-type deep photodiode diffusion layer. Let
JP 2004-253737 A JP 2001-53260 A

  When an additional diffusion layer (corresponding to the p-type surface boron layer) is further formed in the solid-state imaging device having the shallow diffusion layer disclosed in Patent Document 1 described above, there is variation in suppression of potential pocket generation for each product. There was a problem that occurred.

  This is because boron implantation is performed to a part of the shallow diffusion layer by boron implantation for forming the additional diffusion layer. This is caused by misalignment between the mask for forming the additional diffusion layer and the mask for forming the shallow diffusion layer. Specifically, a region where they overlap is formed between the additional diffusion layer and the shallow diffusion layer. As a result, a region having an impurity concentration higher than these occurs between the additional diffusion layer and the shallow diffusion layer. A region having a high impurity concentration causes a potential barrier on the surface side. Accordingly, the generation / non-occurrence of the potential pocket on the surface side causes a large variation due to a manufacturing error such as a mask misalignment. This means that the manufacturing margin is extremely small and not suitable for mass production.

  Further, the solid-state imaging device disclosed in Patent Document 2 has improved transfer efficiency when transferring signal charges generated in a deep portion of the deep photodiode diffusion layer from the generation portion to the surface side of the deep photodiode diffusion layer. it can. However, the solid-state imaging device disclosed in the above-mentioned Patent Document 2 cannot suppress the generation of the surface-side potential pocket described in the above-mentioned Patent Document 1.

The present invention has been made in view of the above-described problems. It is difficult for dark current to occur in a photodiode, the signal charge transfer efficiency along the main transfer path is high, and the transfer efficiency depends on manufacturing errors and the like. and to provide a manufacturing method of a solid-state imaging equipment not.

The first manufacturing method of the solid-state imaging device according to the present invention, a portion of the pixel cell forming region in the upper portion of the semiconductor substrate, a step of forming a deep photodiode diffusion layer of the first conductivity type (a), the deep to include at least part of the surface side of the photodiode diffusion layer, the pixel cell formation region, (b) forming an additional diffusion layer of the second conductivity type, the whole of the pixel cell forming region, the A second conductive type shallow photodiode diffusion layer in the pixel cell forming region so as to include a step (c) of forming a two conductive type shallow diffusion layer and a part of the surface side of the deep photodiode diffusion layer; a step of forming a (d), and (e) forming an insulating film on a region adjacent to the deep photodiode diffusion layer before Symbol semiconductor substrate, on the insulating film, the transfer gate electrode formation to step (f When the insulating layer and is interposed between the transfer gate electrode, the deep photodiode so as to be separated with both diffusion layers and said shallow photodiode diffusion layer, forming a floating diffusion layer in the pixel cell forming region (g) and wherein the deep photodiode diffusion layer accumulates signal charges generated by the incidence of external light, the transfer gate electrode, the deep the signal charge from the photodiode diffusion layer to the floating diffusion layer The additional diffusion layer and the shallow diffusion layer are shallower than the shallow photodiode diffusion layer . In the following, the solid-state imaging device obtained by this method is also referred to as “first solid-state imaging device”.

The second manufacturing method of the solid-state imaging device according to the present invention includes the step (a) of forming an additional diffusion layer of the second conductivity type over the entire pixel cell formation region on the semiconductor substrate, and the additional diffusion. A step (b) of forming a first conductivity type deep photodiode diffusion layer in the pixel cell formation region so as to include a part of the layer; and adjacent to the deep photodiode diffusion layer in the pixel cell formation region A step (c) of forming a second conductivity type shallow diffusion layer in the region , and a second conductivity type shallow region in the pixel cell formation region so as to include a part of the surface side of the deep photodiode diffusion layer. A step (d) of forming a photodiode diffusion layer, a step (e) of forming an insulating film on a region of the semiconductor substrate adjacent to the deep photodiode diffusion layer, and a transfer gate on the insulating film. electrode And forming to step (f), the insulating film and is interposed between the transfer gate electrodes, to be separated and both the deep photodiode diffusion layer and the shallow photodiode diffusion layer, floating on the pixel cell forming region and forming a diffusion layer (g), the shallow diffusion layer includes a region under the transfer gate electrode in said pixel cell forming region, the deeper photodiode diffusion layer is produced by the incidence of outside light Signal charge is accumulated, the transfer gate electrode controls transfer of the signal charge from the deep photodiode diffusion layer to the floating diffusion layer, and the additional diffusion layer and the shallow diffusion layer are the shallow photodiode diffusion. Shallow than layer . In the following, the solid-state imaging device obtained by this method is also referred to as “second solid-state imaging device”.

According to the present invention, on the transfer efficiency of the dark current is hardly generated in the photodiode, and signal charges along the main transfer path is high, the manufacturing method of the solid-state imaging equipment that transfer efficiency does not depend on fabrication errors or the like Can be provided.

The first solid-state imaging device obtained by the first manufacturing method of the solid-state imaging device according to the present invention is formed in the pixel cell formation region so as to include at least part of the surface side of the deep photodiode diffusion layer. A second conductivity type additional diffusion layer shallower than the shallow photodiode diffusion layer and a second conductivity type shallow diffusion layer formed over the pixel cell formation region and shallower than the shallow photodiode diffusion layer. Yes. As a result, a region having a higher impurity concentration is not formed near the boundary between the additional diffusion layer and the shallow diffusion layer. That is, the additional diffusion layer and the shallow diffusion layer are adjacent to each other, and the concentration of these impurities is constant regardless of the location. Therefore, no potential barrier is generated, and no additional current is generated since the additional diffusion layer is formed. In this case, the additional diffusion layer has a higher impurity concentration than the shallow diffusion layer.

Further, the second solid-state imaging device obtained by the second manufacturing method of the solid-state imaging device according to the present invention is formed in a region adjacent to the deep photodiode diffusion layer in the pixel cell formation region , and the shallow photodiode A shallow diffusion layer of the second conductivity type shallower than the diffusion layer, and an additional diffusion layer of the second conductivity type formed over the entire pixel cell formation region above the semiconductor substrate and shallower than the shallow photodiode diffusion layer. . As a result, a region having a higher impurity concentration is not formed near the boundary between the additional diffusion layer and the shallow diffusion layer. That is, the additional diffusion layer and the shallow diffusion layer are adjacent to each other, and the concentration of these impurities is constant regardless of the location. Therefore, no potential barrier is generated, and no additional current is generated since the additional diffusion layer is formed. In this case, the impurity concentration of the shallow diffusion layer is higher than that of the additional diffusion layer.

  Further, the first and second solid-state imaging devices of the present invention may be MOS type solid-state imaging devices or CCD type solid-state imaging devices. The solid-state imaging device according to the present invention may have the same configuration as any known solid-state imaging device except for the shallow diffusion layer and the additional diffusion layer.

Each diffusion layer formed on the semiconductor substrate is formed by implanting a predetermined impurity in a range from the surface of the semiconductor substrate to a predetermined depth through the opening of the mask. In the diffusion layer, the impurities are distributed in a predetermined concentration distribution according to the type of semiconductor substrate, the type of impurities, the implantation energy, the implantation amount (dose amount), and the like in the depth direction (vertical direction). In this specification, each diffusion layer formed in a semiconductor substrate means a portion where the concentration of impurities implanted to form each diffusion layer is 10 ¹⁵ cm ⁻³ or more. The boundary of each diffusion layer can be determined based on the measurement of the concentration profile by SIMS or the like.

The “first conductivity type impurity” described later means an n-type impurity (an element that functions as a donor) or a p-type impurity (an element that functions as an acceptor) inside the semiconductor substrate. The “second conductivity type impurity” described later means a p-type impurity when the first conductivity type impurity is an n-type impurity, and n when the first conductivity type impurity is a p-type impurity. Means type impurities. First second conductivity type impurity to be described later, the second second conductivity type impurity and the third of the second conductivity type impurity, all may be the same kinds of elements, at least one differs from the other types of It may be an element.

  The conductivity type at an arbitrary portion inside the semiconductor substrate is determined by the concentration of the p-type impurity and the concentration of the n-type impurity contained in the portion. In the following, the conductivity type in the region where the vacancy carrier concentration due to the p-type impurity is higher than the concentration of electron carriers due to the n-type impurity is referred to as p-type, and the opposite case is referred to as n-type.

  In the case where a deep photodiode diffusion layer is formed by implanting an n-type impurity into the p-type diffusion region, a p-type semiconductor substrate, an n-type semiconductor substrate having a p-type well formed thereon, or a p-type well is formed. An intrinsic semiconductor substrate can be used. In the opposite case, an n-type semiconductor substrate, a p-type semiconductor substrate in which an n-type well is formed, or an intrinsic semiconductor substrate in which an n-type well is formed can be used as the semiconductor substrate.

In the first and second manufacturing methods of the solid-state imaging device, preferably, the second conductivity deeper than the shallow diffusion layer is formed in the pixel cell formation region so as to include at least a part of the region under the transfer gate electrode. The method further includes a step (h) of forming a deep diffusion layer. Thereby, punch-through in the transfer transistor can be reduced.

In the first and second manufacturing methods of the solid-state imaging device, preferably, the pixel cell formation region is deeper than the shallow diffusion layer and deeper so as to include at least a part of the region under the transfer gate electrode. The method further includes a step (i) of forming an intermediate diffusion layer of the first conductivity type or the second conductivity type that is shallower than the diffusion layer. Thereby, the formation of the deep diffusion layer makes it possible to suppress or reduce the height of the potential barrier that is easily generated.

In the first manufacturing method of the solid-state imaging device of the present invention, preferably, the additional diffusion layer is formed in the pixel cell formation region by ion implantation from a direction oblique to the semiconductor substrate. Accordingly, since the amount of the second conductivity type impurity entering when the additional diffusion layer is formed becomes constant, the additional diffusion layer can be manufactured with high accuracy so as to have a predetermined depth.

In the first manufacturing method of the solid-state imaging device of the present invention, preferably, the pixel cell formation region is formed by ion implantation from a direction having an angle of 10 ° to 45 ° with respect to the vertical direction of the semiconductor substrate. The additional diffusion layer is formed. Accordingly, since the amount of the second conductivity type impurities entering when forming the additional diffusion layer becomes constant, the additional diffusion layer can be manufactured with high accuracy so as to have a predetermined depth.

  Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be specifically described with reference to the drawings.

(Embodiment 1)
In Embodiment 1, a first solid-state imaging device according to the present invention will be described. In the first solid-state imaging device, the configuration of any known solid-state imaging device may be the same except for the shallow diffusion layer and the additional diffusion layer in each pixel cell. The equivalent circuit of the first solid-state imaging device is the same as the circuit shown in FIG. FIG. 1 is a schematic cross-sectional view partially showing a structural example in the vicinity of a transfer transistor in one pixel cell of a solid-state imaging device according to Embodiment 1 of the present invention. In addition, about the member which has the substantially same function as the past, the same referential mark is attached | subjected and the detailed description is abbreviate | omitted.

  As shown in FIG. 1, the solid-state imaging device of Embodiment 1 includes a p-type semiconductor substrate (semiconductor substrate) 100 and a deep photodiode diffusion layer having an n-type impurity (first first conductivity type impurity). 102, a shallow photodiode diffusion layer 103 having a p-type impurity (first second conductivity type impurity), a floating diffusion layer 109 having an n-type impurity, a gate insulating film (insulating film) 105, and a transfer gate electrode 106.

  The p-type semiconductor substrate 100, the deep photodiode diffusion layer 102, and the shallow photodiode diffusion layer 103 constitute an embedded pnp-photodiode 11 (see FIG. 7).

  An additional diffusion layer 113 having a p-type impurity (second second conductivity type impurity) is further formed on the p-type semiconductor substrate 100 so as to include at least part of the surface side of the deep photodiode diffusion layer 102. Yes. The p-type semiconductor substrate 100 has a shallow diffusion layer 134 having a p-type impurity (third second conductivity type impurity) so as to include a region under the transfer gate electrode 106 and the additional diffusion layer 113 on the surface thereof. Further formed. Both the shallow diffusion layer 134 and the additional diffusion layer 113 are shallower than the shallow photodiode diffusion layer 103. Although FIG. 1 illustrates the case where the additional diffusion layer 113 is shallower than the shallow diffusion layer 134, the shallow diffusion layer 134 may be shallower than the additional diffusion layer 113. The concentration distribution of the p-type impurity in the shallow diffusion layer 134 and the concentration distribution of the p-type impurity in the additional diffusion layer 113 are preferably controlled so as not to generate a potential pocket on the surface side. This improves the signal charge transfer efficiency.

  Since both the shallow diffusion layer 134 and the additional diffusion layer 113 contain p-type impurities, the impurity concentration in the region where they overlap is the impurity content of the shallow diffusion layer 134 and the impurity content of the additional diffusion layer 113. It depends on the amount. Therefore, in the shallow diffusion layer 134, the impurity concentration differs between the region where the additional diffusion layer 113 is formed and the region where the additional diffusion layer 113 is not formed. For this reason, the horizontal impurity concentration on the surface side of the shallow diffusion layer 134 has different values around the region under the transfer gate electrode 106, with the end of the region where the additional diffusion layer 113 is formed as a boundary. Therefore, unlike the conventional solid-state imaging device, a region having a higher impurity concentration than the additional diffusion layer and the shallow diffusion layer does not occur, and a potential barrier does not occur. Further, as shown in FIG. 1, the shallow diffusion layer 134 is preferably formed on the entire surface of the region surrounded by the element isolation film 101.

  FIG. 1 illustrates a case where the right end position of the additional diffusion layer 113 and the right end position of the deep photodiode diffusion layer 102 are substantially the same. Here, that the positions are substantially the same means that the positions are not intentionally different, and includes the case where the positions are not exactly the same due to a manufacturing error, a diffusion error, or the like. Means. The production error means an alignment error between the resist mask when implanting the p-type impurity for the additional diffusion layer and the resist mask when implanting the n-type impurity for the deep photodiode diffusion layer. The diffusion error means a diffusion width error resulting from a difference in diffusion rate in the heat treatment depending on the type of implanted impurity.

  In the solid-state imaging device according to the first embodiment, the dark current is reduced because the additional diffusion layer 113 is formed. In order to satisfactorily reduce the dark current, the additional diffusion layer 113 is formed substantially only in the entire region on the surface side of the deep photodiode diffusion layer 102 as shown in FIG. preferable. Further, in the manufacturing process described later, a resist mask for forming the deep photodiode diffusion layer 102 and the additional diffusion layer 113 can also be used, and the manufacturing process can be simplified. In order to satisfactorily reduce the dark current, the p-type impurity for the additional diffusion layer is preferably boron.

  Further, as shown in FIG. 1, the deep diffusion layer 114 is preferably formed in the p-type semiconductor substrate 100 so as to include at least a part of the region under the transfer gate electrode 106. The deep diffusion layer 114 contains a p-type impurity (fourth second conductivity type impurity) for the deep diffusion layer, and is formed deeper than the shallow diffusion layer 134. The conductivity type of the deep diffusion layer 114 is p-type. By controlling the vertical concentration distribution of the p-type impurity for the deep diffusion layer, punch-through in the transfer transistor can be reduced.

  When the deep diffusion layer 114 is formed, a potential barrier is easily generated. However, by providing the intermediate diffusion layer 124, the generation of the potential barrier can be suppressed or the height thereof can be reduced. Specifically, as shown in FIG. 1, intermediate diffusion layer 124 is preferably formed on p-type semiconductor substrate 110 so as to include at least part of the region under transfer gate electrode 106. The intermediate diffusion layer 124 is formed deeper than the shallow diffusion layer 134 and shallower than the deep diffusion layer 114, and is used for the intermediate diffusion layer p-type impurity (fifth second conductivity type impurity) or intermediate diffusion layer. An n-type impurity (second first conductivity type impurity) is contained. The impurity for the intermediate diffusion layer may be appropriately selected in consideration of the vertical concentration distribution of the n-type impurity for the deep photodiode diffusion layer and the vertical concentration distribution of the p-type impurity for the deep diffusion layer. By appropriately controlling the concentration distribution of impurities in the intermediate diffusion layer 124, generation of a potential barrier can be suppressed. The intermediate diffusion layer 124 contains a p-type impurity for the intermediate diffusion layer or an n-type impurity for the intermediate diffusion layer, and in either case, the conductivity type as a result of subtracting the donor concentration from the acceptor concentration is p-type.

  In addition, by controlling the vertical concentration distribution of impurities in the intermediate diffusion layer 124, generation of a potential barrier can be suppressed or its height can be reduced.

  The deep diffusion layer 114 and the intermediate diffusion layer 124 are not essential components of the present invention. However, in order to realize complete transfer of signal charges, it is preferable to form both the deep diffusion layer 114 and the intermediate diffusion layer 124 or only the deep diffusion layer 114. In addition, if the generation of the potential pocket cannot be suppressed, a deeper diffusion layer than the deep diffusion layer 114 may be formed.

  Further, on the surface of the p-type semiconductor substrate 100, the positions of the right end and the left end of the deep diffusion layer 114 are substantially the same as the positions of the right end and the left end of the intermediate diffusion layer 124, respectively, as shown in FIG. Preferably there is. In this case, a resist mask for forming the deep diffusion layer 114 and the intermediate diffusion layer 124 can also be used in the manufacturing process described later, and the manufacturing process can be simplified.

  Note that in the p-type semiconductor substrate 100, the position of a portion where a deep potential pocket may occur (hereinafter abbreviated as “deep potential pocket portion”) and a portion where a potential barrier may occur (hereinafter referred to as “deep potential pocket portion”). In FIG. 5, the position of “potential barrier portion” is shifted not only in the vertical direction but also in the horizontal direction. Therefore, when the horizontal displacement between the position of the deep potential pocket part and the position of the potential barrier part is large, the left end position of the deep diffusion layer 114 and the left end position of the intermediate diffusion layer 124 are not the same. May be preferred.

  Note that, on the surface of the p-type semiconductor substrate 100, the position of the right end of the deep diffusion layer 114 is preferably on the right side of the position of the left end of the floating diffusion layer 109 as shown in FIG. As a result, punch-through of the transfer transistor is favorably reduced. Further, as described in Patent Document 2 described above, the transfer efficiency of signal charges generated in a deep portion of the deep photodiode diffusion layer 102 is improved, and the sensitivity of the deep photodiode diffusion layer 102 is improved.

  As described above, the solid-state imaging device according to the first embodiment is unlikely to generate dark current and has high signal charge transfer efficiency along the main transfer path. Therefore, the quality of the captured image is high. In addition, it is suitable for mass production because variations in transfer efficiency due to manufacturing errors and the like hardly occur.

  In the solid-state imaging device of the first embodiment, the concentration of the p-type impurity in the additional diffusion layer 113 located near the surface of the deep photodiode diffusion layer 102 that contributes to the reduction of dark current contributes to the adjustment of the threshold voltage. This is a preferable structure when it is desired to make the concentration higher than the concentration of the p-type impurity in the shallow diffusion layer 134 located near the surface under the gate electrode 106.

  Here, a method for manufacturing the solid-state imaging device of the first embodiment shown in FIG. 1 will be described. 2A to 2D are schematic cross-sectional views for each process for explaining an example of the method for manufacturing the solid-state imaging device according to Embodiment 1 of the present invention. 2A to 2D partially show structural examples in the vicinity of the transfer transistor in one pixel cell.

  First, as shown in FIG. 2A, an element isolation film 101 is formed on a p-type semiconductor substrate 100. After the element isolation film 101 is formed, a resist mask 141 is formed. An n-type impurity for a deep photodiode diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 141. Thereby, the n-type impurity for the deep photodiode diffusion layer is implanted in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth with a predetermined concentration distribution. In this way, the deep photodiode diffusion layer 102 is formed. Subsequently, the p-type impurity for the additional diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 141. Thereby, the p-type impurity for the additional diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the additional diffusion layer 113 is formed. After forming the deep photodiode diffusion layer 102 and the additional diffusion layer 113, the resist mask 141 is removed.

  Next, as shown in FIG. 2B, a resist mask 142 is formed. After the resist mask 142 is formed, a p-type impurity for a deep diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. Thus, the p-type impurity for the deep diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the deep diffusion layer 114 is formed. Subsequently, a p-type impurity or n-type impurity for the intermediate diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. Thereby, p-type impurities or n-type impurities for the intermediate diffusion layer are implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the intermediate diffusion layer 124 is formed. After forming the deep diffusion layer 114 and the intermediate diffusion layer 124, the resist mask 142 is removed.

  Next, a resist mask (not shown) having an opening in the entire pixel cell formation region is formed. After forming the resist mask, p-type impurities for shallow diffusion layers are ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask. As a result, the p-type impurity for the shallow diffusion layer is implanted in a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth, and as shown in FIG. Layer 134 is formed. After the shallow diffusion layer 134 is formed, the resist mask is removed. At the time of ion implantation for forming the shallow diffusion layer 134, the p-type impurity for the shallow diffusion layer is also ion-implanted into the additional diffusion layer 113. As a result, the concentration distribution of the additional diffusion layer 113 changes. That is, the final concentration distribution of the additional diffusion layer 113 is determined when the shallow diffusion layer 134 is formed. Therefore, in the manufacturing process shown in FIG. 2B, the impurity concentration distribution of the additional diffusion layer 113 is adjusted in consideration of ion implantation in the manufacturing process of FIG. In the solid-state imaging device of the first embodiment, the concentration of the additional diffusion layer 113 is higher than the concentration of the shallow diffusion layer 134.

  As described above, if the formation position of the additional diffusion layer 113 is shifted due to a manufacturing error or the like, the boundary position between the additional diffusion layer 113 and the shallow diffusion layer 134 is shifted. However, the concentration distribution in the vicinity of the boundary between the additional diffusion layer 113 and the shallow diffusion layer 134 does not vary due to manufacturing errors or the like. That is, the impurity concentration of the additional diffusion layer 113 is higher than the impurity concentration of the shallow diffusion layer 134 at any location. Therefore, a potential barrier does not occur, and no problem occurs in the operation of the solid-state imaging device of the first embodiment. Note that the shift of the boundary position between the additional diffusion layer 113 and the shallow diffusion layer 134 caused by a manufacturing error or the like is such that it does not cause a problem in the operation of the solid-state imaging device of the first embodiment.

  Note that the vertical concentration distributions of the p-type impurities for the shallow diffusion layer and the additional diffusion layer are such that the dark current is reduced and the threshold voltage of the transfer transistor becomes a value within a desired range. In addition, these concentration distributions may be optimized so that the surface-side potential barrier in the potential distribution along the main transfer path does not occur or the height of the surface-side potential barrier is low.

  The dark current is adjusted mainly by controlling the vertical concentration distribution of the p-type impurity for the additional diffusion layer in consideration of the concentration distribution of the p-type impurity for the shallow diffusion layer. The additional diffusion layer 113 includes not only the p-type impurity for the additional diffusion layer and the p-type impurity for the shallow diffusion layer, but also impurities for other diffusion layers overlapping the additional diffusion layer 113. Therefore, the vertical concentration distribution of the p-type impurity for the additional diffusion layer may be controlled in consideration of the vertical concentration distribution of the impurity for the other diffusion layer. Specifically, in the case of the configuration shown in FIG. 1, the vertical concentration distribution of the p-type impurity for the additional diffusion layer is controlled only in consideration of the vertical concentration distribution of the p-type impurity for the shallow diffusion layer. Absent. In addition, the vertical concentration distribution of the p-type impurity for the additional diffusion layer is also considered in consideration of the vertical concentration distribution of the n-type impurity for the deep photodiode diffusion layer and the vertical concentration distribution of the p-type impurity for the shallow photodiode diffusion layer. To control.

  On the other hand, the threshold voltage of the transfer transistor is adjusted mainly by controlling the vertical concentration distribution of the p-type impurity for the shallow diffusion layer. When another diffusion layer overlapping the shallow diffusion layer 134 is formed under the transfer gate electrode 106, the vertical concentration distribution of the p-type impurity for the shallow diffusion layer is the vertical concentration distribution of the impurity for the other diffusion layer. Control is also taken into account. For example, in the case of the configuration shown in FIG. 1, the vertical concentration distribution of the p-type impurity for the shallow diffusion layer is the vertical concentration distribution of the p-type impurity for the additional diffusion layer and the vertical concentration of the p-type impurity for the deep diffusion layer. It is controlled in consideration of the distribution and the vertical concentration distribution of the p-type impurity or n-type impurity for the intermediate diffusion layer.

  Next, a resist mask (not shown) is formed on the p-type semiconductor substrate 100, and p-type impurities for shallow photodiode diffusion layers are ion-implanted. As shown in FIG. 2D, a shallow photodiode diffusion layer 103 is formed and the resist mask is removed. After forming the shallow photodiode diffusion layer 103, a gate insulating film 105, a transfer gate electrode 106, a gate insulating film 107, and a reset gate electrode 108 are formed. Note that the gate electrode (not shown) of the amplification transistor, the gate electrode (not shown) of the selection transistor, and the like may be formed simultaneously with the transfer gate electrode 106 and the reset gate electrode 108. After the transfer gate electrode 106 and the reset gate electrode 108 are formed, a resist mask (not shown) is formed. Through the opening of the formed resist mask, n-type impurities are ion-implanted, and the floating diffusion layer 109 and the power source diffusion layer 110 are formed in a lump. Note that the transfer gate electrode 106 or the reset gate electrode 108 is used as part of the mask in the formation of the floating diffusion layer 109 and the power supply diffusion layer 110. Accordingly, the end of the floating diffusion layer 109 on the transfer gate electrode 106 side and the reset gate electrode 108 side, and the end of the power supply diffusion layer 110 on the reset gate electrode 108 side are connected to the transfer gate electrode 106 or the reset gate electrode 108. Can be positioned in a self-aligning manner.

  Through the above process, the main part of the pixel cell of the solid-state imaging device of Embodiment 1 can be manufactured. In manufacturing the solid-state imaging device according to the first embodiment, any known technique may be used. The order of forming the deep photodiode diffusion layer 102, the shallow photodiode diffusion layer 103, the additional diffusion layer 113, the deep diffusion layer 114, the intermediate diffusion layer 124, and the shallow diffusion layer 134 can be changed as appropriate.

  For example, the additional diffusion layer 113 may be formed after the transfer gate electrode 106 is formed. Thereby, since the transfer gate electrode 106 serves as a resist mask, the additional diffusion layer 113 can be positioned in a self-aligned manner with respect to the installation position of the transfer gate electrode 106. This manufacturing method will be described below.

  3A to 3D are schematic cross-sectional views for each process for explaining another example of the method for manufacturing the solid-state imaging device according to Embodiment 1 of the present invention. FIGS. 3A to 3D partially illustrate structural examples in the vicinity of the transfer transistor in one pixel cell.

  First, as shown in FIG. 3A, an element isolation film 101 is formed on a p-type semiconductor substrate 100. After the element isolation film 101 is formed, a resist mask 141 is formed. An n-type impurity for a deep photodiode diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 141. Thereby, the n-type impurity for the deep photodiode diffusion layer is implanted in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth with a predetermined concentration distribution. In this way, the deep photodiode diffusion layer 102 is formed. After forming the deep photodiode diffusion layer 102, the resist mask 141 is removed.

  Next, as shown in FIG. 3B, a resist mask 142 is formed. After forming the resist mask 142, p-type impurities for deep diffusion layers are ion-implanted into the p-type semiconductor substrate 100 through the openings of the resist mask 142. Thus, the p-type impurity for the deep diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the deep diffusion layer 114 is formed. Subsequently, a p-type impurity or n-type impurity for the intermediate diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. Thereby, p-type impurities or n-type impurities for the intermediate diffusion layer are implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the intermediate diffusion layer 124 is formed. After forming the deep diffusion layer 114 and the intermediate diffusion layer 124, the resist mask 142 is removed.

  Next, a resist mask (not shown) having an opening in the entire pixel cell formation region is formed. After forming the resist mask, p-type impurities for shallow diffusion layers are ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask. As a result, the p-type impurity for the shallow diffusion layer is implanted in a predetermined concentration distribution in the range from the surface of the p-type semiconductor substrate 100 to the predetermined depth, and the shallow diffusion is performed as shown in FIG. Layer 134 is formed. After the shallow diffusion layer 134 is formed, the resist mask is removed.

  Next, as shown in FIG. 3D, a gate insulating film 105, a transfer gate electrode 106, a gate insulating film 107, and a reset gate electrode 108 are formed, and an additional diffusion layer 113 is also formed. Note that the gate electrode (not shown) of the amplification transistor, the gate electrode (not shown) of the selection transistor, and the like may be formed simultaneously with the transfer gate electrode 106 and the reset gate electrode 108. After the transfer gate electrode 106 and the reset gate electrode 108 are formed, a resist mask (not shown) is formed. A p-type impurity for the additional diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the formed resist mask. Thereby, the p-type impurity for the additional diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the additional diffusion layer 113 is formed. Note that the transfer gate electrode 106 may be used as part of the mask in the formation of the additional diffusion layer 113. Thereby, the end of the additional diffusion layer 113 on the transfer gate electrode 106 side can be positioned in a self-aligned manner with respect to the transfer gate electrode 106. Further, since the additional diffusion layer 113 is formed by further ion-implanting the portion where the shallow diffusion layer 134 has already been formed, the concentration distribution of the additional diffusion layer 113 and the shallow diffusion layer 134 has a predetermined distribution at the boundary. There is no difference from the value. Note that the concentration of ion implantation for forming the additional diffusion layer 113 is determined in consideration of the concentration of the shallow diffusion layer 134. As described above, the boundary position between the additional diffusion layer 113 and the shallow diffusion layer 134 is determined in a self-aligned manner with respect to the position of the transfer gate electrode 106. Further, the concentration distribution at the boundary between the additional diffusion layer 113 and the shallow diffusion layer 134 has a predetermined value. For these reasons, no potential pocket is generated, and no problem occurs in the operation of the solid-state imaging device of the first embodiment.

  Note that ion implantation for forming the additional diffusion layer 113 may be performed at an angle with respect to the p-type semiconductor substrate 100, that is, so-called oblique implantation. Thereby, since the amount of impurities entering is constant, the additional diffusion layer 113 can be manufactured with high accuracy so as to have a predetermined depth. Specifically, for example, the ion beam is incident at an angle of 45 ° with respect to the perpendicular of the p-type semiconductor substrate 100, whereby the oblique implantation is performed. Note that the ion implantation acceleration energy may be about 15 eV. At this time, the end portion of the additional diffusion layer 113 enters the transfer gate electrode 106 side by about 0.1 μm with respect to the end portion of the transfer gate electrode 106. The angle of ion implantation may be 7 ° or more with respect to the normal of the p-type semiconductor substrate 100. Preferably, the angle of ion implantation may be 10 ° to 45 ° with respect to the normal of the p-type semiconductor substrate 100. For example, the angle of ion implantation is 25 ° and 45 ° with respect to the normal of the p-type semiconductor substrate 100.

  After forming the additional diffusion layer 113, the floating diffusion layer 109 and the power source diffusion layer 110 are formed as shown in FIG. First, a resist mask (not shown) is formed on the p-type semiconductor substrate 100. An n-type impurity is implanted through the opening of the formed resist mask, and the floating diffusion layer 109 and the power source diffusion layer 110 are collectively formed. Note that in forming the floating diffusion layer 109 and the power supply diffusion layer 110, the transfer gate electrode 106 or the reset gate electrode 108 may be used as part of the mask. Accordingly, the end on the transfer gate electrode 106 side and the end on the reset gate electrode 108 side in the floating diffusion layer 109 and the end on the reset gate electrode 108 side in the power source diffusion layer 110 are transferred to the transfer gate electrode 106 or the reset gate electrode 108. It can be positioned in a self-aligning manner.

  Here, modified examples of the deep diffusion layer 114 and the intermediate diffusion layer 124 will be described. FIG. 4 is a schematic cross-sectional view partially showing a change example of the structure in the vicinity of the transfer transistor in the solid-state imaging device according to Embodiment 1 of the present invention. Large horizontal displacement from the position of a potential shallow potential pocket (hereinafter abbreviated as “shallow potential pocket”) to the position of a deep potential pocket or potential barrier This is a preferred configuration in some cases.

  As shown in FIG. 4, the left end position of the deep diffusion layer 214 is preferably on the left side of the right end position of the shallow photodiode diffusion layer 103 on the surface of the p-type semiconductor substrate 100. As a result, the end portion of the deep diffusion layer 214 moves away from the potential pocket portion on the deep side to the left side in the horizontal direction. Therefore, even when the horizontal displacement between the shallow potential pocket portion and the deep potential pocket portion is large, the generation of the potential pocket on the deep side can be satisfactorily suppressed. In addition, the uniformity of the horizontal concentration distribution of the p-type impurity for the deep diffusion layer is improved in the vicinity of the deep potential pocket portion. Therefore, even if the horizontal displacement between the shallow potential pocket portion and the deep potential pocket portion is large, the dependency of the signal charge transfer efficiency, such as manufacturing error, can be reduced. Thus, the individual difference between generation and non-occurrence of the potential pocket on the deep side can be further suppressed.

  Further, it is more preferable that the left end position of the deep diffusion layer 214 is substantially the same as the left end position of the deep photodiode diffusion layer 102 or the left side of the deep diffusion layer 214 on the surface of the p-type semiconductor substrate 100. Thereby, in the deep photodiode diffusion layer 102, the photoelectric conversion efficiency of the portion directly below the shallow photodiode diffusion layer 103 can be made uniform almost independently of the place.

  It should be noted that the left end of the deep diffusion layer 214 should not be positioned between the right end position of the shallow photodiode diffusion layer 103 and the left end position of the deep photodiode diffusion layer 102. With such an arrangement, a portion containing the p-type impurity for the deep diffusion layer and a portion not containing the p-type impurity for the deep diffusion layer are formed, and the photoelectric conversion efficiency changes in those portions. This is because the image quality of the captured image deteriorates.

  As shown in FIG. 4, the left end position of the intermediate diffusion layer 224 is preferably on the left side of the right end position of the shallow photodiode diffusion layer 103 on the surface of the p-type semiconductor substrate 100. This improves the uniformity of the horizontal concentration distribution of the impurity for the intermediate diffusion layer in the vicinity of the potential barrier region. Therefore, even when the horizontal displacement between the shallow potential pocket portion and the potential barrier portion is large, the dependency of the signal charge transfer efficiency such as the manufacturing error can be reduced. More preferably, on the surface of the p-type semiconductor substrate 100, the position of the left end of the intermediate diffusion layer 224 may be substantially the same as the position of the left end of the deep photodiode diffusion layer 102 or the left side of the position. As a result, as in the case of the deep diffusion layer 214 described above, the photoelectric conversion efficiency of the portion immediately below the shallow photodiode diffusion layer 103 in the deep photodiode diffusion layer 102 can be made uniform regardless of the location.

(Embodiment 2)
In Embodiment 2, a second solid-state imaging device according to the present invention will be described. The solid-state imaging device according to the second embodiment has the same configuration as the solid-state imaging device according to the first embodiment except for the shallow diffusion layer and the additional diffusion layer. Therefore, members having substantially the same functions as those of the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted. FIG. 5 is a schematic cross-sectional view partially showing a structural example in the vicinity of the transfer transistor in one pixel cell of the solid-state imaging device according to Embodiment 2 of the present invention.

  As shown in FIG. 5, the p-type semiconductor substrate 100 includes a deep diffusion layer 114, an intermediate diffusion layer 124, and a shallow diffusion having different depths so as to include at least a part of the region under the transfer gate electrode 106. Layer 234 is formed. Further, in the p-type semiconductor substrate 100, an additional diffusion layer 213 is formed so as to include at least part of the surface side of the deep photodiode diffusion layer 102 and a region under the transfer gate electrode 106. In the solid-state imaging device of the second embodiment, dark current can be reduced by forming the additional diffusion layer 213 as in the solid-state imaging device of the first embodiment. In order to satisfactorily reduce the dark current, it is preferable that the entire region on the surface side of the deep photodiode diffusion layer 102 overlaps with the additional diffusion layer 213. As shown in FIG. 5, when the additional diffusion layer 213 is formed in the entire pixel region, the deep photodiode diffusion layer 102 and the additional diffusion layer 213 are on the surface side of the deep photodiode diffusion layer 102. It overlaps reliably in all areas.

  In addition, a region where the shallow diffusion layer 234 and the additional diffusion layer 213 overlap is formed in the region under the transfer gate electrode 106, and the horizontal concentration distribution of impurities in this region is substantially uniform. Thereby, the threshold voltage of the transfer transistor can be favorably controlled. Further, the impurity concentration distribution for the shallow diffusion layer and the impurity concentration distribution for the additional diffusion layer are preferably controlled so as not to generate a potential pocket on the surface side. Thereby, the transfer efficiency of the signal charge is improved.

  Since both the shallow diffusion layer 234 and the additional diffusion layer 213 contain p-type impurities, the impurity concentration of the portion where they overlap is the impurity content of the shallow diffusion layer 234 and the impurity content of the additional diffusion layer 213. It depends on the amount. Therefore, in the additional diffusion layer 213, the impurity concentration differs between the region where the shallow diffusion layer 234 is formed and the region where the shallow diffusion layer 234 is not formed. Therefore, the horizontal impurity concentration on the surface side of the additional diffusion layer 213 has different values around the region under the transfer gate electrode 106, with the edge of the region where the shallow diffusion layer 234 is formed as a boundary. Thus, unlike the conventional solid-state imaging device, there is no portion where the concentration of impurities is higher between the additional diffusion layer and the shallow diffusion layer, and a predetermined concentration distribution can be realized. Will not occur. Further, since the additional diffusion layer 213 is formed, no dark current is generated.

  Further, in the solid-state imaging device of the second embodiment, both the deep diffusion layer 114 and the intermediate diffusion layer 124 or only the deep diffusion layer 114 are formed, as in the case of the solid-state imaging device of the first embodiment. Is preferred. As in the first embodiment, the positions of the right end and the left end of the deep diffusion layer 114 on the surface of the p-type semiconductor substrate 100 are the positions of the right end and the left end of the intermediate diffusion layer 124, respectively, as shown in FIG. And substantially the same. Further, as shown in FIG. 5, the right end and left end positions of the shallow diffusion layer 234 are substantially the same as the right end and left end positions of the deep diffusion layer 114 and the right end and left end of the intermediate diffusion layer 124. Is preferred. In this case, a resist mask for forming the deep diffusion layer 114, the intermediate diffusion layer 124, and the shallow diffusion layer 234 can be used in the manufacturing process described later, and the manufacturing process can be simplified.

  In the p-type semiconductor substrate 100, the position of the deep potential pocket part, the position of the potential barrier part, and the position of the shallow potential pocket part are shifted not only in the vertical direction but also in the horizontal direction. Therefore, when the positional deviation is large, it is preferable that at least one of the left end position of the deep diffusion layer 114, the left end position of the intermediate diffusion layer 124, and the left end position of the shallow diffusion layer 234 is different. There is.

  Note that the deep diffusion layer 114 and the intermediate diffusion layer 124 are not essential components in the solid-state imaging device of the second embodiment as in the case of the solid-state imaging device of the first embodiment.

  In the solid-state imaging device according to the second embodiment, the concentration of the p-type impurity in the additional diffusion layer 213 located in the vicinity of the surface of the deep photodiode diffusion layer 102 that contributes to the reduction of dark current is used to adjust the threshold voltage. This is a preferable structure when it is desired to make the concentration lower than the concentration of the p-type impurity in the shallow diffusion layer 234 located near the surface under 106.

  Here, a method for manufacturing the solid-state imaging device of the second embodiment shown in FIG. 6 will be described. 6A to 6D are schematic cross-sectional views by process for explaining an example of a method for manufacturing the solid-state imaging device according to Embodiment 2 of the present invention. 6A to 6D partially show structural examples in the vicinity of the transfer transistor in one pixel cell.

  First, as shown in FIG. 6A, an element isolation film 101 is formed on a p-type semiconductor substrate 100. After the element isolation film 101 is formed, a resist mask (not shown) having the entire pixel cell formation region as an opening is formed. A p-type impurity for the additional diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask. Thereby, the p-type impurity for the additional diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the additional diffusion layer 213 is formed. After forming the additional diffusion layer 213, the resist mask is removed.

  Next, as shown in FIG. 6B, a resist mask 141 is formed. After forming the resist mask 141, n-type impurities for deep photodiode diffusion layers are ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 141. Thereby, the n-type impurity for the deep photodiode diffusion layer is implanted in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth with a predetermined concentration distribution. In this way, the deep photodiode diffusion layer 102 is formed. After forming the deep photodiode diffusion layer 102, the resist mask 141 is removed.

  Next, as shown in FIG. 6C, a resist mask 142 is formed. After the resist mask 142 is formed, a p-type impurity for a deep diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. Thus, the p-type impurity for the deep diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth. In this way, the deep diffusion layer 114 is formed. Subsequently, a p-type impurity or an n-type impurity for the intermediate diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. Thereby, the p-type impurity or the n-type impurity for the intermediate diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate to a predetermined depth, so that the intermediate diffusion layer 124 is formed. Subsequently, a p-type impurity for a shallow diffusion layer is ion-implanted into the p-type semiconductor substrate 100 through the opening of the resist mask 142. As a result, the p-type impurity for the shallow diffusion layer is implanted with a predetermined concentration distribution in a range from the surface of the p-type semiconductor substrate 100 to a predetermined depth, so that the shallow diffusion layer 234 is formed. After the deep diffusion layer 114, the intermediate diffusion layer 124, and the shallow diffusion layer 234 are formed, the resist mask 142 is removed. Note that the deep diffusion layer 114, the intermediate diffusion layer 124, and the shallow diffusion layer 234 may be formed in any order.

  Note that, on the surface of the p-type semiconductor substrate 100, since the additional diffusion layer 213 is formed at the place where the shallow diffusion layer 234 is formed, the p-type impurity has already been ion-implanted. Therefore, the portion of the shallow diffusion layer 234 that is formed so as to overlap with the additional diffusion layer 213 is affected by the concentration distribution of the additional diffusion layer 213 and has a high concentration. Therefore, the amount of impurities implanted into the shallow diffusion layer 234 is determined in consideration of this. In this case, the concentration of the additional diffusion layer 213 is lower than the concentration of the shallow diffusion layer 234. The additional diffusion layer 213 and the shallow diffusion layer 234 are determined by the difference in concentration.

  As described above, if the formation position of the shallow diffusion layer 234 is shifted due to a manufacturing error or the like, the boundary position between the additional diffusion layer 213 and the shallow diffusion layer 234 is shifted. However, the concentration distribution at the boundary between the additional diffusion layer 213 and the shallow diffusion layer 234 does not vary due to manufacturing errors or the like. That is, the impurity concentration of the shallow diffusion layer 234 is higher than the impurity concentration of the additional diffusion layer 213 at any location in the horizontal direction. Therefore, no potential pocket is generated, and no problem occurs in the operation of the solid-state imaging device of the second embodiment. Note that the deviation of the boundary position between the additional diffusion layer 213 and the shallow diffusion layer 234 caused by a manufacturing error or the like is such that it does not cause a problem in the operation of the solid-state imaging device of the second embodiment.

  The concentration distribution of the p-type impurity for the shallow diffusion layer and the concentration distribution of the p-type impurity for the additional diffusion layer are such that the dark current is reduced and the threshold voltage of the transfer transistor is in a desired range. . These concentration distributions may be optimized so that no potential pockets on the surface side in the potential distribution along the main transfer path are generated or the depth of the potential pockets on the surface side is shallow.

  The dark current is adjusted mainly by controlling the vertical concentration distribution of the p-type impurity for the additional diffusion layer. When another diffusion layer overlapping with the additional diffusion layer 213 is formed, the vertical concentration distribution of the p-type impurity for the additional diffusion layer is controlled in consideration of the vertical concentration distribution of the impurity for the other diffusion layer. The For example, in the configuration shown in FIG. 5, the vertical concentration distribution of the p-type impurity for the additional diffusion layer is the vertical concentration distribution of the n-type impurity for the deep photodiode diffusion layer or the p concentration for the shallow photodiode diffusion layer. It is controlled in consideration of the vertical concentration distribution of the type impurities.

  On the other hand, the threshold voltage of the transfer transistor is adjusted by controlling the vertical concentration distribution of the p-type impurity for the shallow diffusion layer in consideration of the vertical concentration distribution of the p-type impurity for the additional diffusion layer. In the case where other diffusion layers overlapping the shallow diffusion layer 234 are formed under the transfer gate electrode 106 in addition to the additional diffusion layer 213, the diffusion concentration is shallow considering the vertical concentration distribution of impurities for the other diffusion layers. The vertical concentration distribution of the p-type impurity for the diffusion layer is controlled. For example, in the solid-state imaging device shown in FIG. 5, a deep diffusion layer 114 and an intermediate diffusion layer 124 are formed. In this case, the vertical concentration distribution of the p-type impurity for the shallow diffusion layer includes the vertical concentration distribution of the p-type impurity for the additional diffusion layer, the vertical concentration distribution of the p-type impurity for the deep diffusion layer, and the p-type impurity for the intermediate diffusion layer. It is controlled in consideration of the vertical concentration distribution of impurities or n-type impurities.

  Next, as shown in FIG. 6D, similarly to the first embodiment, the gate insulating film 105, the transfer gate electrode 106, the gate insulating film 107, the reset gate electrode 108, the shallow photo A diode diffusion layer 103, a floating diffusion layer 109, and a power source diffusion layer 110 are formed.

  Through the above process, the main part of the pixel cell of the solid-state imaging device of Embodiment 2 can be manufactured. Note that the order of forming the deep photodiode diffusion layer 102, the shallow photodiode diffusion layer 103, the additional diffusion layer 213, the deep diffusion layer 114, the intermediate diffusion layer 124, and the shallow diffusion layer 234 can be changed as appropriate. Any known technique may be used in the manufacture of the solid-state imaging device according to the second embodiment.

  In the first and second embodiments, the case where the first conductivity type impurity is n-type and the second conductivity type impurity is p-type has been described, but they may be of the opposite conductivity type.

  In the first and second embodiments, the amplification type solid-state imaging device has been described as an example, but a solid-state imaging device having another structure may be used. Although the MOS type solid-state imaging device has been described above, the structure from the photodiode to the transfer transistor is almost the same in the CCD type solid-state imaging device. Therefore, the present invention is applied to the CCD solid-state imaging device. You can also

  INDUSTRIAL APPLICABILITY The present invention can be used in a solid-state imaging device in order to reduce dark current and reduce dependency of production error and the like on signal charge transfer efficiency.

1 is a schematic cross-sectional view partially showing a structural example near a transfer transistor in one pixel cell of a solid-state imaging device according to Embodiment 1 of the present invention. Schematic sectional view for explaining an example of a method for manufacturing a solid-state imaging device according to Embodiment 1 of the present invention Schematic sectional view for explaining another example of the method for manufacturing the solid-state imaging device according to Embodiment 1 of the present invention. Schematic cross-sectional view partially showing an example of a change in the structure in the vicinity of the transfer transistor in the solid-state imaging device according to Embodiment 1 of the present invention. Schematic sectional view partially showing a structural example in the vicinity of a transfer transistor in one pixel cell of a solid-state imaging device according to Embodiment 2 of the present invention. Schematic sectional view for explaining an example of a method for manufacturing a solid-state imaging device according to Embodiment 2 of the present invention Conceptual circuit diagram showing equivalent circuit of conventional solid-state imaging device Timing chart for explaining an example of operation of a conventional solid-state imaging device Schematic sectional view showing an example of the structure in the vicinity of a transfer transistor of a conventional solid-state imaging device Explanatory drawing for demonstrating an example of the electric potential distribution along the main transfer path | route in the transfer of the signal charge of the conventional solid-state imaging device Schematic sectional view showing another example of the structure in the vicinity of the transfer transistor in the conventional solid-state imaging device Explanatory drawing for demonstrating another example of the potential distribution along the main transfer path | route in transfer of the signal charge of the conventional solid-state imaging device. Schematic sectional view partially showing another structural example in the vicinity of the transfer transistor in the conventional solid-state imaging device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel part 2 Vertical selection circuit part 3 Row signal holding circuit part 4 Horizontal selection circuit part 5 Load transistor group 10 Pixel cell 11 Photodiode 12 Transfer transistor 13 Amplification transistor 14 Selection transistor 15 Reset transistor 21 Transfer signal line 22 Drain line 23 Vertical Signal line 24 Row selection signal line 25 Reset signal line 26 Column selection signal line 100 p-type semiconductor substrate 101 element isolation film 102 deep photodiode diffusion layer 103 shallow photodiode diffusion layer 105 gate insulating film 106 transfer gate electrode 107 gate insulating film 108 Reset gate electrode 109 Floating diffusion layer 110 Power source diffusion layer 112, 212 Overlap portion 113, 213 Additional diffusion layer 114, 214, 414 Deep diffusion layer 124, 224, 424 Intermediate diffusion layer 134, 34,434 shallow diffusion layers 141 and 142 resist mask 404 threshold diffusion layer 413 surface boron layer

Claims (7)

A step (a) of forming a deep photodiode diffusion layer of the first conductivity type in a part of the pixel cell formation region on the semiconductor substrate;
Forming a second conductivity type additional diffusion layer in the pixel cell formation region so as to include at least part of the surface side of the deep photodiode diffusion layer;
A step (c) of forming a shallow diffusion layer of the second conductivity type over the entire pixel cell formation region;
A step (d) of forming a shallow photodiode diffusion layer of a second conductivity type in the pixel cell formation region so as to include a part of the surface side of the deep photodiode diffusion layer;
And (e) forming an insulating film on a region adjacent to the deep photodiode diffusion layer before Symbol semiconductor substrate,
On the insulating film, and (f) forming a transfer gate electrode,
Forming a floating diffusion layer in the pixel cell formation region so as to be separated from both the deep photodiode diffusion layer and the shallow photodiode diffusion layer with the insulating film and the transfer gate electrode interposed therebetween (g) ) and equipped with a,
The deep photodiode diffusion layer accumulates signal charges generated by incident external light,
The transfer gate electrode controls transfer of the signal charge from the deep photodiode diffusion layer to the floating diffusion layer,
The method for manufacturing a solid-state imaging device, wherein the additional diffusion layer and the shallow diffusion layer are shallower than the shallow photodiode diffusion layer . Performing the step (c) before the step (e) ;
The method of manufacturing a solid-state imaging device according to claim 1, wherein the step (b) is performed after the step (f) using the insulating film and the transfer gate electrode as a mask. A step (a) of forming an additional diffusion layer of the second conductivity type over the entire pixel cell formation region on the semiconductor substrate;
A step (b) of forming a first conductivity type deep photodiode diffusion layer in the pixel cell formation region so as to include a part of the additional diffusion layer;
Forming a shallow diffusion layer of the second conductivity type in a region adjacent to the deep photodiode diffusion layer in the pixel cell formation region;
A step (d) of forming a shallow photodiode diffusion layer of a second conductivity type in the pixel cell formation region so as to include a part of the surface side of the deep photodiode diffusion layer;
Forming an insulating film on a region of the semiconductor substrate adjacent to the deep photodiode diffusion layer (e);
Forming a transfer gate electrode on the insulating film (f);
Forming a floating diffusion layer in the pixel cell formation region so as to be spaced apart from both the deep photodiode diffusion layer and the shallow photodiode diffusion layer with the insulating film and the transfer gate electrode interposed therebetween (g) ) and equipped with a,
The shallow diffusion layer includes a region under the transfer gate electrode in the pixel cell formation region,
The deep photodiode diffusion layer accumulates signal charges generated by incident external light,
The transfer gate electrode controls transfer of the signal charge from the deep photodiode diffusion layer to the floating diffusion layer,
The method for manufacturing a solid-state imaging device, wherein the additional diffusion layer and the shallow diffusion layer are shallower than the shallow photodiode diffusion layer . The step (h) of forming a deep diffusion layer of a second conductivity type deeper than the shallow diffusion layer in the pixel cell formation region so as to include at least a part of the region under the transfer gate electrode is further provided. The manufacturing method of the solid-state imaging device of any one of -3. An intermediate diffusion layer of the first conductivity type or the second conductivity type that is deeper than the shallow diffusion layer and shallower than the deep diffusion layer is formed in the pixel cell formation region so as to include at least a part of the region under the transfer gate electrode. The method for manufacturing a solid-state imaging device according to claim 4, further comprising a step (i) of forming. 3. The method of manufacturing a solid-state imaging device according to claim 1, wherein the additional diffusion layer is formed in the pixel cell formation region by ion implantation from an oblique direction with respect to the semiconductor substrate. 3. The solid-state imaging device according to claim 1, wherein the additional diffusion layer is formed in the pixel cell formation region by ion implantation from a direction having an angle of 10 ° to 45 ° with respect to a vertical direction of the semiconductor substrate. Manufacturing method.

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