JP4760847B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a low-power, high-speed, highly integrated nonvolatile memory using memory cells that store information using magnetic resistance or phase change resistance.

  Magnetic memory random access memory (MRAM) has been developed as a non-volatile memory with no limit on the number of reading and writing. The MRAM stores information using a magnetoresistive effect in which the resistance of the element varies depending on the magnetization direction of the ferromagnetic material in the memory cell. In recent years, development of a magnetic tunnel junction (MTJ) element called magneto resistance (MR) having a larger magnetoresistive change rate than that of a conventional element and its application to MRAM have been promoted, and a static random access memory. (SRAM) high-speed read / write operation is possible, and the possibility of realizing a high degree of integration equivalent to a dynamic random access memory (DRAM) has been shown. This is described in Non-Patent Document 1, for example.

  FIG. 11 shows a basic configuration of an MRAM memory cell. It consists of one MTJ element MTJ and one transistor MT, and is connected to the write word line WW, the read word line WR, and the data line DL. In the MTJ element MTJ, a tunnel insulating film is sandwiched between a ferromagnetic fixed layer whose magnetization direction is fixed in a normal operation and a ferromagnetic free layer whose magnetization direction can be reversed by a write operation. It is a structured. The resistance between the two terminals of the MTJ element changes depending on the direction of magnetization in the two ferromagnetic layers. When the directions are the same, the resistance is in the low resistance state, and when the directions are opposite, the resistance is in the high resistance state.

  The read operation is performed as shown in FIG. That is, by selecting the read word line WR, the transistor MMC is turned on, a voltage is applied between the terminals of the MTJ element MTJ, and the current IDL flowing according to the magnetic resistance of the MTJ element MTJ is detected via the data line DL. As a result, the stored information is read out. On the other hand, the write operation is performed as shown in FIG. That is, the current IWW of the selected write word line WW is set as the write word line current IWS, and the write current ID1 or ID0 corresponding to the write data is supplied to the data line DL. At this time, the magnetization resistance change MR, which is the ratio of the resistance increase in the high resistance state to the low resistance state of the MTJ element, exhibits hysteresis characteristics as shown in FIG. Due to the hard axis magnetic field generated by the write word line current IWS, the magnetization reversal of the MTJ element is likely to occur, and the hysteresis characteristic is narrow with respect to the data line current IDL that generates the easy axis magnetic field. Thereby, only the memory cell selected by the write word line WW can be reversed in magnetization and the stored information can be written. In FIGS. 12 to 14, the low resistance state of the MTJ element is “1” and the high resistance state is “0”, but the reverse is also possible.

Similar to MRAM, a phase change memory is being developed aiming at a high-speed and highly integrated nonvolatile memory. For example, it is described in Non-Patent Document 2. The phase change memory stores information using the fact that the resistance varies depending on the state of the phase change material. The rewriting of the phase change resistor is performed by causing a current to flow to generate heat.

Symposium on VLSI Circuits Digest of Technical Papers, pp. 160-163 (2002) IEE, International Solid-State Circuits Conference, Digest of Technical Papers, pages 202-203 (2002) (2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202-203.)

  Prior to the present application, the inventors of the present application have examined the current consumption in the write operation when the MRAM is highly integrated. At present, the write word line current IWS and the write current ID1 or ID0 shown in FIG. 13 need to have a magnitude of about 2 mA to 8 mA in order to generate a sufficiently large magnetic field. Document 1 proposes a technique called cladding that concentrates magnetic fields generated by word lines and data lines on the MTJ element side, but uses a current of about 4 mA. The inventors of the present application have found that the total write current increases because the write current flows through the same number of data lines as the number of bits simultaneously written increases. In addition, the inventors of the present application have found that, in general, when the area of the ferromagnetic material is reduced, the magnetic field required for magnetization reversal is increased and a larger current is required.

  The phase change memory also requires a large current for writing in order to cause a sufficient temperature rise in the phase change resistance. In addition, reading and writing have the same current path, and in order to prevent disturbance due to reading, it is necessary to make a difference between the reading current and the writing current at a desired ratio. For this reason, the inventors of the present application have found that if the read current is increased for a high-speed read operation, the write current must also be increased.

  Accordingly, an object of the present invention is to realize a highly integrated high-speed nonvolatile memory with low current consumption at the time of writing and low power.

  One representative means of the present invention for achieving the above object is as follows. That is, a memory array including a plurality of memory cells arranged at desired intersections of a plurality of word lines and a plurality of data lines, a write buffer that drives both ends of the data lines and allows a write current to flow. Each of the memory cells includes a phase change resistance element and a transistor, and the write buffer drives the data line only when the memory cell on the data line is reversely written.

  According to the present invention, in a nonvolatile semiconductor memory in which data is written to a memory cell by passing a current through a data line, current consumption can be reduced by reducing the number of bits to be written during a write operation. Accordingly, a semiconductor device having a low power and highly integrated memory can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block in the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). In the drawing, the PMOS transistor is distinguished from the NMOS transistor by attaching an arrow symbol to the body. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise noted, the signal low level is set to “0” and the high level is set to “1”.

(First embodiment)
FIG. 1 is a principal block diagram of a memory according to the present invention. A feature is that a data encoder WC and a data decoder RD are provided. Here, a configuration example of a synchronous memory is shown. A clock buffer CLKB, a command buffer CB, a command decoder CD, an address buffer AB, an address counter ACT, an input buffer DIB, an output buffer DOB, and sectors SCT0, SCT1,... Including a memory array MAR are provided. A sector is provided corresponding to a bank, but a plurality of sectors may be provided per bank. The sector further includes a row predecoder XPD, a column predecoder YPD, a data encoder WC, a data decoder RD, and the like.

  Each circuit block plays the following role. The clock buffer CLKB distributes the external clock CLK as the internal clock CLKI to the command decoder CD and the like. The command decoder CD generates a control signal CP for controlling the address buffer AB, the column address counter YCT, the input buffer DIB, the output buffer DOB, and the like in accordance with an external control signal CMD captured by the command buffer CB. The address buffer AB takes in an external address ADR at a desired timing according to the external clock CLK and sends it to the address counter ACT. The address counter ACT generates an address for performing a burst operation using the address as an initial value, and sends the row address BX to the row address predecoder XPD and the column address BY to the column address predecoder YPD. The row address predecoder XPD predecodes the row address BX and outputs the row predecode address CX to the memory array MAR. Predecoding is performed by the column address predecoder YPD, and the column predecode address CY is output to the memory array MAR. The input buffer DIB takes in the input / output data DQ with the outside at a desired timing. The data encoder WC encodes the input data DI and outputs the write data GI to the memory array MAR as compared with the read data GO from the memory array MAR. On the other hand, the data decoder RD decodes the read data GO and sends the output data DO to the output buffer DOB. The output buffer DOB outputs the output data DO to the input / output data DQ at a desired timing.

  Here, the memory array MAR is configured by arranging memory cells including MTJ elements and transistors, as will be described later. Further, the data encoder WC and the data decoder RD change the data to be written into the memory array MAR to the code that reduces the number of bits to be inverted with respect to the normal binary input / output data DQ. This coding is called Bus-Invert Coding. Non-Patent Document 3: IEE Transactions on Very Large Scale Integration (VLSI) Systems, No. 3 Vol. 1, pp. 49-58, March 1995 (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 49-58. March 1995.) It is the same coding as the existing coding. Document 3 states that the maximum number of bits to be inverted can be reduced by half and the average number of bus data between chips can be reduced by bus invert coding. By using such coding, the maximum value of the number of memory cells to be inverted and written in the memory array MAR can be halved. Thereby, the maximum value of the total current consumption of the memory array MAR at the time of writing can be reduced. Moreover, the average value of current consumption is also reduced.

  By providing the data encoder WC for each sector, the path for transmitting the read data GO read from the memory array MAR to the data encoder WC when the data is encoded is shortened. Thereby, the delay time and power consumption associated with the transmission of the read data GO are reduced. Here, the data decoder RD is also provided for each sector in accordance with the data encoder WC.

  Hereinafter, the configuration and operation of the data encoder WC and the data decoder RD will be described. In the following, a case where 8-bit binary input data DI is encoded into 9-bit write data GI with 1 bit added as a flag by data encoding WC is shown. Conversely, the 9-bit read data GO is decoded by the data decoder RD into 8-bit output data DO with the flags removed. Here, 8-bit binary input data DI is transmitted by complementary signals DI0t to DI7t and DI0b to DI7b. Also, 9-bit write data GI is transmitted by complementary signals GI0t to GI8t and GI0b to GI8b. Similarly, 9-bit read data GO is also transmitted by complementary signals GO0t to GO8t and GO0b to GO8b. On the other hand, 8-bit output data DO is transmitted by true signals DO0 to DO7. The present invention is not limited to this data transmission method, but is not limited to this number of bits, and can be applied to other numbers of bits. However, if the number of bits is large, the circuit scale of the data encoder WC and the data decoder RD is large, and if the number of bits is small, the number of memory cells corresponding to the flag increases. For this reason, a coding level in which 8 bits are changed to 9 bits is appropriate. In the case of a 16-bit memory, it is desirable to code each of the upper 8 bits and lower 8 bits separately.

  FIG. 2 shows a configuration example of the data encoder WC. It is composed of eight data control circuits GIC corresponding to 8-bit input data DI0t to DI7t, DI0b to DI7b, a flag control circuit GFC, and a determination circuit IFD. The data control circuit GIC compares the input data DI0t to DI7t, DI0b to DI7b with the read data GO0t to GO7t, GO0b to GO7b, and is controlled by the control signals DIFt and DIFb output from the determination circuit IFD to write data GI0t to GI7t , GI0b to GI7b are output. The flag control circuit GFC receives the flag read data GO8t and GO8b, is controlled by the control signals DIFt and DIFb, and outputs the flag write data GI8t and GI8b. The determination circuit IFD outputs control signals DIFt and DIFb according to the data comparison results DH0 to DH7 of the eight data control circuits GIC and the flag read data GO8t. The control signals DIFt and DIFb indicate whether or not the data is to be inverted. In the case of inversion, DIFt is “0” and DIFb is “1”.

  FIG. 3 shows a configuration example of the determination circuit IFD in FIG. This circuit determines whether “1” is five or more for nine inputs of the data comparison results DH0 to DH7 and flag read data GO8t. It consists of two logic circuits IC4 and logic circuit IC4D. The logic circuit IC4 includes three 2-input NAND gates, three 2-input NOR gates, a 4-input composite gate that takes a NAND by taking two inputs, and another 2 inputs by taking a 2-input OR. It consists of a composite gate that takes inputs and NAND. The logic circuit IC4 is a circuit that obtains an output corresponding to the number of 4-input '1's. For example, the outputs DHL1 to DHL4 of the logic circuit IC4 to which the data comparison results DH0 to DH3 are input are as follows. DHL1 becomes '1' when any of DH0 to DH3 is '1' and '1' is one or more. DHL2 becomes “1” when there are two or more “1” in DH0 to DH3. DHL3 becomes “1” when there are three or more “1” in DH0 to DH3. DHL4 is “1” when DH0 to DH3 are all “1” and the number of “1” is four. The outputs DHL1 to DHL4 and DHU1 to DHU4 as described above of the logic circuit IC4 and the read data GO8t are input to the logic circuit IC4D. The logic circuit IC4D is composed of two 2-input NOR gates, seven 2-input NAND gates, a composite gate that takes a 4-input OR and takes the NAND from the other inputs, a 4-input NAND gate, and an inverter. Is done. With this logic circuit IC4D, when the number of data comparison results DH0 to DH7 and the read data GO8t of the flag is 9 and '1' is 5 or more, the determination result DIFt is '1' and DIFb is '0'. Become.

  This determination circuit is composed of a static CMOS logic gate and does not use a signal for controlling the timing. Therefore, the delay of write data due to coding can be reduced. This determination circuit uses a composite gate to reduce the number of gate stages, reduce the delay time, and reduce the circuit scale. The determination circuit can also be configured using a multi-input differential amplifier instead of such a CMOS logic gate. In that case, as compared with the determination circuit shown in FIG. 3, a device for securing S / N such as setting of operation timing is required, but the number of elements can be reduced.

  FIG. 4 shows a configuration example of the data control circuit GIC in FIG. The symbol i in the figure corresponds to FIG. 2 when i is 0 to 7. Two logic gates XOR consisting of four PMOS transistors and four NMOS transistors, inverter INV, two two-input NAND gates ND2, and a four-input composite gate that takes the NAND of two inputs each It consists of two ONA2 and two write data drivers GID consisting of a 2-input NAND gate and an inverter. The write data driver GID is controlled by an enable signal GIE and outputs write data GIit and GIib. The logical gate XOR takes exclusive NOR between the input data DIit and DIib of the complementary signal and the read data GOit and GOib, and outputs the data comparison result DHi. Further, the inverter INV and the logic gate XOR take the exclusive OR of the data comparison result DHi and the complementary signal determination results DIFt and DIFb to generate the control signal GIiE. This control signal GIiE is a signal indicating whether or not inversion writing is necessary. If the control signal GIiE is '0', both write data GIit and GIib are set to '0'. If control signal GIiE is '1', and control signal DIFt is '0' and DIFb is '1', the true signal and bar signal of input data DIit and DIib are swapped and output as write data GIit and GIib When DIFt is “1” and DIFb is “0”, the input data DIit and DIib are output as they are as write data GIit and GIib. In this configuration, a desired logic is realized with a small number of gate stages by using a composite gate. In particular, by making input data DIit, DIib and read data GOit, GOib and judgment results DIFt, DIFb as complementary signals, exclusive NOR and exclusive OR are configured with a single-stage gate to reduce delay time reduction. ing.

  FIG. 5 shows a configuration example of the flag control circuit GFC in FIG. Logic gate XOR consisting of 4 PMOS transistors and 4 NMOS transistors, 2 2-input NAND gates ND2, 2 inverters INV, and 2 write data drivers GID consisting of 2-input NAND gates and inverters Consists of. Similar to the data control circuit GIC of FIG. 4, the write data driver GID is controlled by an enable signal GIE and outputs write data GI8t, GI8b. The logic gate XOR takes exclusive NOR between the complementary signal flag read data GO8t, GO8b and the determination results DIFt, DIFb, and generates a control signal GI8E. This control signal GI8E is a signal indicating whether or not inversion writing is necessary, like GIiE, similarly to the control signal in FIG. If the control signal GI8E is “0”, both write data GI8t and GI8b are set to “0”. If the control signal is GI8E “1”, the determination results DIFt and DIFb are output as write data GI8t and GI8b as they are. For the determination results DIFt and DIFb, the path for outputting the write data GI8t and GI8b has the same number of stages as the path for the data control circuit GIC in FIG. 4 to output the write data GIit and GIib, and delay time is almost the same. Can be aligned.

  FIG. 6 shows a configuration example of the data decoder RD. It is provided corresponding to 8-bit output data DO0 to DO7, and is composed of eight data control circuits DOD controlled by flag read data GO8t and GO8b. When the load capacity becomes excessive by inputting the flag read data GO8t and GO8b to the eight data control circuits DOD, a buffer with an even number of inverter rows may be provided.

  FIG. 7 shows a configuration example of the data control circuit DOD in FIG. The symbol i in the figure corresponds to FIG. 6 because i is any one of 0 to 7. It consists of a 4-input composite gate NAO2 that takes an AND of two inputs and takes NOR, and a tri-state inverter TIV composed of two PMOS transistors and two NMOS transistors. The 4-input composite gate NAO2 selects any one of the read data GOit and GOib by the flag read data GO8t and GO8b which are complementary signals. The tri-state inverter TIV outputs the output data DOi when the enable signal DOEb is low and DOEt is high. The reason why the tri-state inverter is used is that the output data DOi is a bus driven from a plurality of sectors SCT0, SCT1,... As shown in FIG. In this way, encoding of read data can be realized with a simple circuit configuration. The delay time is small and the influence on the read access time is small.

  FIG. 8 shows a configuration example of the memory array MAR in FIG. A memory cell array MCA, a row decoder XDEC, a word driver group WDP, and data line control circuits CCN and CCF are included. Here, for simplification, a dummy cell for generating a reference signal is omitted. Depending on the memory capacity, such a configuration may be repeated to form the memory array MAR in FIG. The memory cell array MCA has memory cells MC at the intersections of the write word lines WW0, WW1, WW2, WW3,... And the read word lines WR0, WR1, WR2, WR3,... And the data lines DL0, DL1, DL2, DL3,. Is provided. The memory cell MC is also connected to source lines SL01, SL23,. Write word lines WW0, WW1, WW2, WW3,... And read word lines WR0, WR1, WR2, WR3,... Are controlled by a word driver group WDP including a drive circuit. The data lines DL0, DL1, DL2, DL3,... Are controlled at both ends by data line control circuits CCN, CCF including a sense amplifier and a write buffer.

  Each memory cell MC includes one MTJ element MTJ and one transistor MT. In the MTJ element MTJ, a tunnel insulating film is sandwiched between a ferromagnetic fixed layer whose magnetization direction is fixed in a normal operation and a ferromagnetic free layer whose magnetization direction can be reversed by a write operation. It is a structured. The resistance between the two terminals of the MTJ element changes depending on the direction of magnetization in the two ferromagnetic layers. When the directions are the same, the resistance is in the low resistance state, and when the directions are opposite, the resistance is in the high resistance state. The read operation of the memory cell MC is performed as shown in FIG. That is, by setting the read word line WR selected in WR0, WR1, WR2, WR3,... To a high level, the transistor MT is turned on in the memory cell connected to the word line, and the MTJ element MTJ is connected between the terminals. Is read out by detecting a current IDL flowing through a desired data line in DL0, DL1, DL2, DL3,... According to the magnetic resistance of the MTJ element MTJ. On the other hand, the write operation is performed as shown in FIG. That is, the current IWW of the write word line selected in WW0, WW1, WW2, WW3,... Is the write word line current IWS, and the current of the data line selected in DL0, DL1, DL2, DL3,. The magnetic field is generated by setting the positive write current ID1 or the negative ID0 in accordance with the write data.

  The row decoder XDEC decodes the row predecode address CX and outputs row decode signals XA0, XA1, XA2, XA3,... To the word driver group WDP. The word driver group WDP corresponds to write word lines WW0, WW1, WW2, WW3,... And read word lines WR0, WR1, WR2, WR3,. Is provided. The word driver WWD is selected by the row decode signals XA0, XA1, XA2, XA3,... When the write word line drive enable signal WWE is '1', and the Drive one. The write word lines WW0, WW1, WW2, WW3,... Are grounded on the opposite side across the word driver group WDP and the array, and a write word line current flows through the selected write word line. The word driver WRD is selected by the row decode signals XA0, XA1, XA2, XA3,. Drive one.

  FIG. 9 shows a configuration example of the data line control circuit CCN in FIG. Here, an example in which reading or writing of 9 bits is performed on 144 data lines DL0 to DL143 is shown, and a configuration in which 3 bits are divided into 3 parts is shown. It consists of three column decoders YD16, nine write buffers WBN, nine sense amplifiers SA, and three column selectors YSN3. The column decoder YD16 decodes the column predecode address CY, and pairs of complementary column selection signals YN0t to YN15t and YN0b to YN15b, YN16t to YN31t and YN16b to YN31b, YN32t to YN47t and YN32b to YN47b, one pair at a time. Select. The write buffer WBN includes an inverter, a PMOS transistor, and an NMOS transistor, receives write data GI0t to GI8t, GI0b to GI8b, and drives the common data lines DN0 to DN8. For example, if the write data GI0t is high, the common data line DN0 is driven high, and if GI0b is low, DN0 is driven low. Here, when both the write data GI0t and GI0b are low, a high impedance state is set. The sense amplifier SA detects signals on the common data lines DN0 to DN8 and outputs read data GO0t to GO8t and GO0b to GO8b during a memory cell read operation. The column selector YSN3 is connected to each of 48 data lines DL0 to DL47, DL48 to DL95, DL96 to DL143, respectively, with column selection signals YN0t to YN15t and YN0b to YN15b, YN16t to YN31t, YN16b to YN31b, YN32t to YN47t and YN32b. One PMOS transistor and two NMOSs controlled by ˜YN47b are connected, and three of the 48 data lines are connected to common data lines DN0 to DN2, DN3 to DN5, and DN6 to DN8. Unselected data lines are kept at the ground voltage VSS. For example, when the column selection signal YN0t is high and YN0b is low, the data lines DL0 to DL2 are connected to the common data lines DN0 to DN2, and the data lines DL3 to DL47 are kept at VSS.

  FIG. 10 shows a configuration example of the data line control circuit CCF in FIG. The data line control circuit CCN of FIG. 9 contributes to both reading and writing of the memory cell, whereas the data line control circuit CCF is used only for writing. 9 shows an example in which writing of 9 bits is performed on 144 data lines DL0 to DL143 in correspondence with the data line control circuit CCN of FIG. It consists of three column decoders YD16, nine write buffers WBF, and three column selectors YSF3. The column decoder YD16 decodes the column predecode address CY, and pairs of complementary column selection signals YF0t to YF15t and YF0b to YF15b, YF16t to YF31t and YF16b to YF31b, YF32t to YF47t and YF32b to YF47b, one pair at a time. Select. Like the write buffer WBN in FIG. 9, the write buffer WBF includes an inverter, a PMOS transistor, and an NMOS transistor, receives write data GI0t to GI8t, GI0b to GI8b, and drives the common data lines DF0 to DF8. Here, write data GI0t to GI8t, GI0b to GI8b are connected in reverse to the write buffer WBN in FIG. For example, if the write data GI0t is high, the common data line DF0 is driven low, and if GI0b is low, DF0 is driven high. When the write data GI0t and GI0b are both low, the high impedance state is entered. The column selector YSN3 is connected to each of 48 data lines DL0 to DL47, DL48 to DL95, DL96 to DL143, respectively, with column selection signals YF0t to YF15t and YF0b to YF15b, YF16t to YF31t, YF16b to YF31b, YF32t to YF47t, and YF32b. One PMOS transistor controlled by ~ YF47b and one NMOS are connected, and three of the 48 data lines are connected to the common data lines DF0 to DF2, DF3 to DF5, and DF6 to DF8. For example, when the column selection signal YF0t is high and YF0b is low, the data lines DL0 to DL2 are connected to the common data lines DF0 to DF2.

  By configuring the write buffers WBN and WBF as described above, when both the write data signals are low, both the write buffers are in a high impedance state, and control can be performed so that no current flows through the data lines. That is, unnecessary write current can be prevented.

  When data is coded as in the present embodiment, the number of memory cells selected at the same time is not a power of 2 by adding a flag. When coding 8 bits to 9 bits, the data line control circuits CCN and CCF are configured in this way, and the data path can be aligned by dividing the data line into 3 bits each, making it easy to control the timing of sense amplifiers, etc. become.

  FIG. 15 shows an example of the timing of the read operation of the synchronous MRAM described above. The operation will be described according to this timing chart. Every time the external clock CLK rises, the command decoder CD determines the control signal CMD. When the read command R is given, the row address and the column address are taken into the address buffer AB from the address ADR. With the column address taken into the address buffer AB as an initial value, the address counter ACT operates every clock cycle, and outputs a row address BX and a column address BY. In response to this, the row address predecoder XPD outputs a row predecode address CX, and the column address predecoder YPD outputs a column predecode address CX. Selected. As a result, the data line current IDL flows through the selected data line. This is detected by the sense amplifier SA and the read data GO is output. The data decoder RD decodes the read data GO and sends the output data DO to the output buffer DOB. Further, the output buffer DOB outputs data to the input / output data DQ at a timing according to the external clock CLK. Here, the case where the read command R is output to the input / output data DQ in response to the rise of the clock CLK after two cycles and the read latency is 3 is shown. The above operation is repeated for each cycle of the clock CLK.

  FIG. 16 shows an example of the timing of the write operation. When the read command W is given, the row address and the column address are taken into the address buffer AB from the address ADR. With the column address taken into the address buffer AB as an initial value, the address counter ACT operates every two cycles of the clock CLK, and outputs the row address BX and the column address BY. In response to this, the row address predecoder XPD outputs a row predecode address CX, and the column address predecoder YPD outputs a column predecode address CX. First, the read word line WR and the column selection signal YS are selected in the memory array MAR. As a result, the data line current IDL flows through the selected data line. This is detected by the sense amplifier SA and the read data GO is output. On the other hand, in the next clock cycle when the write command is input, the input buffer DIB takes in the input / output data DQ and outputs the input data DI. The data encoder WD encodes the input data DI in comparison with the read data GO to obtain write data GI. The read word line WR is reset, and a desired current is passed through the write word line current IWW. Further, a current is passed through the data line according to the write data GI by the write buffer. As a result, inversion writing is performed on a desired memory cell. The above operation is repeated every two cycles of the clock CLK.

  Thus, by using a synchronous memory, it is possible to operate at a high frequency by using a synchronous memory that takes in commands and addresses and inputs / outputs data in synchronization with the external clock CLK. Data rate can be realized. The MRAM according to the present invention can be applied to various high-speed memory systems developed for SRAM and DRAM.

  In this example, the read operation in FIG. 15 is performed in the same cycle as the clock CLK, whereas the write operation is performed every two cycles of the clock CLK. This is because in the write operation, the inversion write is performed after the read operation from the memory cell, so that the cycle time becomes longer than the write operation. Thus, by setting the write operation every two cycles, the clock cycle time that becomes the read cycle can be shortened. In some cases, the write operation can be performed every clock cycle. In this case, the clock cycle time becomes longer, but the cycle of the read operation and the write operation is aligned, so that the control becomes easier.

  In the write operation of FIG. 16, input data is fetched after one cycle of the clock CLK with respect to the write command, and the write latency is set to 1. Even in this case, since the write operation of the memory cell is performed after the read operation, the input data does not become a critical path. By setting the write latency to 1, the difference from the read latency is reduced, and the use efficiency of the I / O data DQ bus can be improved.

  In FIG. 15 and FIG. 16, the row address and the column address are fetched simultaneously by the read command R or the write command W. As a result, there is no delay time from row address fetching to column address fetching, which is generally required in DRAMs, and only the information on the selected data line can be detected. Unlike DRAM, MRAM can perform non-destructive reading, and it is not necessary to detect data of all memory cells on the word line, and thus such operation is possible. By detecting only the information of the selected data line, power consumption can be reduced.

  FIG. 8 shows a configuration in which each memory cell MC includes one MTJ element MTJ and one transistor MT. However, Non-Patent Document 4: IEE Eee, International Solid State Circuits. As shown in the Conference, Digest of Technical Papers, pages 128-129 (2000) (2000 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 128-129.) In addition, the present invention can be applied to a memory array in which a memory cell is composed of two MTJ elements and two transistors, and an effect of reducing current consumption during writing can be obtained. In such a memory array, since the data line current at the time of writing flows in a loop shape, it can be controlled on one side, and the configuration of the data line control circuit can be simplified.

(Second embodiment)
The technique for reducing the number of bits to be written as described in the first embodiment is effective not only in the MRAM but also in the phase change memory. A phase change memory to which the present invention is applied can be configured as shown in FIG. 1 like the MRAM, and the data encoder and data decoder shown in FIGS. 2 to 7 can be used. FIG. 17 shows a configuration example of the memory array, which is used as the memory array MAR in FIG. The memory cell array OCA, row decoder XDEC, word driver group WD, and data line control circuit CCO are included. Here, as in FIG. 8, for the sake of simplicity, reference signal generating dummy cells and the like are omitted. Depending on the memory capacity, such a configuration may be repeated to form the memory array MAR in FIG. In the memory cell array OCA, memory cells OC are provided at the intersections of the word lines WL0, WL1, WL2, WL3,... And the data lines OL0, OL1, OL2, OL3,. The memory cell OC is also connected to source lines SL01, SL23,. Each memory cell includes one phase change resistor CR and one transistor MT. The phase change resistance CR is made of a chalcogenide material, and changes into a low resistance state and a high resistance state depending on the state. Word lines WL0, WL1, WL2, WL3,... Are driven by a word driver group WD. The row decoder XDEC decodes the row predecode address CX and outputs row decode signals XA0, XA1, XA2, XA3,... To the word driver group WD, and the word driver group WD selectively selects the word lines WL0, Drives WL1, WL2, WL3,…. The data lines OL0, OL1, OL2, OL3,... Are controlled by a data line control circuit CCO including a sense amplifier and a write buffer.

  FIG. 18 shows a configuration example of the data line control circuit CCO in FIG. Here, as in FIG. 9, an example in which reading or writing of 9 bits is performed on 144 data lines DL0 to DL143 is shown, and a configuration in which 3 bits are divided into 3 parts is shown. It consists of three column decoders YD16, a write pulse generation circuit WPG, nine write buffers WBO, nine sense amplifiers SAO, and three column selectors YSO3. Similarly to the data line control circuit CCN of the MRAM shown in FIG. 9, the column decoder YD16 decodes the column predecode address CY, and complementary column select signals YO0t to YO15t and YO0b to YO15b, YO16t to YO31t and YO16b to Select one pair each from 16 pairs of YO31b, YO32t to YO47t, and YO32b to YO47b. The column selector YSO3 has the same configuration as the column selector YSN3 in FIG. 9, and each of the 48 data lines OL0 to OL47, OL48 to OL95, and OL96 to OL143 is controlled by a column selection signal pair. A PMOS transistor and two NMOSs are connected. Three of the 48 data lines are connected to the common data lines CD0 to CD2, CD3 to CD5, CD6 to CD8, and the unselected data lines are connected to the ground voltage VSS. keep. The write pulse generation circuit WPG outputs “1” and “0” write pulses to the write pulse lines WP1 and WP0. The write buffer WBN includes two inverters and two PMOS transistors, receives write data GI0t to GI8t, GI0b to GI8b, and connects the common data lines DN0 to DN8 to the write pulse lines WP1 and WP0. For example, if the write data GI0t is high, the common data line CD0 is connected to the write pulse line WP1, and if GI0b is low, CD0 is connected to WP0. Here, when both the write data GI0t and GI0b are low, as in the write buffer WBN in FIG. The sense amplifier SAO detects signals on the common data lines CD0 to CD8 and outputs read data GO0t to GO8t and GO0b to GO8b during a memory cell read operation.

  The read operation is performed as shown in FIG. That is, the word line WL selected in WL0, WL1, WL2, WL3,... Is set to the high level, the transistor MT is turned on in the memory cell connected to the word line, and the desired column selection signal pair YOt, YOb is set. By selecting, a voltage is applied between the terminals of the phase change resistor CR from the sense amplifier SAO via the column selector and the data line. The storage information is read from the memory cell OC by the current IOL flowing through the data line according to the state of the phase change resistor CR, detected by the sense amplifier SAO, and read data GO is output. Here, the period during which the data line current IOL flows is determined by the sense amplifier SAO.

  On the other hand, the write operation is performed as shown in FIG. First, similarly to the read operation, a read operation from the memory cell OC is performed. Here, the word line WL and the column selection signal pair YOt, YOb are kept as they are. Write data is determined according to read data. Accordingly, writing to the memory cell OC is performed by changing the state of the phase change resistor CR by heat generated by the flow of the data line current. When performing inversion writing, a write current is supplied to the data line by the write pulse generation circuit WPG and the write buffer WBN in the data line control circuit CCO. In writing “1” (“1” WRITE), a small current ID1 is applied with a long pulse width, and the phase change resistance CR is annealed to reduce the resistance. In writing “1” (“1” WRITE), a large current ID0 is applied with a short pulse width, and the phase change resistance CR is made amorphous to increase the resistance. When inversion writing is unnecessary (WRITE_VOID), the data line current IOL is kept at 0.

  In this way, even in the phase change memory, the number of bits to be written can be reduced and the current consumption can be reduced as in the first embodiment. In particular, the phase change memory has the effect of suppressing the temperature rise and stabilizing the operation. If data is simultaneously written in a large number of memory cells OC, the temperature of the entire memory cell array increases, and the temperature decrease after the pulse of the data line current IOL is delayed. For this reason, even if “0” write (“0” WRITE) is performed with a short pulse, there is a possibility that a low resistance state is obtained. According to the present invention, this problem can be avoided by halving the maximum number of bits to be written.

  Further, in the phase change memory, there is a concern about deterioration of the phase change resistance due to repeated write operations. According to the present invention, since the number of times of writing for each memory cell can be reduced on average, deterioration of phase change resistance can be reduced and high reliability can be achieved.

  Unlike the operation of the MRAM described with reference to FIGS. 12 and 13, in the phase change memory, the word line WL is set to the high level in both the read operation and the write operation. Therefore, the write operation can be performed following the read operation while the word line WL is kept at the high level by the write operation. Therefore, the penalty for performing the read operation before the write operation is small with respect to the current consumption and delay time of the peripheral circuit.

(Third embodiment)
An embodiment without coding will now be described for MRAM. FIG. 21 shows a configuration example different from that of FIG. 8 of the MRAM memory array. The entire MRAM is configured, for example, by deleting the data encoder WC and the data decoder RD from FIG. This memory array configuration includes a memory cell array MCA, a row decoder XDEC, a word driver group WDP, and data line control circuits CCN2 and CCF2. The memory cell array MCA is configured as shown in FIG. 8, although the number of data lines is different. The row decoder XDEC and the word driver group WDP operate in the same manner as in FIG.

  The data line control circuit CCN2 includes a column selector YSN and a plurality of read / write circuits RWN corresponding to read data GO0, GO1,. Here, for simplicity, a column decoder or the like is omitted. The column selector YSN is configured similarly to the column selector YSN3 in FIG. 9, and connects desired data lines to the common data lines DN0, DN1,. The read / write circuit RWN includes a sense amplifier SA and a write buffer WB. In the read operation, the signals of the common data lines DN0, DN1,... Read from the memory cell array are detected by the sense amplifier SA and output as read data GO0, GO1,. Also in the write operation, first, the signals of the common data lines DN0, DN1,... Read from the memory cell array are detected by the sense amplifier SA. In accordance with the result, the data lines are driven by the write buffer WB via the common data lines DN0, DN1,. That is, when “1” is read, it is driven to a high level, and when “0” is read, it is driven to a low level.

  The data line control circuit CCF2 includes a column selector YSF and a plurality of write circuits WF corresponding to the write data GI0, GI1,. Here, for simplicity, a column decoder or the like is omitted. The column selector YSF is configured in the same way as the column selector YSF3 in FIG. 10, and connects desired data lines to the common data lines DF0, DF1,. The write circuit WF includes a write buffer WB and an inverter INV. In the write operation, the input write data GI0, GI1,... Are inverted, and the data lines are driven through the common data lines DF0, DF1,. That is, when '1' is input, it is driven to a high level, and when '0' is input, it is driven to a low level.

  In the write operation, by driving the data line as described above, when the read data and the write data match, both sides of the data line are driven to the same level and no current flows. In the case of mismatch, it flows to the data line between the data line control circuits CCN2 and CCF2 according to the write data. As a result, it is possible to write only the bits to be inverted to the memory cell. For the bits that do not require inversion writing, the data line current does not flow, so the average current of the write operation can be reduced.

  In the first embodiment, coding that adds flag bits by coding is used to reduce the number of bits for inverted writing, and simultaneously reduce the maximum value and the average value of the number of bits to be written. By not performing reverse writing, the average value is reduced. This is a simpler method than the first embodiment, and there is no increase in the number of memory cells by adding flag bits. Further, since write data need only be input to one of the data line control circuits on both sides, the number of wirings can be reduced as compared with the conventional configuration, and the circuit configuration is simplified.

(Fourth embodiment)
An embodiment without phase coding in a phase change memory will now be described. FIG. 22 shows a configuration example different from that of FIG. 17 of the memory array of the phase change memory. As in the third embodiment, the entire phase change memory is configured, for example, by deleting the data encoder WC and the data decoder RD from FIG. This memory array configuration includes a memory cell array OCA, a row decoder XDEC, a word driver group WD, and a data line control circuit CCO2. The memory cell array OCA is configured as shown in FIG. 17, although the number of data lines is different. The row decoder XDEC and the word driver group WD operate in the same manner as in FIG.

  The data line control circuit CCO2 includes a column selector YSO, a plurality of read / write circuits RWO corresponding to the write data GI0, GI1,... And read data GO0, GO1,. Again, for simplicity, column decoders and the like are omitted. The column selector YSO is configured similarly to the column selector YSO3 in FIG. 18, and connects desired data lines to the common data lines CD0, CD1,. The read / write circuit RWO includes a sense amplifier SA, an exclusive OR gate XOR2, an inverter, two NAND gates, and two PMOS transistors. In the read operation, the signals of the common data lines CD0, CD1,... Read from the memory cell array are detected by the sense amplifier SA and output as read data GO0, GO1,. Even in the write operation, first, a signal read from the memory cell array is detected by the sense amplifier SA. The result is compared with the write data GI0, GI1,... By the exclusive OR gate XOR2. In the case of mismatch, the exclusive OR gate XOR2 outputs “1”, and the write pulse lines WP1 and WP0 are connected to the common data line by the PMOS transistor. As a result, '1' and '0' write pulses output from the write pulse generation circuit WPG to the write pulse lines WP1 and WP0 are transmitted to the data lines. As a result, it is possible to write only the bits to be inverted to the memory cell.

  In this embodiment, as in the third embodiment, the data line current does not flow for bits that do not require inversion writing, so that the average current of the write operation can be reduced. Patent Document 1: Japanese Patent Application Laid-Open No. 7-220479 discloses a technique for reducing the current consumption of writing by comparing the sense amplifier output with the write data using an exclusive OR gate and performing only inversion writing with respect to the static RAM. It is disclosed. In the present invention, the technique is applied to the phase change memory. In addition to the effect of reducing the current consumption, as described in the second embodiment, the temperature rise of the entire memory cell array is suppressed and the writing is stabilized. An effect and an effect of reducing the number of times of writing of the phase change resistor to suppress deterioration and increasing reliability can be obtained. Japanese Patent Application Laid-Open No. 9-63286 discloses a method for extending the life of an EEPROM by comparing read data and input data to control an erase circuit and a write circuit to eliminate unnecessary erase operations. Has been. In the method of Patent Document 2, the comparison is performed for each piece of data to be operated simultaneously, whereas in this embodiment, it is determined whether or not the write operation is performed for each bit. For this reason, this embodiment has a greater effect of not performing unnecessary writing, and is particularly effective when the number of bits to be operated simultaneously is large.

  It should be noted that the MRAM can also be configured such that only the inversion write is performed by comparing the sense amplifier output and the write data using an exclusive OR gate as in this embodiment.

  It goes without saying that the present invention described in the above embodiments can be applied not only to a single MRAM and phase change memory but also to semiconductor devices such as a system LSI in which MRAM or phase change memory is embedded. Even in such a case, the effects described in each embodiment can be obtained for the MRAM or the phase change memory.

The block diagram which shows the structural example of the synchronous memory by this invention. The block diagram which shows the structural example of a data encoder. FIG. 3 is a circuit diagram illustrating a configuration example of a determination circuit in FIG. 2. FIG. 3 is a circuit diagram showing a configuration example of a data control circuit in FIG. 2. FIG. 3 is a circuit diagram showing a configuration example of a flag control circuit in FIG. 2. The block diagram which shows the structural example of a data decoder. FIG. 7 is a circuit diagram showing a configuration example of a data control circuit in FIG. 6. The figure which shows the structural example of the memory array of MRAM. FIG. 9 is a diagram showing a configuration example of a data line control circuit in FIG. 8. The figure which shows the structural example of the data line control circuit of the other end in FIG. The figure which shows the structural example of an MRAM cell. The figure which shows the read-out operation | movement of an MRAM cell. The figure which shows the write-in operation | movement of a MRAM cell. The figure which shows the write-in characteristic of an MTJ element. 4 is a timing chart of the read operation of the synchronous MRAM according to the present invention. 4 is a timing chart of the write operation of the synchronous MRAM according to the present invention. The figure which shows the structural example of the memory array of a phase change memory. FIG. 18 is a diagram showing a configuration example of a data line control circuit in FIG. 17. The figure which shows read-out operation | movement of the memory cell of phase change memory. The figure which shows the write-in operation | movement of the memory cell of a phase change memory. The figure which shows another structural example of the memory array of MRAM. The figure which shows another structural example of the memory array of a phase change memory.

Explanation of symbols

AB: Address buffer,
ACT ... Address counter,
ADD ... Address signal from outside,
BX ... low address,
BY ... column address,
CB ... Control signal buffer,
CCF, CCN, CCO, CCF2, CCN2, CCO2 ... Data line control circuit,
CD ... Command decoder,
CLK: External clock,
CKB ... clock buffer,
CLKI: Internal clock,
CMD ... Control command signal from outside,
CP: Control signal,
CX: Row predecode address,
CY ... Column predecode address,
DI: Input data,
DIB ... Input buffer,
DL0 to DL3 ... data line,
DO: Output data,
DOB ... Output buffer,
DOD ... Data control circuit,
DQ: I / O data with external,
GI: Write data,
GFC: Flag control circuit,
GIC: Data control circuit,
GID: Write data driver,
GO: Read data,
IFD: Judgment circuit for data encoding,
MA ... main amp,
MAR ... Memory array
MC ... MRAM memory cell,
MCA, MCA2 ... MRAM memory cell array,
MIO ... Main input / output line,
OC ... Memory cell of phase change memory,
OCA, OCA2 ... Memory cell array of phase change memory,
RD ... Data decoder,
SA, SAO ... sense amplifier,
WBF, WBN ... write buffer,
SCT0, SCT1 ... sector,
WB, WBF, WBN ... write buffer,
WC ... Data encoder,
WD, WDP ... word drivers,
WL, WL0 to WL3 ... word lines,
WPG ... Writing pulse generation circuit W,
WR, WR0 to WR3 ... Read word line,
WRD, WWD ... Word driver,
WW, WW0 to WW3 ... write word line,
XDEC: Row decoder,
XPD: Row address predecoder,
YD16 ... column decoder,
YPD: Column address predecoder,
YSF, YSN, YSO, YSF3, YSN3, YSO3 ... Column selector.

Claims (1)

A semiconductor device,
A memory array including a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data lines;
A first write buffer and a second write buffer disposed at both ends of a current path of a current that flows when information is written to the memory cell;
A sense amplifier that detects signals read from the memory cells on the plurality of data lines;
Each of the plurality of memory cells includes a magnetoresistive element and a transistor,
The first write buffer and the second write buffer allow a write current to flow through the current path only when the memory cell is inverted and written.
The first write buffer drives the current path according to only the output of the sense amplifier,
The second write buffer is a semiconductor device that drives the current path only in accordance with input data .

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