JP4758170B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4758170B2
JP4758170B2 JP2005230329A JP2005230329A JP4758170B2 JP 4758170 B2 JP4758170 B2 JP 4758170B2 JP 2005230329 A JP2005230329 A JP 2005230329A JP 2005230329 A JP2005230329 A JP 2005230329A JP 4758170 B2 JP4758170 B2 JP 4758170B2
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肇 佐々木
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Mitsubishi Electric Corp
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Description

本発明は、半導体装置およびその製造方法に関し、特に、2層構造のT型ゲート電極を有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a T-type gate electrode having a two-layer structure and a manufacturing method thereof.

例えば高周波用半導体装置では、ゲート電極の形成後に熱処理を行うと、ゲート電極材料が半導体基板に拡散してゲート特性が劣化する。このために、WSi等の高融点金属層(バリア層)と、Au等の低抵抗金属層の2層構造からなるゲート電極を用いてゲート特性の劣化を防止している。
2層構造のゲート電極は、高融点金属材料層と低抵抗金属材料層を順次半導体基板上に堆積させた後に、エッチングマスクを用いたイオンミリングにより不要な高融点金属材料層と低抵抗金属材料層とを除去して形成する。通常、ゲート電極は、断面形状がT字型であるT型ゲート電極として形成される。
For example, in a high-frequency semiconductor device, when heat treatment is performed after the formation of the gate electrode, the gate electrode material diffuses into the semiconductor substrate and the gate characteristics deteriorate. For this reason, deterioration of gate characteristics is prevented by using a gate electrode having a two-layer structure of a refractory metal layer (barrier layer) such as WSi and a low resistance metal layer such as Au.
The gate electrode having a two-layer structure is formed by sequentially depositing a refractory metal material layer and a low resistance metal material layer on a semiconductor substrate, and then performing unnecessary ion milling using an etching mask and an unnecessary refractory metal material layer and a low resistance metal material. The layer is removed and formed. Usually, the gate electrode is formed as a T-shaped gate electrode having a T-shaped cross section.

図4は、全体が500で表される、イオンミリングを用いて形成したT型ゲートを有する半導体装置の断面図である。半導体装置500は、半導体基板1を含む。半導体基板1の上には、WSi等の高融点金属層21とAu等の低抵抗金属層22の2層構造からなるT型ゲート電極2が設けられている。また、半導体基板1の表面には、ソース電極3とドレイン電極4が形成されるとともに、表面がパッシベーション膜5で覆われている。
特開平8−45962号公報
FIG. 4 is a cross-sectional view of a semiconductor device having a T-type gate formed by ion milling, the whole being represented by 500. The semiconductor device 500 includes the semiconductor substrate 1. A T-type gate electrode 2 having a two-layer structure of a refractory metal layer 21 such as WSi and a low resistance metal layer 22 such as Au is provided on the semiconductor substrate 1. A source electrode 3 and a drain electrode 4 are formed on the surface of the semiconductor substrate 1, and the surface is covered with a passivation film 5.
Japanese Patent Laid-Open No. 8-45962

図4に示すように、半導体装置500では、T型ゲート電極2の傘部において、高融点金属層21の端部23が鋭角状に突出している。即ち、T型ゲート電極2のゲート長方向の垂直断面において、高融点金属層21の端部23の内角が鋭角となっている。これは、イオンミリングにより高融点金属層21と低抵抗金属層22を同時にエッチングする際に、高融点金属層21が僅かに等方的にエッチングされるため、最初にエッチングが始まった高融点金属層21の表面部分が横方向にもエッチングされるためと考えられる。   As shown in FIG. 4, in the semiconductor device 500, the end portion 23 of the refractory metal layer 21 protrudes at an acute angle in the umbrella portion of the T-type gate electrode 2. That is, in the vertical cross section of the T-type gate electrode 2 in the gate length direction, the inner angle of the end portion 23 of the refractory metal layer 21 is an acute angle. This is because, when the refractory metal layer 21 and the low resistance metal layer 22 are etched simultaneously by ion milling, the refractory metal layer 21 is etched slightly isotropically, so that the refractory metal that has been etched first is started. This is probably because the surface portion of the layer 21 is also etched in the lateral direction.

このように、高融点金属層21の端部23に鋭角状の突起部が形成されると、その上に形成されたパッシベーション膜5が突起部の先端部分で薄くなり、パッシベーション膜5の保護性能が劣化するという問題があった。
また、高温高湿試験を行った結果、突起部近傍のパッシベーション膜5から水分が浸透し、高融点金属層21が腐食することが確認された。
Thus, when an acute-angled protrusion is formed at the end 23 of the refractory metal layer 21, the passivation film 5 formed thereon becomes thin at the tip of the protrusion, and the protection performance of the passivation film 5. There was a problem of deterioration.
Moreover, as a result of performing a high temperature and high humidity test, it was confirmed that moisture permeates from the passivation film 5 in the vicinity of the protrusion and the refractory metal layer 21 is corroded.

そこで、本発明は、2層構造のT型ゲート電極を有する半導体装置において、耐湿性が高く保護性能の劣化しない半導体装置およびその製造方法の提供を目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a two-layer T-type gate electrode, which has high moisture resistance and does not deteriorate protection performance, and a method for manufacturing the same.

本発明は、半導体基板と、半導体基板の上に設けられ、その傘部が高融点金属層とその上に形成された低抵抗金属層とを含むT型ゲート電極と、T型ゲート電極を覆うパッシベーション膜とを含む半導体装置であって、傘部の端部において、高融点金属層の内角が、略90°以上であることを特徴とする半導体装置である。   The present invention covers a semiconductor substrate, a T-type gate electrode provided on the semiconductor substrate, the umbrella portion of which includes a refractory metal layer and a low-resistance metal layer formed thereon, and covers the T-type gate electrode A semiconductor device including a passivation film, wherein an inner angle of the refractory metal layer is approximately 90 ° or more at an end portion of the umbrella portion.

以上の説明から明らかなように、本発明にかかる半導体装置では、パッシベーション膜の耐湿性が良好で、信頼性の高い半導体装置を得ることができる。   As is clear from the above description, in the semiconductor device according to the present invention, it is possible to obtain a highly reliable semiconductor device in which the passivation film has good moisture resistance.

実施の形態1.
図1は、全体が100で表される、本実施の形態1にかかる半導体装置の断面図である。半導体装置100は、GaAs等の半導体基板1を含む。半導体基板1は、リセス11が形成されたリセス構造を有する。半導体基板1の上には、高融点金属層(バリア層)21と低抵抗金属層22の2層構造からなるT型ゲート電極2が設けられている。高融点金属層21としては、WSi、WSiN、Ta、TaN等が用いられる。また、低抵抗金属層22としては、Au等が用いられる。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment, the whole being represented by 100. The semiconductor device 100 includes a semiconductor substrate 1 such as GaAs. The semiconductor substrate 1 has a recess structure in which a recess 11 is formed. A T-type gate electrode 2 having a two-layer structure of a refractory metal layer (barrier layer) 21 and a low resistance metal layer 22 is provided on the semiconductor substrate 1. As the refractory metal layer 21, WSi, WSiN, Ta, TaN or the like is used. As the low resistance metal layer 22, Au or the like is used.

また、半導体基板1の表面には、例えばAuからなるソース電極3とドレイン電極4が形成されている。最終的に、半導体基板1等の表面は例えばSiN、SiOからなるパッシベーション膜5に覆われて保護される。パッシベーション膜5の膜厚は略50nm〜略1μmである。   A source electrode 3 and a drain electrode 4 made of, for example, Au are formed on the surface of the semiconductor substrate 1. Finally, the surface of the semiconductor substrate 1 or the like is covered and protected by a passivation film 5 made of, for example, SiN or SiO. The thickness of the passivation film 5 is about 50 nm to about 1 μm.

半導体装置100では、T型ゲート電極2のゲート長方向(紙面に平行な方向)を含む垂直断面において、高融点金属層21の端部23の内角が略直角となっている。   In the semiconductor device 100, the internal angle of the end portion 23 of the refractory metal layer 21 is substantially perpendicular in the vertical cross section including the gate length direction (direction parallel to the paper surface) of the T-type gate electrode 2.

なお、ここで「内角」とは、T型ゲート電極2のゲート長方向を含む垂直断面において、高融点金属層21の端部23を挟む底面と側面との間の角度をいう。後述のように、底面や側面が外方に湾曲している場合は、端部23における、底面の接線と側面の接線とのなす角をいう。   Here, the “inner angle” refers to an angle between a bottom surface and a side surface sandwiching the end portion 23 of the refractory metal layer 21 in a vertical cross section including the gate length direction of the T-type gate electrode 2. As will be described later, when the bottom surface or the side surface is curved outward, it refers to the angle formed by the bottom surface tangent and the side surface tangent at the end 23.

ゲート電極2等を覆うパッシベーション膜5は、例えばプラズマCVD法で形成するが、一般的に、平坦な部分に比べて、屈曲した部分や突出した部分、ゲート電極の傘部の下部分などには形成しにくい。このため、従来構造の半導体装置500のように、ゲート電極2の端部23に鋭角状の突起部がある場合、突起部近傍ではパッシベーション膜5の膜厚が薄くなったり、膜の組成が化学量論的組成からずれて膜質が劣化するなどの問題があった。   The passivation film 5 that covers the gate electrode 2 and the like is formed by, for example, a plasma CVD method. Generally, the passivation film 5 is formed on a bent portion or a protruding portion, a lower portion of an umbrella portion of the gate electrode, or the like as compared with a flat portion. Hard to form. For this reason, when there is an acute-angled protrusion at the end 23 of the gate electrode 2 as in the conventional semiconductor device 500, the thickness of the passivation film 5 is reduced in the vicinity of the protrusion, or the composition of the film is chemical. There was a problem that the film quality deteriorated due to deviation from the stoichiometric composition.

これに対して、半導体装置100のように、高融点金属層21の端部23の内角を略直角とすることにより、その上に形成されるパッシベーション膜5は、略均一な膜厚で、化学量論的組成からあまりずれることなく形成できる。   On the other hand, as in the semiconductor device 100, by setting the inner angle of the end portion 23 of the refractory metal layer 21 to a substantially right angle, the passivation film 5 formed thereon has a substantially uniform film thickness and a chemical thickness. It can be formed without much deviation from the stoichiometric composition.

半導体装置100の耐湿性は、パッシベーション膜5の膜厚や膜質に依存する。パッシベーション膜5の膜厚が厚いほど水分が膜中を拡散して半導体基板1等に到達する時間が長くなり、耐湿性が向上する。また、化学量論的組成に近く緻密な膜ほど、膜中の水分の拡散速度が遅くなり、耐湿性が向上する。   The moisture resistance of the semiconductor device 100 depends on the thickness and quality of the passivation film 5. The thicker the passivation film 5 is, the longer it takes for moisture to diffuse through the film and reach the semiconductor substrate 1 and the like, thereby improving the moisture resistance. In addition, a denser film with a closer stoichiometric composition has a slower moisture diffusion rate in the film and improves moisture resistance.

このように、本実施の形態1にかかる半導体装置100では、端部23に突起部がないため、端部23近傍におけるパッシベーション膜5の膜厚や膜質の劣化が防止でき、従来の半導体装置500に比較して耐湿性が向上し、信頼性の高い半導体装置100を得ることができる。   As described above, in the semiconductor device 100 according to the first embodiment, since the end portion 23 has no protrusion, the film thickness and film quality of the passivation film 5 in the vicinity of the end portion 23 can be prevented from being deteriorated. As compared with the semiconductor device 100, the moisture resistance is improved and the highly reliable semiconductor device 100 can be obtained.

従来の半導体装置500と本発明の半導体装置100に対して、高温高湿状態での加速試験を行った。実験条件は、温度130℃、湿度85%RH、保持時間は300時間とした。
かかる試験の結果、従来の半導体装置500では、鋭角状の端部23近傍から水分が浸入し、WSiの高融点金属層21全体が水分により酸化または水酸化されて膨潤した。そして、半導体装置500は、動作不良となった。
これに対して、半導体装置100では、高融点金属層21は変質せず、半導体装置100の性能劣化も認められなかった。これは、半導体装置100では、端部23近傍においても、膜質の劣化や膜厚の減少が認められず、良好な耐湿性を有するためと考えられる。
An accelerated test in a high temperature and high humidity state was performed on the conventional semiconductor device 500 and the semiconductor device 100 of the present invention. The experimental conditions were a temperature of 130 ° C., a humidity of 85% RH, and a holding time of 300 hours.
As a result of this test, in the conventional semiconductor device 500, moisture entered from the vicinity of the acute-angled end 23, and the entire refractory metal layer 21 of WSi was oxidized or hydroxylated by moisture to swell. Then, the semiconductor device 500 has malfunctioned.
On the other hand, in the semiconductor device 100, the refractory metal layer 21 did not change, and the performance degradation of the semiconductor device 100 was not recognized. This is presumably because the semiconductor device 100 has good moisture resistance without deterioration of film quality or reduction in film thickness even in the vicinity of the end 23.

次に図2を参照しながら、半導体装置100の製造方法について説明する。かかる製造方法は、以下の工程1〜4を含む。   Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIG. This manufacturing method includes the following steps 1 to 4.

工程1:図2(a)に示すように、GaAs等の半導体基板1を準備する。半導体基板1には、ソース領域やドレイン領域(図示せず)が作製されている。続いて、半導体基板1の表面を部分的にエッチングしてリセス11を作製し、更に、シリコン酸化膜でマスク12を作製する。マスク12を用いて半導体基板1の一部をエッチングする。   Step 1: As shown in FIG. 2A, a semiconductor substrate 1 such as GaAs is prepared. A source region and a drain region (not shown) are formed in the semiconductor substrate 1. Subsequently, the surface of the semiconductor substrate 1 is partially etched to produce a recess 11, and further a mask 12 is made of a silicon oxide film. A part of the semiconductor substrate 1 is etched using the mask 12.

工程2:図2(b)に示すように、スパッタ法を用いてWSi等の高融点金属材料層21’を堆積させる。更に、スパッタ法およびメッキ法でAu等の低抵抗金属材料層22’を堆積させる。   Step 2: As shown in FIG. 2B, a refractory metal material layer 21 'such as WSi is deposited by sputtering. Further, a low resistance metal material layer 22 'such as Au is deposited by sputtering and plating.

工程3:図2(c)に示すように、フォトレジストでレジストマスク24を作製した後、レジストマスク24を用いたドライエッチングで、高融点金属材料層21’と低抵抗金属材料層22’とを一の工程で連続してエッチングし、高融点金属層(バリア層)21と低抵抗金属層22の2層構造からなるT型ゲート電極2を作製する。   Step 3: As shown in FIG. 2C, after forming a resist mask 24 with a photoresist, the refractory metal material layer 21 ′ and the low-resistance metal material layer 22 ′ are formed by dry etching using the resist mask 24. Are continuously etched in one step, and a T-type gate electrode 2 having a two-layer structure of a refractory metal layer (barrier layer) 21 and a low-resistance metal layer 22 is produced.

ドライエッチングには、ECRプラズマエッチングや、反応性イオンエッチング(RIE)が用いられる。エッチングガスにはCl等の塩素系の反応性ガスが用いられる。
エッチングイオン25の入射角のばらつきは、半導体基板1の法線方向から10°以内に抑えることが好ましい。
For dry etching, ECR plasma etching or reactive ion etching (RIE) is used. As the etching gas, a chlorine-based reactive gas such as Cl 2 is used.
The variation in the incident angle of the etching ions 25 is preferably suppressed within 10 ° from the normal direction of the semiconductor substrate 1.

ECRプラズマエッチングを用いる場合は、イオン発生源とエッチング室との間に、メッシュ状の収束グリッドを設け、半導体基板1へのエッチングイオンの入射角度を制御することが好ましい。   When ECR plasma etching is used, it is preferable to provide a mesh-shaped converging grid between the ion generation source and the etching chamber to control the incident angle of the etching ions to the semiconductor substrate 1.

工程4:図2(d)に示すように、レジストマスク24、マスク12を除去した後、例えばAuからなるソース電極3およびドレイン電極4を作製する。
最後に、半導体基板1の表面やゲート電極2を覆うように、例えばプラズマCVD法を用いてSiNやSiOからなるパッシベーション膜5を作製する。
Step 4: As shown in FIG. 2D, after removing the resist mask 24 and the mask 12, the source electrode 3 and the drain electrode 4 made of, for example, Au are produced.
Finally, a passivation film 5 made of SiN or SiO is formed using, for example, a plasma CVD method so as to cover the surface of the semiconductor substrate 1 and the gate electrode 2.

以上の工程により、半導体装置100が完成する。   The semiconductor device 100 is completed through the above steps.

なお、半導体装置100の製造工程として、従来と同じ製造方法で半導体装置500を作製した後に、高融点金属層21の端部23の突起部を選択的に除去しても構わない。   In addition, as a manufacturing process of the semiconductor device 100, after the semiconductor device 500 is manufactured by the same manufacturing method as the conventional method, the protruding portion of the end portion 23 of the refractory metal layer 21 may be selectively removed.

かかる製造方法では、上述の工程1、2を行った後、工程3において、Arガスを用いたイオンミリングで高融点金属材料層21’と低抵抗金属材料層22’とをエッチングし、高融点金属層(バリア層)21と低抵抗金属層22の2層構造からなるT型ゲート電極2を作製する。この時、高融点金属層21の端部23には突起部が形成される。   In such a manufacturing method, after performing the above-described Steps 1 and 2, in Step 3, the refractory metal material layer 21 ′ and the low-resistance metal material layer 22 ′ are etched by ion milling using Ar gas to obtain a high melting point. A T-type gate electrode 2 having a two-layer structure of a metal layer (barrier layer) 21 and a low resistance metal layer 22 is produced. At this time, a protrusion is formed on the end 23 of the refractory metal layer 21.

続いて、工程4でパッシベーション膜5を作製する。この結果、図4に示すような半導体装置500が得られる。   Subsequently, a passivation film 5 is produced in step 4. As a result, a semiconductor device 500 as shown in FIG. 4 is obtained.

次に、フッ酸を用いて、端部23近傍のパッシベーション膜5を選択的に除去する。上述のように、端部23近傍ではパッシベーション膜5の膜厚が薄く膜質も悪いため、かかる部分のパッシベーション膜5が選択的に除去され、高融点金属層21が露出する。   Next, the passivation film 5 near the end 23 is selectively removed using hydrofluoric acid. As described above, since the thickness of the passivation film 5 is thin and the film quality is poor in the vicinity of the end 23, the portion of the passivation film 5 is selectively removed, and the refractory metal layer 21 is exposed.

続いて、露出した部分の高融点金属層21をフッ酸で選択的に除去する。この場合、半導体装置全体をフッ酸に浸すことにより、電池作用により露出した高融点金属層21が選択的にエッチングされる。これにより、端部23における高融点金属層21の内角が、略90°以上となる。   Subsequently, the exposed refractory metal layer 21 is selectively removed with hydrofluoric acid. In this case, the refractory metal layer 21 exposed by the battery action is selectively etched by immersing the entire semiconductor device in hydrofluoric acid. Thereby, the internal angle of the refractory metal layer 21 at the end 23 becomes approximately 90 ° or more.

また、露出した高融点金属層21に高温高湿処理を施して酸化または水酸化することにより、フッ酸によりこの部分を選択的にエッチングすることも可能となる。   Further, this portion can be selectively etched with hydrofluoric acid by subjecting the exposed high melting point metal layer 21 to high temperature and high humidity treatment to oxidize or hydroxylate.

かかる工程で、高融点金属層21の突起部を選択的に除去した後に、再度、プラズマCVD法等でパッシベーション膜5を形成することにより半導体装置100を得ることができる。   In this step, after selectively removing the protrusions of the refractory metal layer 21, the semiconductor device 100 can be obtained by forming the passivation film 5 again by plasma CVD or the like.

実施の形態2.
図3は、全体が200で表される、本実施の形態2にかかる半導体装置の断面図である。図3中、図1と同一符合は、同一又は相当箇所を示す。
Embodiment 2. FIG.
FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment, the whole being represented by 200. 3, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

半導体装置200では、T型ゲート電極2のゲート長方向(紙面に平行な方向)を含む垂直断面において、高融点金属層21の端部23の内角(端部23において高融点金属層21の底面と側面とのなす角)が鈍角(90°より大きな角度)となっている。   In the semiconductor device 200, the internal angle of the end portion 23 of the refractory metal layer 21 (the bottom surface of the refractory metal layer 21 at the end portion 23) in a vertical cross section including the gate length direction (direction parallel to the paper surface) of the T-type gate electrode 2. And the side surface) are obtuse angles (angles greater than 90 °).

このように、高融点金属層21の端部23の内角を鈍角とすることにより、その上に形成されるパッシベーション膜5は、略均一な膜厚で、ほぼ化学量論的組成からずれることなく形成できる。この結果、耐湿性に優れ、信頼性の高い半導体装置200を提供することができる。   In this way, by making the inner angle of the end portion 23 of the refractory metal layer 21 an obtuse angle, the passivation film 5 formed thereon has a substantially uniform film thickness and is not substantially deviated from the stoichiometric composition. Can be formed. As a result, a highly reliable semiconductor device 200 with excellent moisture resistance can be provided.

かかる半導体装置200は、上述の半導体装置100の製造工程3(図2(c))において、低抵抗金属材料層22’をエッチングした後、エッチングイオン25を半導体基板1の法線方向から傾斜させて入射させるともに半導体基板1を回転させながら高融点金属材料層21’をエッチングすることにより形成できる。   In such a semiconductor device 200, after the low resistance metal material layer 22 ′ is etched in the manufacturing process 3 (FIG. 2C) of the semiconductor device 100 described above, the etching ions 25 are inclined from the normal direction of the semiconductor substrate 1. And the refractory metal material layer 21 ′ can be formed by etching while rotating the semiconductor substrate 1.

なお、図3では、端部23において、内角を構成する底面と側面は平坦面として表したが、外方に張り出すように湾曲した面でも構わない。即ち、内角が90°以上であれば、端部23におけるパッシベーション膜5の膜厚や膜質の低下が防止できるため、内角を挟む底面や側面は丸みをもった湾曲面となっても構わない。   In FIG. 3, in the end portion 23, the bottom surface and the side surface constituting the inner angle are expressed as flat surfaces, but may be curved surfaces so as to project outward. That is, if the inner angle is 90 ° or more, the film thickness and film quality of the passivation film 5 at the end portion 23 can be prevented from being lowered. Therefore, the bottom surface and the side surface sandwiching the inner angle may be rounded curved surfaces.

本発明の実施の形態1にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態1にかかる半導体装置の製造工程の断面図である。It is sectional drawing of the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態2にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning Embodiment 2 of this invention. 従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device.

符号の説明Explanation of symbols

1 半導体基板、2 ゲート電極、3 ソース電極、4 ドレイン電極、5 パッシベーション膜、11 リセス、12 マスク、21 高融点金属層、22 低抵抗金属層、23 端部、24 レジストマスク、25 エッチングイオン、100 半導体装置。

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Gate electrode, 3 Source electrode, 4 Drain electrode, 5 Passivation film, 11 Recess, 12 Mask, 21 Refractory metal layer, 22 Low resistance metal layer, 23 End, 24 Resist mask, 25 Etching ion, 100 Semiconductor device.

Claims (2)

T型ゲート電極を有する半導体装置の製造方法であって、
半導体基板を準備する工程と、
該半導体基板上に、高融点金属材料層と低抵抗金属材料層とを順次堆積させる工程と、
該低抵抗金属材料層の上にレジストマスクを形成する工程と、
該レジストマスクをエッチングマスクに用いて、該低抵抗金属材料層と該高融点金属材料層とを連続してエッチングし、高融点金属層と低抵抗金属層の積層構造からなる傘部を有するT型ゲート電極を作製するエッチング工程と、
該T型ゲートを覆うパッシベーション膜を形成する工程とを含み、
該エッチング工程が、反応性のエッチングガスを用いたドライエッチング工程であり、該低抵抗金属材料層をエッチングした後に、該半導体基板を回転させるとともに、該半導体基板の法線方向から所定の角度傾いた方向から該半導体基板にエッチングイオンを入射させ、上記高融点金属材料層をエッチングする工程を含むことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device having a T-type gate electrode,
Preparing a semiconductor substrate;
Sequentially depositing a refractory metal material layer and a low resistance metal material layer on the semiconductor substrate;
Forming a resist mask on the low-resistance metal material layer;
Using the resist mask as an etching mask, the low-resistance metal material layer and the refractory metal material layer are continuously etched, and a T having an umbrella portion having a laminated structure of the refractory metal layer and the low-resistance metal layer. An etching process for producing a mold gate electrode;
Forming a passivation film covering the T-type gate,
The etching step, Ri dry etching process der using reactive etching gas, after etching the low-resistance metal material layer, along with rotating the semiconductor substrate, a predetermined angle from the normal direction of the semiconductor substrate A method of manufacturing a semiconductor device, comprising: etching ions incident on the semiconductor substrate from an inclined direction to etch the refractory metal material layer .
T型ゲート電極を有する半導体装置の製造方法であって、
半導体基板を準備する工程と、
該半導体基板上に、高融点金属材料層と低抵抗金属材料層とを順次堆積させる工程と、
該低抵抗金属材料層の上にレジストマスクを形成する工程と、
該レジストマスクをエッチングマスクに用いて、該低抵抗金属材料層と該高融点金属材料層とを連続してイオンミリングでエッチングし、高融点金属層と低抵抗金属層の積層構造からなる傘部を有するT型ゲート電極を作製する工程と、
該T型ゲートを覆うパッシベーション膜を形成する製膜工程と、
該製膜工程後に、該パッシベーションを選択的にエッチングして該T型ゲート電極の傘部に含まれる該高融点金属層の端部を露出させる工程と、
該高融点金属層の端部を選択的にエッチングして、該端部における該高融点金属層の、高融点金属の端部を挟む底面と側面との間の角度を90°以上にする工程と、
更に、該高融点金属の端部を覆うようにパッシベーション膜を形成する工程とを含むことを特徴とする製造方法。
A method of manufacturing a semiconductor device having a T-type gate electrode,
Preparing a semiconductor substrate;
Sequentially depositing a refractory metal material layer and a low resistance metal material layer on the semiconductor substrate;
Forming a resist mask on the low-resistance metal material layer;
Using the resist mask as an etching mask, the low-resistance metal material layer and the refractory metal material layer are continuously etched by ion milling, and an umbrella portion having a laminated structure of the refractory metal layer and the low-resistance metal layer Producing a T-type gate electrode having :
A film forming step of forming a passivation film covering the T-type gate;
A step of selectively etching the passivation after the film forming step to expose an end portion of the refractory metal layer included in the umbrella portion of the T-type gate electrode;
The edge of the refractory metal layer is selectively etched so that the angle between the bottom surface and the side surface of the refractory metal layer sandwiching the edge of the refractory metal is 90 ° or more. Process,
And a step of forming a passivation film so as to cover an end portion of the refractory metal .
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