JP4748877B2 - Storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-port SRAM (Static Random Access Memory) composed of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and more particularly to a technique for reading and writing data from / to a memory cell of the SRAM.
[0002]
[Prior art]
In an integrated circuit, an SRAM has a function of temporarily storing data and instructions in order to transmit data and data to a CPU in accordance with the timing of a cache, that is, a CPU (Central Processing Unit). Used to memorize. In recent years, the rate at which data is read from or written to the memory has been emphasized. In order to increase the bandwidth of the memory, a technique has been proposed in which a plurality of input / output terminals are provided in an SRAM memory cell. As this technology, a dual port static memory cell having one read port and one write port, and a multi-port having many read terminals and write terminals ( multi port) Static memory cell can be cited as an example.
[0003]
FIG. 51 is a conceptual diagram showing a configuration around a memory cell array of a conventional SRAM. The memory cells are arranged in a matrix of m rows and n columns, and the memory cells in the i rows and j columns are MC._ijLet's show it as In FIG. 51, memory cells MC arranged in the first row and the third column.₁₃The symbol of is described.
[0004]
  The SRAM shown in FIG. 51 employs a configuration in which word lines extend in the row direction and bit lines extend in the column direction. The word line decoder 3 includes a word line group 30_i(I = 1, 2, 3,..., M−1, m) are connected to the input row address RA.CorrespondingWord line group 30_iIs selectively activated. The bit line decoder 4 includes a bit line group 40._jBit line group 40 connected to (j = 1, 2, 3,..., N−1, n) and corresponding to input column address CA._jIs selectively activated.
[0005]
Memory cell MC_ijWord line group 30 in FIG._iAnd bit line group 40_jIntersect. That is, a common word line group is laid on the plurality of memory cells arranged in the row direction, and a common bit line group is laid on the plurality of memory cells arranged in the column direction.
[0006]
Word line group 30_iIs the write word line 31_iRead word line 33_iRead complementary word line 32_iThe latter two form a read word line pair. The bit line group 40_jIs the write bit line 41_jWrite complementary bit line 42_jRead bit line 43_jThe former two form a write bit line pair.
[0007]
FIG. 52 is a circuit diagram illustrating a structure common to all the memory cells MC. Since the structure of the memory cell MC basically does not depend on the position (i, j) of the row or column, the subscript indicating the position of the row or column is omitted here.
[0008]
Memory cell MC includes a storage unit SC (referred to herein as a “storage cell”) SC having a pair of inverters L1 and L2 connected in antiparallel, a read circuit RK, and access transistors QN3 and QN4. ing.
[0009]
In the storage cell SC, the inverter L1 is constituted by series connection of transistors QP1 and QN1, and the inverter L2 is constituted by series connection of transistors QP2 and QN2. Further, the readout circuit RK includes a tristate inverter constituted by series connection of transistors QP3, QP4, QN5, and QN6.
[0010]
N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for the transistors QN1 to QN6, and P-type MOSFETs are used for the transistors QP1 to QP4. For example, the N-type MOSFET is a surface channel type, and the P-type MOSFET is a surface channel type or a buried channel type.
[0011]
The storage cell SC has a pair of nodes N1 and N2, and there is a pair of storage states when the nodes N1 and N2 are “H” and “L”, respectively, and vice versa. “H” means (V_DD+ V_SS) / 2 means logic corresponding to a potential higher than “/ 2”, and “L” means (V_DD+ V_SS) / 2 means a logic corresponding to a potential lower than 2. However, the potential V_SSIn many cases, the ground is selected. Hereinafter, “H” and “L” may mean not only logic but also potentials corresponding to the logic. It should be noted that which one of “H” and “L” corresponds to the SRAM bits “1” and “0” is a matter of design choice.
[0012]
  The N-type MOSFET is turned on when “H” is applied to its gate and turned off when “L” is applied. The P-type MOSFET is turned on when “L” is applied to its gate and turned off when “H” is applied. In the ON state, a current flows between the source / drain, and the two are electrically connected. In the off state, the source / drain is electrically disconnected and the current isAlmostNot flowing.
[0013]
The node N1 is an input terminal of the inverter L2, and a potential corresponding to a logic complementary to the logic corresponding to the potential of the node N1 is output to the node N2. The node N2 is an input terminal of the inverter L1, and an inverted bit of logic complementary to the logic corresponding to the potential of the node N2 is output to the node N1. Therefore, a pair of storage states corresponding to complementary logics exist.
[0014]
Access transistor QN3 is connected to storage cell SC and write bit line 41 at nodes N1 and N4, respectively. Access transistor QN4 is connected to storage cell SC and write complementary bit line 42 at nodes N2 and N5, respectively. The gates of access transistors QN3 and QN4 are commonly connected to write word line 31.
[0015]
In the read circuit RK, the drains of the transistors QP4 and QN5 are commonly connected to the node N3. The gates of the transistors QP3 and QN6 are commonly connected to the node N1. The gates of the transistors QP4 and QN5 are connected to the read supplement word line 32 and the read word line 33, respectively. As described above, a dual port static memory cell is adopted as the memory cell MC.
[0016]
When reading data from the memory cell MC, complementary logic is set in the read word line 33 and the read complementary word line 32. Then, the read word line 33 and the read complementary word line 32 corresponding to the row of the memory cell MC to be read are set to “H” and “L”, respectively, and the read word line 33 and the read corresponding to the other rows are read. The complementary word line 32 is set to “L” and “H”, respectively.
[0017]
Accordingly, the transistors QP4 and QN5 of the read circuit RK of the memory cell MC to be read are all turned on. Thus, a value complementary to node N1 is applied to read bit line 43 via node N3 by the inverter formed by transistors QP3 and QN6. On the other hand, the transistors QP4 and QN5 of the read circuit RK of the memory cell MC that is not the read target are both turned off. As a result, the read bit line 43 is disconnected from the storage cell SC of the memory cell MC that is not the target of reading.
[0018]
When writing data to the memory cell MC, the write word line 31 corresponding to the row of the memory cell MC to be written is set to “H”, and the write word line 31 corresponding to the other rows is set to “H”. L "is set.
[0019]
Accordingly, the access transistors QN3 and QN4 of the memory cell MC to be written are both turned on, and the nodes N1 and N2 of the storage cell SC are connected to the write bit line 41 and the write complementary bit line 42 via the nodes N4 and N5, respectively. Is done. On the other hand, the access transistors QN3 and QN4 of the memory cell MC that is not the target of writing are both turned off, and the nodes N1 and N2 of the storage cell SC are disconnected from the write bit line 41 and the write complementary bit line 42.
[0020]
As described above, since the logic of the nodes N1 and N2 of the storage cell SC has a complementary relationship, the write bit line 41 and the write complementary bit line 42 corresponding to the column of the memory cell MC to be written are complementary. The logic is set. Then, the logic set in the write bit line 41 and the write complementary bit line 42 is written in the nodes N1 and N2.
[0021]
When the write operation is completed, the write word line 31 is set to “L”, and the access transistors QN3 and QN4 are turned off. Therefore, the storage cell SC is disconnected from the write bit line pair, and the data held in the storage cell SC is not rewritten and enters the standby state.
[0022]
[Problems to be solved by the invention]
In the above configuration, when the write word line 31 is set to “H” during the write operation, the access transistors QN3 and QN4 are turned on in all the memory cells MC belonging to the same row as the memory cell MC to be written. . Therefore, in the memory cell MC that belongs to the same row as the memory cell MC to be written and is not to be written, during the write operation, the nodes N1 and N2 are connected to the write bit line 41 and the write through the access transistors QN3 and QN4, respectively. The complementary bit line 42 is connected.
[0023]
On the other hand, both the write bit line 41 and the write complementary bit line 42 corresponding to the column of memory cells MC that are not to be written are normally precharged with the same potential. The precharge potential is, for example, V_DD, (V_DD+ V_SS) / 2, V_SSIt is. Therefore, depending on the potentials of the nodes N1 and N2 of the memory cell MC, the potential of one of the write bit line 41 and the write complementary bit line 42 becomes V_SSAnd the other potential is (V_DD-V_thn) (But the write word line 31 has a potential V)._DDIs applied, and the threshold voltage of transistors QN3 and QN4 is set to V_thn> 0). Application of a potential through the nodes N1 and N2 to the precharged write bit line pair in this way causes unnecessary power consumption.
[0024]
Further, the bit line pair to which the potential is applied by the storage cell SC as described above is precharged again in preparation for the next write operation. At this time, unnecessary power is newly consumed.
[0025]
FIG. 53 is a circuit diagram showing a configuration of a memory cell MC proposed to prevent the above power consumption, and is introduced in, for example, US Pat. No. 6,005,794.
[0026]
NMOS transistors QN9 and QN10 are connected to node N1 and potential V_SSPotential point (hereinafter “potential point V_SSFor example, connected in series with the ground. The gate of the NMOS transistor QN9 is connected to the write bit line 41 at the node N4, and the gate of the NMOS transistor QN10 is connected to the write word line 31. Similarly, the NMOS transistors QN11 and QN12 are connected to the node N2 and the potential point V._SSAre connected in series. The gate of the NMOS transistor QN11 is connected to the write complementary bit line 42 at the node N5, and the gate of the NMOS transistor QN12 is connected to the write word line 31.
[0027]
The write word line 31 corresponding to the memory cell MC to be written (that is, in the selected row) becomes “H” during the write operation, and the transistors QN10 and QN12 are turned on. Since complementary logic is applied to the write bit line 41 and the read bit line 43 corresponding to the memory cell MC (that is, in the selected column), only one of the transistors QN9 and QN11 is turned on. If the write bit line 41 and the write complementary bit line 42 are “H” and “L”, respectively, the node N1 is set to logic “L”. As a result, the node N2 becomes “H”. Conversely, if the write bit line 41 and the write complementary bit line 42 are “L” and “H”, respectively, the node N2 is set to logic “L”. As a result, the node N1 becomes “H”.
[0028]
During such a write operation, any unselected write bit pair lines are at potential V_SSSet to Therefore, since the transistors QN9 and QN11 are turned off in the memory cell MC that is not a write target, the memory cell MC is arranged in a row corresponding to the selected write word line 31 and the write word line 31 is “H”. Even in the MC, the nodes N1 and N2 are not forcibly set from the outside of the storage SC. That is, there is an advantage that the above unnecessary power consumption does not occur.
[0029]
However, this circuit has a problem that the time required for the write operation for changing the stored contents of the storage cell SC is long. That is, one of the nodes N1 and N2 is set to “L” from the outside of the storage cell SC, but there is no function of setting the other to “H” from the outside of the storage cell SC. For example, when the state where the nodes N1 and N2 are “H” and “L”, respectively, is inverted to the complementary state, the transistors QN9 and QN10 are turned on to try to discharge the node N1. Since N2 is “L” and is not set to “H” from the outside of the storage cell SC, the inverter L1 tries to hold the node N1 at “H”. Since the storage cell SC is designed to have a high static noise margin in order to stably hold data, the storage contents of the storage cell SC cannot be reversed quickly only by discharging the node N1.
[0030]
The present invention has been made based on the above background, and an object of the present invention is to provide a technique for reducing unnecessary power consumption while rapidly performing writing to invert stored contents.
[0031]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a storage device comprising: (a) a plurality of word line groups; (b) a plurality of bit line groups; and (c) a plurality of memory cells. Each of the line groups has (a-1) write word lines, and each of the bit line groups has (b-1) write bit lines and (b-2) write provided corresponding to the write bit lines. (C) each of the memory cells is provided corresponding to one word line group and one bit line group, and (c-1) a storage including a first storage node A cell, (c-2) connected between the write bit line of the corresponding one bit line group and the first storage node, and the write word line of the corresponding one word line group; , Conductive only when any of the write control lines is activated And a first switch that. Then, the write control line in the selected bit line group is activated, and the write control line in the unselected bit line group is not activated.
[0032]
  AndEach of the bit line groups further includes (b-3) a write complementary bit line provided corresponding to the write bit line, and each of the storage cells includes (c-1-1) the Each of the memory cells includes: (c-3) the write complementary bit line of the corresponding one bit line group; and a second storage node provided with a logic complementary to the logic in the one storage node. A second switch connected between the second storage node and conducting only when both the write word line of the corresponding one word line group and the write control line are activated; The write bit line and the write complementary bit line adopt complementary logic to each other when the bit line group to which the write bit line belongs are selected, and adopt equal logic to each other when not selected. The bit In the lines, the write control line takes the exclusive OR of the write bit line and write complementary bit line.
[0033]
  Claim of the invention2The claim is1The exclusive OR is obtained after non-inverting amplification of the potentials of the write bit line and the write complementary bit line.
[0037]
According to a third aspect of the present invention, there is provided a storage device comprising (a) a plurality of word line groups, (b) a plurality of bit line groups, and (c) a plurality of memory cells, wherein the word Each of the line groups has (a-1) write word lines, and each of the bit line groups has (b-1) write bit lines and (b-2) write provided corresponding to the write bit lines. (C) each of the memory cells is provided corresponding to one word line group and one bit line group, and (c-1) a storage including a first storage node A cell, (c-2) connected between the write bit line of the corresponding one bit line group and the first storage node, and the write word line of the corresponding one word line group; , Conductive only when any of the write control lines is activated And a first switch that. Then, the write control line in the selected bit line group is activated, and the write control line in the unselected bit line group is not activated.
  AndThe first switch includes (c-2-1) a control electrode, a first current electrode connected to the write bit line, and a second current electrode connected to the first storage node. (C-2-2) a control electrode connected to the write control line, a first current electrode connected to the control electrode of the first transistor, and a write word line And a second transistor having a second current electrode formed thereon.
[0038]
According to a fourth aspect of the present invention, there is provided a storage device comprising (a) a plurality of word line groups, (b) a plurality of bit line groups, and (c) a plurality of memory cells, wherein the word Each of the line groups has (a-1) write word lines, and each of the bit line groups has (b-1) write bit lines and (b-2) write provided corresponding to the write bit lines. (C) each of the memory cells is provided corresponding to one word line group and one bit line group, and (c-1) a storage including a first storage node A cell, (c-2) connected between the write bit line of the corresponding one bit line group and the first storage node, and the write word line of the corresponding one word line group; , Conductive only when any of the write control lines is activated And a first switch that. Then, the write control line in the selected bit line group is activated, and the write control line in the unselected bit line group is not activated.
  AndThe first switch includes (c-2-1) a control electrode to which the write word line is connected, a first current electrode, and a second current electrode connected to the write control line. A first transistor; and (c-2-2) a control electrode connected to the first current electrode of the first transistor; a first current electrode connected to the write bit line; and the first memory. And a second transistor having a second current electrode connected to the node.
[0044]
  Claim of the invention5The claim is3The first transistor is an NMOS transistor formed on an SOI substrate, and the inactive write word line is connected to the first current electrode and the body of the first transistor. A potential to reduce forward bias is applied.
[0051]
DETAILED DESCRIPTION OF THE INVENTION
In the present embodiment, unless otherwise specified, logic “H” corresponds to a state in which a word line is activated, that is, selected, and “L” represents that it is not activated, that is, not selected. A description will be given assuming that it corresponds. Even if these relations are reversed, the following explanation is valid if the conductivity type of the transistor used is appropriately changed.
[0052]
Embodiment 1 FIG.
1 is a conceptual diagram showing a configuration around a memory cell array of an SRAM according to a first embodiment of the present invention. A bit line group 40 compared to the conventional SRAM configuration._jWrite control line 44_jIt is a characteristic structure that is added. Write control line 44_jAlso, the bit line decoder 4 sets the potential (or logic). Specifically, the write control line 44_jIn the write bit line 41,_jLogic and write complementary bit line 42_jIs set to a logic equivalent to an exclusive OR (hereinafter also referred to as “XOR (exclusive OR)”). First, for the sake of simplicity, the write bit line 41_jAnd write complementary bit line 42_jHas a potential V during the precharge period._DD, V_SSIt is assumed that either of the above is given.
[0053]
FIG. 2 is a circuit diagram illustrating one configuration of the memory cell MC shown in FIG. As in the prior art, subscripts indicating row positions and column positions are omitted. The memory cell MC includes a storage cell SC, a read circuit RK, and pass transistors MN9, MN10, MN11, and MN12, all of which are NMOS transistors, a write bit line 41, a write complementary bit line 42, a read bit line 43, and a write A word line 31, a read supplement word line 32, and a read word line 33 are laid.
[0054]
The storage cell SC has inverters L1 and L2 connected in antiparallel, and nodes N1 and N2 exist as output terminals of the storage cells SC. The inverter L1 has a potential V_DD, A PMOS transistor QP1 including a source connected to the node N1, a drain connected to the node N1, a gate connected to the node N2, and a potential V_SSAnd an NMOS transistor QN1 including a drain connected to the node N1 and a gate connected to the node N2. Similarly, the inverter L2 has the potential V_DD, A PMOS transistor QP2 including a source connected to the node N2, a drain connected to the node N2, a gate connected to the node N1, and a potential V_SSAnd an NMOS transistor QN2 including a drain connected to the node N2, and a gate connected to the node N1.
[0055]
The read circuit RK has a potential V_DDA PMOS transistor QP3 including a gate connected to the node N1, a drain connected to the read bit line 43 at the node N3, and a PMOS transistor QP4 including a gate connected to the read complement word line 32; Potential V_SSNMOS transistor QN6 including a gate connected to node N1, a drain connected to read bit line 43 at node N3, and an NMOS transistor QN5 including a gate connected to read word line 33 Tristate inverter. The drain of the transistor QP3 and the source of the transistor QP4 are connected, and the drain of the transistor QN6 and the source of the transistor QN5 are connected.
[0056]
FIG. 3 is a circuit diagram illustrating the configuration of the tri-state inverter, and substantially shows the configuration of the readout circuit RK. Logic A is common to one gate of the pair of NMOS transistors and one gate of the pair of PMOS transistors, logic B is assigned to the other gate of the pair of NMOS transistors, and logic B is assigned to the other gate of the pair of PMOS transistors. Bars (which are complementary to B and are indicated by adding an upper line to B in the figure: the same applies to the other logics). If the logic B is “L”, the output logic Z is not determined by the tristate inverter (tristate condition). However, if the logic B is “H”, the logic Z obtained by inverting the logic A is output.
[0057]
Returning to FIG. 2, the pass transistors MN9 and MN10 are connected in series between the node N4 on the write bit line 41 and the node N1 of the storage cell SC, and both the write control line 44 and the write word line 31 are “H”. ", It functions as a switch for transmitting the logic of the write bit line 41 to the node N1. More specifically, one of the current electrode pair (source / drain pair) of the pass transistor MN9 is connected to the node N1, and one of the current electrode pair of the pass transistor MN10 is connected to the node N4, and the currents of the pass transistors MN9 and MN10. The other electrode pair is connected in common. The gate of the pass transistor MN9 is connected to the write control line 44 at the node N6, and the gate of the pass transistor MN10 is connected to the write bit line 41 at the node N4.
[0058]
Similarly, the pass transistors MN11 and MN12 are connected in series between the node N5 on the write complementary bit line 42 and the node N2 of the storage cell SC, and both the write control line 44 and the write word line 31 are “H”. ", It functions as a switch for transmitting the logic of the write complementary bit line 42 to the node N2. More specifically, one of the current electrode pairs of the pass transistor MN11 is connected to the node N2, one of the current electrode pairs of the pass transistor MN12 is connected to the node N5, and the other of the current electrode pairs of the pass transistors MN11 and MN12 is Connected in common. The gate of the pass transistor MN11 is connected to the write control line 44 at the node N6, and the gate of the pass transistor MN12 is connected to the write bit line 41 at the node N4.
[0059]
The operations of the pass transistors MN10 and MN12 depend on the logic in the write word line 31, similar to the transistors QN10 and QN12 shown in FIG._SSAre connected to the write bit line 41 and the write complementary bit line 42, respectively. Similarly to transistors QN9 and QN11 shown in FIG. 53, pass transistors MN9 and MN11 are interposed between pass transistor MN10 and node N1, and between transistor MN12 and node N2, respectively. Is different depending on the logic in the write control line 44.
[0060]
The write operation for the memory cell having such a configuration is as follows. The selected write word line 31 becomes “H” and the pass transistors MN10 and MN12 are turned on. One of the write bit line 41 and the write complementary bit line 42 constituting the write bit pair line is “H”, and the other is “L”. In response to this, the write control line 44 becomes “H”, so that the pass transistors MN9 and MN11 are turned on.
[0061]
Therefore, the node N1 of the storage cell SC is connected to the write bit line 41 at the node N4 via the pass transistors MN9 and MN10, and the node N2 is connected to the write complementary bit line 42 at the node N5 via the pass transistors MN11 and MN12. The Since the logic set in the write bit line 41 and the write complementary bit line 42 is written to N1 and N2, respectively, the data stored in the storage cell SC is inverted as compared with the circuit shown in FIG. The time required for is short.
[0062]
In order to consider the magnitude of the potential, the threshold voltages of the pass transistors MN9 and MN10 are set to the potential V._thnThe write control line 44, the write word line 31 and the write bit line 41 are set to “H” and the potential V_DDIs given. Since the pass transistors MN9 and MN10 are interposed between the node N4 and the node N1, due to the substrate effect of these two transistors, the potential (V_DD-2V_thn) Is applied.
[0063]
Potential difference (V_DD-V_SS) Becomes 1V or less, the inverters L1 and L2 of the storage cell SC are at the potential (V_DD-2V_thn) May be recognized as “L” instead of “H”. In order to prevent this, the potential applied as “H” to the write word line 31 is set to the potential V_DDHigher than, for example, potential (V_DD+ 2V_thn) May be set. Further, the potential applied as “H” to the write word line 31 and the write control line 44 is set to the potential (V_DD+ V_thn), The same effect can be obtained.
[0064]
Now, the operation of the memory cells MC arranged in the row corresponding to the selected write word line 31 and arranged in the column corresponding to the unselected write bit line pair will be described. In the memory cell MC, the write bit line 41 and the write complementary bit line 42 are both set to “H” or “L” by precharging. In response to this, the write control line 44 is set to “L”. In other words, the write control line 44 is “L” in the unselected column. Therefore, even if the write word line 31 is “H” and the transistors MN10 and MN12 are on, the transistors MN9 and MN11 are off and the storage cell SC is set to the potential of the write bit line 41 and the write complementary bit line 42. There is no impact. Therefore, unnecessary power consumption can be reduced while writing to invert the stored contents is performed quickly.
[0065]
4 to 9 are circuit diagrams illustrating an XOR circuit that obtains the exclusive OR of both from the logics A and B as the logic Z. FIG. These XOR circuits can be employed to obtain the exclusive OR of the logic applied to the write bit line 41 and the logic applied to the write complementary bit line 42 with respect to the write control line 44. Although FIG. 1 shows a mode in which the XOR circuit is built in the bit line decoder 4, a mode in which the XOR circuit is provided separately from the bit line decoder 4 may be adopted.
[0066]
For example, the operation of the XOR circuit shown in FIG. 7 will be described. When the logic A is “H”, the inverter composed of the PMOS transistor TP1 and the NMOS transistor TN1 gives the logic “L” to the node J1. On the other hand, a logic A, that is, “H” is given to the node J2. The PMOS transistor TP2 and the NMOS transistor TN2 are connected in series between the nodes J2 and J1, and both function as an inverter. This inverter inputs logic B and outputs a logic B bar as logic Z to node J3. At this time, since the transmission gate formed by the PMOS transistor TP3 and the NMOS transistor TN3 is off, the collision between the logic B and the logic B bar does not occur at the node J3.
[0067]
When the logic A is “L”, the nodes J1 and J2 are “H” and “L”, respectively. Accordingly, both the transistors TP3 and TN3 are turned on, and the logic B is supplied as the logic Z to the node J3. On the other hand, when the logic B is “H”, the logic “H” at the node J1 is transmitted to the node J3 by the NMOS transistor TN2, and when the logic B is “L”, the logic “H” at the node J2 is transmitted by the PMOS transistor TP2. L ″ is transmitted to the node J3. Therefore, in any case, the logic B is given as the logic Z at the node J3.
[0068]
From the above operation, the circuit of FIG. 7 gives the XOR of logic A and B. In order to obtain a value complementary to the exclusive OR (XNOR: exclusive NOR), the output may be further inverted, or only one of the logic A and the logic B is inverted to obtain the XOR. May be input to the circuit.
[0069]
FIG. 10 is a circuit diagram showing a modification of the present embodiment. Compared to the configuration shown in FIG. 2, the transistor MN9 whose switching is controlled by the logic of the write control line 44 and the transistor MN10 whose switching is controlled by the logic of the write word line 31 are between the nodes N1 and N4. They are common in that they are connected in series, and are different in that their positions are interchanged. Similarly, the positions of the transistors MN11 and MN12 are switched between the nodes N2 and N5 as compared with the configuration shown in FIG. It is natural that such a configuration can achieve the same effect as the configuration shown in FIG.
[0070]
FIG. 11 is a schematic view illustrating the configuration of the pass transistors MN9, MN10, MN11, and MN12. For simplicity, the storage cell SC has inverters L1 and L2 indicated by symbols, while the pass transistors MN9, MN10, MN11, and MN12 have write bit lines 41, write complementary bit lines 42, write control lines 44, and write word lines. The configuration is shown in plan view together with 31. In the figure, the reference numerals shown in parentheses correspond to the configuration shown in FIG. 10, and the reference signs on the left side thereof correspond to the configuration shown in FIG.
[0071]
FIG. 11 will be described in accordance with the configuration shown in FIG. Pass transistors MN9 and MN10 are formed in the active region R1. One of the current electrode pairs of the pass transistor MN9 is connected to the node N1, and one of the current electrode pairs of the pass transistor MN10 is connected to the write bit line 41. In the pass transistors MN9 and MN10, the other of the current electrode pair shares the source / drain region SD1. Similarly, pass transistors MN11 and MN12 are formed in the active region R2. One of the current electrode pairs of the pass transistor MN11 is connected to the node N2, and one of the current electrode pairs of the pass transistor MN12 is connected to the write complementary bit line. In the pass transistors MN11 and MN12, the other of the current electrode pairs shares the source / drain region SD2.
[0072]
A gate line G1 that functions as the gates of the pass transistors MN9 and MN11 and a gate line G2 that functions as the gates of the pass transistors MN10 and MN12 are located above the active regions R1 and R2 via a gate insulating film (not shown). It is laid on the front side of the page. The write control line 44 and the write word line 31 are laid above the gate lines G1 and G2. The write control line 44 and the write word line 31 are connected to the gate wirings G1 and G2 via the via contacts V1 and V2, respectively.
[0073]
Since the pass transistors MN9 and MN10 share the source / drain region SD1 and the pass transistors MN11 and MN12 share the source / drain region SD2 as described above, they can be arranged in a small area.
[0074]
The write bit line 41_jAnd write complementary bit line 42_jIncludes a potential (V_DD+ V_SS) / 2 may be applied. In this case, the write bit line 41 is placed before the XOR circuit._jAnd write complementary bit line 42_jIt is sufficient to provide a circuit for non-inverting amplification of each potential. For example V_SS= 0V, the input margin of the XOR circuit is large and the potential is 2V_DDIs allowed, the amplification factor of the amplifier circuit may be set to double. As a result, the precharge potential becomes V_DD/ 2 even if V_DDEven so, the pair of inputs of the XOR circuit are both “H”. The precharge potential is V_SSIf so, the pair of inputs of the XOR circuit are both “L”. Therefore, the effect of this embodiment can be enjoyed.
[0075]
Embodiment 2. FIG.
FIG. 12 is a conceptual diagram showing a configuration around the memory cell array of the SRAM according to the second embodiment of the present invention. In contrast to the SRAM configuration shown in the first embodiment, a bit line group 40_jWrite auxiliary control line 45_jIs added to the word line group 30._iWrite complementary word line 34_iIt is a characteristic structure that is added.
[0076]
Write auxiliary control line 45_jWrite complementary word line 34_iThe potential (or logic) is set by the bit line decoder 4 and the word line decoder 3, respectively. Specifically, the write auxiliary control line 45_jWrite complementary word line 34_iWrite control lines 44 respectively._jWrite word line 31_iComplementary logic is given.
[0077]
FIG. 13 is a circuit diagram illustrating one configuration of the memory cell MC shown in FIG. As in the prior art, subscripts indicating row positions and column positions are omitted. Compared with the configuration shown in FIG. 2, the memory cell MC is additionally provided with pass transistors MP9, MP10, MP11, and MP12 which are PMOS transistors, and a write complementary control line 45 and a write complementary word line. 34 is additionally laid.
[0078]
The pass transistors MP9, MP10, MP11, and MP12 are connected in parallel with the pass transistors MN9, MN10, MN11, and MN12, respectively. The logic given to the gates of the pass transistors MP9, MP10, MP11, MP12 is complementary to the logic given to the gates of the pass transistors MN9, MN10, MN11, MN12, respectively. That is, the gates of the pass transistors MP9 and MP11 are connected to the write complementary control line 45 at the node N7, and the gates of the pass transistors MP10 and MP12 are connected to the write complementary word line.
[0079]
Therefore, the pass transistors MP9, MP10, MP11, and MP12 constitute a transmission gate together with the pass transistors MN9, MN10, MN11, and MN12, respectively. Therefore, as compared with the configuration shown in FIG. 2, when logic “H” is transmitted from the write bit line 41 to the node N1 (or when logic “H” is transmitted from the write complementary bit line 42 to the node N2). Threshold V due to substrate effect_thnThere is no reduction in minutes. Therefore, there is an advantage that a booster circuit that boosts the potential applied to the write word line 31 is unnecessary.
[0080]
FIG. 14 is a circuit diagram showing a modification of the present embodiment, and corresponds to FIG. 10 according to the first embodiment. That is, in the configuration shown in FIG. 14, the positions of the transmission gates formed by the pass transistors MN9 and MP9 and the transmission gates formed by the pass transistors MN10 and MP10 are compared with the configuration shown in FIG. , N4, and the positions of the transmission gate formed by the pass transistors MN11 and MP11 and the transmission gate formed by the pass transistors MN12 and MP12 are switched between the nodes N2 and N5. It is natural that the effects of the present embodiment can be obtained even with such a configuration.
[0081]
Of course, similarly to the pass transistors MN9 and MN10, the pass transistors MP9 and MP10 can also share a source / drain region to save a necessary area. The same applies to the pass transistors MP11 and MP12.
[0082]
Even if the access transistor is replaced with a transmission gate, the threshold value V due to the substrate effect is applied._thnA decrease in minutes can be avoided. FIG. 15 is a circuit diagram of FIG. 52 in which a write supplement word line 34 is added, the access transistor QN3 is replaced with a transmission gate formed by a PMOS transistor MP10 and an NMOS transistor MN10, and the access transistor QN4 is replaced with a PMOS transistor MP12. A configuration in which the transmission gate formed by the NMOS transistor MN12 is replaced is shown.
[0083]
Similarly to the configuration shown in FIG. 14, the conduction of the transistors MN10 and MN12 is controlled by the logic of the write word line 31, and the transistors MP10 and MP12 are controlled by the logic of the write complementary word line 34. Threshold value V_thnCan be avoided. Therefore, it is not necessary to boost the potential applied to the write word line 31. Compared with the configuration shown in FIGS. 13 and 14, the time for accessing the storage cell SC is shortened as the transmission gate is decreased one by one, the area penalty is small, and the write control line 44 is also reduced. Therefore, there is an advantage that it is not necessary to provide an XOR circuit. However, unlike the present embodiment, the memory cell MC in the non-selected column is inferior in the function of avoiding a potential collision between the storage cell SC and the write bit line pair.
[0084]
Embodiment 3 FIG.
FIG. 16 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, the subscripts indicating the row position and the column position are omitted, but the MC shown in FIG._ijCan be adopted as each of.
[0085]
Compared to the configuration shown in FIG. 52, memory cell MC is provided with access transistors MN2 and MN4 and control transistors MN1 and MN3, both of which are NMOS transistors, instead of access transistors QN3 and QN4.
[0086]
Similar to access transistor QN3, access transistor MN2 controls conduction between nodes N1 and N4. The gate is common to the access transistor QN3 in that a write word line 31 is connected, but is different in that a control transistor MN1 is interposed. The access transistor MN4 also controls conduction between the node N2 and the node N5, and is common to the access transistor QN4 in that the write word line 31 is connected to the gate, but is different in that the control transistor MN3 is interposed.
[0087]
Since the gates of the control transistors MN1 and MN3 are connected to the write control line 44 via the node N6, the conduction between the node N1 and the node N4 and between the node N2 and the node N5 is similar to that in the first embodiment. These are limited to the case where both the write word line 31 and the write control line 44 are “H”. Accordingly, unnecessary power consumption can be reduced while writing to invert the stored contents is performed quickly as in the first embodiment.
[0088]
The above configuration is disadvantageous compared to the configuration described in the first embodiment in that the control transistor MN1 and the access transistor MN2 or the control transistor MN3 and the access transistor MN4 cannot share the source and drain.
[0089]
However, the control transistors MN1 and MN3 are both turned on depending on the logic on the write control line 44, and the logic on the write word line 31 is transmitted to the gates of the access transistors MN2 and MN4 by the conduction. Therefore, as shown in FIG. 17, the control transistor MN3 can be modified by merging it with MN1, and the required area can be reduced.
[0090]
Embodiment 4 FIG.
FIG. 18 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, the subscripts indicating the row position and the column position are omitted, but the MC shown in FIG._ijCan be adopted as each of. In the memory cell MC, the control transistors MN1 and MN3 are replaced with control transistors MN5 and MN6 as compared to the configuration shown in FIG.
[0091]
  The gates of the control transistors MN5 and MN6 are commonly connected to the write word line 31. The control transistor MN5 is interposed between the write bit line 41 and the gate of the access transistor MN2, and the control transistor MN6 is connected to the write complementary bit line 42 and the access transistor MN.4It is interposed between the gates. Therefore, as in the first embodiment, conduction between the node N1 and the node N4 and between the node N2 and the node N5 is limited only when both the write word line 31 and the write control line 44 are “H”. It is done. Accordingly, unnecessary power consumption can be reduced while writing to invert the stored contents is performed quickly as in the first embodiment.
[0092]
The above configuration is disadvantageous compared to the configuration described in the first embodiment in that the control transistor MN5 and the access transistor MN2 or the control transistor MN6 and the access transistor MN4 cannot share the source and drain.
[0093]
However, the control transistors MN5 and MN6 are both turned on depending on the logic on the write word line 31, and the conduction of the control transistors MN5 and MN6 transmits the logic on the write control line 44 to the gates of the access transistors MN2 and MN4. Therefore, as shown in FIG. 19, a modification in which the control transistor MN6 is merged with MN5 is possible, and a necessary area can be reduced.
[0094]
Embodiment 5 FIG.
FIG. 20 is a circuit diagram illustrating one configuration of the memory cell MC according to this embodiment. As in the prior art, the subscripts indicating the row position and the column position are omitted, but the MC shown in FIG._ijCan be adopted as each of. However, the auxiliary write control line 45 is not necessary. The memory cell MC is mainly different from the configuration shown in FIG. 53 by two points.
[0095]
As a first difference, the transistor QN9 is not directly connected to the node N1, and the pass transistor MN9 is interposed between the two. Similarly, the transistor QN11 is not directly connected to the node N2, and a pass transistor MN11 is interposed between the two. As in the first embodiment, the gates of the pass transistors MN9 and MN11 are connected to the write control line 44 at the node N6. A connection point between the transistors QN9 and MN9 is represented as a node N8, and a connection point between the transistors QN11 and MN11 is represented as a node N9.
[0096]
The second difference is that the potential V_DDPotential point (hereinafter “potential point V_DD) And the node N8, transistors MP3 and MP4, both of which are PMOS transistors, are connected in series. Similarly, the potential point V_DDTransistors MP5 and MP6, both of which are PMOS transistors, are connected in series between the node N9 and the node N9. In either of the transistors MP4 and MP6, the potential V is applied to one of the current electrode pairs._DDIs applied, and a write complementary word line 34 is connected to the gate thereof. Nodes N8 and N9 are connected to one of the current electrode pairs of the transistors MP3 and MP5, respectively. The other of the current electrode pairs of the transistors MP3 and MP4 and the other of the current electrode pairs of the transistors MP5 and MP6 are connected in common. The gates of the transistors MP3 and MP5 are connected to the write bit line 41 and the write complementary bit line 42, respectively.
[0097]
In the above configuration, the transistors MP3 and MP4 that can set the node N1 to “H” from the outside of the storage cell SC and the transistors MP5 and MP6 that can set the node N2 to “H” are provided. Thus, it is possible to quickly perform writing to invert the stored contents. Moreover, the conduction between the nodes N1 and N8 and the conduction between the nodes N2 and N9 depend on the logic of the write control line 44 by the pass transistors MN9 and MN10, respectively. Therefore, unnecessary power consumption due to potential collision between the node N1 and the write bit line 41 and between the node N2 and the write complementary bit line 42 can be reduced.
[0098]
Transistors MP3, MP4, QN9, and QN10 and transistors MP5, MP6, QN11, and QN12 constitute a tri-state inverter having nodes N8 and N9 as output terminals, respectively. The operation of the memory cell MC according to the present embodiment will be described below from the viewpoint of the operation of these tristate inverters.
[0099]
  These tri-state inverters function as inverters only when the write word line 31 is “H” and therefore the write complementary word line 34 is “L”. That is, logic complementary to the logic of the write bit line 41 is applied to the node N8, and logic complementary to the logic of the write complementary bit line 42 is applied to the node N9. When the write word line 31 is “L” and therefore the write supplement word line 34 is “H”, the potential of the node N8 is tristate even if the transistors MP3 and QN9 are turned on.InverterNot set (tristate condition). Even if the transistors MP5 and QN11 are turned on, the potential of the node N9 is tristated.InverterNot set by
[0100]
In the word line group 30 of the row to which the memory cell MC to be written belongs, that is, the selected word line group 30, potentials “H” and “L” are applied to the write word line 31 and the write complementary word line 34, respectively. The nodes N8 and N9 are given logic complementary to the write bit line 41 and the write complementary bit line 42, respectively. Further, in the bit line group 40 of the column to which the memory cell MC to be written belongs, that is, the selected bit line group 40, the write bit line 41 and the write complementary bit line 42 are given complementary logics. The logic in the write control line 44 is “H”, and the pass transistors MN9 and MN11 are turned on. Therefore, the logic complementary to the write bit line 41 and the write complementary bit line 42 is quickly stored in the nodes N1 and N2, even if the stored contents of the storage cell SC are inverted.
[0101]
In the memory cells MC arranged in the row corresponding to the selected word line group 30, the tristate inverter functions as an inverter. However, in the memory cells MC arranged in the column corresponding to the unselected bit line group 40, the write bit line 41 and the write complementary bit line 42 are precharged to substantially the same potential, so the logic in the write control line 44 is Since it is “L”, the pass transistors MN9 and MN11 do not conduct. Therefore, the node N1 and the write bit line 41 and the node N2 and the write complementary bit line 42 are cut off, and unnecessary power consumption due to potential collision can be reduced.
[0102]
In order to avoid a voltage drop corresponding to the threshold value of the pass transistors MN9 and MN10 due to the substrate effect, these may be replaced with a transmission gate. Alternatively, the potential of the write word line 31 may be boosted by a threshold value to compensate for the substrate effect of the pass transistors MN9 and MN10.
[0103]
FIG. 21 is a circuit diagram showing a configuration of the memory cell MC according to the first modification of the present embodiment. The configuration shown in FIG. 20 has a configuration in which the order of series connection of transistors QN9 and QN10 is changed, and the order of series connection of transistors QN11 and QN12 is changed. Naturally, the effect of the present embodiment can be obtained even in such a modification.
[0104]
FIG. 22 is a circuit diagram showing a configuration of the memory cell MC according to the second modification of the present embodiment. In contrast to the configuration shown in FIG. 21, the transistors MP3, MP4, MP5, and MP6 that supply the logic “H” to the storage cell SC are deleted. Further, the order of series connection of the pass transistor MN9 and the transistor QN10 and the order of series connection of the pass transistor MN11 and the transistor QN12 are interchanged.
[0105]
Or, compared with the circuit shown in FIG. 53, the node N1 and the potential point VV of the transistors QN9 and QN10._SSA pass transistor MN9 whose conduction is controlled by logic in the write control line 44 is interposed between the transistors QN9 and QN10. Similarly, nodes N2 and potential point V of transistors QN11 and QN12_SSThe pass transistor MN11 whose conduction is controlled by the logic in the write control line 44 is interposed between the transistors QN11 and QN12.
[0106]
In such a configuration, “H” cannot be set to the storage cell SC from the outside. Therefore, it is disadvantageous in that writing that reverses the contents stored in the storage cell SC cannot be performed quickly. However, as compared with the configuration shown in FIGS. 20 and 21, there is an advantage that the write complementary word line 34 is not required and can be employed as the memory cell MC of the SRAM shown in FIG. Further, as compared with the configuration shown in FIG. 53, the potentials of the write bit line 41 and the write complementary bit line 42 of the unselected bit line group 40 may be precharged to either “L” or “H”. It is also advantageous.
[0107]
Of course, there are six series connection orders of the transistors QN10, MN9, and QN9, and it is natural that the above-described effects can be obtained regardless of which order is employed. The same applies to the order of series connection of the transistors QN12, MN11, and QN11.
[0108]
FIG. 23 is a circuit diagram of a dual write port type static memory cell according to a third modification of the present embodiment. Here, two sets of tri-state inverters corresponding to the word line group (excluding the read complementary word line 32 and the read word line 33), the bit line group (excluding the read bit line 43), and the bit line group are provided. In the first group and the second group, codes obtained by adding symbols a and b to the end of the codes employed in FIG. 21 are employed.
[0109]
Even in such a dual write port type static memory cell, it is natural that when the stored contents of the storage cell SC are inverted, it can be stored quickly, and unnecessary power consumption due to potential collision can be reduced.
[0110]
FIG. 24 is a circuit diagram showing a configuration of the memory cell MC according to the fourth modification of the present embodiment. In contrast to the configuration shown in FIG. 21, the configuration of an element interposed between the node N8 serving as the output terminal of the tristate inverter and the transistors MP3 and QN9 and the node N1, and the node N9 serving as the output terminal of another tristate inverter. The configuration of the elements interposed between the transistors MP5 and QN11 and the node N2 is changed.
[0111]
  The node N8 is connected to the transistor MP3 via the PMOS transistor MP9, to the transistor QN9 via the NMOS transistor MN9, and via the NMOS transistor QN10.TenoAre connected to the node N1, respectively. The node N9 is connected to the transistor MP5 via the PMOS transistor MP11, to the transistor QN11 via the NMOS transistor MN11, and via the NMOS transistor QN12.TenoAre connected to the node N2, respectively.
[0112]
In this modification, the write complementary word line 34 is not employed, and the write complementary control line 45 is employed instead. The gates of the transistors MP9 and MP11 are connected to the complementary write control line 45 at the node N7, and the gates of the transistors MN9 and MN11 are connected to the write control line 44 at the node N6. The gates of the transistors QN10 and QN12 are connected to the write word line 31.
[0113]
In the selected row, the write word line 31 is activated, and the transistors QN10 and QN12 are turned on. Therefore, nodes N1 and N2 are electrically connected to nodes N8 and N9, respectively. In the selected column, the write control line 44 and the write supplement control line 45 become “H” and “L”, respectively, so that the transistors MP9, MP11, MN9, and MN11 are all turned on. Therefore, the logic applied to the write bit line 41 and the logic applied to the write complementary bit line 42 are inverted to the nodes N1 and N2 of the memory cell MC to be written through the nodes N8 and N9, respectively. Thus, data to be written is given. This is quickly performed even when the data stored in the storage cell SC is inverted.
[0114]
In the memory cell MC that is arranged in the selected row but is not a write target (that is, the memory cell MC arranged in the non-selected column), the write control line 44 and the write supplement control line 45 are “L”, respectively. Since it becomes “H”, the transistors MP9, MP11, MN9, and MN11 are all turned off. Nodes N8 and N9 have a tristate condition. Accordingly, the logic is not forcibly set from the outside of the storage cell SC to the nodes N1 and N2, and unnecessary power consumption due to potential collision can be prevented.
[0115]
FIG. 25 is a circuit diagram showing a configuration of the memory cell MC according to the fifth modification of the present embodiment. This configuration is different from the configuration of FIG. 24 in that the node N8 and the potential point V_DDThe order of the series connection of the transistors MP3 and MP9 is exchanged between the node N8 and the potential point V_SSThe order of the series connection of the transistors MN9 and QN9 between the node N9 and the potential point V_DDThe order of the series connection of the transistors MP5 and MP11 is exchanged between the node N9 and the potential point V_SSThe order of the series connection of the transistors MN11 and QN11 is exchanged with the other. Therefore, even the configuration shown in FIG. 25 is effective in writing data quickly and reducing unnecessary power consumption.
[0116]
FIG. 26 is a circuit diagram showing a configuration of the memory cell MC according to the sixth modification of the present embodiment. In contrast to the configuration shown in FIG. 21, the node N8 and the potential point V_DDThe order of the series connection of the transistors MP3 and MP4 between the node N9 and the potential point V_DDThe order of the serial connection of the transistors MP5 and MP6 is exchanged with the transistors MP4 and MP6, and the transistors MP4 and MP6 are merged to provide one transistor. Similarly, the node N8 and the potential point V_SSThe order of series connection of the transistors QN9 and QN10 between the node N9 and the potential point V_SSThe order of series connection of the transistors QN11 and QN12 is exchanged with the transistors QN10 and QN12, and the transistors QN10 and QN2 are merged to provide one transistor. Therefore, as compared with the circuit shown in FIG. 21, the number of transistors can be reduced and the area necessary for obtaining the effect of this embodiment can be reduced.
[0117]
Nodes N8 and N9 have the same connection relationship as nodes N1 and N2 shown in FIG._SSIt is connected to the. However, the transistors MN9 and MN11 are electrically connected between the node N8 and the node N1 and between the node N9 and the node N2, respectively, only when the write control line 44 is “H”. This applies even when the potentials of the write bit line 41 and the write complementary bit line 42 of the unselected bit line group 40 are precharged to either “L” or “H”. Therefore, the same effect as FIG. 21 can be obtained.
[0118]
  FIG. 27 shows the memory cell MC in the I row. _i1 ~ MC _in FIG. 27 is a circuit diagram showing a configuration in which the configuration shown in FIG. 26 is applied. Multiple memory cells MC belonging to the same row _ij Uses the write word line 31 and the write complementary word line 34 in common. Therefore, n memory cells MC _i1 ~ MC _in , The transistor MP4 (or transistor MP6) and the transistor QN10 (or QN12) can be merged into one PMOS transistor MP400 and NMOS transistor QN100, respectively. Such merging can further reduce the number of transistors.
[0119]
Embodiment 6 FIG.
In the present embodiment, the configuration appearing in the circuit diagram is the same as that in the first to fifth embodiments. A characteristic point in the present embodiment is that a MOSFET constituting the memory cell MC is formed on an SOI (Semiconductor On Insulator or Silicon On Insulator) substrate.
[0120]
First, a problem that occurs when a MOSFET constituting the conventional memory cell MC is formed on an SOI substrate will be described. FIG. 28 is a cross-sectional view illustrating a configuration in the case where access transistor QN4 shown in FIG. 52 is formed as a MOS transistor on an SOI substrate.
[0121]
A semiconductor substrate 91, a buried oxide film 92, and an SOI substrate 93 are stacked in this order. An insulating separator 94 is selectively embedded in the SOI substrate 93. The SOI substrate 93 is connected to nodes N2 and N5, respectively, and is divided into an n-type drain 93a and source 93b, and a drain 93a and source 93b, and a P-type channel region 93c. A pn junction J11 is formed between the source 93b and the channel region 93c, and a pn junction J12 is formed between the drain 93a and the channel region 93c. The gate electrode 98 is provided to face the channel region 93 c through the gate insulating film 95, and the top surface and side surfaces thereof are covered with the insulating film 96. The sidewall 97 is provided to face the side surface of the gate electrode 98 with the insulating film 96 interposed therebetween. The gate electrode 98 is formed by laminating doped polysilicon 98a, tungsten nitride film 98b, and tungsten 98c in order from the side closer to the gate insulating film 95. In such a configuration, since the insulating separator 94 insulates the SOI substrate 93 from the surroundings, it is normally in a so-called floating body state unless a mechanism for fixing the potential of the channel region 93c is separately provided.
[0122]
52. The memory cells MC having the structure shown in FIG. 52, both of which belong to the jth column_xj, MC_yjIs assumed. Memory cell MC_xjAfter “L” and “H” are written in the nodes N1 and N2, respectively, the memory cell MC_yjConsider the so-called half-select write disturb when performing the operation of writing "H" and "L" to the nodes N1 and N2, respectively.
[0123]
Memory cell MC_xjAfter the end of the write operation, the write word line 31_xIs “L” and the memory cell MC_yjIn the write operation to the write word line 31_xRemains “L”, in the access transistor QN4, the source 93b, the channel region 93c, and the drain 93a form a lateral parasitic bipolar transistor, which functions as an emitter / base / collector, respectively.
[0124]
Memory cell MC_xjAfter completion of the write operation, the write bit line 41_jWrite complementary bit line 42_jAre precharged to “H”, so that the memory cell MC_xjThe access transistor QN4 is not turned on and its source 93b and drain 93a are kept at "H". Since the channel region 93c is P-type and in a floating state, holes (schematically indicated by + marks in the figure) are thermally accumulated therein.
[0125]
In such a state, the memory cell MC_yjWrite bit line 41 for write operation_j"H" in the write complementary bit line 42_jWhen “L” is precharged to the memory cell MC,_xjThe pn junction J11 of the access transistor QN4 is forward biased. Therefore, electrons are injected from the source 93b into the channel region 93c, and the holes accumulated in the channel region 93c are discharged. At this time, the current I1 flowing through the pn junction J11 functions as an effective base current of the parasitic bipolar transistor described above. Therefore, a spike-like current I2 that flows from the drain 93a to the channel region 93c is induced. Especially the memory cell MC_yjWhen the time until writing is long, the amount of holes accumulated thermally increases and the current I2 also increases. In that case, the charge stored in the node N2 is discharged and the potential is lowered from "H" to "L", and the memory cell MC_xjThe stored contents may be reversed.
[0126]
However, when the circuit configuration of the present invention is adopted, the above problem can be avoided. For example, in the configuration shown in FIG. 2, the logic of the write complementary bit line 42 is written to the node N2 via the transistors MN11 and MN12. In general, the wiring for connecting the transistors MN11 and MN12 to each other is very short compared to the write complementary bit line. Therefore, as compared with the access transistor QN4 of the memory cell MC having the structure shown in FIG. 52, the transistor MN11 has a smaller parasitic capacitance connected to the current electrode pair closer to the write complementary bit line 42 (for example, the source). This is especially true when the impurity region is shared as shown in FIG. Therefore, even if the transistor MN11 is the SOIFET shown in FIG. 28, the parasitic bipolar transistor does not operate sufficiently. Therefore, by adopting the circuit configuration of the present embodiment, the probability of occurrence of half-select write disturb can be reduced.
[0127]
Note that the potential corresponding to the logic “L” in the unselected write word line 31 is lower than the potential corresponding to the logic “L” in the write complementary bit line 42, for example, V_SS-0.3Vb ~ V_SSIt is also desirable to set it to about -Vb. Here, Vb is a built-in voltage formed by the drain 93a and the channel region 93c. By applying such a potential to the non-selected write word line 31, forward bias at the pn junction J11 can be reduced while avoiding accumulation in the channel region 93c. Such setting of the potential of the write word line 31 is particularly effective in the circuit configuration shown in FIG. This is because the current electrode pair of the transistor MN4 is connected to the nodes N2 and N5 and is similar to the transistor QN4 shown in FIG. 52 from the viewpoint of parasitic capacitance.
[0128]
Of course, the half-select write disturb may be avoided by adopting a configuration in which the potential of the channel region 93c is fixed.
[0129]
Although the dual port static memory cell has been described as an example in the above-described embodiment, it is needless to say that it can be applied to a multi-port static memory cell.
[0130]
Embodiment 7 FIG.
In the first to sixth embodiments, a predetermined effect is obtained by permitting a write operation by activating not only the write word line 31 but also the write control line 44. However, to determine the logic of the write control line 44, the potential V_SS, V_DDOr potential (V_DD+ V_SS) / 2, it is necessary to determine the potentials of the write bit line 41 and the write complementary bit line 42 by precharging. In other words, if the write bit line 41 and the write complementary bit line 42 are allowed to be in a floating state, the potential of the write control line 44 may not be determined. Even when the write bit line 41 and the write complementary bit line 42 are in a floating state, the write bit line 41 and the write bit in the memory cell that belongs to the same row and a different column as the target memory cell. There is a possibility that power consumption occurs due to the storage cell SC charging / discharging the complementary bit line 42.
[0131]
In particular, when there is a plurality of read / write paths in each cell, such as a multi-port SRAM, for example, a dual-port SRAM, and binary information can be read and written independently and asynchronously, the storage cell SC writes In some cases, not only the bit line 41 and the write complementary bit line 42 but also the read bit line 43 is driven in parallel.
[0132]
FIG. 54 is a block diagram showing a connection between a dual port SRAM 80 having first and second ports, one of which serves as a write port and the other serves as a read port, and a device for controlling the operation thereof. . The first microprocessor 81 performs a read / write operation using the first port of the dual port SRAM 80 via the first read / write control circuit 82. On the other hand, the second microprocessor 84 performs a read / write operation using the second port of the dual port SRAM 80 via the second read / write control circuit 83.
[0133]
FIG. 29 is a circuit diagram illustrating the configuration of a memory cell MC that can be employed in the dual port SRAM 80. Compared to the configuration shown in FIG. 52, access transistors QN13 and QN14, both of which are NMOS transistors, are provided instead of the read circuit RK. Access transistor QN 13 is interposed between node N 1 and read bit line 43, and has its gate connected to read word line 33. Access transistor QN14 is interposed between node N2 and read complementary bit line 46, and has its gate connected to read word line 33.
[0134]
The configuration shown in FIG. 29 has an advantage that the number of transistors per memory cell MC can be reduced by two as compared with the configuration shown in FIG. However, in the storage cell SC, when the transistors QN13 and QN14 are turned on, the read bit line 43 and the read complementary bit line 46 having a larger capacitance than the gates of the transistors QP3 and QN6 of the read circuit RK are connected to the nodes N3 and N10, respectively. The battery will be charged and discharged. Therefore, all of the memory cells MC arranged in the i-th row_ix, MC_iyWhen the write operation by the first read / write control circuit 82 and the read operation by the second read / write control circuit 83 are performed in parallel for (x ≠ y), the write word line 31_iRead word line 33_iThere is a period during which becomes “H” at the same time. During this period, the memory cell MC_iyThe storage cell SC drives not only the read bit line 43 and the read complementary bit line 46 but also the write bit line 41 and the write complementary bit line 42, and there is a possibility that the read operation is delayed.
[0135]
FIG. 30 is a conceptual diagram showing the configuration around the memory cell array of the SRAM according to the seventh embodiment of the present invention. Compared with the configuration shown in FIG. 1, the write control line 44 is replaced with the read complementary bit line 46, and the read complementary word line 32 is omitted.
[0136]
FIG. 31 is a circuit diagram illustrating one configuration of memory cell MC shown in FIG. As in the prior art, subscripts indicating row positions and column positions are omitted. 29 has a structure provided with NMOS transistors QN15, QN16, QN17, and QN18 instead of the transistors QN3 and QN4. Of course, the read complementary word line 32 may also be used to employ the read circuit RK in place of the transistors QN13 and QN14 in the memory cell MC. However, this embodiment is particularly effective when the nodes N1 and N2 have a read mechanism that can charge / discharge the read bit line 43 and the read complementary bit line 46 instead of the gates of the transistors as described above. It is.
[0137]
One of the current electrode pairs of the transistor QN17, for example, the source has a potential V_SSAnd the node N2 is connected to the other of the current electrode pair, for example, the drain. One of the current electrode pairs of the transistor QN18, for example, the source has a potential V_SSIs supplied, and the node N1 is connected to the other of the current electrode pair, for example, the drain.
[0138]
The write bit line 41 is connected to one of the current electrode pairs of the transistor QN15 at, for example, the node N4 at the source, and the gate of the transistor QN17 is connected to the other of the current electrode pairs, for example, the drain. The write complementary bit line 42 is connected to one of the current electrode pairs of the transistor QN16, for example, the source, and the gate of the transistor QN18 is connected to the other of the current electrode pairs, for example, the drain. The gates of the transistors QN15 and QN16 are both connected to the write word line 31.
[0139]
In the write operation in such a configuration, first, the potential corresponding to the logic to be applied to the nodes N1 and N2 is precharged to the write bit line 41 and the write complementary bit line 42, respectively. For example, the potential V corresponds to “H” and “L”, respectively._DD, V_SSIs supplied to the write bit line 41 and the write complementary bit line 42. Thereafter, the write word line 31 is activated, the transistors QN15 and QN16 are turned on, and the potentials (V) are applied to the gates of the transistors QN17 and QN18, respectively._DD-V_thn), V_SS(However, the threshold voltage of the transistor QN15 is set to V_thn> 0). As a result, the transistors QN17 and QN18 are turned on and off, respectively. Since the transistor QN17 is on, the potential V_SSIs transmitted. Therefore, the logic “H” is stored in the node N1 by the function of the inverter L1.
[0140]
Thereafter, both the write bit line 41 and the write complementary bit line 42 are at the potential V._SSTo set the gates of the transistors QN17 and QN18 to "L", which are turned off. Thereafter, the write word line 31 is deactivated and becomes “L”, the transistors QN15 and QN16 are turned off, and the gates of the transistors QN17 and QN18 are brought into a floating state.
[0141]
In the read operation, when the read word line 33 is activated, the transistors QN13 and QN14 are turned on, and the logic stored in the nodes N1 and N2 is read in the read bit line 43 and the read complementary bit line 46 in the nodes N3 and N10, respectively. Is transmitted to. In order to increase the read speed, it is desirable that precharge is performed prior to activation of the read word line 33.
[0142]
In the configuration as described above, the charge is not supplied from the write bit line 41 and the write complementary bit line 42 to the storage cell SC in the write operation, but the potential V_SSIs given only to one of the nodes N1 and N2. That is, there is no path through which charges move directly between the write bit line 41 and the write complementary bit line 42 and the nodes N1 and N2. Therefore, even when the write word line 31 is activated and the write bit line 41 and the write complementary bit line 42 are in a floating state, they are not charged / discharged by the storage cell SC, and unnecessary power is consumed. Not. Therefore, even if there is a period in which the write word line 31 and the read word line 33 are simultaneously “H”, the read operation is not delayed.
[0143]
The procedure for turning off the transistors QN15 and QN16 after the transistors QN17 and QN18 are turned off at the end of the above write operation has been described. However, conversely, the transistors QN17 and QN18 can be turned off after the transistors QN15 and QN16 are turned off. In this case, since either of the transistors QN17 and QN18 is turned on and the respective gates shift to the floating state, there is an effect of backing up the information of the storage cell SC. For example, a soft error in which the contents stored in the storage cell SC are reversed due to irradiation with cosmic rays such as neutron rays can be considered. Therefore, by backing up the information in the storage cell SC, the critical charge amount necessary for causing the soft error increases, that is, the soft error can be made difficult to occur.
[0144]
FIG. 32 is a circuit diagram showing a modification of the present embodiment. The write word line 31 is replaced with the write complementary word line 34, and the transistors QN15 and QN16 are both replaced with PMOS transistors QP15 and QP16.
[0145]
This configuration also has the same effect as the configuration shown in FIG. 31 in terms of logic propagation. However, when "H" is applied to the gates of the transistors QN17 and QN18, the threshold voltage V_thnIt can be avoided that the potential decreases by (> 0).
[0146]
On the other hand, the threshold voltages of the PMOS transistors QP15 and QP16 are set to V_thpIf (<0), when “L” is applied to the gates of the transistors QN17 and QN18, the potential is V_SS-V_thpAnd rise. Therefore, the transistors QN17 and QN18 are surely turned off, and the potential point V from the nodes N1 and N2_SSThe configuration shown in FIG. 31 is more advantageous in terms of suppressing the leak current.
[0147]
FIG. 33 is a circuit diagram showing a further modification of the present embodiment. Both the write word line 31 and the write complementary word line 34 are employed, and a transmission gate is connected between the node N4 and the gate of the transistor QN17 by the parallel connection of the transistors QP15 and QN15, and the node N5 and the gate of the transistor QN18. Is connected to a transmission gate by parallel connection of transistors QP16 and QN16. The gates of the PMOS transistors QP15 and QP16 are connected to the write complementary word line 34, and the gates of the NMOS transistors QN15 and QN16 are connected to the write word line 31, respectively.
[0148]
With such a configuration, on / off of the transistors QN17 and QN18 can be accurately controlled.
[0149]
Embodiment 8 FIG.
FIG. 34 is a circuit diagram illustrating one configuration of the memory cell MC according to this embodiment. As in the prior art, the subscripts indicating the row position and the column position are omitted, but the MC shown in FIG._ijCan be adopted as each of.
[0150]
The memory cell MC is characteristically different from the configuration shown in FIG. 53 in the configuration of the storage cell SC. In short, the storage cell SC does not have the transistors QN1 and QN2, but is constituted by a cross couple of the transistors QP1 and QP2.
[0151]
More specifically, storage node N2 is connected to potential point V only through the series connection of transistors QN9 and QN10._SSIt is connected to the. The gates of the transistors QN9 and QN10 are connected to the write bit line 41 and the write word line 31, respectively, and their conduction is controlled by these logics. Similarly, storage node N1 is connected to potential point V only through a series connection of transistors QN11 and QN12._SSIt is connected to the. The gates of the transistors QN11 and QN12 are connected to the write complementary bit line 42 and the write word line 31, respectively, and conduction is controlled by these logics.
[0152]
Compared to the configuration shown in FIG. 53, the configuration for reading from storage nodes N1 and N2 of storage cell SC is different. That is, not the readout circuit RK but the transistors QN13 and QN14 shown in the seventh embodiment are used. When the read word line 33 is activated, the transistors QN13 and QN14 are turned on, and the logic stored at the nodes N1 and N2 is transmitted to the read bit line 43 and the read complementary bit line 46 at the nodes N3 and N10, respectively. . In order to increase the read speed, it is desirable that the read bit line 43 and the read complementary bit line 46 are precharged before the read word line 33 is activated.
[0153]
FIG. 35 is an example of a timing chart showing the operation of the memory cell MC shown in FIG. (A), (b), (c), (d), and (e) show the potentials of the read word line 33, the read complementary bit line 46, the write word line 31, the write bit line 41, and the storage node N2, respectively. Show. In this example, “L” is written to the storage node N2 in which “H” is stored.
[0154]
Time t₁Previously, it was a standby time, and the read complementary bit line 46 together with the read bit line 43 has the potential V_SSOr the potential (V_DD+ V_SS) / 2 is precharged. And time t₁Thus, the read complementary bit line 46 together with the read bit line 43 has a potential (V_DD+ V_SS) / 2 is precharged. Then time t₂Read word line 33 at potential V_DDThe transistor QN14 is turned on together with the transistor QN13 in response to the transition. As a result, time t_ThreeIn FIG. 5, the read complementary bit line 46 is caused by the logic "H" stored in the storage node N2, so that its potential is the potential V._DDBegin to transition to. Then time t_FourRead word line 33 at potential V_SSAt the time t5 after which the write bit line 41 is at the potential V_DDStart transition to. In response to this transition, the transistor QN9 is turned on. After that, time t₆The write word line 31 also has the potential V_DDThe transistor QN10 is also turned on in response to the transition. Thereby, the storage node N2 is connected to the potential point V via the transistors QN9 and QN10._SSAt time t₇The potential of storage node N2 is at potential V_DDTo potential V_SSBegin to transition to. Thereafter, the write word line 31 is set to the potential V._SSAnd the write bit line 41 is also at the potential V._SSTransition to.
[0155]
Of course, when “L” is written in the state where “L” is stored in the storage node N2, the potential V_SSIt is realized by connecting to. When “L” is written to the storage node N2, the transistor QP1 is turned on, and the storage node N1 is connected to the potential point V V via this._DD"H" is written by being connected to.
[0156]
Also in the present embodiment, as in the seventh embodiment, there is no path through which charges move directly between the write bit line 41 and the write complementary bit line 42 and the nodes N1 and N2. Therefore, even when the write word line 31 is activated and the write bit line 41 and the write complementary bit line 42 are in a floating state, they are not charged / discharged by the storage cell SC, and unnecessary power is consumed. Not. Therefore, even if there is a period in which the write word line 31 and the read word line 33 are simultaneously “H”, the read operation is not delayed.
[0157]
In addition, since the number of transistors is small compared to the configuration shown in FIG. 53, the area can be reduced by two transistors per storage cell. The inverters L1 and L2 are designed to have a high static noise margin in order to stably hold information, and it takes time to invert the stored contents. However, in the structure of this embodiment mode, memory is held by transistor cross-coupling, so that a writing operation can be performed at high speed.
[0158]
In the memory cell having the configuration of this embodiment, half-select write disturb can be avoided. FIG. 36 is a circuit diagram showing a part of a configuration in which the memory cells MC having the structure shown in FIG. 34 are arranged in a matrix. The memory cell MC belonging to the xth row and the jth column_xjAnd the memory cell MC belonging to the xth row and the zth column_xzAnd the memory cell MC belonging to the yth row and the jth column_yjAnd extracted.
[0159]
First, memory cell MC_xjAssume that information is written to the storage node N1. Write bit line 41_jWrite complementary bit line 42_jAre “H” and “L”, respectively, the write word line 31_xBecomes “H”, the memory cell MC_xjThe potential V is applied to the storage node N2 through the transistors QN9 and QN10._SSIs given. At this time, the memory cell MC_xjThe transistor QN11 is off. Further, the potential V is applied to the storage node N2._SSMemory cell MC_xjTransistor QP1 is turned on, and the potential V is applied to the storage node N1._DDIs given.
[0160]
At this time, the memory cell MC_xzThe transistors QN10 and QN12 of the write word line 31 also_xTurns ON when becomes “H”. However, the write bit line 41_zWrite complementary bit line 42_zAre both potential V_SSMemory cell MC by precharging the memory cell MC_xzThe transistors QN9 and QN11 can be turned off. Therefore, the memory cell MC_xzThe stored contents of will not be rewritten.
[0161]
In addition, the memory cell MC_yjThe transistor QN9 also has a write bit line 41._jTurns ON when becomes “H”. However, the write word line 31_yIs not selected, so it is “L”, so the memory cell MC_yjThe transistors QN10 and QN12 can be turned off. Therefore, the memory cell MC_yjThe stored contents of will not be rewritten. From the above, half-select write disturb can be avoided.
[0162]
FIG. 37 is a circuit diagram showing a configuration of the memory cell according to the first modification of the present embodiment. The memory cell employs a write complementary word line 34 instead of the write word line 31 in the configuration shown in FIG. The NMOS transistors QN10 and QN12 are replaced with PMOS transistors QP10 and QP12, respectively. Since the complementary logic to the write word line 31 is given to the write complementary word line 34 in the write operation, the PMOS transistors QP10 and QP12 are NMOS transistors with respect to the logic given to the write word line 31 and the write complementary word line 34. The same operation as QN10 and QN12 is performed. Therefore, the configuration shown in FIG. 37 can achieve the same effects as the configuration shown in FIG.
[0163]
FIG. 38 is a circuit diagram showing a configuration of the memory cell according to the second modification of the present embodiment. In the memory cell, NMOS transistors QN9 and QN11 are replaced with PMOS transistors QP11 and QP9, respectively, in the configuration shown in FIG. A write bit line 41 and a write complementary bit line 42 are connected to the gates of the PMOS transistors QP9 and QP11, respectively. Since the write bit line 41 and the write complementary bit line 42 are given complementary logics in the write operation, the PMOS transistors QP9 and QP11 have the logic given to the write bit line 41 and the write complementary bit line 42, respectively. In contrast, the operation is similar to that of the NMOS transistors QN11 and QN9. Therefore, the configuration shown in FIG. 38 can achieve the same effect as the configuration shown in FIG.
[0164]
FIG. 39 is a circuit diagram showing a configuration of a memory cell according to the third modification of the present embodiment. The memory cell has a configuration shown in FIG. 34 and a configuration in which the high potential side and the low potential side are interchanged. That is, the storage node N2 is connected to the potential point V only through the series connection of the transistors QP11 and QP10._DDIt is connected to the. The gates of the transistors QP11 and QP10 are connected to the write bit line 41 and the write complementary word line 34, respectively, and conduction is controlled by these logics. Similarly, storage node N1 is connected to potential point V only through the series connection of transistors QP9 and QN12._DDIt is connected to the. The gates of the transistors QP9 and QP12 are connected to the write complementary bit line 42 and the write complementary word line 34, respectively, and conduction is controlled by these logics. Obviously, even with such a configuration, the same effect as the configuration shown in FIG. 34 can be obtained.
[0165]
FIG. 40 is a circuit diagram showing a configuration of a memory cell according to the fourth modification of the present embodiment. The memory cell employs the write word line 31 instead of the write complementary word line 34 in the configuration shown in FIG. The PMOS transistors QP10 and QP12 are replaced with NMOS transistors QN10 and QN12, respectively. Since the complementary logic to the write word line 31 is given to the write complementary word line 34 in the write operation, the NMOS transistors QN10 and QN12 are PMOS transistors with respect to the logic given to the write word line 31 and the write complementary word line 34. The same operation as QP10 and QP12 is performed. Therefore, the configuration shown in FIG. 40 can achieve the same effect as the configuration shown in FIG.
[0166]
FIG. 41 is a circuit diagram showing a configuration of a memory cell according to the fifth modification of the present embodiment. In the memory cell, PMOS transistors QP9 and QP11 are replaced with NMOS transistors QN11 and QN9, respectively, in the configuration shown in FIG. A write bit line 41 and a write complementary bit line 42 are connected to the gates of the NMOS transistors QN11 and QN9, respectively. Since the write bit line 41 and the write complementary bit line 42 are given complementary logics in the write operation, the NMOS transistors QN9 and QN11 have the logic given to the write bit line 41 and the write complementary bit line 42, respectively. In contrast, the same operation as that of the PMOS transistors QP11 and QP9 is performed. Therefore, the configuration shown in FIG. 41 can achieve the same effect as the configuration shown in FIG.
[0167]
FIG. 42 is a circuit diagram showing a configuration of a memory cell according to the sixth modification of the present embodiment. The cell has a configuration in which the transistor QN12 is also used as the transistor QN10 in the configuration shown in FIG. FIG. 43 is a circuit diagram showing a configuration of the memory cell according to the seventh modification of the present embodiment. The cell has a configuration in which the transistor QP12 is also used as the transistor QP10 in the configuration shown in FIG. In both the sixth modification and the seventh modification, two transistors are merged per memory cell to reduce the number of transistors by one. Thereby, the effect of the present embodiment can be obtained while reducing the area occupied by the memory cell.
[0168]
FIG. 44 shows the memory cell MC in the i-th row_i1~ MC_inFIG. 43 is a circuit diagram showing a configuration in which the configuration shown in FIG. 42 is applied. Multiple memory cells MC belonging to the same row_ijUses the write word line 31 in common. Therefore, n memory cells MC_i1~ MC_inThe transistor QN10 (or QN12) can be merged into one NMOS transistor QN100. FIG. 45 shows the memory cell MC in the i-th row_i1~ MC_in44 is a circuit diagram showing a configuration in which the configuration shown in FIG. 43 is applied. Multiple memory cells MC belonging to the same row_ijUses the write complementary word line 34 in common. Therefore, n memory cells MC_i1~ MC_inThe transistor QP10 (or QP12) can be merged into one PMOS transistor QP100. Such merging can further reduce the number of transistors.
[0169]
The transistor described in this embodiment may be formed using a silicon substrate, or may be formed using a known SOI substrate or SON (Silicon On Nothing) substrate.
[0170]
Embodiment 9 FIG.
FIG. 46 is a circuit diagram illustrating one configuration of the memory cell MC according to this embodiment. As in the prior art, the subscripts indicating the row position and the column position are omitted, but the MC shown in FIG._ijCan be adopted as each of. However, the readout circuit is omitted.
[0171]
The memory cell MC shown in FIG. 46 is characteristically different from the configuration shown in FIG. 10 in that the storage cell SC is constituted by a pair of cross-coupled transistors. That is, the drain of the transistor QN1 and the gate of the transistor QN2 are connected in common to the storage node N1, the gate of the transistor QN1 and the drain of the transistor QN2 are connected in common to the storage node N2, and the transistors QN1, The potential point V is commonly used for the sources of QN2._SSIs connected.
[0172]
By configuring the storage cell SC with a pair of cross-coupled transistors instead of a pair of cross-coupled inverters, the area can be reduced by two transistors per storage cell. Moreover, the design which gives a high static noise margin like the inverters L1 and L2 is not performed, and the write operation can be performed at high speed.
[0173]
The transistors MN9 and MN10 are connected in series between the storage node N1 and the write bit line 41, and the transistors MN11 and MN12 are connected in series between the storage node N2 and the write complementary bit line 42. The transistors MN9 and MN11 are both NMOS transistors, and a write control line 44 is connected to the gates of the transistors MN9 and MN11. The transistors MN10 and MN12 are both NMOS transistors, and the write word line 31 is connected to the gates thereof in common.
[0174]
Accordingly, the transistors MN10 and MN12 of the memory cells sharing the write word line 31 of the selected row are made conductive. However, the transistors MN9 and MN11 of the memory cells in the non-selected column are not turned on. Conversely, the transistors MN9 and MN11 of the memory cells that share the write control line 44 of the selected column are turned on. However, the transistors MN10 and MN12 of the memory cells in the non-selected row are not turned on. Therefore, half-select write disturb can be avoided.
[0175]
47 to 49 are circuit diagrams showing modifications of the present embodiment. The configuration shown in FIG. 47 is different from the configuration shown in FIG. 46 in that the write control line 44 is replaced with a write complementary control line 45 and the NMOS transistors MN9 and MN11 are replaced with PMOS transistors MP9 and MP11, respectively. Have. Since the complementary logic to the write control line 44 is given to the write complementary control line 45, it is obvious that the configuration shown in FIG. 47 operates similarly to the configuration shown in FIG.
[0176]
The configuration shown in FIG. 48 is different from the configuration shown in FIG. 46 in that the write word line 31 is replaced with the write complementary word line 34, and the NMOS transistors MN10 and MN12 are replaced with PMOS transistors MP10 and MP12, respectively. Have. Since the complementary logic to the write word line 31 is given to the write complementary word line 34 in the write operation, the PMOS transistors MP10 and MP12 are NMOS transistors with respect to the logic given to the write word line 31 and the write complementary word line 34. The same operation as that of MN10 and MN12 is performed. Therefore, the configuration shown in FIG. 48 can achieve the same effect as the configuration shown in FIG.
[0177]
The configuration shown in FIG. 49 is different from the configuration shown in FIG. 48 in that the write control line 44 is replaced with a write complementary control line 45 and the NMOS transistors MN9 and MN11 are replaced with PMOS transistors MP9 and MP11, respectively. Have. It is obvious that the configuration shown in FIG. 49 operates in the same manner as the configuration shown in FIG.
[0178]
FIG. 50 is a circuit diagram showing another modification of the present embodiment. In the configuration shown in FIG. 49, only the configuration of the storage cell SC is different. In FIG. 50, the pair of cross-coupled transistors are PMOS transistors QP1 and QP2. That is, the drain of the transistor QP1 and the gate of the transistor QP2 are connected in common to the storage node N1, the gate of the transistor QP1 and the drain of the transistor QP2 are connected in common to the storage node N2, and the transistors QP1, The potential point V is commonly used for the sources of QP2._DDIs connected. It is apparent that the configuration shown in FIG. 50 operates in the same manner as the configuration shown in FIG.
[0179]
In the configuration shown in FIG. 46, since all the memory cells MC are composed of NMOS transistors, there is no need to provide an isolation region between the PMOS transistor and the NMOS transistor, and the area occupied by the memory cell MC can be reduced. Can do. In the configuration shown in FIG. 50, since all the memory cells MC are composed of PMOS transistors, the area occupied by the memory cells MC can be reduced in the same manner.
[0180]
In the configuration shown in FIG. 46, the logic applied to the write bit line 41 is “L” and the potential V_SS, The thresholds of the NMOS transistors MN9 and MN10 do not matter, and the potential V is applied to the storage node N1._SSIs given. However, the logic applied to the write bit line 41 is “H” and the potential V_DDIs given, the threshold voltage of the NMOS transistors MN9 and MN10 is V_thn(> 0), the potential (V_DD-2V_thn) Is given. Therefore, when “H” is written to the storage node N1, the stability of the storage cell SC is slower than when “L” is written.
[0181]
49 and 50, the potential V is applied to the write bit line 41._DD, The threshold values of the PMOS transistors MP9 and MP10 are not a problem, and the potential V is applied to the storage node N1._DDIs given. However, the potential V is applied to the write bit line 41._SSIs given, the threshold voltage of the PMOS transistors MP9 and MP10 is set to V_thp(<0), the potential (V_SS-2V_thp) Is given. Therefore, when “L” is written to the storage node N1, the stability of the storage cell SC is delayed as compared with the case where “H” is written.
[0182]
On the other hand, in the configuration shown in FIG._DD, There is no decrease by the threshold value in the PMOS transistor MP9, and the potential (V_DD-V_thn) Is given. Conversely, the potential V is applied to the write bit line 41._SS, There is no decrease by the threshold value in the NMOS transistor MN10, and the potential (V_SS-V_thp) Is given. Therefore, the worst value (maximum value) of the time required for the stability of the storage cell SC can be made smaller than the configuration shown in FIG. 49 or FIG. The same applies to the configuration shown in FIG.
[0183]
Although all the descriptions of the present embodiment have described the write circuit, it is obvious that these can be adopted for the read circuit. That is, the write word line 31, the write complementary word line 34, the write bit line 41, and the write complementary bit line 42 may be read as the read word line 33, the read complementary word line 32, the read bit line 43, and the read complementary bit line 46, respectively. . Further, the write control line 44 and the write supplement control line 45 may be read as the read control line and the read supplement control line, respectively.
[0184]
Here, a signal that is activated (for example, “H”) at the time of reading and inactivated (for example, “L”) at the time of standby is given to the reading control line, and the reading complementary control line is complementary to the reading control line at the reading time. A signal that takes the correct logic is given. As a signal given to the read control line, a logical exclusive sum of the logic given to the read word line 33 and the logic given to the read complementary word line 32 can be adopted.
[0185]
Of course, a word line pair and a bit line pair can be used for both reading and writing. This embodiment can be applied to both multi-port and single-port types.
[0186]
The transistor described in this embodiment may be formed using a silicon substrate, or may be formed using a known SOI substrate or SON (Silicon On Nothing) substrate.
[0187]
【The invention's effect】
According to the memory device of the first aspect of the present invention, during the write operation, both the write word line and the write control line are activated in the memory cell to be written, so the first memory The node is connected to the write bit line through the first switch. Therefore, the time required to invert the logic stored in the first storage node is short regardless of the logic applied to the write bit line. On the other hand, since the write control line is not activated in a memory cell that is not a write target, the first switch does not connect the first storage node to the write bit line. Therefore, unnecessary power consumption in the memory cell can be reduced.
[0188]
  AndIn the unselected bit line group, the write bit line and the write complementary bit line are precharged. In this precharge, normally, the write bit line and the write complementary bit line are set to the same potential, so that the write control line can be inactivated by taking the exclusive OR of both.
[0189]
  Claim of the invention2According to the storage device, even when the potential applied to the write bit line and the write complementary bit line at the time of precharging is an intermediate potential between two potentials corresponding to complementary logic, Can be obtained accurately.
[0190]
  Claim of the invention3Or claims4According to the storage device, the first switch can be realized by the first and second transistors.
[0194]
  Claim of the invention5According to the storage device, even if the second transistor is formed on the SOI substrate, it is possible to suppress the effective base current from flowing between the first current electrode and the body when the write word line is inactive. So-called half-select write disturb can be solved.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing an SRAM according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram illustrating one of memory cells according to the first embodiment of the invention;
FIG. 3 is a circuit diagram illustrating a tri-state inverter.
FIG. 4 is a circuit diagram illustrating an XOR circuit.
FIG. 5 is a circuit diagram illustrating an XOR circuit.
FIG. 6 is a circuit diagram illustrating an XOR circuit.
FIG. 7 is a circuit diagram illustrating an XOR circuit.
FIG. 8 is a circuit diagram illustrating an XOR circuit.
FIG. 9 is a circuit diagram illustrating an XOR circuit.
FIG. 10 is a circuit diagram showing a modification of the first embodiment of the present invention.
FIG. 11 is a schematic view illustrating the first embodiment of the invention.
FIG. 12 is a conceptual diagram showing an SRAM according to a second embodiment of the present invention;
FIG. 13 is a circuit diagram illustrating one of memory cells according to a second embodiment of the invention;
FIG. 14 is a circuit diagram showing a modification of the second embodiment of the present invention.
FIG. 15 is a circuit diagram showing another modification of the second embodiment of the present invention.
FIG. 16 is a circuit diagram illustrating one of memory cells according to a third embodiment of the invention;
FIG. 17 is a circuit diagram showing a modification of the third embodiment of the present invention.
FIG. 18 is a circuit diagram illustrating one of memory cells according to a fourth embodiment of the invention;
FIG. 19 is a circuit diagram showing a modification of the fourth embodiment of the present invention.
FIG. 20 is a circuit diagram illustrating one of memory cells according to a fifth embodiment of the invention;
FIG. 21 is a circuit diagram showing a memory cell according to a first modification of Embodiment 5 of the present invention;
FIG. 22 is a circuit diagram showing a memory cell according to a second modification of the fifth embodiment of the present invention;
FIG. 23 is a circuit diagram showing a memory cell according to a third modification of the fifth embodiment of the present invention.
FIG. 24 is a circuit diagram showing a memory cell according to a fourth modification of the fifth embodiment of the present invention;
FIG. 25 is a circuit diagram showing a memory cell according to a fifth modification of the fifth embodiment of the present invention;
FIG. 26 is a circuit diagram showing a memory cell according to a sixth modification of the fifth embodiment of the present invention.
FIG. 27 is a circuit diagram showing a plurality of memory cells according to a sixth modification of the fifth embodiment of the present invention;
FIG. 28 is a cross-sectional view illustrating a conventional access transistor.
FIG. 29 is a circuit diagram illustrating a memory cell that can be employed in a dual port SRAM;
FIG. 30 is a conceptual diagram showing an SRAM according to a seventh embodiment of the present invention;
FIG. 31 is a circuit diagram illustrating one of memory cells according to a seventh embodiment of the invention;
FIG. 32 is a circuit diagram showing a memory cell according to a modification of the seventh embodiment of the present invention.
FIG. 33 is a circuit diagram showing a memory cell according to a further modification of the seventh embodiment of the present invention.
FIG. 34 is a circuit diagram illustrating one of memory cells according to an eighth embodiment of the invention;
FIG. 35 is a timing chart illustrating the operation of the memory cell according to the eighth embodiment of the invention;
FIG. 36 is a circuit diagram showing a part of a configuration in which memory cells according to an eighth embodiment of the present invention are arranged in a matrix.
FIG. 37 is a circuit diagram showing a configuration of a memory cell according to a first modification of Embodiment 8 of the present invention;
FIG. 38 is a circuit diagram showing a configuration of a memory cell according to a second modification of Embodiment 8 of the present invention;
FIG. 39 is a circuit diagram showing a configuration of a memory cell according to a third modification of the eighth embodiment of the present invention;
FIG. 40 is a circuit diagram showing a configuration of a memory cell according to a fourth modification of the eighth embodiment of the present invention.
FIG. 41 is a circuit diagram showing a configuration of a memory cell according to a fifth modification of Embodiment 8 of the present invention;
FIG. 42 is a circuit diagram showing a configuration of a memory cell according to a sixth modification of the eighth embodiment of the present invention.
FIG. 43 is a circuit diagram showing a configuration of a memory cell according to a seventh modification of the eighth embodiment of the present invention.
FIG. 44 is a circuit diagram showing a plurality of memory cells according to a sixth modification of the eighth embodiment of the present invention.
FIG. 45 is a circuit diagram showing a plurality of memory cells according to a seventh modification of the eighth embodiment of the present invention.
FIG. 46 is a circuit diagram illustrating one configuration of a memory cell MC according to a ninth embodiment of the invention;
FIG. 47 is a circuit diagram showing a modification of the ninth embodiment of the present invention.
FIG. 48 is a circuit diagram showing a modification of the ninth embodiment of the present invention.
FIG. 49 is a circuit diagram showing a modification of the ninth embodiment of the present invention.
FIG. 50 is a circuit diagram showing another modification of the ninth embodiment of the present invention.
FIG. 51 is a conceptual diagram showing a conventional SRAM.
FIG. 52 is a circuit diagram illustrating a conventional memory cell.
FIG. 53 is a circuit diagram illustrating a conventional memory cell.
FIG. 54 is a block diagram showing a connection between a dual port SRAM and a device for controlling the operation thereof.
[Explanation of symbols]
30 word line group, 31 write word line, 32 read complementary word line, 33 read word line, 34 write complementary word line, 40 bit line group, 41 write bit line, 42 write complementary bit line, 43 read bit line, 44 write Control line, 45 write complementary control line, 46 read complementary bit line, MC
Memory cell.

Claims (5)

(A) each of (a-1) a plurality of word line groups having a write word line;
(B) each is (b-1) a write bit line;
(B-2) a write control line provided corresponding to the write bit line;
(B-3) a plurality of bit line groups each having a write complementary bit line provided corresponding to the write bit line ;
(C) provided corresponding to one word line group and one bit line group;
(C-1) a storage cell including a first storage node;
(C-2) The write word line of the corresponding one word line group connected between the write bit line of the corresponding one bit line group and the first storage node, and the write A plurality of memory cells having a first switch that conducts only when any of the control lines is activated;
Each of the storage cells
(C-1-1) including a second storage node to which a logic complementary to the logic in the first storage node is given,
Each of the memory cells
(C-3) The write complementary bit line of the corresponding one bit line group and the second storage node connected to the corresponding write word line of the corresponding one word line group; A second switch that conducts only when any of the write control lines is activated
Further comprising
The write control line in the selected bit line group is activated,
The write control line in the bit line group that is not selected is not activated ,
The write bit line and the write complementary bit line take a complementary logic when the bit line group to which the write bit line belongs are selected, and take a logic equal to each other when not selected.
In one bit line group, the write control line takes an exclusive OR of the write bit line and the write complementary bit line . Said write bit line and the potential of the write complement bit line Ru said exclusive OR is taken from the non-inverting amplifier, memory device according to claim 1, wherein. (A) Each
(A-1) Write word line
A plurality of word line groups having
(B) Each
(B-1) a write bit line;
(B-2) a write control line provided corresponding to the write bit line;
A plurality of bit line groups having
(C) provided corresponding to one word line group and one bit line group;
(C-1) a storage cell including a first storage node;
(C-2) The write word line of the corresponding one word line group connected between the write bit line of the corresponding one bit line group and the first storage node, and the write A first switch that conducts only when either of the control lines is activated;
A plurality of memory cells having
With
The first switch is
(C-2-1) a first transistor comprising a control electrode, a first current electrode connected to the write bit line, and a second current electrode connected to the first storage node;
(C-2-2) A control electrode connected to the write control line, a first current electrode connected to the control electrode of the first transistor, and a second current connected to the write word line A second transistor comprising an electrode;
Including
The write control line in the selected bit line group is activated,
A memory device in which the write control line in the unselected bit line group is not activated . (A) Each
(A-1) Write word line
A plurality of word line groups having
(B) Each
(B-1) a write bit line;
(B-2) a write control line provided corresponding to the write bit line;
A plurality of bit line groups having
(C) provided corresponding to one word line group and one bit line group;
(C-1) a storage cell including a first storage node;
(C-2) The write word line of the corresponding one word line group connected between the write bit line of the corresponding one bit line group and the first storage node, and the write A first switch that conducts only when either of the control lines is activated;
A plurality of memory cells having
With
The first switch is
(C-2-1) a first transistor comprising a control electrode to which the write word line is connected, a first current electrode, and a second current electrode connected to the write control line;
(C-2-2) A control electrode to which the first current electrode of the first transistor is connected, a first current electrode connected to the write bit line, and a first storage node. A second transistor comprising a second current electrode;
Including
The write control line in the selected bit line group is activated,
A memory device in which the write control line in the unselected bit line group is not activated . The first transistor is an NMOS transistor formed on an SOI substrate,
4. The storage device according to claim 3, wherein the inactive write word line is supplied with a potential for reducing a forward bias with respect to the first current electrode and the body of the first transistor .

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