KR100452902B1 - Memory device - Google Patents

Abstract

A memory device is provided which reduces the consumption of unnecessary power while quickly performing writing that inverts the stored contents.

The transistors MN9 and MN10 are connected in series between the node N1 and the write bit line 41. Gates of the transistors MN9 and MN10 are connected to the write control line 44 and the write word line 31, respectively. The write control line 44 is provided with a potential corresponding to an exclusive logical sum of the write bit line 41 and the write complementary bit line 42. The transistor MN9 is turned off by precharging the write bit line 41 and the write complementary bit line 42 which are not used in the write operation to the same potential.

Description

Storage device {MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport static random access memory (SRAM) constituted by a metal insulator semiconductor field effect transistor (MISFET), and more particularly, to a technique for writing and reading data into a memory cell of the SRAM.

SRAM is used to cache data or instructions in an integrated circuit, that is, to temporarily hold data to deliver data to the CPU at the timing of a central processing unit (CPU), or to store the state of a sequential circuit. It is becoming. In recent years, the rate of reading data from or writing data to the memory has become important. In order to increase the bandwidth of a memory, a technique of providing a plurality of input / output terminals in a memory cell of an SRAM has been proposed. With this technique, a dual port static memory cell with one read port and one write port, or a multiport static with multiple read and write terminals For example, memory cells.

Fig. 51 is a conceptual diagram showing the configuration around the memory cell array of the conventional SRAM. The memory cells are arranged in a matrix form of m rows n columns, and the memory cells in the i rows j columns are denoted as MC _ij . In FIG. 51, symbols of the memory cells MC ₁₃ arranged in the first row and the third column are marked.

In the SRAM shown in FIG. 51, a word line extends in the row direction and a bit line extends in the column direction. The word line decoder 3 is connected to the word line group 30 _i (i = 1, 2, 3, ..., m-1, m) and selectively selects the word line group 30 _i corresponding to the input row address RA. Activate it. In addition, the bit line decoder 4 bit military first _{(40 j) (j = 1} , 2, 3, ..., n-1, n) is connected to the bit military first (40 _j) corresponding to the column address CA is input Selectively activate it.

The word line group 30 _i and the bit line group 40 _j intersect in the memory cell MC _ij . That is, a common word line group is provided in a plurality of memory cells arranged in a row direction, and a common bit line group is provided in a plurality of memory cells arranged in a column direction.

The word line group 30 _i is composed of a write word line 31 _i , a read word line 33 _i , and a read complementary word line 32 _i , and the latter two constitute a read word line pair. The bit line group 40 _j is composed of a write bit line 41 _j , a write complementary bit line 42 _j , and a read bit line 43 _j . The first two constitute a write bit line pair.

52 is a circuit diagram illustrating a structure common to all memory cells MC. Since the structure of the memory cell MC basically does not depend on the position (i, j) of the row or column, the subscripts indicating the position of the row or column are omitted here.

The memory cell MC includes a storage unit SC (herein referred to as a "storage cell") SC, a read circuit RK, and access transistors QN3 and QN4 constituting a latch circuit in which a pair of inverters L1 and L2 are cross-coupled.

In the storage cell SC, inverter L1 is connected in series to transistors QP1 and QN1, and inverter L2 is configured in series to transistors QP2 and QN2. The readout circuit RK also includes a three-state inverter configured in series connection to the transistors QP3, QP4, QN5 and QN6.

N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used for the transistors QN1 to QN6, and P-type MOSFETs are used for the transistors QP1 to QP4, respectively. For example, an N-type MOSFET is a surface channel type, and a P-type MOSFET is a surface channel type or a buried channel type.

The storage cell SC has a pair of nodes N1 and N2, and a pair of storage states exist when the nodes N1 and N2 are "H" and "L", and vice versa. In addition, "H" means logic corresponding to a potential higher than (V _DD + V _SS ) / 2, and "L" means logic corresponding to a potential lower than (V _DD + V _SS ) / 2. However, ground is often selected for the potential V _SS . Hereinafter, "H" and "L" each mean not only logic but also a potential corresponding to the logic. In addition, it is a design option whether all states of "H" and "L" correspond to "1" and "0" of the bit of the SRAM.

The N-type MOSFET turns on when "H" is applied to its gate and turns off when "L" is applied. The P-type MOSFET turns on when "L" is applied to its gate and turns off when "H" is applied. In the on state, current flows between the source / drain and both are electrically conductive. In the off state, the current is electrically cut off between the source and the drain, and almost no current flows.

Node N1 is an input terminal of inverter L2, and a potential corresponding to logic complementary to logic corresponding to potential of node N1 is output to node N2. The node N2 is an input terminal of the inverter L1, and an inversion bit of logic complementary to the logic corresponding to the potential of the node N2 is output to the node N1. Therefore, there are a pair of memory states corresponding to mutually complementary logic.

The access transistor QN3 is connected to the storage cell SC and the write bit line 41 at the nodes N1 and N4, respectively. The access transistor QN4 is connected to the storage cell SC and the write complementary bit line 42 at nodes N2 and N5, respectively. The gates of the access transistors QN3 and QN4 are commonly connected to the write word line 31.

In the read circuit RK, the drains of the transistors QP4 and QN5 are connected to the node N3 in common. The gates of the transistors QP3 and QN6 are commonly connected to the node N1. The gates of the transistors QP4 and QN5 are connected to the read complementary word line 32 and the read word line 33, respectively. As described above, the dual port static memory cell is employed as the memory cell MC.

When reading data from the memory cell MC, complementary logic is set for the read word line 33 and the read complementary word line 32. Then, the read word lines 33 and the read complementary word lines 32 corresponding to the rows of the memory cells MC to be read are set to "H" and "L", respectively, and the read word lines corresponding to the other rows. Reference numeral 33 and the read complementary word line 32 are set to "L" and "H", respectively.

Therefore, the transistors QP4 and QN5 of the read circuit RK of the memory cell MC to be read are turned on. Accordingly, a value complementary to the node N1 is provided to the read bit line 43 through the node N3 by the inverters constituted by the transistors QP3 and QN6. On the other hand, the transistors QP4 and QN5 of the read circuit RK of the memory cell MC which are not subject to reading are turned off. As a result, the read bit line 43 is cut off from the storage cell SC of the memory cell MC which is not a read target.

When data is written to the memory cell MC, the write word line 31 corresponding to the row of the memory cell MC to be written is set to "H", and the write word line 31 corresponding to the other rows is set. Is set to "L".

Therefore, all of the access transistors QN3 and QN4 of the memory cell MC to be written on are turned on, and the nodes N1 and N2 of the storage cell SC are connected to the write bit line 41 and the write complementary bit line 42 through the nodes N4 and N5, respectively. Is connected to. On the other hand, all of the access transistors QN3 and QN4 of the memory cell MC which are not subject to writing are turned off, and the write bit lines 41 and the write complementary bit lines 42 of the nodes N1 and N2 of the storage cell SC are cut off.

As described above, the logics of the nodes N1 and N2 of the storage cell SC have a complementary relationship, and therefore are complementary to the write bit line 41 and the write complementary bit line 42 corresponding to the column of the memory cell MC to be written. Logic is set. The logic set in the write bit line 41 and the write complementary bit line 42 is written to the nodes N1 and N2.

When the write operation ends, the write word line 31 is set to "L", and the access transistors QN3 and QN4 are turned off. Thus, the storage cell SC is cut off from the write bit line pair, and the data held in the storage cell SC is not rewritten, but in a standby state.

In the above configuration, when the write word line 31 is set to " H " during the write operation, the access transistors QN3 and QN4 are turned on in all the memory cells MC belonging to the same row as the memory cell MC to be written. Therefore, in the memory cell MC belonging to the same row as the memory cell MC to be written and not the object to be written, the nodes N1 and N2 are written through the access transistors QN3 and QN4, respectively, during the write operation. It is connected to the bit line 42.

On the other hand, both the write bit line 41 and the write complementary bit line 42 corresponding to the columns of the memory cells MC which are not subject to writing are usually precharged with the same potential. The potentials of the precharges are, for example, V _DD , (V _DD + V _SS ) / 2, and V _SS . Therefore, based on the potentials of the nodes N1 and N2 of the memory cell MC, one potential of the write bit line 41 and the write complementary bit line 42 becomes V _SS and the other potential becomes (V _DD -V _thn ). Are respectively tensioned (a potential V _DD is applied to the write word line 31, and the threshold voltages of the transistors QN3 and QN4 are referred to as V _thn > 0). Application of the potentials through the nodes N1 and N2 to the precharged write bit line pairs thus causes unnecessary power consumption.

In addition, as described above, precharge is performed again in the next write operation to the bit line pair to which the potential is applied by the storage cell SC. At this time, too much unnecessary power is consumed.

Fig. 53 is a circuit diagram showing the configuration of the memory cell MC proposed to prevent the above-described power consumption, and is introduced, for example, in US Patent Publication 6,005,794.

NMOS transistors QN9, QN10 is (hereinafter also referred to as "transition point V _SS") node N1 and the potential V _SS potential point that provides, for example, are connected in series between the ground. The gate of the NMOS transistor QN9 is connected to the write bit line 41 at the node N4, and the gate of the NMOS transistor QN10 is connected to the write word line 31. In a similar manner, the NMOS transistors QN11 and QN12 are connected in series between the node N2 and the potential point V _SS . The gate of the NMOS transistor QN11 is connected to the write complementary bit line 42 at the node N5, and the gate of the NMOS transistor QN12 is connected to the write word line 31, respectively.

The write word line 31 corresponding to the memory cell MC to be written (ie, in the selected row) becomes " H " during the write operation, and the transistors QN10 and QN12 are turned on. Since complementary logic is provided to the write bit line 41 and the read bit line 43 (that is, in the selected column) corresponding to the memory cell MC, only one of the transistors QN9 and QN11 is turned on. If the write bit line 41 and the write complementary bit line 42 are "H" and "L", the node N1 is set to a logic "L". As a result, the node N2 becomes "H". Conversely, if the write bit line 41 and the write complementary bit line 42 are "L" and "H", the node N2 is set to a logic "L". As a result, the node N1 becomes "H".

All of the write bit pair lines not selected in such a write operation are set to the potential V _SS . Therefore, the transistors QN9 and QN11 are turned off in the memory cell MC that is not the write target, so that even if the memory cell MC is disposed in the row corresponding to the selected write word line 31 and the write word line 31 becomes "H", the node N1 is used. , N2 is not forcibly set in potential from the outside of the storage SC. That is, there is an advantage that the unnecessary power consumption described above does not occur.

However, this circuit has a problem in that the time required for the write operation for changing the storage contents of the storage cell SC becomes long. That is, one of the nodes N1 and N2 is set to "L" from the outside of the storage cell SC, but there is no function of setting the other to "H" from the outside of the storage cell SC. For example, when the states N1 and N2 are inverted to "H" and "L" states, respectively, the transistors QN9 and QN10 are turned on and attempt to discharge the node N1, but the node N2 is "L". Since this may not be set to "H" from the outside of the storage cell SC, the inverter L1 tries to keep the node N1 as "H". Since the storage cell SC is designed to have a high static noise margin in order to keep data stable, the storage contents of the storage cell SC cannot be reversed quickly by only discharging the node N1.

SUMMARY OF THE INVENTION The present invention has been made on the basis of the above-described background, and an object thereof is to provide a technique for reducing unnecessary power consumption while quickly performing writing for inverting stored contents.

1 is a conceptual diagram illustrating an SRAM according to Embodiment 1 of the present invention.

Fig. 2 is a circuit diagram illustrating one of the memory cells according to the first embodiment of the present invention.

3 is a circuit diagram illustrating a three state inverter.

4 is a circuit diagram illustrating an XOR circuit.

5 is a circuit diagram illustrating an XOR circuit.

6 is a circuit diagram illustrating an XOR circuit.

7 is a circuit diagram illustrating an XOR circuit.

8 is a circuit diagram illustrating an XOR circuit.

9 is a circuit diagram illustrating an XOR circuit.

Fig. 10 is a circuit diagram showing a variation of Embodiment 1 of the present invention.

11 is a schematic diagram illustrating Example 1 of the present invention.

Fig. 12 is a conceptual diagram showing an SRAM according to the second embodiment of the present invention.

Fig. 13 is a circuit diagram illustrating one of the memory cells according to the second embodiment of the present invention.

Fig. 14 is a circuit diagram showing a variation of Embodiment 2 of the present invention.

Fig. 15 is a circuit diagram showing another modification of the second embodiment of the present invention.

Fig. 16 is a circuit diagram illustrating one of the memory cells according to the third embodiment of the present invention.

Fig. 17 is a circuit diagram showing a modification of Embodiment 3 of the present invention.

18 is a circuit diagram illustrating one of the memory cells according to the fourth embodiment of the present invention.

Fig. 19 is a circuit diagram showing a modification of Embodiment 4 of the present invention.

20 is a circuit diagram illustrating one of the memory cells according to the fifth embodiment of the present invention.

Fig. 21 is a circuit diagram showing a memory cell according to the first modification of Embodiment 5 of the present invention.

Fig. 22 is a circuit diagram showing a memory cell according to the second modification of the fifth embodiment of the present invention.

Fig. 23 is a circuit diagram showing a memory cell according to the third modification of the fifth embodiment of the present invention.

Fig. 24 is a circuit diagram showing a memory cell according to the fourth modification of the fifth embodiment of the present invention.

Fig. 25 is a circuit diagram showing a memory cell according to the fifth modification of the fifth embodiment of the present invention.

Fig. 26 is a circuit diagram showing a memory cell according to the sixth modification of Embodiment 5 of the present invention.

Fig. 27 is a circuit diagram showing a plurality of memory cells according to the sixth modification of Embodiment 5 of the present invention.

28 is a cross-sectional view illustrating a conventional access transistor.

29 is a circuit diagram illustrating a memory cell that may be employed in a dual port SRAM.

30 is a conceptual diagram illustrating an SRAM according to a seventh embodiment of the present invention.

Fig. 31 is a circuit diagram illustrating one of the memory cells according to the seventh embodiment of the present invention.

Fig. 32 is a circuit diagram showing a memory cell in accordance with a variation of Embodiment 7 of the present invention.

Fig. 33 is a circuit diagram showing a memory cell according to another variation of Embodiment 7 of the present invention.

Fig. 34 is a circuit diagram illustrating one of the memory cells according to the eighth embodiment of the present invention.

35 is a timing chart illustrating the operation of a memory cell according to Embodiment 8 of the present invention.

Fig. 36 is a circuit diagram showing a part of the configuration in which memory cells according to Embodiment 8 of the present invention are arranged in a matrix.

Fig. 37 is a circuit diagram showing the construction of the memory cell according to the first modification of Embodiment 8 of the present invention.

Fig. 38 is a circuit diagram showing the construction of a memory cell according to the second modification of the eighth embodiment of the present invention.

Fig. 39 is a circuit diagram showing the construction of the memory cell according to the third modification of the eighth embodiment of the present invention.

40 is a circuit diagram showing a configuration of the memory cell according to the fourth modification of the eighth embodiment of the present invention;

Fig. 41 is a circuit diagram showing the construction of the memory cell according to the fifth modification of Embodiment 8 of the present invention.

Fig. 42 is a circuit diagram showing the construction of the memory cell according to the sixth modification of the eighth embodiment of the present invention.

Fig. 43 is a circuit diagram showing the construction of the memory cell according to the seventh modification of Embodiment 8 of the present invention.

Fig. 44 is a circuit diagram showing a plurality of memory cells according to the sixth modification of the eighth embodiment of the present invention.

Fig. 45 is a circuit diagram showing a plurality of memory cells according to the seventh modification of the eighth embodiment of the present invention.

Fig. 46 is a circuit diagram illustrating one configuration of the memory cell MC according to the ninth embodiment of the present invention.

Fig. 47 is a circuit diagram showing a modification of Embodiment 9 of the present invention.

48 is a circuit diagram showing a modification of Embodiment 9 of the present invention;

Fig. 49 is a circuit diagram showing a modification of Embodiment 9 of the present invention.

50 is a circuit diagram showing another modification of the ninth embodiment of the present invention;

Fig. 51 is a conceptual diagram showing a conventional SRAM.

Fig. 52 is a circuit diagram illustrating a conventional memory cell.

Fig. 53 is a circuit diagram illustrating a conventional memory cell.

Fig. 54 is a block diagram showing a connection between a dual port SRAM and a device for controlling its operation.

<Explanation of symbols for the main parts of the drawings>

30: word group

31: write word line

32: read complementary word line

33: read word line

34: write complementary word line

40: beat line group

41: write bit line

42: write complementary bit line

43: read bit line

44: write control line

45: write complementary control line

46: read complementary bit line

MC: memory cell

The present invention provides a memory device comprising (a) a plurality of word line groups, (b) a plurality of bit line groups, and (c) a plurality of memory cells, wherein each of the word line groups includes (a-1) a write word line. Each of the bit line groups includes (b-1) a write bit line and (b-2) a write control line corresponding to the write bit line, and (c) each of the memory cells includes one word. (C-1) a storage cell provided corresponding to a line group and one said bit line group, (c-2) said write bit line of said one bit line group and said first bit line group; And a first switch connected between the storage nodes and conducting only when both the write word line and the write control line of the corresponding one word line group are activated. The write control line in the selected bit line group is activated, and the write control line in the unselected bit line group is not activated.

In the storage device according to the present invention, each of the bit line groups further includes (b-3) a write complementary bit line provided corresponding to the write bit line, and each of the storage cells is (c-1-1). A second memory node provided with logic complementary to the logic at the first memory node, each of the memory cells comprising (c-3) the write complementary bit line of the corresponding one bit line group; And a second switch connected between second memory nodes and conducting only when both the write word line of the corresponding one word line group and the write control line are activated, wherein the write bit line and the write complementary bit A line adopts complementary logic to each other when the bit line group to which it belongs is selected, and takes the same logic to each other when not selected, and the write control line in one bit line group. It takes the write bit line and write complementary bit exclusive-OR line.

In the memory device according to the present invention, the exclusive OR is employed after non-inverting and amplifying the potentials of the write bit line and the write complementary bit line.

In the memory device according to the present invention, the first switch includes (c-2-1) a control electrode to which the write control line is connected, a first transistor including first and second current electrodes, and (c- 2-2) a second transistor including a control electrode to which the write word line is connected, a first transistor and a first current electrode; and the first and second current electrodes of the first transistor, and the second transistor. The first and second current electrodes of the transistor are connected in series between the first memory node and the write bit line.

In the memory device according to the present invention, the first switch (c-2-3) includes a control electrode provided with logic complementary to the write control line, and a first current connected to the second current electrode of the first transistor. A third transistor comprising a current electrode, a second current electrode connected to the first current electrode of the first transistor, and having a different conductivity type from the first transistor, (c-2-4) the write word A control electrode provided with logic complementary to the line, a first current electrode connected to the second current electrode of the second transistor, and a second current electrode connected to the first current electrode of the second transistor; And a fourth transistor having a conductivity type different from that of the second transistor.

In the memory device according to the present invention, the first current electrode of the first transistor and the second current electrode of the second transistor are shared.

In the storage device according to the present invention, the first switch includes (c-2-1) a control electrode, a first current electrode connected to the write bit line, and a second current electrode connected to the first memory note. (C-2-2) a control electrode connected to the write control line, a first current electrode connected to the control electrode of the first transistor, and a first connected to the write word line. And a second transistor comprising two current electrodes.

In the storage device according to the present invention, the first switch (c-2-1) includes a control electrode connected to the write word line, a first current electrode, and a second current electrode connected to the write control line. (C-2-2) a control electrode to which the first current electrode of the first transistor is connected, a first current electrode connected to the write bit line, and a first storage node And a second transistor including the second current electrode.

The present invention relates to a memory device comprising (a) a plurality of word line groups, (b) a plurality of bit line groups, and (c) a plurality of memory cells, wherein each of the word line groups includes (a-1) a write word line. Each of the bit line groups includes (b-1) a write bit line, and (b-2) a write control line corresponding to the write bit line, wherein each of the memory cells includes one word line group; (C-1) a storage cell including a first memory node, (c-2) the write word line of the corresponding one word line group, and the write control line Only when is activated, a first potential setting section for providing logic complementary to logic in the write bit line of the one bit line group corresponding to the first memory node. The write control line in the selected bit line group is activated, and the write control line in the unselected bit line group is not activated.

In the memory device according to the present invention, the first potential setting portion (c-2-1) is a first potential point for supplying a potential corresponding to the first logic, and (c-2-2) the write control line. A first switch for controlling conduction between the first memory node and the first connection point by the logic of (c-2-3); and logic of the write bit line and logic of the write word line And a second switch for controlling conduction between the first connection point and the first potential point.

In the memory device according to the present invention, the first potential setting section (c-2-4) includes a second potential point for supplying a potential corresponding to the second logic complementary to the first logic, and (c-2- 5) a third switch for controlling conduction between the first connection point and the second potential point by both logic in the write bit line and logic complementary to the logic in the write word line. .

In the memory device according to the present invention, the first potential setting section (c-2-1) is provided at a first potential point for supplying a potential corresponding to the first logic, and (c-2-2) at the write word line. A first switch whose conduction between the first storage node and the first connection point is controlled by the logic of (c-2-3), and both of the logic in the write control line and the logic in the write bit line. And a second switch in which conduction between the first connection point and the first potential point is controlled.

In the memory device according to the present invention, the first potential setting section (c-2-4) includes a second potential point for supplying a potential corresponding to the second logic complementary to the first logic, and (c-2- 5) and a second switch in which conduction between the first connection point and the second potential point is controlled by both logic complementary to the logic at the write control line and logic at the write bit line.

In the memory device according to the present invention, the first transistor is an NMOS transistor formed on an SOI substrate, and an inactive write word line has a potential for reducing a net bias for the first current electrode and the body of the first transistor. Is provided.

The present invention relates to a memory device comprising (a) a plurality of word line groups, (b) a plurality of bit line groups, and (c) a plurality of memory cells, wherein each of the word line groups includes (a-1) a write word line. Wherein each of the bit line groups includes a write bit line (b-1), each of the memory cells is provided corresponding to one of the word line group and one of the bit line groups, and (c-1) the first A storage cell including a storage node, (c-2) a switch connected between the first storage node and a first potential point for supplying a first potential corresponding to a first logic, and (c-3) a correspondence; And a control element for allowing opening and closing control of the switch by logic provided to the write bit line of the corresponding one bit line group when the write word line of the one word line group is activated.

In the memory device according to the present invention, the switch includes (c-2-1) a first current electrode connected to the first memory node, a second current electrode connected to the first potential point, and a control electrode. And a first transistor comprising: (c-3-1) a first current electrode connected to a control electrode of the first transistor, a second current electrode connected to the write bit line, and A second transistor including a control electrode connected to the write word line is included.

In the storage device according to the present invention, the control element comprises (c-3-2) a first current electrode connected to the second current electrode of the second transistor and a first current electrode of the second transistor. And a third transistor comprising a connected second current electrode and a control electrode provided with a potential corresponding to logic complementary to the logic in the write word line.

The present invention is provided in correspondence with (a) a plurality of write word lines, (b) a plurality of write bit lines, (c) one word line and one bit line, and each is a (c-1) memory node. And (c-2) the first transistor whose conduction is controlled by logic provided to the write bit line, and (c-3) the conduction is controlled by logic provided to the write word line. A plurality of memory cells having a second transistor, said storage cell being provided with a first current electrode connected to said storage node and a second current electrode provided with a second potential corresponding to logic complementary to said first logic; And a third transistor having a control electrode, a first current electrode connected to the control electrode of the third transistor, a second current electrode provided with the second potential, and a control electrode connected to the storage node. Further comprising a fourth transistor having, The memory node is a memory device connected to a first potential point for supplying a first potential corresponding to a first logic through only the series connection of the first transistor and the second transistor.

According to the present invention, in the storage device, the storage cell is composed of two transistors cross-coupled.

According to the present invention, the memory device has a different conductivity type from the first transistor and the second transistor.

Embodiment of the Invention

Unless otherwise specified in the present embodiment, the logic "H" corresponds to the state where the word line is activated, that is, selected, and "L" corresponds to the state where it is not activated, that is, not selected. Even if these relationships are reversed, the following description is valid if the conductive type of the transistor used is appropriately replaced.

Example 1.

1 is a conceptual diagram showing a configuration around a memory cell array of an SRAM according to a first embodiment of the present invention. Is a military first bit _(j 40) the write control line is characterized by a structure (44 _j) added to the configuration of a conventional SRAM. The potential (or logic) of the write control line 44 _j is also set by the bit line decoder 4. Specifically, the write control line 44 _j includes an exclusive logical sum of logic provided to the write bit line 41 _j and logic provided to the write complementary bit line 42 _j (hereinafter also referred to as "XOR (exclusive OR)"). Logic) is set. First, for simplicity, it will be explained that the write bit line 41 _j and the write complementary bit line 42 _j are provided with one of the potentials V _DD and V _SS in the precharge period.

FIG. 2 is a circuit diagram illustrating one configuration of the memory cell MC shown in FIG. 1. As in the prior art, subscripts indicating row positions and column positions are omitted. Memory cell MC includes storage cell SC, read circuit RK, and pass transistors MN9, MN10, MN11, MN12, all of which are NMOS transistors, and further includes write bit line 41, write complementary bit line 42, read bit line 43 ), A write word line 31, a read complementary word line 32, and a read word line 33 are provided.

The storage cell SC has inverters L1 and L2 cross-coupled, and nodes N1 and N2 exist as respective output terminals. Inverter L1 is a PMOS transistor QP1 comprising a source to which the potential V _DD is applied, a drain connected to the node N1, a gate connected to the node N2, a source to which the potential V _SS is applied, a drain connected to the node N1, a node N2. It consists of the NMOS transistor QN1 containing the connected gate. In a similar manner, the inverter L2 is a PMOS transistor QP2 including a source to which the potential V _DD is applied, a drain connected to the node N2, a gate connected to the node N1, a source to which the potential V _SS is applied, a drain connected to the node N2, It consists of an NMOS transistor QN2 including the gate connected to the node N1.

The read circuit RK is connected to the PMOS transistor QP3 including the source to which the potential V _DD is applied, the gate connected to the node N1, the drain connected to the read bit line 43 at the node N3, and the read complementary word line 32. PMOS transistor QP4 including a gate, a source to which potential V _SS is applied, an NMOS transistor QN6 including a gate connected to node N1, a drain connected to read bit line 43 at node N3, and a read word line 33 Is a three-state inverter composed of an NMOS transistor QN5 including a gate connected to the. The drain of transistor QP3 and the source of transistor QP4, the drain of transistor QN6 and the source of transistor QN5 are connected, respectively.

3 is a circuit diagram illustrating the configuration of the three-state inverter, and substantially shows the configuration of the read circuit RK. Logic A is common to one gate of a pair of NMOS transistors and one gate of a pair of PMOS transistors, logic B to the other gate of a pair of NMOS transistors, and logic B (B and As complementary logic, an upper line is added to B in the figure, which is the same for other logic). If logic B is "L", the output logic Z is not determined by the tri-state inverter (tristate condition). However, if logic B is " H ", logic Z inverting logic A is output.

Returning to FIG. 2, the pass transistors MN9 and MN10 are connected in series between the node N4 on the write bit line 41 and the node N1 of the storage cell SC, and the write control line 44 and the write word line 31 are connected in series. When both are "H", it functions as a switch for transferring the logic of the write bit line 41 to the node N1. More specifically, one of the current electrode pairs (source-drain pair) of the pass transistor MN9 is connected to the node N1, one of the current electrode pairs of the pass transistor MN10 is connected to the node N4, and the currents of the pass transistors MN9 and MN10. The other of an electrode pair is connected in common. The gate of the pass transistor MN9 is connected to the write control line 44 at the node N6, and the gate of the pass transistor MN10 is connected to the write bit line 41 at the node N4.

Similarly, the pass transistors MN11 and MN12 are connected in series between the node N5 on the write complementary bit line 42 and the node N2 of the storage cell SC, so that both the write control line 44 and the write word line 31 are " H ″, it functions as a switch for transferring the logic of the write complementary bit line 42 to the node N2. More specifically, one of the current electrode pairs of the pass transistor MN11 is connected to the node N2, one of the current electrode pairs of the pass transistor MN12 is connected to the node N5, and the other of the current electrode pairs of the pass transistors MN11 and MN12 are common. Is connected. The gate of the pass transistor MN11 is connected to the write control line 44 at the node N6, and the gate of the pass transistor MN12 is connected to the write bit line 41 at the node N4.

The pass transistors MN10 and MN12 are similar to the transistors QN10 and QN12 shown in FIG. 36, and their operation depends on the logic at the write word line 31, but their sources are not connected to the potential point V _SS , respectively. It differs in that it is connected to the bit line 41 and the write complementary bit line 42. Also, the pass transistors MN9 and MN11 are similar to the transistors QN9 and QN11 shown in FIG. 36, and are interposed between the transistors MN12 and N2 between the pass transistor MN10 and the node N1, respectively, but the conduction is logic in the write control line 44. It is different in that it depends.

The write operation for the memory cell of such a configuration is as follows. The selected write word line 31 becomes " H " so that pass transistors MN10 and MN12 are turned on. One of the write bit lines 41 and the write complementary bit lines 42 constituting the write bit pair line becomes "H" and the other becomes "L". Corresponding to this, since the write control line 44 becomes "H", the pass transistors MN9 and MN11 are turned on.

Therefore, node N1 of storage cell SC is connected to write bit line 41 at node N4 through pass transistors MN9 and MN10, and node N2 is connected to write complementary bit line 42 at node N5 through pass transistors MN11 and MN12, respectively. do. Since the logic set in the write bit line 41 and the write complementary bit line 42 is written to N1 and N2, respectively, compared with the circuit shown in Fig. 53, the time required for inverting the data stored in the storage cell SC is short. .

In order to consider the magnitude of the potential, the threshold voltages of the pass transistors MN9 and MN10 are set to the potential V _thn , and the potential is set to "H" for the write control line 44, the write word line 31, and the write bit line 41. It is _assumed that V _DD is provided. Since the pass transistors MN9 and MN10 are interposed between the node N4 and the node N1, the potential V _DD -2V _thn is applied to the node N1 in accordance with the substrate effect of these two transistors.

When the potential difference V _DD -V _SS becomes 1 V or less, the inverters L1 and L2 of the storage cell SC may recognize the potential V _DD -2V _{thn as} "L" instead of "H". In order to prevent this, the potential applied as "H" to the write word line 31 may be set to a potential higher than the potential V _DD , for example, the potential V _DD + 2V _thn . The same effect can be obtained even if both of the potentials applied as "H" to the write word line 31 and the write control line 44 are set to the potential V _DD + V _thn .

By the way, the operation of the memory cell MC disposed in the row corresponding to the selected write word line 31 and arranged in the column corresponding to the unselected write bit line pair will be described. In this memory cell MC, both the write bit line 41 and the write complementary bit line 42 are set to "H" or "L" by precharging. Correspondingly, the write control line 44 is set to "L". In other words, the write control line 44 becomes "L" in the unselected column. Therefore, even when the transistors MN10 and MN12 are turned on as the write word line 31 is "H", the transistors MN9 and MN11 are turned off, and the storage cell SC affects the potentials of the write bit line 41 and the write complementary bit line 42. There is no giving. Therefore, it is possible to reduce unnecessary power consumption while quickly writing the inverted contents.

4 to 9 are circuit diagrams illustrating an XOR circuit for obtaining an exclusive OR of both from logics A and B as logic Z. FIG. These XOR circuits can be employed for the write control line 44 to obtain an exclusive logical sum of the logic provided to the write bit line 41 and the logic provided to the write complementary bit line 42. In FIG. 1, the XOR circuit is incorporated in the bit line decoder 4, but the XOR circuit may be provided separately from the bit line decoder 4.

For example, the operation of the XOR circuit shown in FIG. 7 will be described. When logic A is "H", the inverter consisting of PMOS transistor TP1 and NMOS transistor TN1 provides logic "L" to node J1. On the other hand, the node J2 is provided with a logic A, that is, "H". The PMOS transistor TP2 and the NMOS transistor TN2 are connected in series between the nodes J2, J1, and both function as inverters. This inverter inputs logic B and outputs logic B bar as logic Z to node J3. At this time, since the transmission gates constituted by the PMOS transistors TP3 and the NMOS transistor TN3 are turned off, the collision between the logic B and the logic bar does not occur at the node J3.

When logic A is "L", nodes J1 and J2 become "H" and "L", respectively. Therefore, both transistors TP3 and TN3 are turned on, so that logic B is provided to node J3 as logic Z. On the other hand, when logic B is "H", logic "H" at node J1 is transferred to node J3 by NMOS transistor TN2, and when logic B is "L", logic at node J2 by PMOS transistor TP2. "L" is passed to node J3. In any case, therefore, logical B is provided as logical Z at node J3.

From the above operation, the circuit of Fig. 7 provides the XOR of logics A and B. In order to obtain an exclusive OR and complementary value (XNOR: exclusive NOR), the output may be further inverted, or only one of logic A and logic B may be inverted and input to a circuit for obtaining XOR.

10 is a circuit diagram showing a variation of this embodiment. Compared with the configuration shown in FIG. 2, the transistors MN9 whose switching is controlled by the logic of the write control line 44 and the transistors MN10 whose switching is controlled by the logic of the write word line 31 are nodes N1 and N4. They are common in that they are connected in series between each other, and their positions are different. By doing the same, the positions between the nodes N2 and N5 are replaced as compared with the configuration shown in Fig. 2 as well. It is natural that even in such a configuration, the same effect as that shown in FIG. 2 can be obtained.

11 is a schematic diagram illustrating the configuration of pass transistors MN9, MN10, MN11, and MN12. In order to simplify the storage cell SC, inverters L1 and L2 are represented by symbols, while the pass transistors MN9, MN10, MN11, and MN12 are the write bit line 41, the write complementary bit line 42, and the write control line 44. ) Together with the write word line 31 is shown in plan view. In the drawings, reference numerals in parentheses correspond to the configuration illustrated in FIG. 10, and reference numerals described in the left side correspond to the configurations illustrated in FIG. 2.

FIG. 11 is described according to the configuration shown in FIG. 2. Pass transistors MN9 and MN10 are formed in active region R1. One of the current electrode pairs of the pass transistor MN9 is connected to the node N1, and one of the current electrode pairs of the pass transistor MN10 is connected to the write bit line 41. The pass transistors MN9 and MN10 share the source drain region SD1 among the other of the current electrode pairs. Similarly, pass transistors MN11 and MN12 are formed in active region R2. One of the current electrode pairs of the pass transistor MN11 is connected to the node N2, and one of the current electrode pairs of the pass transistor MN12 is connected to the write complementary bit line 42. The pass transistors MN11 and MN12 share the source drain region SD2 among the other of the current electrode pairs.

The gate wiring G1 serving as the gates of the pass transistors MN9 and MN11 and the gate wiring G2 serving as the gates of the pass transistors MN10 and MN12 are both located above the active regions R1 and R2 through the gate insulating film (not shown). Is laid on. The write control line 44 and the write word line 31 are provided above the gate lines G1 and G2. The write control line 44 and the write word line 31 are connected via the gate lines G1 and G2 and via contacts V1 and V2, respectively.

As described above, the pass transistors MN9 and MN10 share the source and drain regions SD1, and the pass transistors MN11 and MN12 share the source and drain regions SD2, so that they can be arranged in a small area.

The potential V _DD + V _SS / 2 may be applied to the write bit line 41 _j and the write complementary bit line 42 _j in the precharge period. In this case, a circuit for non-inverting and amplifying the potential of each of the write bit line 41 _j and the write complementary bit line 42 _j may be provided in front of the XOR circuit. For example, if V _SS = 0 V and the input margin of the potential 2V _DD is allowed even if the input margin of the XOR circuit is large, the amplification factor of the amplifier circuit may be set to twice. Accordingly, the pair of inputs of the XOR circuit, whether the precharge potential is V _DD / 2 or V _DD , are all "H". If the precharge potential is V _SS, the pair of inputs of the XOR circuit are all "L". Therefore, the effects of the present embodiment can be enjoyed.

Example 2.

12 is a conceptual diagram showing a configuration around a memory cell array of an SRAM according to a second embodiment of the present invention. The write complementary control line 45 _j is added to the bit line group 40 _j and the write complementary word line 34 _i is added to the word line group 30 _i with respect to the configuration of the SRAM shown in the first embodiment. It is of an architectural structure.

The potential of the write complementary control line 45 _j and the write complementary word line 34 _i is set by the bit line decoder 4 and the word line decoder 3, respectively. Specifically, the write complementary control line 45 _j and the write complementary word line 34 _i are provided with complementary logic to the write control line 44 _j and the write word line 31 _i , respectively.

FIG. 13 is a circuit diagram illustrating the configuration of one of the memory cells MC shown in FIG. 12. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted. Compared with the configuration shown in Fig. 2, the memory cell MC is provided with the addition of the pass transistors MP9, MP10, MP11, and MP12, which are all PMOS transistors, and the write complementary control line 45 and the write complementary word line 34 are provided. It is added and laid.

The pass transistors MP9, MP10, MP11, and MP12 are connected in parallel with the pass transistors MN9, MN10, MN11, and MN12, respectively. The logic provided to the gates of the pass transistors MP9, MP10, MP11, and MP12 is complementary to the logic provided to the gates of the pass transistors MN9, MN10, MN11, and MN12, respectively. That is, the gates of the pass transistors MP9 and MP11 are connected to the write complementary control line 45 at the node N7, and the gates of the pass transistors MP10 and MP12 are connected to the write complementary word line 34.

Therefore, the pass transistors MP9, MP10, MP11, and MP12 form a transmission gate together with the pass transistors MN9, MN10, MN11, and MN12, respectively. Thus, compared to the configuration shown in FIG. 2, when transferring logic "H" from the write bit line 41 to the node N1 (or when transferring logic "H" from the write complementary bit line 42 to the node N2). As a result, a drop by the threshold value V _thn due to the substrate effect does not occur. Therefore, there is an advantage that a boosting circuit for boosting the potential provided to the write word line 31 becomes unnecessary.

FIG. 14 is a circuit diagram showing a variation of the present embodiment, and corresponds to FIG. 10 according to the first embodiment. That is, compared with the structure shown in FIG. 13, the structure shown in FIG. 14 has a position between the transmission gate which the pass transistors MN9 and MP9 comprise, and the transmission gate which the pass transistors MN10 and MP10 comprise between nodes N1 and N4. The positions of the transmission gates constituted by the pass transistors MN11 and MP11 and the transmission gates constituted by the pass transistors MN12 and MP12 are replaced between the nodes N2 and N5. Naturally, even in such a configuration, the effects of the present embodiment can be obtained.

As a matter of course, by similarly to the pass transistors MN9 and MN10, the pass transistors MP9 and MP10 also share the source and drain regions, thereby saving the required area. The same applies to the pass transistors MP11 and MP12.

In addition, even if the access transistor is replaced in the transmission gate, it is possible to avoid the drop in the threshold V _thn due to the substrate effect. FIG. 15 adds a write complementary word line 34 to the circuit shown in FIG. 52, replaces access transistor QN3 with a transmission gate constituted by PMOS transistor MP10 and NMOS transistor MN10, and replaces access transistor QN4 with PMOS transistor MP12. The structure substituted by the transmission gate which the NMOS transistor MN12 comprises is shown.

As in the configuration shown in Fig. 14, the conduction of transistors MN10 and MN12 is controlled in accordance with the logic of the write word line 31, and the transistors MP10 and MP12 are controlled in accordance with the logic of the write complementary word line 34. The fall of the threshold value V _thn can be avoided. Therefore, it is not necessary to boost the potential provided to the write word line 31. In addition, as compared with the configuration shown in Fig. 13 or 14, as the transmission gate decreases by one, the time for accessing the storage cell SC is shorter, the area reduction is smaller, and further the write control line 44 The advantage is that no XOR circuit needs to be installed. However, unlike the present embodiment, the function of avoiding the potential collision between the storage cell SC and the write bit line pair in the memory cell MC of the unselected column is inferior.

Example 3.

16 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted, but may be employed as each of MC _ij shown in FIG.

The memory cell MC is provided with access transistors MN2, MN4 and control transistors MN1, MN3, which are all NMOS transistors, in place of the access transistors QN3, QN4 in comparison with the configuration shown in FIG.

The access transistor MN2, like the access transistor QN3, controls the conduction between the node N1 and the node N4. The gate is common to the access transistor QN3 in that the write word line 31 is connected to the gate, but differs in that the control transistor MN1 is interposed. The access transistor MN4 also controls the conduction between the node N2 and the node N5 and is common to the access transistor QN4 in that the write word line 31 is connected to the gate thereof, but differs in that the control transistor MN3 is interposed.

Since the gates of the control transistors MN1 and MN3 are connected to the write control line 44 through the node N6, similarly to the first embodiment, all the conduction between the node N1 and the node N4 and between the node N2 and the node N5 is the write word line 31. And the case where the write control line 44 is "H". Therefore, in the same manner as in the first embodiment, unnecessary power consumption can be reduced while quickly performing the inversion of the stored contents.

In the above-described configuration, the control transistor MN1 and the access transistor MN2 or the control transistor MN3 and the access transistor MN4 are disadvantageous in comparison with the configuration shown in the first embodiment in that the source drain cannot be shared.

However, both the control transistors MN1 and MN3 conduct depending on the logic in the write control line 44 and transfer the logic in the write word line 31 to the gates of the access transistors MN2 and MN4 by these conductions. Therefore, as illustrated in FIG. 17, a modification in which the control transistor MN3 is merged with MN1 is possible, and the required area can be reduced.

Example 4.

18 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted, but may be adopted as each of MC _ij shown in FIG. In the memory cell MC, the control transistors MN1 and MN3 are replaced with the control transistors MN5 and MN6 in comparison with the configuration shown in FIG.

The gates of the control transistors MN5 and MN6 are commonly connected to the write word line 31. The control transistor MN5 is interposed between the write bit line 41 and the gate of the access transistor MN2, and the control transistor MN6 is interposed between the write complementary bit line 42 and the gate of the access transistor MN4. Therefore, similarly to the first embodiment, the conduction between the node N1 and the node N4 and between the node N2 and the node N5 is limited to the case where both the write word line 31 and the write control line 44 are "H". Therefore, in the same manner as in the first embodiment, unnecessary power consumption can be reduced while quickly performing writing for reversing the stored contents.

The above-described configuration is disadvantageous compared with the configuration shown in Embodiment 1 in that the control transistor MN5 and the access transistor MN2 or the control transistor MN6 and the access transistor MN4 cannot share the source drain.

However, both the control transistors MN5 and MN6 conduct depending on the logic in the write word line 31, and transfer the logic in the write control line 44 to the gates of the access transistors MN2 and MN4 by their conduction. Therefore, as illustrated in FIG. 19, the control transistor MN6 may be modified to MN5, and the required area may be reduced.

Example 5.

20 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted, but can be employed as each of MC _ij shown in FIG. However, the write complementary control line 45 is unnecessary. The memory cell MC is mainly different from two in comparison with the configuration shown in FIG.

As a first difference, the transistor QN9 is not directly connected to the node N1, and the pass transistor MN9 is interposed between them. In the same manner, the transistor QN11 is not directly connected to the node N2, and the pass transistor MN11 is interposed between the transistors QN11. As in the first embodiment, the gates of the pass transistors MN9 and MN11 are connected to the write control line 44 at the node N6. Connection points of the transistors QN9 and MN9 are shown as nodes N8, and connection points of the transistors QN11 and MN11 are shown as nodes N9, respectively.

A second upper point, the electric potential (hereinafter also referred to as "transition point V _DD") to provide a potential point V _DD node and all PMOS transistors of the transistor MP3, MP4 between N8 are connected in series. Similarly, transistors MP5 and MP6, which are PMOS transistors, are connected in series between the potential point V _DD and the node N9. In both transistors MP4 and MP6, the potential V _DD is applied to one of the current electrode pairs, and a write complementary word line 34 is connected to the gate thereof. The nodes N8 and N9 are connected to one of the current electrode pairs of the transistors MP3 and MP5, respectively. Others of the current electrode pairs of the transistors MP3 and MP4 are connected in common to each other of the current electrode pairs of the transistors MP5 and MP6. Gates of the transistors MP3 and MP5 are connected to the write bit line 41 and the write complementary bit line 42, respectively.

In the above configuration, since transistors MP3 and MP4 capable of setting node N1 to "H" are provided from outside of storage cell SC, transistors MP5 and MP6 capable of setting node N2 to "H" are provided. Can be performed quickly. Further, the conduction between the nodes N1 and N8 and the conduction between the nodes N2 and N9 all depend on the logic of the write control line 44 by the pass transistors MN9 and MN10, respectively. Therefore, unnecessary power consumption due to the collision of potentials between the node N1 and the write bit line 41 and the node N2 and the write complementary bit line 42 can be reduced.

Transistors MP3, MP4, QN9, QN10 and transistors MP5, MP6, QN11, and QN12 constitute a three-state inverter with nodes N8 and N9 as output terminals, respectively. The operation of the memory cell MC according to the present embodiment will be described below from the viewpoint of the operation of these three-state inverters.

These three-state inverters function as inverters only when the write word line 31 is "H" and therefore the write complementary word line 34 is "L". That is, logic complementary to the logic of the write bit line 41 is provided to the node N8, and logic complementary to the logic of the write complementary bit line 42 is provided to the node N9. In the case where the write word line 31 is "L" and therefore the write complementary word line 34 is "H", the potential of the node N8 is not set depending on the three-state inverter even if the transistors MP3 and QN9 are turned on ( tristate condition). In addition, even if the transistors MP5 and QN11 are turned on, the potential of the node N9 is not set depending on the three-state inverter.

In the word line group 30, i.e., the selected word line group 30, of the row to which the memory cell MC to be written belongs, the potentials of "H" and "L" are respectively applied to the write word line 31 and the write complementary word line 34, respectively. The nodes N8 and N9 are provided with logic complementary to the write bit line 41 and the write complementary bit line 42, respectively. In addition, since the complementary logic is provided to the write bit line 41 and the write complementary bit line 42 in the bit line group 40 of the column to which the memory cell MC to be written, that is, the selected bit line group 40, is written. The logic in the control line 44 becomes " H " so that the pass transistors MN9 and MN11 are conducted. Therefore, the logics complementary to the write bit line 41 and the write complementary bit line 42 are quickly stored in the nodes N1 and N2 even if the storage contents of the storage cell SC are reversed.

In the memory cells MC arranged in the row corresponding to the selected word line group 30, the three-state inverter functions as an inverter. However, in the memory cell MC arranged in the column corresponding to the unselected bit line group 40, since the write bit line 41 and the write complementary bit line 42 are precharged to substantially the same potential, the write control line 44 The logic in is " L ", and the pass transistors MN9 and MN11 are not conductive. Therefore, the node N1 and the write bit line 41 and the node N2 and the write complementary bit line 42 are cut off to reduce unnecessary power consumption due to a potential collision.

In order to avoid voltage drop of the threshold value of the pass transistors MN9 and MN10 due to the substrate effect, these may be replaced with a transmission gate. Alternatively, the potential of the write word line 31 may be boosted by a threshold value to compensate for the substrate effects of the pass transistors MN9 and MN10.

21 is a circuit diagram showing a configuration of the memory cell MC according to the first modification of this embodiment. The arrangement shown in FIG. 20 has a configuration in which the order of series connection of the transistors QN9 and QN10 is replaced and the order of series connection of the transistors QN11 and QN12 is reversed. Naturally, even in such a modification, the effects of the present embodiment can be obtained.

Fig. 22 is a circuit diagram showing the configuration of the memory cell MC according to the second modification of this embodiment. The transistors MP3, MP4, MP5, and MP6 for supplying the logic "H" to the storage cell SC are deleted for the configuration shown in FIG. In addition, the order of the series connection of the pass transistor MN9 and the transistor QN10 and the order of the series connection of the pass transistor MN11 and the transistor QN12 are reversed, respectively.

Or logic in the Compared to the circuit, transistor QN9, QN10 node N1 and potential point V _SS to replace the order of the series connection between and, and the write control line 44, between transistors QN9, QN10 shown in FIG. 53 The pass transistor MN9 through which conduction is controlled is interposed. Similarly, the pass transistor MN11 in which the transistors QN11 and QN12 change the order of series connection between the node N2 and the potential point V _SS , and conduction is controlled by logic in the write control line 44 between the transistors QN11 and QN12. Is interposed.

In this configuration, the "H" cannot be set externally to the storage cell SC. Therefore, it is disadvantageous in that writing to invert contents stored in the storage cell SC cannot be performed quickly. However, there is an advantage that it can be employed as the memory cell MC of the SRAM shown in FIG. 1 without requiring the write complementary word line 34 as compared with the configuration shown in FIG. 20 or FIG. In addition, the potentials of the write bit line 41 and the write complementary bit line 42 of the bit line group 40 that are not selected as compared with the configuration shown in FIG. 53 may be precharged to any of "L" and "H". Is advantageous in

Of course, there are six orders of serial connection of the transistors QN10, MN9, and QN9, and it is natural that the above-described effects can be obtained by employing any of the sequences. The same applies to the procedure of series connection of the transistors QN12, MN11, and QN11.

Fig. 23 is a circuit diagram of a static write cell of the dual write port type according to the third modification of this embodiment. Here, two sets of three-state inverters corresponding to the word line group (except the read complementary word line 32 and the read word line 33) and the bit line group (except the read bit line 43) and the bit line group are provided. have. In the first and second articles, symbols obtained by adding symbols a and b to the end of the symbols employed in FIG. 21 are employed, respectively.

It is natural that such a dual write-port type static memory cell can quickly store memory when the contents of the storage cell SC are inverted and reduce unnecessary power consumption due to potential collisions.

24 is a circuit diagram showing a configuration of the memory cell MC according to the fourth modification of the present embodiment. The configuration of the device interposed between the node N8 and the transistors MP3, QN9 and node N1 as the output stage of the tri-state inverter for the configuration shown in FIG. 21, the node N9 and the transistors MP5, QN11 and node serving as the output stages of the other three-state inverter The structure of the element interposed between N2 is changed.

The node N8 is connected to the transistor MP3 through the PMOS transistor MP9, to the transistor QN9 through the NMOS transistor MN9, and to the memory node N1 through the NMOS transistor QN10. The node N9 is connected to the transistor MP5 through the PMOS transistor MP11, to the transistor QN11 through the NMOS transistor MN11, and to the memory node N2 through the NMOS transistor QN12.

In this modification, the write complementary word line 34 is not employed. Instead, the write complementary control line 45 is employed. The gates of the transistors MP9 and MP11 are connected to the write complementary control line 45 at the node N7, and the gates of the transistors MN9 and MN11 are connected to the write control line 44 at the node N6, respectively. The gates of the transistors QN10 and QN12 are connected to the write word line 31.

In the selected row, the write word line 31 is activated, and the transistors QN10 and QN12 are turned on. Therefore, the nodes N1 and N2 are in communication with the nodes N8 and N9, respectively. Since the write control line 44 and the write complementary control line 45 become "H" and "L" in the selected column, the transistors MP9, MP11, MN9, and MN11 are all turned on. Therefore, data written to the nodes N1 and N2 of the memory cell MC to be written inverts each of the logic provided to the write bit line 41 and the logic provided to the write complementary bit line 42 through the nodes N8 and N9, respectively. Is provided. This is done quickly even when inverting the data stored in the storage cell SC.

In the memory cell MC which is arranged in the selected row but is not a write object (ie, the memory cell MC arranged in the unselected column), the write control line 44 and the write complementary control line 45 are "L" and "H", respectively. The transistors MP9, MP11, MN9, MN11 are all turned off. Nodes N8 and N9 are in a tri-state condition. Therefore, logic is not forcibly set in the nodes N1 and N2 from the outside of the storage cell SC, and it is possible to prevent unnecessary power consumption due to potential collisions.

25 is a circuit diagram showing a configuration of the memory cell MC according to the fifth modification of the present embodiment. This configuration exchanges the sequence of the serial connection of the transistors MP3 and MP9 between the node N8 and the potential point V _DD in the configuration of FIG. 24, and the series connection of the transistors MN9 and QN9 between the node N8 and the potential point V _SS. The order of the series connection of transistors MP5 and MP11 between node N9 and potential point V _DD , and the order of the series connection of transistors MN11 and QN11 between node N9 and potential point V _SS. It has a configuration. Therefore, even in the configuration shown in FIG. 25, there is an effect of quickly writing data and reducing unnecessary power consumption.

Fig. 26 is a circuit diagram showing the configuration of the memory cell MC according to the sixth modification of this embodiment. Also and for the configuration shown in 21 exchange the order of the series connection of the transistors MP3, MP4 between the node N8 and the potential point V _DD, the node N9 to the potential that transistor between the V _DD MP5, the order of series connection of MP6 Are replaced, and the transistors MP4 and MP6 are merged and provided as one transistor. Similarly, the order of series connection of transistors QN9 and QN10 is exchanged between node N8 and potential point V _SS , and the order of series connection of transistors QN11 and QN12 is exchanged between node N9 and potential point V _SS , and the transistor is further replaced. QN10 and QN2 are merged and provided as one transistor. Therefore, compared with the circuit shown in FIG. 21, the number of transistors can be reduced and the area required for obtaining the effect of this embodiment can be made small.

The nodes N8 and N9 are connected to the potential point V _SS in the same connection relationship as the nodes N1 and N2 shown in FIG. However, the transistors MN9 and MN11 are conducted only when the write control line 44 is "H" between the node N8 and the node N1 and between the node N9 and the node N2, respectively. This is suitable even when the potentials of the write bit line 41 and the write complementary bit line 42 of the unselected bit line group 40 are precharged to any of "L" and "H". Therefore, the same effect as in FIG. 21 can be obtained.

FIG. 27 is a circuit diagram showing a configuration in which the configuration shown in FIG. 26 is applied to the memory cells MC _{I1 to} MC _In in the I row. The plurality of memory cells MC _Ij belonging to the same row use the write word line 31 and the write complementary word line 34 in common. Accordingly, the transistor MP4 (or transistor MP6) and the transistor QN10 (or QN12) may be merged into one PMOS transistor MP400 and NMOS transistor QN100 for n memory cells MC _{I1 to} MC _In , respectively. Such merging can further reduce the number of transistors.

Example 6.

In the present embodiment, the configuration shown in the circuit diagram is the same as that of the first to fifth embodiments. The characteristic feature in this embodiment is that the MOSFET constituting the memory cell MC is formed on a semiconductor on insulator or silicon on insulator (SOI) substrate.

First, the problem in the case where the MOSFET constituting the conventional memory cell MC is formed on the SOI substrate will be described. FIG. 28 is a cross-sectional view illustrating the configuration when the access transistor QN4 shown in FIG. 52 is formed as a MOS transistor on an SOI substrate.

The semiconductor substrate 91, the buried oxide film 92, and the SOI substrate 93 are stacked in this order. An insulating separator 94 is optionally embedded in the SOI substrate 93. The SOI substrate 93 is connected to the nodes N2 and N5, respectively, and is interposed between the n-type drain 93a, the source 93b, the drain 93a and the source 93b, and the P-type channel region 93c. Separated by. A pn junction J11 is formed between the source 93b and the channel region 93c, and a pn junction J12 is formed between the drain 93a and the channel region 93c, respectively. The gate electrode 98 is provided to face the channel region 93c via the gate insulating film 95, and the top and side surfaces thereof are covered with the insulating film 96. The side wall 97 is provided to face the side of the gate electrode 98 through the insulating film 96. The gate electrode 98 is formed by stacking doped polysilicon 98a, tungsten nitride film 98b, and tungsten 98c sequentially from the side closest to the gate insulating film 95. As shown in FIG. In this configuration, since the insulating separator 94 insulates the SOI substrate 93 from the surroundings, unless the mechanism for fixing the potential of the channel region 93c is provided separately, the access transistor Q4 is usually in a state of a so-called floating body. Is in.

As the memory cell MC having the structure shown in FIG. 52, two memory cells MC _xj and MC _yj all belonging to the jth column are assumed. So-called when "L" and "H" are written into the nodes N1 and N2 of the memory cell MC _xj , respectively, and then "H" and "L" are written into the nodes N1 and N2 of the memory cell MC _yj , respectively. Consider half-select write disturb.

Writing after operation termination of the memory cell MC _xj is the write word line (31 _x) is "L", because the write word line (31 _x) in the writing operation to the memory cell MC _yj is "L" state, the access transistor QN4 In the source 93b, the channel region 93c, and the drain 93a constitute a horizontal parasitic bipolar transistor, and function as an emitter / base / collector, respectively.

After the memory cell MC writing operation end of _xj, write bit lines (41 _j), the write complementary bit line (42 _j) are all so precharged to "H", the memory cell MC _xj of the access transistor QN4 is in a non-state The state where the source 93b and the drain 93a are "H" is maintained. Since the channel region 93c is in a floating state in the P-type, holes (typically indicated by + in the drawing) are thermally accumulated therein.

In this state, when " H " is precharged to the write bit line 41 _j and " L " is respectively written to the write complementary bit line 42 _j for the write operation to the memory cell MC _yj , access of the memory cell MC _xj is performed. The pn junction J11 of the transistor QN4 becomes forward bias. Therefore, electrons are injected from the source 93b into the channel region 93c, and holes accumulated in the channel region 93c are discharged. At this time, the current I1 flowing through the pn junction J11 functions as an effective base current of the parasitic bipolar transistor described above. Therefore, a spike current I2 flowing from the drain 93a to the channel region 93c is caused. In particular, when the time to writing to the memory cell MC _yj is long, the amount of holes that are thermally accumulated increases and the current I2 is also large. In that case, the electric charge stored in the node N2 is discharged, the potential thereof is lowered from " H " to " L &quot;, and the contents of the memory cell MC _xj may be reversed.

However, when the circuit configuration of the present invention is adopted, the above problem can be avoided. For example, in the configuration shown in Fig. 2, the logic of the write complementary bit line 42 is written to the node N2 through the transistors MN11 and MN12. In general, the wiring connecting the transistors MN11 and MN12 to each other is very short as compared with the write complementary bit line 42. Therefore, compared with the access transistor QN4 of the memory cell MC having the structure shown in FIG. 35, in the transistor MN11, the parasitic capacitance connected to the side closer to the write complementary bit line 42 (for example, the source) of the current electrode pair is smaller. This is further the case when the impurity regions are shared as shown in FIG. Therefore, even if the transistor MN11 is the SOIFET shown in Fig. 28, the parasitic bipolar transistor does not operate sufficiently. Therefore, by adopting the circuit configuration of this embodiment, the probability of occurrence of half-select write disturb can be reduced.

Further, the potential corresponding to logic "L" in the unselected write word line 31 is lower than the potential corresponding to logic "L" in the write complementary bit line 42, for example, V _SS -0.3 It is also preferable to set it as about Vb- _VSS- Vb. Here, Vb is a built-in voltage formed by the drain 93a and the channel region 93c. By providing this potential to the unselected write word line 31, the forward bias at the pn junction J11 can be reduced while avoiding accumulation in the channel region 93c. This setting of the potential of the write word line 31 is particularly effective in the circuit configuration shown in FIG. This is because the current electrode pair of the transistor MN4 is connected to the nodes N2 and N5 and is the same as the transistor QN4 shown in FIG. 52 from the viewpoint of parasitic capacitance.

Of course, the half-select write disturb may be avoided by employing a configuration in which the potential of the channel region 93c is fixed.

In the above-described embodiment, the dual port static memory cell has been described as an example, but of course, it can be applied to a multiport static memory cell.

Example 7.

In the first to sixth embodiments, the write operation is allowed by the activation of the write control line 44 as well as the write word line 31, thereby obtaining a predetermined effect. However, in order to determine the logic of the write control line 44, even if the potential V _SS , V _DD , or the potential (V _DD + V _SS ) / 2 is precharged, the write bit line 41 and the write complementary bit line ( It is necessary to determine the potential of 42). In other words, if the write bit line 41 and the write complementary bit line 42 are allowed to be in a floating state, the potential of the write control line 44 may not be determined. In addition, even when the write bit line 41 and the write complementary bit line 42 are in a floating state, the write bit line 41 belongs to the same row as the memory cell to be subjected to the write operation and belongs to another column. In addition, there is a possibility that power consumption may occur as the storage cell SC charges and discharges the write complementary bit line 42.

In particular, the storage cell SC writes when there are a plurality of write and read passes in each cell, such as a multiport SRAM, for example, a dual port SRAM, and the writing and reading of binary information can be performed independently and asynchronously. In addition to the bit line 41 and the write complementary bit line 42, the read bit line 43 is also driven in parallel.

Fig. 54 is a block diagram showing a connection between a dual port SRAM 80 including first and second ports, one of which becomes a write port and the other of which is a read port, and an apparatus for controlling the operation thereof. . The first microprocessor 81 performs write and read operations using the first port of the dual port SRAM 80 through the first read / write control circuit 82. On the other hand, the second microprocessor 84 performs write and read operations using the second port of the dual port SRAM 80 through the second read / write control circuit 83.

FIG. 29 is a circuit diagram illustrating a configuration of a memory cell MC that can be employed in the dual port SRAM 80. In comparison with the configuration shown in Fig. 52, access transistors QN13 and QN14, which are all NMOS transistors, are provided in place of the read circuit RK. The access transistor QN13 is interposed between the node N1 and the read bit line 43, and the gate thereof is connected to the read word line 33. The access transistor QN14 is interposed between the node N2 and the read complementary bit line 46, and the gate thereof is connected to the read word line 33.

The configuration illustrated in FIG. 29 includes an advantage of reducing two transistors per memory cell MC compared with the configuration illustrated in FIG. 52. However, when the transistors QN13 and QN14 are turned on, the storage cell SC uses the read bit line 43 and the read complementary bit line 46 each having a larger capacitance than the gates of the transistors QP3 and QN6 of the read circuit RK. Charged and discharged at N10. Therefore, the write operation by the first read / write control circuit 82 and the second read / write control circuit 83 respectively for the memory cells MC _ix and MC _iy (x ≠ y) arranged in the i-th row, respectively. In the case where the read operation by () is performed in parallel, there is a period in which the write word line 31 _i and the read word line 33 _i become " H " simultaneously. In this period, the storage cell SC of the memory cell MC _iy drives not only the read bit line 43 and the read complementary bit line 46, but also the write bit line 41 and the write complementary bit line 42, so that the read operation is performed. This may be delayed.

30 is a conceptual diagram showing the configuration around the memory cell array of the SRAM according to the seventh embodiment of the present invention. Compared with the configuration shown in Fig. 1, the write control line 44 is replaced with the read complementary bit line 46, and the read complementary word line 32 is omitted.

FIG. 31 is a circuit diagram illustrating one configuration of the memory cell MC shown in FIG. 30. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted. The memory cell MC has a structure including transistors QN15, QN16, QN17, and QN18 of all NMOS transistors instead of the transistors QN3 and QN4 in the configuration shown in FIG. Of course, the read complementary word line 32 may also be used to employ the read circuit RK in place of the transistors QN13 and QN14 in the memory cell MC. However, this embodiment is particularly in the case where the nodes N1 and N2, as described above, are not gates of transistors and include a read mechanism capable of charging and discharging the read bit line 43 and the read complementary bit line 46. effective.

A potential V _SS is supplied to one of the current electrode pairs of the transistor QN17, for example, a source, and a node N2 is connected to the other of the current electrode pairs, for example, a drain. A potential V _SS is supplied to one of the current electrode pairs of the transistor QN18, for example, a source, and a node N1 is connected to the other of the current electrode pairs, for example, a drain.

One of the current electrode pairs of the transistor QN15, for example, the source, is connected to the write bit line 41 at the node N4, and the other side of the current electrode pair, for example, the drain, is connected to the gate of the transistor QN17. The write complementary bit line 42 is connected to one of the current electrode pairs of the transistor QN16, for example, the source, and the gate of the transistor QN18 is connected to the other, for example, drain, of the current electrode pair. The gates of the transistors QN15 and QN16 are both connected to the write word line 31.

In the write operation in this configuration, first, the potential corresponding to the logic to be provided to the nodes N1 and N2 is precharged to the write bit line 41 and the write complementary bit line 42, respectively. For example, the potentials V _DD and V _SS are provided to the write bit line 41 and the write complementary bit line 42 respectively corresponding to "H" and "L". After that, the write word line 31 is activated, and the transistors QN15 and QN16 are turned on, and the potentials V _DD -V _thn and V _SS are applied to the gates of the transistors QN17 and QN18, respectively (although the threshold voltage of the transistor QN15 is applied). With V _thn > 0). As a result, the transistors QN17 and QN18 are turned on and off, respectively. Since the transistor QN17 is turned on, the potential V _SS is transferred to the node N2. Therefore, the logic "H" is stored in the node N1 in accordance with the function of the inverter L1.

Thereafter, both the write bit line 41 and the write complementary bit line 42 are set to the potential V _{SS so} that the gates of the transistors QN17 and QN18 become "L", and these are turned off. After that, the write word line 31 is deactivated to become " L &quot;, and the transistors QN15 and QN16 are turned off, and the gates of the transistors QN17 and QN18 are made floating.

In the read operation, the transistors QN13 and QN14 are turned on by the read word line 33 being activated, and the logics stored in the nodes N1 and N2 are read bit lines 43 and read complementary bit lines 46 at the nodes N3 and N10, respectively. Is passed to. Precharging is preferably performed prior to activation of the read word line 33 to speed up the read speed.

In the above configuration, electric charge is not supplied from the write bit line 41 and the write complementary bit line 42 to the storage cell SC in the write operation, and the potential V _SS is provided only to one of the nodes N1 and N2. That is, there is no path in which charge directly moves between the write bit line 41 and the write complementary bit line 42 and the nodes N1 and N2. Therefore, even when the write word line 31 is activated and the write bit line 41 and the write complementary bit line 42 are in a floating state, they are not charged or discharged by the storage cell SC and unnecessary power is not consumed. . Therefore, even if there is a period in which the write word line 31 and the read word line 33 become " H " simultaneously, the read operation is not delayed.

At the end of the above-described write operation, the procedures for turning off the transistors QN15 and QN16 after the transistors QN17 and QN18 are turned off have been described. However, on the contrary, it is also possible to turn off the transistors QN17 and QN18 after the transistors QN15 and QN16 are turned off. In this case, since each gate transitions to a floating state when either one of the transistors QN17 and QN18 is on, there is an effect of backing up the information of the storage cell SC. For example, a soft error in which contents stored in the storage cell SC are reversed due to irradiation of a spacecraft such as neutron beams can be considered. Therefore, by backing up the information of the storage cell SC, the threshold amount of charge required for soft error can be increased, that is, it is difficult to produce soft error.

32 is a circuit diagram showing a variation of the present embodiment. The write word line 31 is replaced with the write complementary word line 34, and the transistors QN15 and QN16 are all replaced with the PMOS transistors QP15 and QP16.

This configuration also has the same effect as the configuration shown in FIG. 31 in that the logic is propagated. However, when " H " is provided to the gates of the transistors QN17 and QN18, it is possible to avoid the potential drop only at the threshold voltage V _thn (> 0).

On the other hand, when the threshold voltages of the PMOS transistors QP15 and QP16 are set to V _thp (<0), when "L" is provided to the gates of the transistors QN17 and QN18, the potential rises to V _SS -V _thp . Therefore, the configuration shown in FIG. 31 is advantageous in that the transistors QN17 and QN18 are surely turned off and the leakage current from the nodes N1 and N2 to the potential point V _SS is suppressed.

33 is a circuit diagram showing still another modification of the present embodiment. Both the write word line 31 and the write complementary word line 34 are employed, and a transmission gate according to the parallel connection of the transistors QP15 and QN15 is connected between the node N4 and the gate of the transistor QN17, and the node N5 and the transistor QN18 are connected. The transmission gate according to the parallel connection of transistors QP16 and QN16 is connected between the gates. The gates of the PMOS transistors QP15, QP16 are connected to the write complementary word line 34, and the gates of the NMOS transistors QN15, QN16 are connected to the write word line 31, respectively.

According to this configuration, it is possible to accurately control the on / off of the transistors QN17 and QN18.

Example 8.

34 is a circuit diagram illustrating the configuration of one memory cell MC according to the present embodiment. As in the prior art, subscripts indicating the position of the row and the position of the column are omitted, but can be employed as each of MC _ij shown in FIG.

The memory cell MC is characteristically different from the configuration of the storage cell SC compared with the configuration shown in FIG. 53. In short, the storage cell SC does not have the transistors QN1 and QN2 but is constituted by the cross coupling of the transistors QP1 and QP2.

More specifically, the memory node N2 is connected to the potential point V _SS only through the series connection of the transistors QN9 and QN10. The gates of the transistors QN9 and QN10 are connected to the write bit line 41 and the write word line 31, respectively, and conduction is controlled in accordance with these logics. Similarly, the memory node N1 is connected to the potential point V _SS only through the series connection of the transistors QN11 and QN12. The gates of the transistors QN11 and QN12 are connected to the write complementary bit line 42 and the write word line 31, respectively, and conduction is controlled by these logics.

In addition, the configuration for reading out from the storage nodes N1 and N2 of the storage cell SC is different from that shown in FIG. In other words, the transistors QN13 and QN14 shown in the seventh embodiment are used instead of the read circuit RK. When the read word line 33 is activated, the transistors QN13 and QN14 are turned on, and the logic stored at the nodes N1 and N2 is transferred to the read bit line 43 and the read complementary bit line 46 at the nodes N3 and N10, respectively. . In order to increase the read speed, it is preferable that the precharge of the read bit line 43 and the read complementary bit line 46 is performed prior to the activation of the read word line 33.

35 is an example of a timing chart illustrating an operation of the memory cell MC shown in FIG. 34. 35 (a), (b), (c), (d), and (e) show read word lines 33, read complementary bit lines 46, write word lines 31, and write bit lines ( 41) the potential of the storage node N2 is shown. Here, the case where "L" is written into the storage node N2 stored as "H" is illustrated.

Before the time t ₁ is standby, the read complementary bit line 46 is precharged to the potential V _SS together with the read bit line 43 at the potential V _SS as in the solid line or at the potential (V _DD + V _SS ) / 2 as the broken line. It is. Then, at time t ₁ , the read complementary bit line 46 is precharged to the potential (V _DD + V _SS ) / 2 together with the read bit line 43. Thereafter, the read word line 33 starts the transition to the potential V _DD at time t ₂ , and the transistor QN14 is turned on together with the transistor QN13 at the time of the transition. Accordingly, at time t ₃ , the read complementary bit line 46 starts to transition to the potential V _DD due to the logic " H " stored in the storage node N2. Then, at time t ₄ the read word line 33 is the potential V _SS to the start of the transition, and also the write bit line 41 at the time t after ₅ initiates a transition to the potential V _DD. The transistor QN9 is turned on in response to the transition. After that, at time t ₆ , the write word line 31 also starts the transition to the potential V _DD , and the transistor QN10 is also turned on due to the transition. As a result, the storage node N2 is connected to the potential point V _SS through the transistors QN9 and QN10, and the potential of the storage node N2 starts to transition from the potential V _DD to the potential V _SS at time t7. Thereafter, the write word line 31 transitions to the potential V _SS for a standby operation, and the write bit line 41 also transitions to the potential V _SS .

Of course, the case where "L" is written in the state where "L" is stored in the memory node N2 is similarly realized by being connected to the potential point V _SS through the transistors QN9 and QN10. When L "is written, the transistor QP1 is turned on, and the memory node N1 is connected to the potential point V _DD , thereby writing" H ".

In this embodiment as well, according to the seventh embodiment, there is no path for direct transfer of charge between the write bit line 41 and the write complementary bit line 42 and the nodes N1 and N2. Therefore, even when the write word line 31 is activated and the write bit line 41 and the write complementary bit line 42 are in a floating state, they are not charged or discharged by the storage cell SC and unnecessary power is not consumed. Therefore, even if there is a period in which the write word line 31 and the read word line 33 become " H " simultaneously, the read operation is not delayed.

In addition, since the number of transistors is small as compared with the configuration shown in FIG. 53, the area of two transistors per storage cell can be reduced. In addition, the inverters L1 and L2 are designed to have a high static noise margin in order to stably hold information, and it takes time to invert the stored contents. However, in the structure of this embodiment, since the memory is held by the cross coupling of the transistors, the writing operation can be performed at high speed.

In addition, in the memory cell having the configuration of the present embodiment, half-select write disturb can be avoided. 36 is a circuit diagram showing a part of the configuration in which memory cells MC having the structure shown in FIG. 34 are arranged in a matrix. And the memory cell MC _xj belonging to the j th column as the x th row, the memory cell MC _xz belonging to the z th column as the x th row, and the memory cell belonging to the j th column as the y th row. MC _yj is extracted and drawn.

First, _suppose that information is written into the storage node N1 of the memory cell MC _xj . When the write word line 31 _x becomes "H" when the write bit line 41 _j and the write complementary bit line 42 _j are "H" and "L", the transistors QN9, of the memory cell MC _xj , The potential V _SS is provided to the storage node N2 via QN10. At this time, the transistor QN11 of the memory cell MC _xj is turned off. In addition, since the potential V _SS is provided to the memory node N2, the transistor QP1 of the memory cell MC _x j is turned on, and the potential V _DD is provided to the memory node N1.

At this time, the transistors QN10 and QN12 of the memory cell MC _xz also turn on as the write word line 31 _x becomes " H &quot;. But it can both write bit line (41 _z), the write complementary bit line (42 _z) for all the potential V _SS to the precharge transistors QN9 and QN11 off, the memory cell MC according to the _xz placing it in a standby state. Therefore, the stored contents of the memory cell MC _xz are not rewritten.

The transistor QN9 of the memory cell MC _yj is also turned on as the write bit line 41 _j becomes " H &quot;. However, since the write word line 31 _y is not selected, it is " L &quot;, so that the transistors QN10 and QN12 of the memory cell MC _yj can be turned off. Therefore, the memory contents of the memory cell MC _yj are not rewritten. From the above, half-select write disturb can be avoided.

37 is a circuit diagram showing a configuration of the memory cell according to the first modification of this embodiment. In the memory cell, the write complementary word line 34 is employed instead of the write word line 31 in the configuration shown in FIG. NMOS transistors QN10 and QN12 are replaced with PMOS transistors QP10 and QP12, respectively. Since the logic complementary to the write word line 31 is provided to the write complementary word line 34 in the write operation, it relates to the logic provided to the write word line 31 and the write complementary word line 34. QP12 has the same operation as that of the NMOS transistors QN10 and QN12. Therefore, the configuration shown in FIG. 37 can have the same effect as the configuration shown in FIG. 34.

38 is a circuit diagram showing a configuration of the memory cell according to the second modification of the present embodiment. In the memory cell, the NMOS transistors QN9 and QN11 are replaced with the PMOS transistors QP11 and QP9 in the configuration shown in FIG. A write bit line 41 and a write complementary bit line 42 are connected to the gates of the PMOS transistors QP9 and QP11, respectively. Since the write bit line 41 and the write complementary bit line 42 are provided with complementary logics in the write operation, the PMOS transistors QP9 and QP11 are provided to the write bit line 41 and the write complementary bit line 42. The same operation as in the NMOS transistors QN11 and QN9 is performed. Therefore, the configuration shown in FIG. 38 can have the same effect as the configuration shown in FIG.

39 is a circuit diagram showing a configuration of the memory cell according to the third modification of this embodiment. The memory cell has a configuration shown in Fig. 34 and a configuration in which the high potential side and the low potential side are replaced. That is, the memory node N2 is connected to the potential point V _DD only through the series connection of the transistors QP11 and QP10. The gates of the transistors QP11 and QP10 are connected to the write bit line 41 and the write complementary word line 34, respectively, and conduction is controlled in accordance with their logic. Similarly, the memory node N1 is connected to the potential point V _DD only through the series connection of the transistors QP9 and QN12. The gates of the transistors QP9 and QP12 are connected to the write complementary bit line 42 and the write complementary word line 34, respectively, and conduction is controlled by these logics. It is clear that even in such a configuration, the same effect as that shown in FIG. 34 can be obtained.

40 is a circuit diagram showing a configuration of the memory cell according to the fourth modification of the present embodiment. In the memory cell, the write word line 31 is employed instead of the write complementary word line 34 in the configuration shown in FIG. The PMOS transistors QP10 and QP12 are replaced with the NMOS transistors QN10 and QN12, respectively. Since the logic complementary to the write word line 31 is provided to the write complementary word line 34 in the write operation, the NMOS transistor QN10 relates to the logic provided to the write word line 31 and the write complementary word line 34. , QN12 has the same operation as PMOS transistors QP10 and QP12. Therefore, the configuration shown in FIG. 40 can have the same effect as the configuration shown in FIG. 39.

Fig. 41 is a circuit diagram showing the configuration of the memory cell according to the fifth modification of this embodiment. In the memory cell, the PMOS transistors QP9 and QP11 are replaced with the NMOS transistors QN11 and QN9 in the configuration shown in FIG. A write bit line 41 and a write complementary bit line 42 are connected to the gates of the NMOS transistors QN11 and QN9, respectively. Since the write bit line 41 and the write complementary bit line 42 are provided with complementary logics in the write operation, the NMOS transistors QN9 and QN11 are provided with the write bit line 41 and the write complementary bit line 42. The same operation as that of the PMOS transistors QP11 and QP9 is performed. Therefore, the same effect as that shown in FIG. 39 can also be obtained.

Fig. 42 is a circuit diagram showing the configuration of the memory cell according to the sixth modification of this embodiment. In the configuration shown in Fig. 34, the cell has a configuration in which transistor QN12 is also used in transistor QN10. 43 is a circuit diagram showing the configuration of the memory cell according to the seventh modification of the present embodiment. In the configuration shown in Fig. 39, the cell has a configuration in which transistor QP12 is combined with transistor QP10. Sixth and Seventh strains, two transistors per memory cell are merged to reduce the number of transistors by one. Thereby, the effect of this embodiment can be obtained while reducing the occupied area of the memory cell.

FIG. 44 is a circuit diagram illustrating a configuration in which the configuration shown in FIG. 42 is applied to the memory cells MC _{i1 to} MC _in in the i-th row. The plurality of memory cells MC _ij belonging to the same row use the write word line 31 in common. Therefore, the transistor QN10 (or QN12) can be merged into one NMOS transistor QN100 for the n memory cells MC _{i1 to} MC _in . FIG. 45 is a circuit diagram illustrating a configuration in which the configuration shown in FIG. 43 is applied to the memory cells MC _{i1 to} MC _in in the i-th row. The plurality of memory cells MC _ij belonging to the same row use the write complementary word line 34 in common. Therefore, the transistor QP10 (or QP12) can be merged into one PMOS transistor QP100 for the n memory cells MC _{i1 to} MC _in . Such merging can further reduce the number of transistors.

The transistor shown in this embodiment may be formed using a silicon substrate, or may be formed using a known SOI substrate or a silicon on nothing (SON) substrate.

Example 9.

46 is a circuit diagram illustrating one configuration of the memory cell MC according to the present embodiment. As in the prior art, the subscripts indicating the position of the row and the position of the column are omitted, but can be employed as each of MC _ij shown in FIG. However, the read circuit is omitted.

The memory cell MC shown in FIG. 46 is characteristically different in that the storage cell SC is composed of a pair of transistors cross-coupled with respect to the configuration shown in FIG. 10. That is, the drain of the transistor QN1 and the gate of the transistor QN2 are commonly connected to the memory node N1, the gate of the transistor QN1 and the drain of the transistor QN2 are connected in common to the memory node N2, and are common to the sources of the transistors QN1 and QN2. The potential point V _SS is connected.

By constructing the storage cell SC with a pair of cross-coupled transistors rather than a pair of cross-coupled inverters, an area of two transistors per storage cell can be reduced. In addition, there is no case in which a design having a high static noise margin is performed like the inverters L1 and L2, and the writing operation can be performed at high speed.

The transistors MN9 and MN10 are connected in series between the memory node N1 and the write bit line 41, and the transistors MN11 and MN12 are connected in series between the memory node N2 and the write complementary bit line 42. The transistors MN9 and MN11 are both NMOS transistors and are common to their gates, and the write control line 44 is connected to them. The transistors MN10 and MN12 are both NMOS transistors and have a write word line 31 connected to their gates in common.

Therefore, the transistors MN10 and MN12 of each of the memory cells having the write word line 31 of the selected row are conductive. However, the transistors MN9 and MN11 of each of the memory cells in the unselected rows are not conductive. In contrast, the transistors MN9 and MN11 of each of the memory cells having the write control line 44 in the selected column are conductive. However, the transistors MN10 and MN12 of each of the memory cells in the unselected rows do not conduct. Therefore, half-select write disturb can be avoided.

47 to 49 are circuit diagrams showing modifications of the present embodiment. The configuration shown in FIG. 47 replaces the configuration in which the write control line 44 is replaced by the write complementary control line 45 and the NMOS transistors MN9 and MN11 are replaced with the PMOS transistors MP9 and MP11, respectively. Have Since the write complementary control line 45 is provided with logic complementary to the write control line 44, it is apparent that the configuration shown in FIG. 47 performs the same operation as the configuration shown in FIG.

The configuration shown in FIG. 48 replaces the configuration in which the write word line 31 is replaced with the write complementary word line 34, and the NMOS transistors MN10 and MN12 are replaced with the PMOS transistors MP10 and MP12, respectively. Have Since the logic complementary to the write word line 31 is provided to the write complementary word line 34 in the write operation, the write complementary word line 34 relates to the logic provided to the write word line 31 and the write complementary word line 34. MP12 performs the same operation as the NMOS transistors MN10 and MN12. Therefore, the configuration shown in FIG. 48 can have the same effect as the configuration shown in FIG.

The configuration shown in FIG. 49 replaces the configuration in which the write control line 44 is replaced with the write complementary control line 45 and the NMOS transistors MN9 and MN11 are replaced with the PMOS transistors MP9 and MP11, respectively. Have It is apparent that the configuration shown in FIG. 49 operates similarly to the configuration shown in FIG. 46.

50 is a circuit diagram showing another modification of the present embodiment. In the configuration shown in Fig. 49, only the configuration of the storage cell SC is different. In FIG. 50, the pair of cross-coupled transistors is the PMOS transistors QP1 and QP2. That is, the drain of the transistor QP1 and the gate of the transistor QP2 are commonly connected to the memory node N1, and the gate of the transistor QP1 and the drain of the transistor QP2 are connected in common to the memory node N2, and common to the sources of the transistors QP1 and QP2. The potential point V _DD is connected. It is apparent that the configuration shown in FIG. 50 operates similarly to the configuration shown in FIG. 46.

In the configuration shown in Fig. 46, since the memory cells MC are all composed of NMOS transistors, there is no need to provide an isolation region between the PMOS transistors and the NMOS transistors, so that the occupied area of the memory cells MC can be reduced. In the configuration shown in Fig. 50, since the memory cells MC are all composed of PMOS transistors, the area occupied by the memory cells MC can be made smaller in the same manner.

In the configuration shown in Fig. 46, when the potential V _SS is provided with the logic provided to the write bit line 41 at " L &quot;, the thresholds of the NMOS transistors MN9 and MN10 are not a problem, and the potential V _SS is stored at the storage node N1. Is provided. However, in the case where the potential provided by the write bit line 41 is "H" and the potential V _DD is provided, the threshold voltages of the NMOS transistors MN9 and MN10 are set to V _thn (> 0), and the potential (V _DD -2V is applied to the storage node N1). _thn ) is provided. Therefore, when writing to the storage node N1 with "H", the stability of the storage cell SC is slower than when writing with "L".

49 and 50, when the potential V _DD is provided to the write bit line 41, the thresholds of the PMOS transistors MP9 and MP10 do not matter, and the potential V _DD is provided to the storage node N1. However, when the potential V _SS is provided to the write bit line 41, the threshold voltages of the PMOS transistors MP9 and MP10 are set to V _thp (<0), and the potential V _SS -2V _thp is provided to the storage node N1. Therefore, when "L" is written to the storage node N1, the stability of the storage cell SC is slower than when "H" is written.

On the other hand, in the configuration shown in Fig. 47, when the potential V _DD is provided to the write bit line 41, there is no reduction of the threshold value in the PMOS transistor MP9, and the potential V _DD -V _thn is provided to the storage node N1. . On the contrary, when the potential V _SS is provided to the write bit line 41, there is no decrease of the threshold value in the NMOS transistor MN10, and the potential V _SS -V _thp is provided to the storage node N1. Therefore, the worst value (maximum value) of time required for stabilization of the storage cell SC can be made smaller than the configuration shown in FIG. 49 or FIG. This also applies to the configuration shown in FIG.

Although all the description of the present embodiment has been described with respect to the write circuit, it is obvious that they can be employed for the read circuit. That is, the write word line 31, the write complementary word line 34, the write bit line 41, and the write complementary bit line 42 are respectively read word lines 33, read complementary word lines 32, and read bit lines. (43) may be written to the read complementary bit line 46. The write control line 44 and the write complementary control line 45 may be rewritten to the read control line and the read complementary control line, respectively.

Here, the read control line is provided with a signal that is activated (e.g., "H") at the time of reading and deactivated (e.g., "L" at the time of standby, and the read complementary control line is logic complementary to the read control line at the time of reading. A signal that employs is provided. As a signal provided to the read control line, a logical exclusive sum of the logic provided to the read word line 33 and the logic provided to the read complementary word line 32 can be employed.

Of course, word line pairs and bit line pairs may be employed for both reading and writing. This embodiment can be applied to any type of multi-port and single port.

The transistor shown in this embodiment may be formed using a silicon substrate, or may be formed using a known SOI substrate or a silicon on nothing (SON) substrate.

According to the memory device of the present invention, during the write operation, since both the write word line and the write control line are activated in the memory cell to be written, the first memory node is connected to the write bit line through the first switch. Therefore, the time required for inverting the logic stored in the first storage node is short regardless of the logic provided in the write bit line. On the other hand, since the write control line is not activated in the memory cell that is not the write target, the first switch does not connect the first memory node to the write bit line. Therefore, unnecessary power consumption in such a memory cell can be reduced.

According to the storage device of the present invention, in the unselected bit line group, the write bit line and the write complementary bit line are precharged. Since this precharge normally sets the write bit line and the write complementary bit line to the same potential, the write control line can be deactivated by adopting the exclusive logical sum of both.

According to the storage device of the present invention, even when the potential provided by the write bit line and the write complementary bit line at the precharge is in the middle of two potentials corresponding to complementary logic, an exclusive logical sum can be obtained accurately.

According to the storage device of the present invention, the first switch can be realized by the first and second transistors.

According to the memory device of the present invention, it is possible to avoid the situation that the potential provided to the first memory node is lowered by the threshold of the first and second transistors than the potential provided to the write bit line. Thus, a circuit for boosting the potential of the write word line is unnecessary.

According to the storage device of the present invention, the first switch can be realized in a small area.

According to the memory device of the present invention, during the write operation, both the write word line and the write control line are activated in the memory cell to be written. In that case, the first storage node is provided with logic complementary to that of the write bit line. However, since the write control line is not activated in the memory cells that are not subject to writing, the first potential setting section does not set logic for the first memory node. Therefore, unnecessary power consumption in the memory cell can be reduced.

According to the memory device of the present invention, even when the second transistor is formed on the SOI substrate, since the effective base current can be prevented from flowing between the first current electrode and the body when the write word line is inactive, so-called half-select write It can eliminate disturbance.

According to the memory device of the present invention, when the write word line is activated, control of opening and closing of the switch is performed by logic provided to the write bit line, and conduction / non-conduction between the first memory node and the first potential point is controlled. Therefore, there is no path for direct charge transfer between the first memory node and the write bit line. Therefore, the storage cell does not charge / discharge the write bit line in the memory cell that is the object of the write operation or the memory cell in which the memory cell is the object of the write operation and the write word line, so that there is no unnecessary power consumption. Further, even when a read operation is performed in a memory cell which is the object of a write operation and a memory cell in which the write word line is common, the operation can be performed quickly.

According to the memory device of the present invention, it is possible to accurately control the on / off of the first transistor.

According to the memory device of the present invention, there is no path for direct charge transfer between the memory node and the write bit line. Therefore, in the memory cell to be subjected to the write operation or the memory cell to which the memory cell to be written and the write word line are common, the storage cell does not charge and discharge the write bit line, and there is no unnecessary power consumption. Since the storage cell is formed by cross coupling of the third transistor and the fourth transistor, two transistors per storage cell and area can be reduced as compared with the case of employing a cross-coupled inverter. Also, the write operation can be performed at high speed.

According to the storage device of the present invention, the area of two transistors per storage cell can be reduced, and the write operation can be performed at high speed, compared with the case where the storage cell is constituted by a crosslinked inverter.

According to the memory device of the present invention, the worst value (maximum value) of the time required for stabilization of the storage cell can be reduced as compared with the case where the conductivity types of the first transistor and the second transistor are the same.

Claims (3)

In the memory device, (a) each (a-1) Write word line A plurality of word line groups having: (b) each (b-1) the write bit line; (b-2) a write control line provided corresponding to the write bit line; A plurality of bit line groups having: (c) corresponding to one word line group and one bit line group, respectively, (c-1) a storage cell including a first storage node; (c-2) The write word line of the corresponding one word line group and the write control line are both activated between the write bit line of the corresponding one bit line group and the first memory node. First switch conducting only in one case A plurality of memory cells having Including, The write control line in the selected bit line group is activated, And the write control line in the unselected bit line group is not activated. In the memory device, (a) each (a-1) Write word line A plurality of word line groups having: (b) each (b-1) the write bit line; (b-2) a write control line provided corresponding to the write bit line A plurality of bit line groups having: (c) corresponding to one word line group and one bit line group, respectively, (c-1) a storage cell including a first storage node; (c-2) In the write bit line of the one bit line group corresponding to the first memory node only when both the write word line of the corresponding one word line group and the write control line are activated. A first potential setting section providing logic complementary to the logic of A plurality of memory cells having Including, The write control line in the selected bit line group is activated, And the write control line in the unselected bit line group is not activated. In the memory device, (a) each (a-1) Write word line A plurality of word line groups having: (b) each (b-1) Write bit line A plurality of bit line groups having: (c) corresponding to one word line group and one bit line group, respectively, (c-1) a storage cell including a first storage node; (c-2) a switch connected between the first memory node and a first potential point for supplying a first potential corresponding to the first logic; (c-3) A control element that permits opening and closing control of the switch in accordance with logic provided to the write bit line of the corresponding one bit line group when the write word line of the corresponding one word line group is activated. A plurality of memory cells having Memory comprising a.