JP4738182B2 - Thin film capacitor - Google Patents

Description

  The present invention relates to a capacitor in which a dielectric layer is sandwiched between a lower electrode layer and an upper electrode layer, and more particularly to a capacitor having reduced electrical resistance and excellent electrical characteristics.

Background F technology

  Conventionally, a thin film capacitor is known in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially formed on a support substrate, and the dielectric layer is sandwiched between the lower electrode layer and the upper electrode layer (for example, Patent Documents). 1). In the thin film capacitor having such a structure, a thin film capacitor having a structure in which two capacitors are electrically connected in series by a common lower electrode layer has been proposed (see, for example, Patent Document 2). The structure of such a conventional thin film capacitor will be described below.

  FIG. 22 is a principal cross-sectional view showing an example of a thin film capacitor having a structure in which two capacitors are electrically connected in series by a conventional common lower electrode layer, and FIG. 23 is a plan view thereof. In the thin film capacitor shown in FIG. 22, there are two capacitors configured by sequentially laminating a lower electrode layer 2, a dielectric layer 3 a and a dielectric layer 3 b, an upper electrode layer 4 a and an upper electrode layer 4 b on the support substrate 1. Is formed. Here, the upper electrode layers 4a and 4b are spaced apart from each other. In the case of the thin film capacitor having such a configuration, if the upper electrode layers 4a and 4b are used as signal input / output terminals, the currents flowing through the two capacitors are as shown by broken arrows in FIG. The path passes through the lower electrode layer 2 common to the two capacitors. With such a configuration, it is not necessary to newly provide wiring for connecting capacitors in series, so that the thin film capacitor can be reduced in size.

  By the way, in such a thin film capacitor, in order to obtain a large capacity with a small area, a crystalline dielectric material having a high dielectric constant in the dielectric layer 3 (hereinafter also referred to as a high dielectric), particularly strontium titanate, titanium It is generally known that a perovskite oxide dielectric material such as barium oxide, barium strontium titanate, lead titanate or the like may be used.

  However, these high dielectric materials do not exhibit excellent dielectric properties unless the crystallinity is good. The crystallinity of the dielectric layer 3 is greatly influenced by the crystal lattice constant, crystal orientation, and the like of the material constituting the support substrate 1 and the lower electrode layer 2 existing below the dielectric layer 3. Among these, the lower electrode layer 2 located immediately below the dielectric layer 3 is particularly important. That is, the lower electrode layer 2 is required to have good lattice matching with the dielectric layer 3 and good surface morphology. Further, since the high dielectric film as described above is generally formed in a high temperature atmosphere, the lower electrode layer 2 also needs to have excellent heat resistance that can withstand this high temperature.

  As a material satisfying these conditions, platinum, an oxide conductor, or the like is generally used as a material for forming the lower electrode layer 2. However, these are excellent in lattice matching with the dielectric layer 3 and heat resistance, but have a higher electric resistance than gold, copper, aluminum, etc., which are used as general electrode materials. It is unsuitable. However, in view of the crystallinity of the dielectric layer 3 as described above, it is necessary to use these materials even if the resistance is high.

As described above, in the conventional thin film capacitor, the lower electrode layer 2 having a high specific resistance having the structure as shown in FIGS. 22 and 23 is used.
Japanese Patent No. 3246274 JP 10-199755 A

  By the way, the parasitic resistance in the thin film capacitor deteriorates the electrical characteristics of the capacitor. For this reason, the capacitor is required to have a structure in which the parasitic resistance is as small as possible. In a conventional thin film capacitor having a structure in which two capacitors are electrically connected in series by a common lower electrode layer 2, when a material having a high specific resistance is used for the lower electrode layer 2, Due to the parasitic resistance due to the electrode layer 2, there is a problem that the electrical characteristics as a capacitor deteriorate. In order to solve this problem, it is important to select a structure in which the parasitic resistance due to the lower electrode layer 2 is reduced as much as possible.

  In the thin film capacitor having a structure in which two capacitors are electrically connected in series by the common lower electrode layer 2 shown in FIG. 22, in order to reduce the parasitic resistance due to the lower electrode layer 2, the lower electrode layer 2 is It is effective to have a structure in which the path length of the flowing current is as short as possible and the path width is as wide as possible. Therefore, in the conventional thin film capacitor, as shown in FIG. 24, the total length of the opposing sides of the adjacent upper electrode layers 4a and 4b is as long as possible, and the distance between the opposing sides is as long as possible. Must be shortened.

  However, the thin film capacitor has a size limit determined by market needs and a size limit determined by a required capacitance value, and the total length of the opposing sides of the upper electrode layers 4a and 4b is freely increased. In reality, capacitors must be created within limited dimensions. Further, due to the limitations of the microfabrication technology, the distance between adjacent sides of the adjacent upper electrode layers 4a and 4b cannot be brought close to 0 infinitely.

  For this reason, the conventional thin film capacitor has not been devised enough to reduce the parasitic resistance due to the lower electrode layer 2, and the electrical characteristics as a thin film capacitor such as a decrease in the Q value are due to the parasitic resistance due to the lower electrode layer 2. There was a problem of deterioration.

  The present invention has been made in view of such problems in the prior art, and an object of the present invention is to provide a thin film capacitor having a small parasitic resistance due to a lower electrode layer and excellent electrical characteristics as a capacitor. is there.

The thin film capacitor of the present invention (hereinafter sometimes simply referred to as a capacitor) includes (1) a lower common electrode, and a plurality of capacitance forming portions comprising a dielectric layer and an upper electrode layer stacked on the lower common electrode. A thin film capacitor having the capacitance forming portion connected in series , wherein the upper electrode layer is electrically insulated from and adjacent to the first upper electrode layer. and a second upper electrode layer arranged, the first upper electrode layer and the second upper electrode layer opposed sides each other have a shape interlocking, the dielectric layer is spaced from each other A first dielectric layer and a second dielectric layer, wherein the first upper electrode layer is formed on the first dielectric layer, and the second upper electrode layer is formed on the second dielectric layer; It is formed above .

The thin film capacitor of the present invention includes (2) a lower common electrode, and a plurality of capacitance forming portions each including a dielectric layer and an upper electrode layer laminated on the lower common electrode , A thin film capacitor connected in series , wherein the upper electrode layer includes: a first upper electrode layer; a second upper electrode layer connected to the first upper electrode layer; the first upper electrode layer; Between the second upper electrode layer and the first upper electrode layer, the first upper electrode layer and the opposite sides of the first upper electrode layer are opposed to the opposite sides of the first upper electrode layer. a third upper electrode layer having a corresponding contour and possess, the dielectric layer comprises a first dielectric layer and a second dielectric layer disposed apart from each other, wherein the first upper electrode At least one of the layer and the second upper electrode layer includes the first dielectric Formed on the layer, the third upper electrode layer, and is formed on the second dielectric layer.

  In the capacitor according to the present invention, in the configurations of (1) and (2), the opposite side of the upper electrode layer has a sum of lengths of sides corresponding to each other as A. When the maximum value of the distance between two points on the outer periphery of the upper electrode layer is B, A / (2B)> 1 is satisfied.

  According to the capacitor of the present invention, (1) a capacitor including a lower common electrode, and a plurality of capacitance forming portions composed of a dielectric layer and an upper electrode layer laminated on the lower common electrode, The electrode layer includes a first upper electrode layer and a second upper electrode layer that is electrically insulated from and disposed adjacent to the first upper electrode layer. The first upper electrode layer and the second upper electrode Since the layers have a shape in which the opposite sides mesh with each other, the sum of the lengths of the sides where the first upper electrode layer and the second upper electrode layer face each other with the opposed sides approaching each other is calculated. Since it can be enlarged, the width of the current path passing through the lower common electrode, which is usually formed of a high resistance material, can be made wider than that of the conventional structure. As a result, a parasitic resistance can be reduced, and a capacitor having a larger Q value than the conventional one and excellent in electrical characteristics can be provided.

  According to the capacitor of the present invention, (2) a capacitor comprising a lower common electrode, and a plurality of capacitance forming portions comprising a dielectric layer and an upper electrode layer laminated on the lower common electrode, The upper electrode layer includes a first upper electrode layer, a second upper electrode layer connected to the first upper electrode layer, and the first and second upper electrode layers between the first upper electrode layer and the second upper electrode layer. And a third upper electrode layer that is disposed insulated from the upper electrode layer and has an outer shape corresponding to the opposite side of the first upper electrode layer and the opposite side of the second upper electrode layer, respectively. Since the total length of the sides where the first upper electrode layer, the second upper electrode layer, and the third upper electrode layer face each other can be increased with the opposing sides kept close to each other, it is usually high resistance. Current path through the lower common electrode formed from different materials Width can be made wider than that of the conventional structure. As a result, a parasitic resistance can be reduced, a capacitor having a high Q value and excellent electrical characteristics can be provided.

  Further, according to the capacitor of the present invention, in the above configuration, the opposing sides of the upper electrode layer have a sum of lengths of sides corresponding to each other as A, and are on the outer periphery of the upper electrode layer. When the maximum distance between the two points is B, and A / (2B)> 1 is satisfied, the sum of the lengths of the sides where the first upper electrode layer and the second upper electrode layer face each other is increased. Therefore, the width of the current path passing through the lower common electrode, which is usually formed of a high resistance material, can be made wider than that of the conventional structure. As a result, a parasitic resistance can be reduced, a capacitor having a high Q value and excellent electrical characteristics can be provided.

  According to the capacitor of the present invention, in the configurations of (1) and (2), the dielectric layer is shared by the plurality of capacitance forming portions. Since the capacitance forming portion can be formed, manufacturing is facilitated and a highly productive capacitor can be provided.

  According to the capacitor of the present invention, in the configuration of (1), the dielectric layer includes a first dielectric layer and a second dielectric layer that are spaced apart from each other, and the first upper electrode layer is The capacitor is formed on the first dielectric layer, and the second upper electrode layer is formed on the second dielectric layer, so that the capacitor composed of the lower common electrode, the first dielectric layer, and the first upper electrode layer is formed. Since it is possible to prevent unnecessary capacitance from being formed between the formation portion and the capacitance formation portion composed of the lower common electrode, the second dielectric layer, and the second upper electrode layer, a desired capacitance variable rate can be accurately obtained. A capacitor which can be obtained well can be provided.

  According to the capacitor of the present invention, in the configuration of (2), the dielectric layer includes a first dielectric layer and a second dielectric layer that are spaced apart from each other, and the first upper electrode layer and Since at least one of the second upper electrode layers is formed on the first dielectric layer and the third upper electrode layer is formed on the second dielectric layer, the lower common electrode and the first dielectric layer are formed. And at least one of a capacitance forming portion comprising the first upper electrode layer and a lower common electrode, a first dielectric layer and a second upper electrode layer, a lower common electrode, a second dielectric layer and a third upper portion Since it is possible to prevent unnecessary capacitance from being formed between the capacitance forming portion made of the electrode layers, it is possible to provide a capacitor capable of accurately obtaining a desired capacitance variable rate.

  Hereinafter, an example of an embodiment of a capacitor of the present invention will be described with reference to the drawings.

  FIG. 1A is a principal plan view showing an example of the first embodiment of the capacitor of the present invention, and FIG. 1B is a principal plan view showing a modification of the shape and arrangement of the upper electrode layer. FIG. In FIG. 1, the capacitor according to the first embodiment includes a lower common electrode 2 formed on a support substrate 1, and first dielectric layers stacked on the lower common electrode 2 and spaced apart from each other. A plurality of dielectric layers 3 comprising a dielectric layer 3a as a dielectric layer and a dielectric layer 3b as a second dielectric layer, and an upper electrode layer 4 formed thereon, in this example, two capacitance forming portions; The upper electrode layer 4 includes a first upper electrode layer 4A and a second upper electrode layer 4B that is electrically insulated from and disposed adjacent to the first upper electrode layer 4A. The first upper electrode layer 4A and the second upper electrode layer 4B have a configuration in which opposing sides mesh with each other.

  Here, the opposing sides refer to portions facing each other when viewed from above, and include not only a linear region but also a curved region. The capacitance forming portion is formed by the lower common electrode 2, the dielectric layer 3, and the first upper electrode layer 4A or the second upper electrode layer 4B.

  Note that, in the following drawings, the same reference numerals are given to the same portions, and duplicate descriptions are omitted. In addition, in order to make the configuration of the capacitor easy to understand, some layers located at the top may be omitted.

The support substrate 1 has high heat resistance and has a strength capable of supporting the capacitance forming portion formed on the substrate 1. The surface of the lower common electrode 2 and the dielectric layer 3 formed on the substrate 1 is smooth. Therefore, it is preferable to have a surface roughness with sufficient flatness. The material is not particularly limited as long as the surface (upper surface) on the side where the capacitance forming portion is laminated has an insulating property. For example, Al ₂ O ₃ , SiO ₂ / Si, MgO, LaAlO ₃ , SrTiO ₃ A ceramic substrate such as sapphire or a single crystal substrate such as sapphire can be used.

  Since the lower common electrode 2 may need to be processed at a high temperature when the dielectric layer 3 is formed, it is desirable to use a material having a high melting point in consideration of heat resistance. Further, in order to grow the dielectric layer 3 on the upper surface with good orientation, it is desirable that the crystallinity and surface morphology are good and the lattice constant is close to that of the dielectric layer 3. Furthermore, when the dielectric layer 3 is made of a metal oxide, it is desirable that the dielectric layer 3 be a metal that is not easily oxidized. From the above, platinum, an oxide conductor, or the like is generally used as a material suitable for the lower common electrode 2.

  The thickness of the lower common electrode 2 is preferably thick when considering the resistance component as an electrode and the continuity of the lower common electrode 2, but when considering the adhesion with the support substrate 1, The thinner one is desirable and is determined in consideration of both. Specifically, it is 0.1 μm to 10 μm. This is because if the thickness is less than 0.1 μm, the resistance of the lower common electrode 2 itself increases, and the continuity of the electrodes may not be ensured. On the other hand, if the thickness is greater than 10 μm, This is because there is a possibility that the adhesiveness of the substrate may be lowered or the support substrate 1 may be warped.

  For the dielectric layer 2, it is desirable to use a crystalline dielectric material having a high dielectric constant, particularly a perovskite oxide dielectric material such as strontium titanate, barium titanate, barium strontium titanate, lead titanate or the like.

  The upper electrode layer 4 is preferably made of a material having high conductivity in order to reduce the resistance due to the upper electrode layer 4. For example, gold, aluminum, copper, or the like can be suitably used.

  The thickness of the upper electrode layer 4 is preferably thick when considering the resistance component as an electrode and the continuity of the upper electrode layer 4, but when considering the adhesion with the dielectric layer 3, the thickness is relatively high. It is desirable that the thickness be determined in consideration of both. Specifically, it is 0.1 μm to 10 μm. This is because if the thickness is less than 0.1 μm, the resistance of the upper electrode layer 4 itself increases, and the continuity of the electrodes may not be ensured. On the other hand, if the thickness is greater than 10 μm, the dielectric layer 3 This is because there is a possibility that the adhesiveness with the lowering.

  Here, the first upper electrode layer 4 </ b> A and the second upper electrode layer 4 </ b> B have a configuration in which opposing sides mesh with each other. Here, the shape in which the opposite sides mesh with each other means that the first upper electrode layer 4A and the second upper portion are formed when two points are connected by a line segment so that the distance between the two points on the opposite sides is maximum. The shape crossing at least one of the electrode layers 4B shall be said. That is, in plan view or plan view, at least a part of the first upper electrode layer 4A that is opposed is second than the one end of the adjacent second upper electrode layer 4B in the juxtaposed direction of the electrode layers 4A and 4B. The second upper electrode layer 4B is disposed so as to protrude to the upper electrode layer 4B side, and the portion of the second upper electrode layer 4B on the first upper electrode layer 4A side (opposite portion) has a shape corresponding to the shape of the first upper electrode layer 4A. It has become. Since it has such a configuration, the sum of the lengths of the sides where the first upper electrode layer 4A and the second upper electrode layer 4B arranged adjacent to each other face each other can be made longer than that of the conventional structure. The width of the current path passing through the lower common electrode 2 formed of a resistive material can be made wider than that of the conventional structure, and the parasitic resistance of the capacitor can be reduced as compared with the conventional one.

  As shown in FIG. 1A, the shape and arrangement of the first upper electrode layer 4A and the second upper electrode layer 4B are such that the first upper electrode layer 4A has comb teeth on the side facing the second upper electrode layer 4B. The second upper electrode layer 4B has a comb-shaped second comb-tooth region on the side facing the first upper electrode layer 4A so as to mesh with the first comb-tooth region. It may be a thing. Further, as shown in FIG. 1B, the shape of the first upper electrode layer 4A having a shape that includes a curved portion in the outer shape and the shape of the portion facing the first upper electrode layer 4A are the first upper electrode layer 4A. The second upper electrode layer 4B having a shape corresponding to the shape may be arranged. In particular, when the configuration shown in FIG. 1A is used, the total length of the sides where the first upper electrode layer 4A and the second upper electrode layer 4B face each other can be greatly increased. The width of the current path passing through the lower common electrode 2 formed of a resistive material can be made wider than that of the conventional structure. As a result, a parasitic resistance can be reduced, a capacitor having a high Q value and excellent electrical characteristics can be provided.

  At this time, the opposite sides of the upper electrode layer 4 have a maximum value of the distance between two points on the outer periphery of the upper electrode layer 4 where A is the sum of the lengths of the sides corresponding to each other. It is desirable that A / (2B)> 1 when B is B.

  Here, the effect of the configuration in which the opposing sides of the upper electrode layer 4 satisfy A / (2B)> 1 will be examined in detail while comparing with the conventional thin film capacitor shown in FIG. .

  In FIG. 23, in the opposite sides of the upper electrode layer 4a and the upper electrode layer 4b, the sum of the lengths of the portions corresponding to each other is assumed to be A, and on the outer periphery of the upper electrode layers 4a and 4b. Let B be the maximum distance between two points. Here, B is equal to the length of the diagonal line of the rectangular region in which the upper electrode layers 4a and 4b are arranged, and is defined by the size of the part determined by market needs and the like. In the conventional configuration, B is expressed as follows.

B = [(A / 2) ² + {G + 2 (S / A)} ² ] ^(1/2)
Here, G is a distance between opposing sides of the upper electrode layers 4a and 4b arranged to face each other, and S is an area of the capacitance forming portion.

  Parasitic resistance due to the lower common electrode 2 can be minimized in principle by making the length A / 2 of the opposing sides as large as possible and G as small as possible. At this time, B is infinitely close to A / 2.

  However, since B corresponds to the hypotenuse of a triangle having one side that faces each other, the following equation holds in principle.

A / (2B) <1
On the other hand, according to the capacitor as shown in FIG. 1A of the present application, even if the size of the region where the upper electrode layer 4 is arranged is similar to the example shown in FIG. A / (2B)> 1 can be easily achieved by increasing the number of comb teeth, or by increasing the length of the portion engaged with the comb teeth, for example. For this reason, the parasitic resistance can be drastically reduced to a level that cannot be realized by the conventional configuration.

  In the example of the first embodiment, the method of electrically connecting the first upper electrode layer 4A and the second upper electrode layer 4B and the external circuit may be realized by, for example, wire bonding or soldering. At this time, the resistance of the first upper electrode layer 4A and the second upper electrode layer 4B is preferably lower than the resistance of the lower common electrode 2.

  As another method for electrically connecting the first upper electrode layer 4A and the second upper electrode layer 4B and the external circuit, for example, as shown in FIG. After the contact hole 6a reaching the first upper electrode layer 4A and the contact hole 6b reaching the second upper electrode layer 4B are formed in the protective film 5, the first upper electrode layer 4A exposed in the contact hole 6a is electrically A lead electrode layer 7a that is electrically connected and a lead electrode layer 7b that is electrically connected to the second upper electrode layer 4B exposed in the contact hole 6b are formed on the protective film 5 to the outside of the capacitance forming portion. Thus, an electrical connection with an external circuit may be realized. The resistances of the extraction electrode layer 7a and the extraction electrode layer 7b are preferably lower than the resistance of the lower common electrode 2. The resistance of the first upper electrode layer 4A and the second upper electrode layer 4B is preferably lower than the resistance of the lower common electrode 2, but the resistance of the extraction electrode layer 7a and the extraction electrode layer 7b is lower than that of the lower common electrode 2. If lower than that, the resistances of the first upper electrode layer 4A and the second upper electrode layer 4B are not necessarily lower than the resistance of the lower common electrode 2. When the resistances of the extraction electrode layer 7a and the extraction electrode layer 7b are sufficiently lower than those of the first upper electrode layer 4A and the second upper electrode layer 4B, as shown in FIG. 3, the contact hole 6a and the contact hole 6b Is located at the inner side of the outer shape of the upper electrode layers 4a and 4b at least in a portion engaging in a comb-like shape, and when the shape corresponds to the shape of the first upper electrode layer 4A and the second upper electrode layer 4B, the parasitic resistance is reduced. This is desirable because it can be reduced.

  Here, the protective film 5 may be made of an insulating material in order to maintain insulation between the extraction electrode layer 7 and the lower common electrode 2, but it can prevent moisture from entering the capacitance forming portion. For this reason, silicon oxide or the like is preferably formed by a CVD method or the like with good coverage. The extraction electrode layer 7 may be made of Au, which is a conductive material with low resistance.

  Further, in the first embodiment, the same number of dielectric layers 3 are provided for the two capacitance forming portions. For example, as shown in FIG. The dielectric layers 3 may be provided, and the number of the dielectric layers 3 may be smaller than the number of capacitance forming portions. In the former case, by suppressing the fringe capacitance, it is possible to prevent unnecessary capacitance from being formed between adjacent capacitance forming portions, and a desired capacitance value can be obtained. In the latter case, since a plurality of capacitance forming portions can be formed only by patterning the upper electrode layer 4, manufacturing is facilitated and a highly productive capacitor can be provided.

  Next, FIG. 5 is a plan view showing an example of the second embodiment of the capacitor of the present invention. As shown in FIG. 5, the capacitor of the present invention includes a lower common electrode 2 formed on a support substrate 1, and dielectric layers 3a to 3d formed on the lower common electrode 2 so as to be spaced apart from each other. Electrode layers 4a to 4d as upper electrode layers 4 formed on the dielectric layers 3a to 3d, respectively. At this time, the electrode layer 4a and the electrode layer 4b, the electrode layer 4b and the electrode layer 4c, the electrode layer 4c and the electrode layer 4d are arranged to face each other, and the opposite sides (outer shapes) in which the opposite sides correspond to each other. It has become. The electrode layer 4a and the electrode layer 4c are electrically connected, and the electrode layer 4b and the electrode layer 4d are electrically connected.

  Here, for example, if the electrode layers 4a, 4b, and 4c are a first upper electrode layer, a third upper electrode layer, and a second upper electrode layer, respectively, the third upper electrode layer is the first and second upper electrode layers. Insulated between each other. By arranging the upper electrode layer 4 in this way, the total length of the opposing sides of the adjacent upper electrode layers 4 is longer than that of the conventional structure, so that the parasitic resistance is reduced. Can be reduced more.

  When the dielectric layer 3a or the dielectric layer 3c is the first dielectric layer and the dielectric layer 3b is the second dielectric layer, at least one of the first upper electrode layer and the second upper electrode layer is the first dielectric layer. The third upper electrode layer is formed on the body layer, and is formed on the second dielectric layer. With such a configuration, since the fringe capacity can be suppressed, it is possible to prevent unnecessary capacity from being formed in adjacent capacity forming portions of at least one combination and obtain a desired capacity. it can. In the example shown in FIG. 5, the same number of dielectric layers 3 are provided for a plurality of capacitance forming portions. For example, the dielectric layers 3a, 3c and 3b, 3c are integrated with each other. The dielectric layers 3a, 3b and 3c, 3d may be formed integrally, or the dielectric layers 3a, 3b, 3c may be formed integrally. Good.

  At this time, the opposing sides of the electrode layers 4a to 4d are A on the outer periphery of the upper electrode 4 composed of the electrode layers 4a to 4d, where A is the sum of the lengths of the sides corresponding to each other. When the maximum value of the distance between two points is B, it is desirable to satisfy A / (2B)> 1. As shown in FIG. 5, when there are a plurality of combinations of opposing sides, the sum of all the plurality of sets is set as a sum A of the lengths of the opposing sides. In the example shown in FIG. 5, the diagonal length of the region where the electrode layers 4 a to 4 d are arranged is equivalent to B.

  The method of electrically connecting the electrode layer 4a and the electrode layer 4c, and the electrode layer 4b and the electrode layer 4d may be performed by, for example, wire bonding or soldering. At this time, in order to reduce the parasitic resistance of the entire capacitor, it is desirable that the surface resistance of the electrode layers 4 a to 4 d is lower than the surface resistance of the lower common electrode 2.

  Further, for example, as shown in FIG. 6, a protective film 5 is formed so as to cover the capacitance forming portion, and a contact hole 6a reaching the electrode layer 4a and a contact hole 6b reaching the electrode layer 4b and the electrode layer are formed in the protective film 5. After the contact hole 6c reaching 4c and the contact hole 6d reaching the electrode layer 4d are formed, the electrode layer 4a exposed in the contact holes 6a, 6c and the extraction electrode layer 7a electrically connected to the electrode layer 4c, and the contact By forming on the protective film 5 the electrode layer 4b exposed in the holes 6b and 6d and the lead electrode layer 7b electrically connected to the electrode layer 4d, and between the electrode layer 4a and the electrode layer 4c, and the electrode An electrical connection between the layer 4b and the electrode layer 4d may be realized. At this time, in order to reduce the parasitic resistance of the capacitor as a whole, the surface resistance of the electrode layer 4a, the electrode layer 4b, the electrode layer 4c, and the electrode layer 4d is lower than the surface resistance of the lower common electrode 2, or the extraction electrode It is desirable that the surface resistance of the layer 7 is lower than the surface resistance of the lower common electrode 2.

  In the present embodiment, the shape of the electrode layers 4a to 4d constituting the upper electrode layer 4 is rectangular, but the shape of the upper electrode layer 4 of the capacitor of the present invention is not limited to this shape. For example, the shape of the upper electrode layer 4 may be a triangle as shown in FIG. 7 or a shape including a curve as shown in FIG. Further, for example, the electrode layers 4a to 4d need not all have the same shape. As shown in FIG. 9, various shapes can be mixed as long as opposing sides have shapes corresponding to each other. You may do it. In addition, when the opposing sides have a shape that meshes with each other, the width of the current path passing through the lower common electrode 2 can be made wider than that of the conventional structure, and the parasitic resistance is reduced. can do. Moreover, when using the triangular electrode layers 4a to 4d as shown in FIG. 7, if the longest sides are arranged to face each other, the opposing sides in the region where the electrode layers 4a to 4d are arranged The sum of the lengths of can be increased. Furthermore, for example, the electrode layers 4a to 4d are not necessarily arranged in an orderly manner, and the arrangement positions may be shifted from side to side as shown in FIG. In either case, the total length of the opposing sides of the upper electrode layers 4 arranged adjacent to each other is longer than that of the conventional structure, so that the parasitic resistance can be reduced as compared with the conventional thin film capacitor.

  In the example of the second embodiment of the present invention, there are a plurality of capacitance forming portions, and there are the same number of dielectric layers 3. However, for example, as shown in FIG. A common dielectric layer 3 may be used. In this case, since a plurality of capacitance forming portions can be formed only by patterning the upper electrode layer 4, manufacturing is facilitated and a highly productive capacitor can be provided.

  Further, in the example of the second embodiment of the present invention, the upper electrode layer 4 is shown as an example composed of four electrode layers 4a to 4d. However, the upper electrode layer 4 is actually the first to third upper portions. Any number of three or more including the electrode layer is included in the scope of the present invention. For example, FIG. 12 shows another example of the embodiment of the present invention in which the upper electrode layer 4 includes ten electrode layers 4a to 4j. In principle, the larger the number of electrode layers 4a to 4j constituting the upper electrode layer 4, the longer the total sum of the opposing sides, which is desirable because the effect of the present invention is increased.

  Next, an example of the method for manufacturing a capacitor according to the present invention will be described using the capacitor according to the present invention shown in FIG. 6 as an example. FIGS. 13 to 16 show the respective steps of the method of manufacturing the capacitor shown in FIG. 6, and (a) and (b) are an upper plan view and a sectional view, respectively.

  First, as shown in FIG. 13, a first platinum film 2 i having a thickness of 0.1 to 10 μm is formed on a support substrate 1, a barium strontium titanate film 3 i is further formed thereon, and a thickness of 0.01 to 1 μm is formed thereon. Each of the second platinum films 4i is continuously formed using a sputtering method.

  Next, as shown in FIG. 14, after applying a resist on the second platinum film 4i and patterning by photolithography, etching is performed using this as a mask to pattern the second platinum film 4i. Thus, the electrode layer 4a, the electrode layer 4b, the electrode layer 4c, and the electrode layer 4d are formed. After removing the resist, a new resist is applied, and patterning is performed by photolithography so that the electrode layer 4a, the electrode layer 4b, the electrode layer 4c, and the electrode layer 4d have a larger shape. The barium strontium film 3i is etched to form a dielectric layer 3a, a dielectric layer 3b, a dielectric layer 3c, and a dielectric layer 3d, and the resist is removed. Next, a resist is applied, and patterning is performed by photolithography so as to cover a region where the dielectric layer 3a, the dielectric layer 3b, the dielectric layer 3c, and the dielectric layer 3d are formed, and this is masked. Then, the first platinum film 2i is etched to form the lower common electrode 2, and the resist is removed.

Next, as shown in FIG. 15, a protective film 5 made of SiO ₂ is formed on the support substrate 1 by the CVD (Chemical Vapor Deposition) method, covering the entire surface of the capacitance forming portion. Next, a resist is applied thereon, patterning is performed by photolithography, and then etching is performed to form openings 6a, 6b, 6c, and 6d serving as contact holes reaching the lower common electrode 2, and the resist is formed. Remove.

  Thereafter, as shown in FIG. 16, the extraction electrode layer 7a connected to the electrode layer 4a and the electrode layer 4c through the opening 6a and the opening 6c, and the connection to the electrode layer 4b and the electrode layer 4d through the opening 6b and the opening 6d. The extraction electrode layer 7b to be formed is formed using a gold alloy material.

  A capacitor comprising the lower common electrode 2 and a plurality of capacitance forming portions composed of the dielectric layer 3 and the upper electrode layer 4 stacked on the lower common electrode 2 in the process as described above. The layer 4 includes an electrode layer 4a which is a first upper electrode layer, an electrode layer 4c which is a second upper electrode layer connected to the electrode layer 4a which is a first upper electrode layer, and an electrode which is a first upper electrode layer. Between the layer 4a and the electrode layer 4c which is the second upper electrode layer, the electrode layers 4a and 4c which are the first and second upper electrode layers are disposed so as to be insulated, and the electrode layer which is the first upper electrode layer It is possible to provide a capacitor having an electrode layer 4b which is a third upper electrode layer having an outer shape corresponding to the opposite side of 4a and the opposite side of the electrode layer 4c which is the second upper electrode layer. it can.

  In this embodiment, platinum and a gold alloy are used for the lower common electrode 2 and the extraction electrode 7, respectively, but other metals, oxide conductors, or multilayer films thereof may be used.

  In the present embodiment, the thickness range of the lower common electrode 2 and the upper electrode layer 4 is not less than 0.1 μm and not more than 10 μm. Originally, it is not limited to this range as long as the adhesiveness to the portion can be secured. In addition, the stress is not necessarily limited to this range as long as the stress on the base portion caused by increasing the thickness is within an allowable range that does not cause problems such as warpage or peeling of the base portion.

  Next, examples of the capacitor of the present invention will be described with reference to the drawings. Specifically, simulation was performed using HFFS (High-Frequency Structure Simulator), which is an electromagnetic field simulator of Ansoft, and the Q values of the capacitor of the present invention and the thin film capacitor of the conventional configuration were compared.

  This will be described below with reference to the model diagram used in the simulation.

FIG. 17 is a diagram showing a model 1 which is a model of a conventional thin film capacitor used in the simulation. FIGS. 17A and 17B are a plan view and a cross-sectional view of a main part, respectively. In the thin film capacitor model 1 shown in FIG. 17, a lower common electrode 2 having a thickness of 0.2 μm, a dielectric layer 3 having a thickness of 0.2 μm, and an electrode layer 4 a serving as an upper electrode layer having a thickness of 2 μm are formed on a support substrate 1. In addition, two capacitance forming portions configured by sequentially laminating electrode layers 4b as upper electrode layers having a thickness of 2 μm are connected in series by sharing the lower common electrode 2. The electrode layers 4a and 4b are formed to extend to the support substrate 1 outside the capacitance forming portion, and the regions on the support substrate 1 are denoted by 1a and 1b. Here, the physical properties of sapphire were used for the support substrate 1. The physical property value of Pt was used for the lower common electrode 2. The dielectric layer 3 has a relative dielectric constant of 60 and a Q value of 200. The electrode layers 4a and 4b are ideal conductors. The areas of the electrode layer 4a and the electrode layer 4b were each 4500 μm ² . In this model 1, the signal is incident (input) from the region 1a and radiated (output) from the region 2b.

  Next, FIG. 18A is a plan view and FIG. 18B is a cross-sectional view of the main part of the model 2 which is a capacitor model of the present invention used in the simulation. In the capacitor model 2 shown in FIG. 18, the conditions were the same as those of the model 1 except that four electrode layers 4 a and 4 b as the upper electrode layer 4 which were two in the model 1 were provided. Only the changes will be described below.

In the model 2, electrode layers 4a to 4d as upper electrode layers having a thickness of 2 μm are arranged on the dielectric layer 3, and these electrode layers 4a to 4d extend to the support substrate 1 outside the capacitance forming portion. If the regions on the support substrate 1 are defined as 1a to 1d, signals are incident from the electrically connected regions 1a and 1c, and from the electrically connected regions 1b and 1d. Radiated. The sum of the areas of the electrode layer 4a and the electrode layer 4c was 4500 μm ² , and the sum of the areas of the electrode layer 4 b and the electrode layer 4 d was 4500 μm ² .

Next, in FIG. 19, (a) is a plan view and (b) is a cross-sectional view of the main part of the model 3, which is another model of the capacitor of the present invention used in the simulation. In the capacitor model 3 shown in FIG. 19, the conditions were the same as those of the model 1 except that eight electrode layers 4a and 4b as the upper electrode layer 4 which were two in the model 1 were provided. Only the changes will be described below. On the dielectric layer 3, electrode layers 4 a to 4 h as upper electrode layers having a thickness of 2 μm are arranged, and these electrode layers 4 a to 4 h are formed extending to the support substrate 1 outside the capacitance forming portion. When the regions on the respective support substrates 1 are defined as 1a to 1h, signals are incident from the electrically connected regions 1a, 1c, 1e and 1g and electrically connected to the regions 1b and 1b. 1d, emitted from the region 1f and the region 1h. The sum of the areas of the electrode layer 4a, the electrode layer 4c, the electrode layer 4e, and the electrode layer 4g is 4500 μm ² , and the sum of the areas of the electrode layer 4b, the electrode layer 4d, the electrode layer 4f, and the electrode layer 4h is 4500 μm ^2. It is.

Table 1 shows the A, B and A / (2B) calculations defined in this specification for the above three models.

  In this embodiment, model 1 corresponds to a conventional thin film capacitor, and model 2 and model 3 correspond to the capacitor of the present invention. In this example, the distance between the opposing sides of each electrode layer of the upper electrode layer 4 was 2 μm.

  As shown in Table 1, in the conventional thin film capacitor, the value of A / (2B) is less than 1, and in the capacitor of the present invention, the value of A / (2B) is 1 or more, and the upper electrode layer 4 As the number of electrode layers increased and the number of opposing sides increased, the value increased. Moreover, since the value of B was substantially constant in Models 1 to 3, it was confirmed that the size of the capacitor was substantially constant even when the number of electrode layers as the upper electrode layer 4 was increased.

  In this example, the Q value at 1 GHz was simulated in a state where three of each of the three types of models were connected in series. FIG. 20 is a perspective view when three models 3 are connected in series. Here, the rectangular parallelepiped in FIG. 20 indicates the boundary set when the simulation is performed. At the boundary of this rectangular parallelepiped, it indicates that the surface other than the surface including the region where the signal is incident (for example, the region 1a in the case of the model 1) is grounded and becomes the reference potential.

  The result of the simulation performed in this way is shown in FIG. In FIG. 21, the horizontal axis represents the value of A / (2B), and the vertical axis represents the Q value on the left side and the parasitic resistance (unit: Ω) on the right side. From FIG. 21, it became clear that the parasitic resistance at 1 GHz is greatly reduced as A / (2B) increases. In particular, when A / (2B) is near 1, the degree of reduction in parasitic resistance is large, and the effect of the present invention has been demonstrated. It was also found that the Q value was greatly improved along with the reduction of the parasitic resistance. Also in the Q value, the degree of improvement was large when A / (2B) was around 1, and the effect of the present invention was demonstrated.

  Since the area of the upper electrode layer 4 is constant in the models 1 to 3, according to the capacitor of the present invention, the parasitic resistance can be greatly reduced and the Q value can be greatly improved without increasing the size of the capacitor. Was confirmed.

  Note that the above are merely examples of the embodiments of the present invention, and the present invention is not limited to these embodiments, and various modifications and improvements may be added without departing from the scope of the present invention. .

(A) is a principal part top view which shows an example of 1st Embodiment of the capacitor | condenser of this invention, (b) is a principal part top view which shows the modification. (A), (b) is the top view which shows the structure for connecting the capacitor | condenser shown to Fig.1 (a) with an external circuit, respectively, and principal part sectional drawing in an XY line. (A), (b) is the top view which shows the modification of FIG. 2, respectively, and the principal part sectional drawing in XY line. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the example of 2nd Embodiment of the capacitor | condenser of this invention. (A), (b) is the top view which shows the modification of the capacitor | condenser shown in FIG. 5, respectively, and principal part sectional drawing in an XY line. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the modification of the capacitor | condenser shown in FIG. It is a top view which shows the modification of the capacitor | condenser shown in FIG. (A), (b) is the top view which shows the process of the manufacturing method of the capacitor | condenser shown in FIG. 6, respectively, and sectional drawing in XY line. (A), (b) is the top view which shows the process of the manufacturing method of the capacitor | condenser shown in FIG. 6, respectively, and sectional drawing in XY line. (A), (b) is the top view which shows the process of the manufacturing method of the capacitor | condenser shown in FIG. 6, respectively, and sectional drawing in XY line. (A), (b) is the top view which shows the process of the manufacturing method of the capacitor | condenser shown in FIG. 6, respectively, and sectional drawing in XY line. (A), (b) is the top view of the model 1, and the principal part sectional drawing in XY line, respectively. (A), (b) is the top view of the model 2, and the principal part sectional drawing in XY line, respectively. (A), (b) is the top view of the model 3, and the principal part sectional drawing in XY line, respectively. FIG. 20 is a perspective view of a model in which three models 3 shown in FIG. 19 are connected in series. It is a diagram which shows the simulation result of Q value and the parasitic resistance value with respect to the value of A / (2B) of each model in the Example of the capacitor | condenser of this invention. It is principal part sectional drawing of the structure of the conventional thin film capacitor. It is a top view explaining the thin film capacitor shown in FIG. It is a typical top view explaining an example of the structure of the conventional thin film capacitor.

Explanation of symbols

1: Support substrate 2: Lower common electrode 3: Dielectric layer 4: Upper electrode layer 5: Protective film 6: Contact hole 7: Lead electrode layer

Claims (4)

A thin film capacitor comprising a lower common electrode, and a plurality of capacitance forming portions comprising a dielectric layer and an upper electrode layer laminated on the lower common electrode , wherein the capacitance forming portions are connected in series ;
The upper electrode layer includes a first upper electrode layer, and a second upper electrode layer that is electrically insulated from and disposed adjacent to the first upper electrode layer,
Said first upper electrode layer and the second upper electrode layer have a shape that opposing sides each other interlocking,
The dielectric layer includes a first dielectric layer and a second dielectric layer that are spaced apart from each other,
The first upper electrode layer is formed on the first dielectric layer,
The second upper electrode layer is a thin film capacitor formed on the second dielectric layer . A thin film capacitor comprising a lower common electrode, and a plurality of capacitance forming portions comprising a dielectric layer and an upper electrode layer laminated on the lower common electrode , wherein the capacitance forming portions are connected in series ;
The upper electrode layer is
A first upper electrode layer;
A second upper electrode layer connected to the first upper electrode layer;
Between the first upper electrode layer and the second upper electrode layer, the first upper electrode layer and the second upper electrode are disposed so as to be insulated from the first and second upper electrode layers. A third upper electrode layer having an outer shape corresponding to each of opposite sides of the layer;
I have a,
The dielectric layer includes a first dielectric layer and a second dielectric layer that are spaced apart from each other,
At least one of the first upper electrode layer and the second upper electrode layer is formed on the first dielectric layer;
The third upper electrode layer is a thin film capacitor formed on the second dielectric layer . The opposing sides of the upper electrode layer have a sum of the lengths of the sides corresponding to each other as A, and the maximum distance between two points on the outer periphery of the upper electrode layer is B. The thin film capacitor according to claim 1 or 2, wherein A / (2B)> 1 is satisfied. The dielectric layer is made of a perovskite oxide dielectric material,
The thin film capacitor according to claim 1 , wherein the lower common electrode layer is made of Pt or an oxide conductor .

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