JP2002015949A - Thick-film capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thick-film capacitor array structured for reducing the capacitance characteristics variation for each capacitor element. SOLUTION: The thick-film capacitor array 10 has an insulation board 1, lower electrodes 2 formed on the insulation board 1 surface, thick-film dielectric layers 3a, 3b formed on the upsides of the lower electrodes 2, and upper electrodes 4a-4d which are formed on the dielectric layers 3a, 3b, opposite to the lower electrodes 3. Two or four upper electrodes 4a-4d, 41a-42d are formed on one dielectric layer 3a, 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film capacitor array having a plurality of capacitor elements provided on an insulating substrate.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic devices such as a camera-integrated VTR, a portable telephone, a notebook personal computer, and a palmtop computer, various electronic components used for these devices have also been miniaturized. In addition, the terminal structure of the electronic component has shifted from a lead type to a terminal electrode made of a conductive film, and surface mounting technology (SMT) has been actively adopted. Electronic components used in this SMT are collectively called surface mount components (SMD). For example, in the case of capacitors, a chip type multilayer ceramic capacitor, a thick film capacitor array in which a plurality of capacitors are incorporated in an element, and the like are given. .

In particular, with the miniaturization of electronic equipment, a plurality of multilayer ceramic capacitors have been arranged at high density on a printed wiring board as a capacitor array component.

A conventional thick film capacitor array has a sectional structure shown in FIG. 4 and a planar structure shown in FIG.

In FIGS. 4 and 5, reference numeral 50 denotes a thick film capacitor array, 51 denotes an insulating substrate, 52 denotes a common lower electrode, 53 denotes a common thick dielectric layer, and 54a
Reference numeral 54d denotes an upper electrode, and 55 denotes a protective layer.

A common lower electrode 52 extending in one direction, for example, the X direction, is formed on an insulating substrate 51 of alumina or the like by printing and baking a conductive paste. Further, a continuous common thick film dielectric layer 53 is formed on the common lower electrode 52 over a plurality of capacitor elements. Here, the end in the X direction of the common lower electrode 52 exposed from the common thick film dielectric layer 53 functions as a lead-out portion of the common lower electrode 52. This drawer is indicated by reference numeral 52x on the drawing.

On the common thick film dielectric layer 53, a plurality of upper electrodes 54a to 54d facing the common lower electrode 52 are provided.
Is formed. Each of the upper electrodes 54a to 54a
4d are each formed so as to extend in the Y direction orthogonal to the extending direction (x direction) of the common lower electrode 52, and a plurality of upper electrodes 54a to 54d are arranged in the x direction. still,
Each of the upper electrodes 54a to 54d has a drawing portion extending below the common thick film dielectric layer 53 in the drawing. This drawer is indicated by reference numerals 54w to 54z.

That is, the plurality of upper electrodes 54 arranged in the X direction on the common thick film dielectric layer 53 face the common lower electrode 52 via the common thick film dielectric layer 53, respectively. As a result, the four thick film capacitor elements C
51 to C54 are arranged, and the common lower electrode 5
An array structure is connected through the two.

Then, the lead portion 5 of the common lower electrode 52
A predetermined capacitance of the capacitor element C51 is obtained from between the 2x and the lead portion 54w of the upper electrode 54a, and a predetermined capacitance of the capacitor element C52 is obtained between the lead portion 52x of the common lower electrode 52 and the lead portion 54x of the upper electrode 54b. The capacitor element C is obtained between the lead portion 52x of the common lower electrode 52 and the lead portion 54y of the upper electrode 54c.
A predetermined capacitance of 53 is obtained, and a predetermined capacitance of the capacitor element C54 is obtained from between the leading portion 52x of the common lower electrode 52 and the leading portion 54z of the upper electrode 54d.

Further, each of the capacitor elements C51 to C54 formed on the insulating substrate 51 has lead portions 52x and 54w.
A protective layer 35 made of glass, epoxy resin, or the like is formed so as to expose .about.54z. This is because the common thick-film dielectric layer 53 is a dielectric layer formed by a thick-film method, and has a relatively low porcelain density and becomes a porous porcelain. To prevent the insulation resistance from deteriorating. Note that it is desirable to use crystallized glass or the like for the protective layer 55.

Although the above-described common thick film dielectric layer 53 is shown as being formed of one dielectric layer in the thickness direction, the capacitance of each of the capacitor elements C51 to C54 is taken into consideration. Alternatively, the printing, drying, and baking processes of the dielectric paste may be repeated to form the common thick film dielectric layer 53 into a substantially laminated structure. For example, a dielectric layer may be printed, dried, and fired in a single pass of dielectric paste, resulting in about 10
Since a thickness of about 20 μm is obtained, for example, the thickness of the common thick film dielectric layer may be controlled to about 30 to 60 μm by repeating about three times. Each firing temperature was 900
It is performed at around ° C. The upper electrode 34 is formed by printing, drying, and baking a conductive paste, and the baking process is performed at about 900 ° C.

In such a thick-film capacitor array 50, a plurality of single capacitors can be integrated as one component, the variation in the size and shape of each capacitor can be suppressed, and the work of mounting on a circuit board can be simplified. can do. Also, for example, when mounting a single capacitor on a printed circuit board or the like, the electrode pads are provided concentrated on the wiring board, so that high-density mounting is possible. In addition, since each of the capacitor elements C51 to C54 has the common lower electrode 52, the number of electrode pads connected to the common lower electrode 53 can be reduced. further,
As shown in FIG. 5, the extending direction of the common lower electrode 52 is the X direction, and the extending direction of the upper electrodes 54a to 54d is the Y direction, so that the common lower electrode 52 and the upper electrodes 54a to 54d are extended.
However, even if the position shift occurs in the X direction or the Y direction, the opposing areas do not change, and each capacitor element C5
The capacities of 1 to C54 do not change. By changing the area of the upper electrode 34, the desired capacitor element C51 can be formed.
~ C54 capacity can be obtained.

[0013]

However, as described above,
The common thick film dielectric layer 53 includes a plurality of capacitor elements C51.
To C54. Then, to form four capacitor elements C51 to C54 on the common thick film dielectric layer 53, the four upper electrodes 54a to
54d is formed. If the common lower electrode 52
And the upper electrodes 54a to 54d have the same opposing area to obtain the same capacitance, the two capacitors C52 and C53 closer to the center and the two capacitors C51 and C54 closer to the outside have different capacitance values. Will occur.

This is because, in the series of common thick film dielectric layers 53, the sintering conditions are different between the portions where the capacitor elements C51 and C54 are formed and the portions where the capacitor elements C52 and C53 are formed. I think that the. In other words, the common thick-film dielectric layer 53 near the center (where the capacitor elements C52 and C53 are formed) is in an insufficiently sintered state, and as a result, the characteristics such as the capacitance vary.

At this time, the detailed mechanism is unknown, but to prevent the common lower electrode 52 from being over-sintered,
The firing temperature of the common thick-film dielectric layer 53 is lowered to about 900 ° C., and the firing process is performed, and a difference in temperature distribution occurs in the continuous common thick-film dielectric layer 53 during firing. It is thought to be due to such factors.

Actually, when the sintering state of the common thick film dielectric layer 53 is examined by SEM analysis, it is apparent that the progress of the sintering reaction is clearly observed at the peripheral portion and the central portion of the common thick film dielectric layer 53. We confirmed that they were different.

Moreover, in the structure in which the common thick film dielectric layer 53 is formed by laminating a plurality of layers in order to obtain a predetermined thickness, in particular, the difference in the sintering state (the difference in the variation in capacitance characteristics).
Is amplified.

The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a thick film capacitor array capable of effectively suppressing variations in capacitance characteristics among a plurality of capacitor elements. It is in.

[0019]

According to the present invention, there is provided a thick film comprising a plurality of capacitor elements comprising a common lower electrode, a thick film dielectric layer formed by baking a dielectric paste, and an upper electrode on an insulating substrate. In the capacitor array, the thick film dielectric layer may be divided into a plurality of pieces, and the upper electrodes may be arranged in at least one direction on each of the divided thick film dielectric layers. This is a characteristic thick film capacitor array.

Further, preferably, the upper electrode is
A thick-film capacitor array, wherein two are arranged on the thick-film dielectric layer in one direction and in the other direction orthogonal to the one direction.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thick film capacitor array according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a thick film capacitor array according to the present invention, and FIG. 2 is a plan view of a first embodiment (an example in which capacitor elements are arranged in one direction).

The insulating substrate 1 is a heat-resistant insulating substrate such as alumina. A common lower electrode 2 is formed on the insulating substrate 1 so as to extend over the plurality of capacitor elements C1 to C4. The extending direction of the common lower electrode 2 (X in the drawing)
Direction) extends from the region where the capacitor elements C1 to C4 are formed. The extending portion serves as a lead portion 2x of the common lower electrode 2.

On the common lower electrode 2, a plurality of, for example, two divided thick film dielectric layers 3a and 3b are formed. The thick film dielectric layers 3a and 3b have, for example, three dielectric layers (not shown) laminated in the thickness direction in order to obtain a predetermined capacitance. The thick dielectric layers 3a, 3a
b is formed so as to expose the extraction electrode 2x of the common lower electrode 2.

Two upper electrodes 4a and 4b are formed on the thick dielectric layer 3a, and two upper electrodes 4c and 4d are formed on the thick dielectric layer 3b. The upper electrodes 4a to 4
d is the same direction as the extending direction of the common lower electrode 2 (X direction)
Are arranged side by side, and each upper electrode 4a
To d extend in a direction (Y direction) orthogonal to the arrangement direction. That is, the upper electrodes 4a to 4d extend to the lower side in the drawing of the thick film dielectric layers 3a and 3b, and serve as lead portions 4w to 4z of the upper electrodes 4a to 4d.

Thus, on the insulating substrate 1, the first capacitor element C1 including the common lower electrode 2, the thick dielectric layer 3a and the upper electrode 4a, the common lower electrode 2, the thick dielectric layer 3a and the upper A second capacitor element C2 comprising an electrode 4b, a common lower electrode 2, a third capacitor element C3 comprising a thick dielectric layer 3b and an upper electrode 4c, a common lower electrode 2, a thick dielectric layer 3b, and an upper electrode 4d. Is formed.

The lead portions 2x of the common lower electrode 2 and the lead portions 4w-4z of the upper electrodes 4a-4d.
Is exposed, and the protective layer 5 is formed so as to cover the entire capacitor elements C1 to C4.

Although the above-mentioned insulating substrate 1 has the shape of one thick film capacitor array 10, for example, a large flat plate-like substrate from which a plurality of insulating substrates 1 can be formed may be used. In this case, slits for dividing vertically and horizontally are formed in the large substrate in advance according to the shape of each thick film capacitor array 10, and divided into predetermined sizes in the final step of the manufacturing process of the thick film capacitor array 10. You may do it.

The insulating substrate 1 is not limited to alumina ceramic, but may be a low-temperature fired glass ceramic mixed with glass, for example. Further, a multilayer circuit board having a predetermined wiring formed therein may be used as the insulating substrate 1.

The common lower electrode 2 and its lead portion 2x
Is a method in which a conductive paste of an Ag-based material (Ag alone or an Ag alloy such as Ag-Pd or Ag-Pt) is printed in a predetermined pattern, dried, and baked. still,
As the electrode material, in addition to Ag-based materials, Pt, Au, C
u, Ni or the like may be used.

The thick film dielectric layers 3 a and 3 b are formed independently so as to cover the common lower electrode 2. Specifically, for example, a dielectric paste formed by homogeneously mixing a powder of a lead relaxer material or a titanium-based material with an organic vehicle is printed in a predetermined shape by screen printing, and then dried and fired. It forms by doing. The thickness formed by each process of printing, drying, and firing the dielectric paste is 10 to 20 μm. Incidentally, in order to increase the thickness of the thick film dielectric layers 3a and 3b, the respective processes of printing, drying and baking may be repeated by the number of layers. still,
The firing temperature is set to about 9 in consideration of oversintering of the common lower electrode 2.
It is baked at around 00 ° C. A small amount of glass may be added to improve the sinterability of the above-mentioned dielectric paste. Further, the thick film dielectric layer 3 has a laminated structure, and the upper electrodes 4a to 4a
The dielectric layer in contact with d may be left in an unfired state, and may be sintered together with the upper electrodes 4a to 4d.

The upper electrodes 4a to 4d and the lead portions 4w to 4z have two independent thick film dielectric layers 3a,
3b. For example, the upper electrodes 4a and 4b are arranged side by side in the X direction on the thick dielectric layer 3a, and the upper electrodes 4c and 4d are formed on the thick dielectric layer 3b. They are juxtaposed in the X direction. Note that the upper electrodes 4a to 4d and the lead portions 4w to 4z are similar to the common lower electrode 2 in that
g, Pt, Au, Cu, Ni, etc. are used.

The protective layer 5 is formed by printing a glass paste made of crystallized glass or amorphous glass and baking the glass paste. The protective layer 5 preferably has a two-layer structure of a crystallized glass layer and an amorphous glass layer, each having a thickness of, for example, about 20 μm.

In the present invention, the thick film dielectric layers 3a and 3b are separately formed on the common lower electrode 2 independently, and one of them is formed on each of the thick film dielectric layers 3a and 3b. Two upper electrodes 4a to 4b in the direction, for example, the X direction,
4c to 4d are arranged and formed. That is, a dielectric layer is not formed between the two thick film dielectric layers 3a and 3b, and a groove is formed to expose the common lower electrode 2.

By adopting such a structure, two capacitor elements C constituted by one thick film dielectric layer 3a are formed.
1 and C2, and between two capacitor elements C3 and C4 composed of another thick-film dielectric layer 3b, the difference in the sintering state between the peripheral portion and the internal portion of the thick-film dielectric layers 3a and 3b. The variation in capacitance characteristics caused by the above can be reduced.

This is because the thick film dielectric layers 3a and 3b, which are divided and independent from each other, have a peripheral portion and a central portion (inside) as compared with the common dielectric layer 53 formed continuously as in the prior art.
This is because the difference in the sintering reaction can be reduced.

Further, even if there is a slight difference in the sintering state between the peripheral portion and the central portion (inside) of the thick film dielectric layers 3a, 3b, for example, Δ, the upper electrodes 4a, 4b are applied. It is possible to set conditions that approximate the sintering state of the thick film dielectric layer 3a at the site. That is, unlike the conventional case, the upper electrodes 54b and 54c on the inner side formed on the common dielectric layer 53 where the sintering reaction has not sufficiently proceeded are not present. Thereby, the sintering property of the thick film dielectric layer 3a can be made substantially the same between the capacitor element C1 and the capacitor element C2. Variations in capacitance characteristics obtained from the elements C1 and C2 can be suppressed. Similarly, the same applies to the capacitor element C3 and the capacitor element C4, so that the variation in the capacitance characteristics obtained from the four capacitor elements C1 to C4 can be suppressed.

As described above, the width of the groove dividing the thick film dielectric layers 3a and 3b affects the sinterability of the thick film dielectric layers 3a and 3b. The groove width is 50 in consideration of sinterability.
It is sufficient if there is an interval of μm or more. The upper limit is practically 1 m in consideration of the high density of the capacitor array 10.
m is the limit.

FIG. 3 is a plan view of the second embodiment (an example in which capacitor elements are arranged in one direction and the other direction).

In this embodiment, four upper electrodes 41a to 41d and 42a to 42d are formed on two thick film dielectric layers 3a and 3b formed on the common lower electrode 2, respectively. On one thick-film dielectric layer 3a, a total of four upper electrodes 41a, 41b and 42a, 42b are arranged, two each in the X direction and the Y direction. That is, the upper electrodes 41a, 41b and 42 are arranged in a matrix (2 rows × 2 examples).
a and 42b are arranged. Similarly, on the other thick film dielectric layer 3b, a total of four upper electrodes 41c, 41d and 42c, 42d are respectively arranged in the X direction and the Y direction. That is, the upper electrodes 41c, 41d and 42c, 42d are arranged in a matrix (2 rows × 2 examples).

A part of the upper electrodes 41a to 41d is formed as a lead portion 41w to 41z, for example, as shown in FIG.
It extends below the thick film dielectric layers 3a, 3b. Also,
A part of the upper electrodes 42a to 42d is
42z, for example, in the figure, the thick film dielectric layers 3a, 3b
Extends above.

Therefore, the thick film capacitor array 30
Are capacitor elements C11, C12, C21 and C22 using the thick-film dielectric layer 3a as a dielectric layer, and the thick-film dielectric layer 3b
Elements C31, C32, and C4 each having a dielectric layer
It is composed of a total of eight elements, namely C1 and C42.

Such upper electrodes 41a to 41d, 42
Also in the arrangement structure of a to 42d, each of the upper electrodes 41a to 41d
Two sides of 41d and 42a to 42d are thick film dielectric layers 3a,
The difference in the sintering state between the periphery and the inner side of the thick film dielectric layers 3a, 3b, which can be located on the outer peripheral side of the upper electrode 3b, is set to be substantially the same for each of the upper electrodes 41a to 41d, 42a to 42d. it can. As a result, the capacitor elements C11, C11
12, C21, C22, C31, C32, C41, C4
Harassment of the capacitance characteristic of No. 2 can be reduced.
1 to 3, the extending direction (X
Direction), two thick film dielectric layers 3a and 3b are formed. In addition to the two thick film dielectric layers, one or more thick film dielectric layers are further formed in a matrix-like manner. No problem. The thickness of the thick dielectric layers 3a and 3b may be a single layer or a structure in which a plurality of layers are stacked in order to obtain a desired capacitance. In addition, the thick dielectric layers 3a, 3a
Since b has a layered structure, baking treatment may be performed for each layer, or printing and drying of the dielectric paste may be repeated a plurality of times, and then baking treatment may be performed collectively.

The lead portions 2x of the common lower electrode 2 and the lead portions 4w-4z, 41w-41z, 42w-42 of the upper electrodes 4a-4d, 41a-41d, 42a-42d.
z may be routed from the end surface of the insulating substrate 1 to the back surface of the substrate, and another passive element connected to each capacitor element may be provided on the back surface of the insulating substrate 1. For example, a resistor element or a coil element may be formed on the back surface of the insulating substrate 1 so as to correspond to the capacitor element, so that a CR composite array component or an LC composite array component may be formed.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The thick film capacitor array 10 shown in FIGS.
The electrode width Y1 in the Y direction is 280 μm (thickness 10 to 15).
μm), the thickness of one thick film dielectric layer 3a, 3b is 40 to 45 μm, and the width X2 in the X direction is 230 to 300 μm (thickness 10 to 15 μm).
m) Upper electrodes 4a to 4d were formed. The upper electrodes 4a and 4a adjacent to each other in the same thick dielectric layer 3a, 3b
b, the distance X3 in the X direction between 4c and 4d is 600 μm,
The distance X1 in the X direction between the end of the thick film dielectric layer 3a and the end of the upper electrode 4a was set to 300 μm, and the distance X4 between the two thick film dielectric layers 3a and 3b in the X direction was set to 500 μm. Thus, the capacitance of one capacitor element C1 to C4 is 4
500 thick film capacitor arrays 10 each having a capacitance of 7 pF were prepared, and variations in capacitance characteristics of the capacitor elements C1 and C2 (C3 and C4) were examined.

At the same time, a conventional thick film capacitor array 50 having the same electrode dimensions and having a series of thick film dielectric layers 53 over four capacitor elements C51 to C54 was examined.

As a result, the conventional thick film capacitor array 5
0, the capacitor elements C51, C54 located on the outside
The average value of the capacitance characteristics of the capacitor elements C52 and C53 located inside from the average value of the capacitance characteristics of Example 1 was reduced by 6 to 22%, and the variation of the capacitance characteristics was large. In contrast,
In the thick film capacitor array 10 of the present invention, the difference between the average values of the capacitance characteristics of the capacitor elements C1 and C2 (C3 and C4) is 1
%.

[0048]

As described above, the independent thick film dielectric layer is provided on the common lower electrode, and the upper electrodes are formed on the thick film dielectric layer so that at least two upper electrodes are arranged in at least one direction. Have been. For this reason, the influence of the variation in the capacitance characteristics of the capacitor elements due to the variation in the sintering state of the thick-film dielectric layer can be reduced, and the capacitance characteristics of each capacitor element become very stable.

[Brief description of the drawings]

FIG. 1 is a sectional view of a thick film capacitor array of the present invention.

FIG. 2 is a plan view of the thick film capacitor array of the present invention.

FIG. 3 is a plan view of another thick film capacitor array of the present invention.

FIG. 4 is a cross-sectional view of a conventional thick film capacitor array.

FIG. 5 is a plan view of a conventional thick film capacitor array.

[Explanation of symbols]

10, 30, 50: thick film capacitor array 1, 51: insulating substrate 2, 52: common lower electrode 2x ... lead-out portions 3a, 3b, 53 ... thick film dielectric layers 4a to 4d, 41a to 42d , 54a to 54d, upper electrode 4w to 4z, 41w to 42z, lead portion 5, 55, protective layer C1 to C4, capacitor element

Claims (2)

[Claims] 1. A thick-film capacitor array comprising: a plurality of capacitor elements each comprising a common lower electrode, a thick-film dielectric layer formed by baking a dielectric paste, and an upper electrode on an insulating substrate; The thick film capacitor array, wherein the body layer is divided into a plurality of parts, and the two upper electrodes are arranged in at least one direction on each of the divided thick film dielectric layers. 2. The device according to claim 1, wherein two upper electrodes are arranged on the thick dielectric layer in one direction and another direction orthogonal to the one direction.
A thick-film capacitor array as described.