JP4725263B2 - Transfer gate circuit and integrated circuit device and electronic equipment using the same - Google Patents

Description

  The present invention relates to a transfer gate circuit, an integrated circuit device using the same, and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

  In addition, when a user mounts a display driver on a liquid crystal panel to manufacture a display device, various adjustments are necessary on the display driver side. For example, by adjusting the display driver according to the specifications of the panel (amorphous TFT, low-temperature polysilicon TFT, QCIF, QVGA, VGA, etc.) and driving conditions, or by adjusting the display characteristics so that there is no variation between the panels. is there. The IC manufacturer also needs to adjust the oscillation frequency and output voltage, switch to redundant memory, etc. during IC inspection.

Conventionally, adjustment on the user side has been performed by an external E ² PROM (ELECTRICAL ERASABLE PROGRAMABLE READ ONLY MEMORY) and an external trimmer resistance (variable resistance). Switching to a redundant memory on the IC manufacturer side is performed by fusing a fuse element provided in the integrated circuit device.

  However, the external mounting operation of the components is complicated for the user, and the trimmer resistor is expensive, large in size, and easily broken. For the IC manufacturer side, the work of cutting the fuse element and the subsequent operation confirmation are also complicated.

  Therefore, the present inventors tried to take in the data for adjustment described above into the display driver.

  Here, as a non-volatile memory device that can be manufactured at a low cost with a simple manufacturing process as compared with a stacked gate type non-volatile memory device that requires two layers of gates, the non-volatile memory described in Patent Document 1 Storage devices have been proposed. In the nonvolatile memory device described in Patent Document 1, the control gate is an N-type impurity region in the semiconductor layer, and the floating gate electrode is formed of a conductive layer such as a single polysilicon layer (hereinafter referred to as “single-layer gate”). Type non-volatile memory device). Such a single-layer gate type nonvolatile memory device can be formed in the same manner as a process of a normal CMOS transistor because it is not necessary to stack gate electrodes.

  In order to connect this type of non-volatile memory device to the bit line, a transfer gate is used in each memory cell. The P-type and N-type MOS transistors constituting the transfer gate must be designed to satisfy the requirements required for both programming and reading.

Here, FIGS. 2 and 3 of Patent Document 2 have a gate made of two N-type MOS transistors or a gate made of two P-type MOS transistors, and only one of the two transistors of the same conductivity type is turned on. It is disclosed that the other is turned off.
JP 63-166274 A JP2000-148064

  An object of the present invention is to secure a withstand voltage in a first connection mode such as reading for turning on / off a relatively low voltage signal and a first connection mode for turning on / off a relatively high voltage signal. Another object of the present invention is to provide a transfer gate circuit in which the control of the P-type and N-type MOS transistors is changed in the second connection mode.

  Another object of the present invention is to control P-type and N-type MOS transistors at the time of programming and at the time of reading as a switch for connecting / disconnecting a bit line and a memory cell that mainly stores adjustment data set by a user It is an object to provide an integrated circuit device and an electronic device provided with a transfer gate circuit in which the above is changed.

  A transfer gate circuit according to an aspect of the present invention is provided between a first line and a second line, includes P-type and N-type MOS transistors, and connects the first line and the second line. A transfer gate to be disconnected; and a control circuit for controlling connection / disconnection at the transfer gate by controlling a voltage applied to the gates of the P-type and N-type MOS transistors of the transfer gate. In the first connection mode, the control circuit applies different logic voltages to the gates of the P-type and N-type MOS transistors to turn on both the P-type MOS transistor and the N-type MOS transistor. In the second connection mode in which a voltage higher than that in the first connection mode is supplied to the first or second line, the P-type and By applying a voltage of the same logic to the gate of the mold MOS transistors, the P-type MOS transistor is turned on, characterized in that turns off the N-type MOS transistor.

  An N-type MOS transistor has an off breakdown voltage that is a breakdown voltage when a channel current does not flow (that is, when the channel current does not flow) than an on breakdown voltage that is the lowest breakdown voltage in the entire operation region (that is, when the transistor is on). Is higher. In order to increase the ON breakdown voltage, the gate length must be increased. If the gate length is increased, the current driving capability is reduced, so that the gate width must be increased, and the size of the N-type MOS transistor is eventually increased.

  In one embodiment of the present invention, the N-type MOS transistor is turned off in the second connection mode in which a voltage higher than that in the first connection mode is supplied to the first or second line. Therefore, in the second connection mode, the N-type MOS transistor can use the off breakdown voltage, and the gate length and the gate width of the N-type MOS transistor can be shortened to reduce the size. In the second connection mode, current driving is performed only by the P-type MOS transistor.

  From the above, in one embodiment of the present invention, the voltage supplied to the first or second line in the second connection mode is a breakdown voltage when no channel current flows through the N-type MOS transistor. The voltage may be lower than the off breakdown voltage.

  In one embodiment of the present invention, the voltage supplied to the first or second line in the second connection mode is higher than the power supply voltage applied to the gate of the N-type MOS transistor in the first connection mode. In addition, it can be higher than the ON breakdown voltage. Thus, high speed driving can be realized.

  In one embodiment of the present invention, the channel length and the channel width of the N-type MOS transistor can be designed so as to satisfy the current driving capability required in the first connection mode.

  This is because the off-breakdown voltage can be used in the second connection mode, so that the on-breakdown voltage only needs to be considered in the first connection mode. The channel length and the channel width of the N-type MOS transistor may be determined so as to satisfy the current drive capability in the first connection mode under the condition of satisfying the ON breakdown voltage in the second connection mode.

  An integrated circuit device according to another aspect of the present invention includes a plurality of memory cells connected to one of a plurality of word lines, a plurality of bit lines connected to the plurality of memory cells, and the plurality of word lines. A memory block including a word line decoder for selecting at least one of the plurality of memory cells, each of the plurality of memory cells having a transfer gate connected to one of the plurality of bit lines, A P-type and N-type MOS transistor connected to the word line decoder, and when the plurality of memory cells connected to one of the plurality of word lines are selected, in a read and erase mode Then, different voltage voltages are applied to the gates of the P-type and N-type MOS transistors from the word line decoder, and the P-type MOS transistor and the N-type MOS transistor are applied. In the program mode, the same logic voltage is applied from the word line decoder to the gates of the P-type and N-type MOS transistors to turn on the P-type MOS transistor, and the N-type MOS transistor is turned on. The transistor is turned off.

  Another aspect of the present invention defines an integrated circuit device in which a transfer gate according to one aspect of the present invention is connected between a memory cell and a bit line. Unlike the read and erase modes corresponding to the first connection mode, only the P-type MOS transistor is turned on in the program mode corresponding to the second connection mode. Thereby, the off breakdown voltage can be used as the breakdown voltage of the N-type MOS transistor in the program mode.

  In another aspect of the present invention, the maximum voltage supplied to the bit line connected to the selected memory cell in the program mode is lower than the off breakdown voltage of the N-type MOS transistor, and the gate of the N-type MOS transistor in the read and erase modes. Higher than the power supply voltage applied to the capacitor, and further higher than the ON breakdown voltage. As a result, the programming speed during programming can be increased while ensuring the breakdown voltage.

  In another aspect of the present invention, one word line can be hierarchized into one main word line and a plurality of sub word lines. In this case, the word line decoder means a sub word line decoder provided between one main word line and one of a plurality of sub word lines.

  In another aspect of the present invention, each of the plurality of memory cells includes a write / read transistor and an erase transistor formed on a semiconductor substrate, and a floating gate shared by the gates of the write / read transistor and the erase transistor. And a control gate formed in an impurity region formed in the semiconductor substrate and in a position where the floating gate is opposed to the insulating layer through an insulating layer, and the write / read transistor and the bit line The transfer gate can be connected between the two.

  Although it has a “single layer gate” structure with only a floating gate, it differs from the prior art in that writing and erasing are performed by MOS transistors having different channel conductivity types. Compared with the case where erasing is performed at the same location as the writing region, the withstand voltage against the erasing voltage can be improved.

  In another aspect of the present invention, when the semiconductor substrate is P-type, an N-type deep well formed on the semiconductor substrate, a P-type surface well formed on the N-type deep well, and the N-type A triple well structure formed by an N-type annular surface well surrounding the P-type surface well on a deep well, and an outermost impurity region formed in the P-type surface well and the N-type annular surface well The control gate, the write / read transistor, and the N-type MOS transistor are formed in the P-type surface layer well, and the N-type annular surface well has two long side regions, The erase transistor is formed on one side, an N-type strip surface layer well is formed adjacent to the other of the two long side regions, and the P-type MOS is formed on the N-type strip surface layer well. It is possible to form a transistor.

  Thus, the memory cell is formed with a triple well structure. In particular, by surrounding the P-type surface layer well where the write / read transistor and the control gate are formed with the N-type annular surface well where the erase transistor is formed, and disposing the N-type deep layer well below them, The P-type surface well can be electrically separated from the semiconductor substrate, and both can be set to different potentials.

  In one aspect of the present invention, the memory cell array block in which the plurality of memory cells are arranged is divided into a first region and a second region with a central region as a boundary, and the plurality of memory cells arranged in the first region and the second region are arranged. Two main word line drivers that respectively drive main word lines of the memory cells and two control gates that respectively drive the control gates of the plurality of memory cells arranged in the first and second regions are provided. be able to.

  In this way, the length of the word line and the control gate can be halved to prevent signal delay, and it can be driven at the shortest distance from each driver.

  In another aspect of the present invention, the memory cell array block has a plurality of column blocks divided in a direction in which the plurality of main word lines extend, and the one sub word line is provided for each of the plurality of column blocks. Each of the plurality of column blocks has a memory cell region and a sub word line decoder region further divided in a direction in which the plurality of word lines extend, and the memory cell region and the sub word line decoder region are It can be formed in a common well region formed on the semiconductor substrate.

  Thus, the memory cell region and the sub word line decoder region do not have to be provided with separate wells, so that the area of the memory cell array block can be reduced.

  In this case, a transistor forming the sub word line decoder disposed in the sub word line decoder region can be formed in the P-type surface layer well and the N-type band-shaped surface layer well.

  Still another aspect of the present invention defines an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Integrated Circuit Device FIG. 1 shows a configuration example of the integrated circuit device 10 of the present embodiment. In the present embodiment, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is defined as a first direction D1, and the opposite direction of D1 is defined as a third direction D3. Yes. The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 1, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side SD1. May be.

  As shown in FIG. 1, the integrated circuit device 10 of this embodiment includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. In this embodiment, circuit blocks CB1 to CBN are arranged in the D1 direction.

  The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). In the present embodiment in which the integrated circuit device 10 is a display driver, a programmable ROM block (memory block in a broad sense) is essential, and a circuit block to which data from the programmable ROM block goes, for example, a logic circuit (gate array block). Alternatively, a power circuit block is essential.

  For example, FIG. 2 shows examples of various types of display drivers and circuit blocks incorporated therein.

  3A and 3B show examples of a planar layout of the integrated circuit device 10 of the display driver of this embodiment. 3A and 3B are examples for an amorphous TFT panel with a built-in memory. FIG. 3A targets a display driver for, for example, QCIF and 32 gradations, and FIG. The display driver for gradation is targeted.

  In FIG. 3A, the programmable ROM 20 is between the power supply circuit PB and the logic circuit LB. In other words, the programmable ROM 20 is adjacent to each block of the power supply circuit PB and the logic circuit LB in the direction D1.

  On the other hand, in FIG. 3B, the block of the programmable ROM 20 is adjacent to the block of the power supply circuit PB in the direction D1.

  This is because the main destination of data read from the programmable ROM 20 is the power supply circuit PB and / or the logic circuit LB. That is, data from the programmable ROM 20 can be supplied to the power supply circuit PB and / or the logic circuit LB through a short path. The data read from the programmable ROM 20 will be described later.

  3A and 3B, in addition to the three blocks described above, memories MB1 to MB4 in which display data is stored, data drivers DB1 to DB4 arranged adjacent to each memory, and gradation voltages The generation circuit GB and one or two scan drivers SB (or SB1, SB2) are included.

  FIG. 4A shows an example of a cross-sectional view along the direction D2 of the integrated circuit device 10 of the present embodiment. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. W is the width of the integrated circuit device 10 in the direction D2.

  In this embodiment, as shown in FIG. 4A, in the direction D2, no other circuit block is interposed between the circuit blocks CB1 to CBN and the output side and input side I / F regions 12 and 14. . Therefore, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 can be satisfied, and a narrow integrated circuit device can be realized. Specifically, the width W in the D2 direction can be set to W <2 mm, and more specifically, W <1.5 mm. In consideration of chip inspection and mounting, it is desirable that W> 0.9 mm. The length LD in the long side direction (see FIGS. 3A and 3B) can be 15 mm <LD <27 mm. The chip shape ratio SP = LD / W can be set to SP> 10, and more specifically, SP> 12.

  FIG. 4B shows a comparative example in which two or more circuit blocks are arranged along the direction D2. In the D2 direction, a wiring region is formed between the circuit blocks or between the circuit block and the I / F region. Therefore, the width W of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a slim elongated chip cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened, and the output pitch becomes narrow, which makes mounting difficult.

  In the present embodiment, since the plurality of circuit blocks CB1 to CBN are arranged along the direction D1, it is possible to easily cope with a change in product specifications and the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved.

2. Programmable ROM data 2.1. Grayscale voltage data In the integrated circuit device of this embodiment, the data stored in the programmable ROM 20 may be adjustment data for adjusting the grayscale voltage. Then, the gradation voltage generation circuit (γ correction circuit) generates a gradation voltage based on the adjustment data stored in the programmable ROM 20. Hereinafter, the operation of the gradation voltage generation circuit (γ correction circuit) will be described.

  FIG. 5 shows a programmable ROM 20, a logic circuit LB, and a gradation voltage generation circuit (γ correction circuit) GB among the circuit blocks shown in FIG.

  Adjustment data for adjusting the gradation voltage is input to the programmable ROM 20 by, for example, a user (display device manufacturer). The adjustment register 126 is provided in the logic circuit LB. The adjustment register 126 can set various setting data that can adjust the gradation voltage. By reading the adjustment data stored in the program ROM 20 into the adjustment register 126, the setting data is output. The setting data read from the adjustment register 126 is supplied to the gradation voltage generation circuit GB.

  The gradation voltage generation circuit GB includes a selection voltage generation circuit 122 and a gradation voltage selection circuit 124. The selection voltage generation circuit 122 (voltage division circuit) outputs a selection voltage based on the high power supply voltages VDDH and VSSH generated by the power supply circuit PB. Specifically, the selection voltage generation circuit 122 includes a ladder resistor circuit having a plurality of resistor elements connected in series. A voltage obtained by dividing VDDH and VSSH by the ladder resistor circuit is output as a selection voltage. The gradation voltage selection circuit 124 selects, for example, 64 voltages in the case of 64 gradations from among the selection voltages based on the gradation characteristic setting data supplied from the adjustment register 126, to Output as regulated voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel.

  The adjustment register 126 may include an amplitude adjustment register 130, a tilt adjustment register 132, and a fine adjustment register 134. In the amplitude adjustment register 130, the inclination adjustment register 132, and the fine adjustment register 134, gradation characteristic data is set.

  For example, by reading the 5-bit setting data stored in the programmable ROM 20 to the amplitude adjustment register 130, the voltage levels of the power supply voltages VDDH and VSSH change as shown by B1 and B2 in FIG. The voltage amplitude can be adjusted.

  Further, by reading the setting data stored in the programmable ROM 20 to the inclination adjustment register 132, as shown in B3 to B6 of FIG. The inclination of the characteristic can be adjusted. That is, the resistance values of the resistance elements RL1, RL3, RL10, and RL12 constituting the ladder resistance change based on the 4-bit setting data VRP0 to VRP3 set in the inclination adjustment register 132, and the inclination adjustment as shown in B3 is performed. Is possible.

  Further, by reading out to the fine adjustment register 134 stored in the programmable ROM 20, as shown in B7 to B14 of FIG. Adjustment is possible. That is, based on the 3-bit setting data VP1 to VP8 set in the fine adjustment register 134, the 8to1 selectors 141 to 148 select one of eight taps of the eight resistance elements RL2, RL4 to RL9, and RL11. Two taps are selected, and the voltages of the selected taps are output as VOP1 to OP8. As a result, fine adjustment as shown in B7 to B14 of FIG.

  The gradation amplifier unit 150 outputs gradation voltages V0 to V63 based on the outputs VOP1 to VOP8 of the 8to1 selectors 142 to 148, VDDH, and VSSH. Specifically, the gradation amplifier unit 150 includes first to eighth impedance conversion circuits (operational amplifiers connected to voltage followers) to which VOP1 to VPOP8 are input. Then, for example, by dividing the output voltage of the adjacent impedance conversion circuit among the first to eighth impedance conversion circuits by resistance, the gradation voltages V1 to V62 are generated.

  By performing the adjustment as described above, it is possible to obtain the optimum gradation characteristic (γ characteristic) according to the type of the display panel, and to improve the display quality. In the present embodiment, the programmable ROM 20 stores adjustment data for obtaining optimum gradation characteristics (γ characteristics) according to the type of display panel. Therefore, it is possible to obtain optimum gradation characteristics (γ characteristics) for each type of display panel, and to improve display quality.

  In the present embodiment, the programmable ROM 20 and the logic circuit block LB are disposed adjacent to each other along the first direction D1. In this way, the adjustment data signal line from the programmable ROM 20 can be connected to the logic circuit block LB through a short path, and therefore an increase in chip area caused by the wiring region can be prevented.

  Furthermore, in this embodiment, as shown in FIG. 3A, the logic circuit block LB and the gradation voltage generation circuit block GB may be arranged adjacent to each other along the direction D1. In this way, since the signal line from the logic circuit block LB can be connected to the gradation voltage generation circuit block GB through a short path, an increase in chip area due to the wiring region can be prevented.

2.2. Panel Setting Voltage Data In the integrated circuit device of this embodiment, the data stored in the programmable ROM 20 may be adjustment data for adjusting the panel voltage. The adjustment data for adjusting the panel voltage may be data for adjusting the voltage applied to the counter electrode VCOM, for example.

  FIG. 7 shows a block diagram of a configuration example of a display device including an electro-optical device. The display device of FIG. 7 realizes a function as a liquid crystal device. The electro-optical device realizes a function as a liquid crystal panel.

  The liquid crystal device 160 (display device in a broad sense) includes a liquid crystal panel (display panel in a broad sense) 162 using TFTs as switching elements, a data line driving circuit 170, a scanning line driving circuit 180, a controller 190, and a power supply circuit 192. .

  The gate electrode of the TFT is connected to the scanning line G, the source electrode of the TFT is connected to the data line S, and the drain electrode of the TFT is connected to the pixel electrode PE. A liquid crystal capacitor CL (liquid crystal element) and an auxiliary capacitor CS are formed between the pixel electrode PE and a counter electrode VCOM (common electrode) facing each other with a liquid crystal element (electro-optical material in a broad sense) interposed therebetween. . Then, liquid crystal is sealed between the active matrix substrate on which the TFT, the pixel electrode PE, and the like are formed, and the counter substrate on which the counter electrode VCOM is formed, according to the applied voltage between the pixel electrode PE and the counter electrode VCOM. The transmittance of the pixel is changed.

  In the present embodiment, the programmable ROM 20 may store adjustment data for adjusting the voltage applied to the counter electrode VCOM. Based on the adjustment data, the voltage of the power supply circuit 192 is adjusted and applied to the counter electrode VCOM. Display quality can be improved by setting the adjustment data for each display panel.

  In the present embodiment, as shown in FIG. 3A, the programmable ROM 20 and the power supply circuit block PB are arranged adjacent to each other along the first direction D1. In this way, the adjustment data signal line from the programmable ROM 20 can be connected to the power supply circuit block PB through a short path, and therefore an increase in chip area due to the wiring region can be prevented.

2.3. Other User Setting Information In the integrated circuit device of the present embodiment, the data stored in the programmable ROM 20 is not limited to these. For example, the programmable ROM 20 may store adjustment data for adjusting a given timing as display driver adjustment data. That is, various control signals for controlling the refresh cycle and display timing of the memory may be generated based on the adjustment data. Alternatively, the programmable ROM 20 may store adjustment data for adjusting the startup sequence setting of the integrated circuit device as display driver adjustment data.

  The above adjustment data is programmed by the user, but data adjusted by the IC manufacturer in the IC manufacturing / inspection process may be stored.

3. Programmable ROM
3.1. Overall Configuration of Programmable ROM FIG. 8 shows a programmable ROM 20 arranged in the integrated circuit device 10. The programmable ROM 20 roughly includes a memory cell array block 200 and a control circuit block 202. The memory cell array block 200 and the control circuit block 202 are adjacent to each other in the direction D1 that is the long side direction of the integrated circuit device 10.

  The memory cell array block 200 is provided with a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL extend along the direction D2 which is the short side direction of the integrated circuit device 10. The plurality of bit lines BL extend along the direction D1 which is the long side direction of the integrated circuit device 10. The reason is as follows.

  The storage capacity of the programmable ROM 20 can be increased or decreased for each model depending on the specifications on the user side. In the present embodiment, the increase or decrease in storage capacity is dealt with by changing the number of word lines WL. That is, the length of the word line WL is constant even when the storage capacity is changed. As a result, the number of memory cells connected to one word line WL is fixed. If the number of word lines WL is increased, the storage capacity of the program ROM 20 is increased. Even if the storage capacity of the program ROM 20 is increased, the memory cell array block 200 does not become longer in the short side direction (D2 direction) of the integrated circuit device 10. Therefore, the slim shape described in FIG. 1 can be maintained.

  As another reason, even if the storage capacity of the programmable ROM 20 is increased or decreased, the control circuit block 202 does not become longer in the short side direction (D2 direction) of the integrated circuit device 10. Therefore, the slim shape described in FIG. 1 can be maintained. In FIG. 9 as a comparative example, the memory cell array block 200 becomes longer in the short side direction (D2 direction) of the integrated circuit device 10 as a result of increasing the storage capacity of the program ROM 20. In this case, the circuit design of the control circuit block 202 must be redone. However, this is not necessary in the layout of FIG. 8 of the present embodiment in which the layout of FIG. 9 as a comparative example is rotated by 90 °. Therefore, even when the storage capacity of the programmable ROM 20 is increased or decreased, the design efficiency of the control circuit block 202 can be improved.

  As yet another reason, the bit line BL extends along the direction D1 which is the long side direction of the integrated circuit device 10, and the control circuit block 202 can be disposed on the extended line of the bit line BL. One function of the control circuit block 202 is to detect data read through the bit line BL by a sense amplifier and supply it to other circuit blocks. With the above-described layout, data read from the memory cell array block 200 can be supplied to the control circuit block 202 through a short path as compared with the comparative example of FIG.

3.2. Single Layer Gate Memory Cell FIG. 10 is a plan view of a single layer gate memory cell MC disposed in the memory cell array block 200 shown in FIG. FIG. 11 is an equivalent circuit diagram of a single-layer gate memory cell MC.

  In FIG. 10, this memory cell MC has a control gate portion 210, a write / read transistor 220, and an erase transistor 230, and a floating gate FG formed of polysilicon extends in these three regions. . As shown in FIG. 11, the memory cell MC has a first transfer gate 240 provided between the drain of the write / read transistor 220 and the bit line BL. The first transfer gate 240 connects / disconnects the drain of the write / read transistor 220 and the bit line BL based on the logic of the sub word line SWL and the logic of the inverted sub word line XSWL. The first transfer gate 240 includes a P-type MOS transistor Xfer (P) and an N-type MOS transistor Xfer (N). When the word lines are not hierarchized, the first transfer gate 240 is controlled by the logic of the word line and the inverted word line.

  The single-layer gate is an N-type (second conductivity type in a broad sense) impurity layer NCU in which a control gate CG is formed in a P-type well PWEL of a semiconductor substrate (for example, P-type, first conductivity type in a broad sense). This means that only one polysilicon floating gate FG is formed. That is, the two-layer gate of the control gate CG and the floating gate FG is not formed of polysilicon. A coupling capacitor is formed by the control gate CG and the floating gate FG facing the control gate CG.

  One embodiment of the present invention also has a “single layer gate” structure with only a floating gate, but differs from the prior art in that writing and erasing are performed by MOS transistors having different channel conductivity types. Thus, the advantage of performing writing and erasing with different MOS transistors is as follows. Erasing is performed by applying a voltage to a portion with small capacitive coupling and setting the portion with large capacitive coupling to 0 V, thereby extracting electrons injected into the floating gate by the FN tunnel current. As a conventional single layer gate type nonvolatile memory device, there is a type in which writing and erasing are performed by the same MOS transistor (same location). In a single-layer gate type nonvolatile memory device, the capacity between the control gate and the floating gate electrode needs to be larger than the capacity of the writing area, so the capacity of the writing area is designed to be small. ing. That is, when erasing, a large voltage for erasing must be applied to a portion having a small capacitive coupling.

  However, in particular, in the case of a fine nonvolatile memory device, a sufficient breakdown voltage cannot be ensured with respect to the voltage applied at the time of erasing, and the MOS transistor may be destroyed. Therefore, in the programmable ROM block according to the present embodiment, writing and erasing are performed by different MOS transistors, and the channel conductivity types of the respective MOS transistors are different. If, for example, a P-channel type MOS transistor is formed as the MOS transistor for erasing, the MOS transistor for erasing is formed on the N-type well. Therefore, at the time of erasing, a voltage up to the junction breakdown voltage of the N-type well and the substrate (semiconductor layer) can be applied. As a result, the withstand voltage against the erasing voltage can be improved as compared with the case where erasing is performed at the same location as the writing region, miniaturization is achieved and reliability is improved.

  In the integrated circuit device 10 of the present embodiment, there are an LV (Low Voltage) system (for example, 1.8 V), an MV system (Middle Voltage) system (for example, 3 V), and an HV (High Voltage) system (for example, 20 V). However, the memory cell MC has an MV-type withstand voltage structure. The write / read transistor 220 and the N-type MOS transistor Xfer (N) are MV N-type MOS transistors, and the erase transistor 230 and the P-type MOS transistor Xfer (P) are MV P-type MOS transistors.

  FIG. 12 shows a data write (program) operation to the memory cell MC. For example, 8V is applied to the control gate CG, and for example, 8V is applied to the drain of the write transistor 220 via the bit line BL and the first transfer gate 240. The potential of the source of the write / read transistor 220 and the P-type well PWEL is 0V. Thereby, hot electrons are generated in the channel of the write / read transistor 220, and the electrons are drawn into the floating gate of the write / read transistor 220. As a result, the threshold value Vth of the write / read transistor 220 becomes higher than the initial state as shown in FIG.

  On the other hand, at the time of erasing, as shown in FIG. 14, for example, 20V is applied to the drain of the erasing transistor 230, and the control gate CG is grounded. The potential of the source of the erase transistor 230 and the N-type well NWEL is, for example, 20V. Thus, since a high voltage is applied between the control gate CG and the N-type well NWEL, electrons in the floating gate FG are drawn to the N-type well NWEL side. Data is erased by this FN (Fowler-Nordheim) tunnel current. At this time, as shown in FIG. 15, the threshold value Vth of the write / read transistor 220 is a negative threshold value lower than the initial state.

  At the time of data reading, as shown in FIGS. 16 and 17, the control gate CG is grounded and 1 V, for example, is applied to the drain of the write / read transistor 220. At this time, the potential of the source of the write / read transistor 220 and the P-type well PWEL is 0V. In the write state shown in FIG. 16, since the floating gate FG has an excess of electrons, no current flows through the channel. On the other hand, in the erased state shown in FIG. 17, since the floating gate FG has excess holes, electrons flow through the channel. Data can be read with or without the current.

In the programmable ROM 20 of the present embodiment, as described above, the user mainly stores adjustment data instead of the conventional E ² PROM or trimmer resistor, or the IC manufacturer stores the adjustment data at the manufacturing / inspection stage. Used as a memory. For this reason, it is sufficient to compensate the number of rewrites about 5 times.

3.3. Memory cell array block 3.3.1. Planar Layout FIG. 18 is an enlarged plan view showing the memory cell array block 200 and a part thereof. In the memory cell array block 200, a formation region 250 of the main word line driver MWLDrv and the control gate line driver CGDrv is provided at the center position in the short side direction (D2 direction) of the integrated circuit device 10. With this formation region 250 as a boundary, the memory cell array block 200 is divided into two parts, a first region and a second region. In the present embodiment, eight column blocks are provided in each of the first and second regions, and a total of 16 column blocks 0 to 15 are provided. Eight memory cells MC are arranged in the D2 direction in one column block. In the present embodiment, the length W of the short side of the integrated circuit device 10 shown in FIG. 3A is set to 800 μm, and the memory cell MC accommodated in the length W is based on the length of one memory cell MC in the D2 direction. The number of memory cells is 16 columns × 8 memory cells. In order to increase or decrease the storage capacity of the programmable ROM 20, the number of word lines may be increased or decreased. In addition, two main word line drivers MWLDrv and two control gate line drivers CGDrv are provided, one for each of the divided areas. One main word line driver MWLDrv and control gate line driver CGDrv may be provided at the end of the memory array block 200.

  In FIG. 18, a total of 34 main word lines MWL driven by one main word line driver MWLDrv are provided. Two are test main word lines T1 and T0 connected to memory cells for test bits of the IC manufacturer, and the remaining 32 are user main word lines MWL0 to MWL31. Further, a control gate line CG (N-type impurity layer NCU shown in FIG. 10) driven by one control gate line driver CGDrv extends in parallel with the main word line MWL.

  Each of the 16 column blocks 0 to 15 has a memory cell region 260 and a sub word line decoder region 270. The sub word line decoder area 270 is provided with a sub word line decoder SWLDec connected to each main word line MWL. In the area of the control circuit block 202, a column driver CLDrv is provided for each sub word line decoder area 270. The output lines of the column driver CLDrv are commonly connected to all the sub word line decoders SWLDec arranged in each sub word line decoder region 270.

  A sub word line SWL and an inverted sub word line XSWL extend from one sub word line decoder SWLDec toward the adjacent memory cell region 260. In one column block, for example, eight memory cells MC commonly connected to the sub word line SWL and the inverted sub word line XSWL are arranged in the memory cell region 260.

  In the layout shown in FIG. 18, one main word line MWL is selected by the main word line driver MWLDrv, and one column block is selected by the column driver CLDrv, so that one sub word line decoder SWLDec is selected. The Eight memory cells MC connected to the selected sub word line decoder SWLDec are selected cells, and data is programmed (written) or read. When erasing data, all memory cells are selected and erased collectively.

3.3.2 Well Layout of Memory Cell Region and Sub-Word Line Decoder Region FIG. 18 shows a well layout common to the memory cell region 260 and the sub-word line decoder region 270. Three wells are used to form one memory cell MC in the memory cell region 260. One is a P-type well PWEL (first conductivity type surface layer well in a broad sense) extending in a direction (D2 direction) along the main word line MWL, and the other is an annular shape surrounding the P-type well PWEL. N-type well NWEL1 (second conductivity type annular surface layer well in a broad sense), and another one extends in the direction along the main word line MWL (D2 direction) on the side of annular N-type well NWEL1. This is an N-type well NWEL2 (second conductivity type belt-shaped surface layer well in a broad sense). One long side region of the annular N-type well NWEL1 is NWEL1-1, and the other long side region (NWEL2 side) is NWEL1-2.

  One memory cell MC is formed on three wells (PWEL, NWEL1, NWEL2) over the length region L of one memory cell shown in FIG. In the length region L in each memory cell region 260, as shown in FIG. 18, eight memory cells MC commonly connected to one sub word line decoder SWLDec are formed.

  In FIG. 18, a P-type impurity ring 280 (a first conductivity type impurity ring in a broad sense) surrounding each of the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 is provided. This will be described later. To do.

  In FIG. 18, the above-described three wells (PWEL, NWEL1, NWEL2) are also formed in the sub word line decoder region 270. However, the formation region of the transistors constituting the sub word line decoder SWLDec is on the P-type well PWEL and the strip-like N-type well NWEL2 shown as dot regions in FIG. 18, and is not formed on the annular N-type well NWEL1.

3.3.3. FIG. 19 is a planar layout of two memory cells MC adjacent to each other in FIG. FIG. 20 is a cross-sectional view of one memory cell MC, showing the CC ′ cross-section of FIG. Note that the cross section indicated by the broken line in the direction D2 among the broken lines CC ′ in FIG. 19 is omitted in FIG. Further, in the CC ′ fracture line of FIG. 19, there is a portion where the dimension in the D1 direction and the dimension in the D1 direction of FIG.

  In FIG. 19, two memory cells MC are mirror-arranged in plan view. As described above, the memory cell MC is formed across three wells (PWEL, NWEL1, and NWEL2) as shown in FIG. As shown in FIG. 20, a deep N-type well DNWEL (second conductivity type deep well in a broad sense) is provided in the lower layer inside the outer edge region of the annular N-type well NWEL1 and the lower layer of the strip-shaped N-type well NWEL2. ing. As shown in FIG. 20, since three wells (PWEL, NWEL1, NWEL2) on the deep layer N-type well DNWEL are provided with P-type or N-type impurity regions (in the broad sense, the outermost layer impurity region), The memory cell MC of the embodiment has a triple well structure. Thereby, the P-type substrate Psub and the P-type well PWEL can be set to different potentials. Note that not only the programmable ROM 20 is formed on the P-type substrate Psub, but also other circuit blocks are formed, and there is a need for application of a back gate voltage. Therefore, the potential of the P-type substrate Psub is not necessarily fixed to the ground potential. Not always.

  As shown in FIGS. 19 and 20, a floating gate FG made of polysilicon is formed on one long side region NWEL1-1 of the annular N-type well NWEL1 and an upper layer of the P-type well PWEL via an insulating film (not shown). Is formed. The floating gate FG functions as a common gate for the write / read transistor 220 formed in the PWEL and the erase transistor 230 formed in one long side region NWEL1-1 of the annular N-type well NWEL1. Further, an N-type impurity region NCU is formed in a P-type well PWEL region facing the floating gate FG via an insulating film. The N-type impurity region NCU is applied with a control gate voltage VCG and functions as a control gate CG.

  The P-type well PWEL is provided with the N-type MOS transistor Xfer (N) of the first transfer gate 240 shown in FIG. Further, a P-type MOS transistor Xfer (P) of the first transfer gate 240 is provided in the strip-shaped N-type well NWEL2. As shown in FIG. 19, a plurality of P-type MOS transistors Xfer (P) are provided, and these are connected in parallel to secure the gate width and secure the drive capability.

  In the other long side region NWEL1-2 of the annular N-type well NWEL1, only an N-type impurity region is provided, and no active element is provided. The other long side region NWEL1-2 is provided only to be connected to the one long side region NWEL1-1 and surround the P-type well PWEL in an annular shape. This is because if the other long side region NWEL1-2 is not formed, the P-type well PWEL cannot be electrically separated from the P-type substrate Psub even if the deep N-type well DNWEL is arranged.

  In the present embodiment, the P-type well PWEL, which is the upper layer of the deep N-type well DNWEL, is separated from the outer annular N-type well NWEL1. This separation space G1 is for securing a withstand voltage of 20 V between the annular N-type well NWEL1 to which 20 V is applied during erasure and the P-type well PWEL set to the VSS potential. In the present embodiment, the distance G1 of the separation space is set to 1 μm. If the withstand voltage is secured between the annular N-type well NWEL1 and the P-type well PWEL, the separation space G1 is not necessary. For example, if the design rule is 0.25 μm, the separation space G1 is not necessary, but in the design rule of 0.18 μm, the withstand voltage may be secured by the separation space G1.

  Next, a separation space G2 is also provided between the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2. In particular, the deep N-type well DNWEL is not disposed in the space G2 in order to electrically isolate the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2. Instead, a deep P-type well DPWEL (first conductivity type annular deep well) is formed. The deep layer P-type well DPWEL has a slightly higher impurity concentration than the P-type substrate Psb and a lower concentration than the surface P-type well PWEL, so that the breakdown voltage between the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 It is provided to raise. The deep P-type well DPWEL is annularly arranged so as to surround the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 in FIG.

  In addition, in the present embodiment, a P-type impurity layer (P-type ring, first conductivity type impurity ring in a broad sense) 280 is arranged in a ring shape in plan view on the surface layer of the separation space G2. The formation region of the P-type ring 280 surrounds both the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 as shown in FIG.

  Providing the P-type ring 280 prevents the potential in the separation space G2 from being inverted by turning on the parasitic transistor even if the metal wiring that can serve as the gate of the parasitic transistor straddles the separation space G2. It is. In this embodiment, the length of the separation space G2 is 4.5 μm, and the width of the P-type ring 280 located at the center of the separation space G2 is 0.5 μm. However, from the viewpoint of preventing the potential inversion, the polysilicon layer and the first layer metal wiring that can be the gate of the parasitic transistor are not formed across the separation space G2. The metal wiring of the second layer or higher is designed to be able to straddle the separation space G2.

  FIG. 21 can be given as a modification of FIG. In FIG. 21, the annular deep layer P-type well DPWEL is not provided in the separation space G2, but an annular surface layer P-type well SPWEL (first conductivity type annular surface well in a broad sense) is provided instead. The P-type ring 280 is formed in an annular surface layer P-type well SPWEL. A space G1 (for example, 1 μm) between the other long side region NWEL1-1 of the annular N-type well NWEL1 and the surface layer P-type well SPWEL is provided to ensure a withstand voltage of 20 V for the same reason as described above.

3.3.4. Control Circuit Block Next, the control circuit block 202 shown in FIG. 8 will be described. FIG. 22 is a block diagram of the control circuit block 202, and FIG. 23 is a layout diagram of the control circuit block 202. The control circuit block 202 is a circuit block for controlling data programming (writing), reading and erasing to the memory cells MC in the memory cell array block 200. As shown in FIG. 22, the control circuit block 202 includes a power supply circuit 300, a control circuit 302, an X predecoder 304, a Y predecoder 306, a sense amplifier circuit 308, a data output circuit 310, a program driver 312, and a data input circuit. 314 and the column driver 316 (CLDrv) described above. The input / output buffer 318 shown in FIG. 23 includes the data output circuit 310 and the data input circuit 314 shown in FIG. The power supply circuit 300 includes a VPP switch 300-1, a VCG switch 300-2, and an ERS (erase) switch 300-3.

  As shown in FIG. 23, the memory cell array block 200 and the control circuit block 202 are adjacent in the D1 direction. The data read from the memory cell array block 200 passes through the control circuit block 202 and the input / output buffer 318 in the control circuit block 202 in the direction (D1) in which the bit line BL of the memory cell array block 200 extends. Direction).

  Here, as described with reference to FIGS. 3A and 3B, the programmable ROM 20 is arranged adjacent to the block of the logic circuit LB or the power supply circuit PB, which is the data transfer destination, in the D1 direction. . In addition, if the control circuit block 202 of the programmable ROM 20 is arranged adjacent to the block of the logic circuit LB or the power supply circuit PB, which is the data transfer destination, in the D1 direction, data is supplied through a shorter path. it can.

3.4. Operation example of programmable ROM 3.4.1. Applied Voltage in Each Mode FIG. 24 shows applied voltages to the selected memory cell in each mode of standby (Stdby), erase (Ers), program (Pgm), and read (Read). FIG. 25 shows voltages applied in each mode to the memory cells in the selected column connected to the unselected main word line. FIG. 26 shows voltages applied in the respective modes to the memory cells in the non-selected columns connected to the selected main word line.

  Among these operating voltages, the operating voltages at the time of erasing, programming, and reading are as described with reference to FIGS. 12, 14, 16, and 17. In the standby state, the main word line, the sub word line, and the column are not selected for any memory cell, and the voltage of the control gate CG, the voltage of the erase terminal ERS, and the voltage of the bit line BL are all 0V. Become.

3.4.2. Transfer Gate Control During Programming of Selected Memory Cell With reference to FIGS. 24 to 26, control of the first transfer gate 240 of FIG. 11 will be described. In general, the first transfer gate 240 composed of the P-type MOS transistor Xfer (P) and the N-type MOS transistor Xfer (N) is the gate of each of the P-type MOS transistor Xfer (P) and the N-type MOS transistor Xfer (N). In general, the first transfer gate 240 is turned on and off as a whole by applying voltages having different logics. For example, at the time of reading the selected memory cell shown in FIG. 24 and at the time of batch erasing (Ers) of the memory cells shown in FIGS. 24 to 26 (first connection mode in a broad sense), an N-type MOS transistor The sub-word line SWL connected to the gate of Xfer (N) is set to 3V, the inverted sub-word line XSWL connected to the gate of the P-type MOS transistor Xfer (P) is set to 0V, and the P-type MOS transistor Xfer (P) and the N-type Both MOS transistors Xfer (N) are turned on. On the contrary, when the memory cell shown in FIGS. 24 to 26 is in a standby state (Stdby) or during programming (Pgm) and reading of a non-selected memory cell shown in FIGS. N), the sub-word line SWL connected to the gate of N) is set to 0V, and the inverted sub-word line XSWL connected to the gate of the P-type MOS transistor Xfer (P) is set to 3V (8V at the time of programming). ) And the N-type MOS transistor Xfer (N) are both turned off.

  A characteristic operation example of the present embodiment is an operation at the time of programming (Pgm) of the selected memory cell shown in FIG. 24 (second connection mode in a broad sense), and includes a P-type MOS transistor Xfer (P) and an N-type MOS. A voltage of 0 V having the same logic is applied to the transistor Xfer (N). As a result, in the transfer gate 240 connected to the selected memory cell, the P-type MOS transistor Xfer (P) is turned on and the N-type MOS transistor Xfer (N) is turned off only at the time of programming (Pgm).

  Thus, the reason why the N-type MOS transistor Xfer (N) of the first transfer gate 240 connected to the selected memory cell is turned off at the time of programming (Pgm) is as follows.

  FIG. 27 is a characteristic diagram showing on-breakdown voltage and off-breakdown voltage of an MV (3 V) N-type MOS transistor Xfer (N) having a gate length of 0.6 μm and a gate width of 10 μm. FIG. 27 is a characteristic diagram in which the drain current (vertical axis) is measured when the gate voltage is changed from 0 V to 8 V and the drain voltage (horizontal axis) is increased under each gate voltage. The breakdown drain voltage is the breakdown voltage when the drain current flowing under each gate voltage becomes infinite. A curve obtained by plotting the breakdown voltage for each gate voltage is defined as a withstand voltage curve R here.

  In this specification, the off breakdown voltage is a breakdown voltage when the channel current does not flow through the N-type MOS transistor Xfer (N), that is, a voltage immediately before the N-type MOS transistor Xfer (N) is OFF. In the characteristic diagram of FIG. 27, the off breakdown voltage is about 12V. That is, when the N-type MOS transistor Xfer (N) is OFF (when the gate voltage is equal to or lower than the threshold value), a voltage higher than the off breakdown voltage (for example, 12 V) is applied to the drain (bit line BL). The drain current becomes infinite and the N-type MOS transistor Xfer (N) breaks down. In other words, if the N-type MOS transistor Xfer (N) is turned off, the N-type MOS transistor can be applied even if a voltage lower than the off-breakdown voltage (for example, 12 V) is applied as the drain voltage (voltage of the bit line BL). Xfer (N) means no breakdown.

  On the other hand, in this specification, the on breakdown voltage means the lowest breakdown voltage in the entire operation region (on-time) of the N-type MOS transistor Xfer (N), and the on breakdown voltage is less than the off breakdown voltage. In FIG. 27, the ON breakdown voltage in the vicinity where the breakdown voltage curve R stands almost vertically is about 9V. This on-breakdown voltage depends on the gate length L of the transistor. When the gate length L is long, the on-breakdown voltage is high, and when the gate length L is short, it is low. That is, in the conventional technique for turning on the N-type MOS transistor Xfer (N) at the time of programming (Pgm), the channel length L must be increased in order to increase the ON breakdown voltage. When the channel length L is increased, the current drive capability of the transistor is lowered, so the channel width W must be increased, and the transistor size is increased.

  In this embodiment, as shown in FIGS. 24 to 26, the voltage of the bit line BL is 8 V (for example, corresponding to logic “H”) or 0 V (for example, corresponding to logic “L”) during programming (Pgm). Become. Here, since the N-type MOS transistor Xfer (N), which is a component of the first transfer gate 240, is an MV (3V) system, as shown in FIGS. 24 to 26, except during programming (Pgm), The drain voltage (voltage of the bit line BL) is about 0V or 1V, and the gate voltage (voltage applied to the sub word line SWL) is 3V (MV power supply voltage VDD) or 0V (MV power supply voltage VSS). .

  As described above, in the present embodiment, the MV (3 V) N-type MOS transistor Xfer (N) is applied with the voltage 8V higher than the MV power supply voltage VDD = 3 V to the bit line BL during the program (Pgm). ing.

  However, in this embodiment, at the time of programming (Pgm) in which a voltage 8V far higher than the power supply voltage (3V) is applied to the drain (bit line BL) of the MV (3V) N-type MOS transistor Xfer (N). 24 to 26, the gate voltage (the voltage of the sub word line SWL) is 0 V, and the N-type MOS transistor Xfer (N) is turned off. Therefore, since the breakdown voltage of the N-type MOS transistor Xfer (N) at this time is the off breakdown voltage (12V) shown in FIG. 27, the N-type MOS transistor Xfer (N) does not break down.

  In particular, as shown in FIG. 24, the first transfer gate 240 connected to the selected memory cell MC must be turned on during programming (Pgm). At this time, the N-type MOS transistor Xfer (N) is turned off, but the P-type MOS transistor Xfer (P) is turned on, so that the selected memory cell MC is selected by the current driving capability of the P-type MOS transistor Xfer (P). Can be programmed to "H" or "L".

  As shown in FIGS. 24 to 26, the N-type MOS transistor Xfer (N) is turned on when 3V is applied to the drain (bit line BL) (that is, the sub word line SWL is 3V). However, the N-type MOS transistor Xfer (N) is an MV (3V) transistor, and can ensure a sufficient on-voltage when 3V is applied. Eventually, by turning off the N-type MOS transistor Xfer (N) particularly at the time of programming, only the off breakdown voltage needs to be considered at the time of programming, so that the channel length L can be minimized. Since high speed is required at the time of reading, if the channel length L is short, the N-type MOS transistor Xfer (N) can exhibit a high current driving capability at the time of reading and shorten the read time. That is, the channel length and channel width of the N-type MOS transistor may be designed according to the current driving capability required at the time of reading rather than at the time of programming. In the present embodiment, the gate length L = 0.6 μm can be realized. That is, in the case of the transistor having a channel length of 0.6 μm shown in FIG. 27, it is possible to apply only up to 9V when both P / N are turned on, but in this embodiment, up to 12V of the off breakdown voltage can be applied.

3.4.3. Improvement of writing (programming) speed As a writing speed, when the storage capacity of the programmable ROM 20 is 4 Kbits, a writing speed of about 1 second is required as a writing speed in all storage areas. In this case, the writing speed to one memory cell (also referred to as a single cell) MC is about 1 ms / Byte.

  As a measure for improving the writing speed, it is preferable to increase the writing voltage (bit line BL). In FIG. 28, the horizontal axis represents the write voltage VPP, and the vertical axis represents the write speed Tpgm (sec).

  As can be seen from FIG. 28, the higher the write voltage VPP, the faster the write speed. For this reason, in the above-described embodiment, the write voltage (the voltage of the bit line BL) is 8 V. However, the write voltage may be higher than that, for example, higher than the ON breakdown voltage (about 9 V) shown in FIG. As described above, since the N-type MOS transistor Xfer (N) is turned off during programming, the N-type MOS transistor Xfer (N) is turned off (12 V) even if the write voltage is higher than the on-breakdown voltage (about 9 V). This is because it has a breakdown voltage and does not break down. Under the condition that the writing voltage is lower than the off breakdown voltage (12 V), the P-type MOS transistor Xfer (P) exhibits a high current driving capability, and the writing speed can be improved. Since the P-type MOS transistor Xfer (P) having the same channel length as the N-type MOS transistor Xfer (N) has a higher ON breakdown voltage than the N-type MOS transistor Xfer (N), the P-type MOS transistor Xfer (P) There is no breakdown.

3.4.4. Configuration of Sub-Word Line Decoder FIG. 29 is a circuit diagram of the sub-word line decoder SWLDec that generates voltages for the sub-line SWL and the inverted sub-word line XSWL shown in FIGS. The sub word line decoder SWLDec shown in FIG. 29 is composed of six transistors with the number of transistors reduced by two compared to the conventional sub word line decoder SWLDec consisting of eight transistors shown in FIG.

  In FIG. 29, the sub word line decoder SWLDec includes a first P-type MOS transistor 600 having a source connected to the voltage supply line of the voltage VPP, and a second P-type MOS transistor 600 connected in series to the drain of the first P-type transistor 600. Transfer gate 610. The second transfer gate 610 includes a second P-type MOS transistor 612 and a first N-type MOS transistor 614.

  Further, the sub word line decoder SWLDec includes a second N-type MOS transistor 620 whose source is grounded, and a third transfer gate 630 connected in series to the drain of the second N-type transistor 620. The third transfer gate 630 includes a third P-type MOS transistor 632 and a third N-type MOS transistor 634.

  One of a plurality of main word lines MWL is connected to the gates of the first P-type MOS transistor 600 and the first N-type MOS transistor 614, and the gate of the second P-type MOS transistor 612 is connected to the first P-type MOS transistor 614. An inverted main word line XMWL that is paired with the main word line MWL connected to the gate of the N-type MOS transistor 614 is connected.

  The output XCL of the corresponding column driver CLDrv is supplied to the common source of the first N-type MOS transistor 614 and the second P-type MOS transistor 612.

  The drains of the first P-type MOS transistor 600 are commonly connected to the gates of the second N-type MOS transistor 620 and the third P-type MOS transistor 632. The program line PGM is connected to the gate of the third N-type MOS transistor 634, and the inverted program line XPGM is connected to the common source of the third N-type MOS transistor 634 and the third P-type MOS transistor 632. .

  The drain of the second N-type MOS transistor 620 is connected to the corresponding sub word line SWL, and the drain of the first P-type MOS transistor 600 is connected to the corresponding inverted sub word line XSWL.

  In the above configuration, the reason why the sub word line decoder SWLDec can be configured by six transistors is that the signal lines XCL and XPGM are connected to the source instead of the gate of the transistor. This is because if the logic circuit of the sub word line decoder SWLDec is configured by a general method using FIGS. 24 to 26 as truth tables, the signal lines CL and PGM become gate lines as shown in FIG. In the present embodiment, the sub word line decoder SWLDec can be configured with six transistors by connecting the signal lines XCL and XPGM to the source of the transistor.

  As shown in FIG. 18, one sub word line decoder SWLDec is provided in the memory cell array block for each memory cell MC that is simultaneously read or programmed (eight in the present embodiment). Therefore, since the area occupied by two transistors can be reduced to constitute one sub word line decoder SWLDec, it can greatly contribute to the reduction in the area of the memory cell array block.

4). Electronic Device FIGS. 31A and 31B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic device may include components other than those shown in FIGS. 31A and 31B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  31A and 31B, the host device 410 is, for example, an MPU (Micro Processor Unit), a baseband engine (baseband processor), or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. An image processing controller (display controller) 420 in FIG. 31B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  The display panel 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. The display panel 400 can be constituted by an active matrix panel using switching elements such as TFTs and TFDs. Note that the display panel 400 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel.

  In the case of FIG. 31A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 31B, an integrated circuit device 10 without a built-in memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input-side I / F) described at least once together with different terms having a broader meaning or the same meaning (first interface region, second interface region, etc.) (Area, etc.) can be replaced with the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

  For example, in the present invention, the first conductivity type of the semiconductor substrate on which the programmable ROM is mounted can be an N type.

It is a figure which shows the structural example of the integrated circuit device of this embodiment. It is a figure which shows the example of various types of display drivers and the circuit block which it incorporates. 3A and 3B are diagrams showing an example of a planar layout of the integrated circuit device of this embodiment. 4A and 4B are diagrams illustrating examples of cross-sectional views of the integrated circuit device. It is a block diagram which shows the relationship between programmable ROM, a logic circuit, and a gradation voltage generation circuit among the circuit blocks shown to FIG. 3 (A). 6A, 6B, and 6C are characteristic diagrams showing gradation voltages adjusted by the circuit of FIG. It is a block diagram of the structural example of the display apparatus containing an electro-optical apparatus. It is a figure which shows the layout of the programmable ROM block in an integrated circuit device. It is a figure which shows the layout of the comparative example with respect to FIG. It is a top view of the memory cell of the single layer gate arrange | positioned in programmable ROM. FIG. 11 is an equivalent circuit diagram of the memory cell shown in FIG. 10. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a program (write) principle in a memory cell. It is a figure explaining transition of the threshold value of the write / read transistor after programming. FIG. 11 shows a cross section taken along line B-B ′ of FIG. It is a figure explaining transition of the threshold value of the write / read transistor after erasure. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a principle of reading data from a memory cell in a write state. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a principle of reading data from an erased memory cell. It is a top view of the memory cell array block of programmable ROM. It is a top view of two adjacent memory cells. It is C-C 'sectional drawing of FIG. It is a figure which shows the modification of FIG. It is a block diagram of programmable ROM. It is a figure which shows the planar layout of the whole programmable ROM. It is a characteristic view which shows the operating voltage in each mode of a selection memory cell. FIG. 10 is a characteristic diagram showing an operating voltage in each mode of a memory cell in a selected column connected to an unselected main word line. FIG. 10 is a characteristic diagram showing operating voltages of memory cells in a non-selected column connected to a selected word line. It is a characteristic view which shows the ON breakdown voltage and the OFF breakdown voltage of an N-type MOS transistor. FIG. 6 is a characteristic diagram for explaining an improvement in write speed of a transfer gate. It is a circuit diagram of a sub word line decoder of the present embodiment. It is a circuit diagram of a conventional sub word line decoder. 31A and 31B are diagrams each illustrating a configuration example of an electronic device.

Explanation of symbols

  CB1 to CBN 1st to Nth circuit blocks, 10 integrated circuit device, 12 output side I / F area, 14 input side I / F area, 20 programmable ROM, 200 memory cell array block, 202 control circuit block, 210 control gate Part, 220 write / read transistor, 230 erase transistor, 240 first transfer gate, 250 main word line / control gate line driver area, 260 memory cell area, 270 sub word line decoder area, 280 P-type ring, 300 power supply circuit, 302 control circuit, 304 X predecoder, 306 Y predecoder, 308 sense amplifier circuit, 310 data output circuit, 312 program driver, 314 data input circuit, 318 in Output / output buffer, 600 first P-type MOS transistor, 610 second transfer gate, 612 second P-type MOS transistor, 614 first N-type MOS transistor, 620 second N-type MOS transistor, 630 Third transfer gate, 632 Third P-type MOS transistor, 634 Third N-type MOS transistor, BL bit line, CG (NCU) control gate, CLDrv column driver, FG floating gate, LB logic circuit (gate array ), MC memory cell, NWEL1 annular N-type well, NWEL2 strip N-type well, PB power supply circuit, PWELP P-type well, Xfer (P) transfer gate PMOS, Xfer (N) transfer gate NMOS MWL main word line, SWL sub-word line

Claims (16)

A transfer gate provided between the first line and the second line, having P-type and N-type MOS transistors, for connecting / disconnecting the first line and the second line;
A control circuit for controlling connection / disconnection at the transfer gate by controlling a voltage applied to the gates of the P-type and N-type MOS transistors of the transfer gate;
Have
In the first connection mode, the control circuit applies different logic voltages to the gates of the P-type and N-type MOS transistors to turn on both the P-type MOS transistor and the N-type MOS transistor, In the second connection mode in which a voltage higher than that in the first connection mode is supplied to the first or second line, the same logic voltage is applied to the gates of the P-type and N-type MOS transistors, A transfer gate circuit, wherein the P-type MOS transistor is turned on and the N-type MOS transistor is turned off. In claim 1,
The voltage supplied to the first or second line in the second connection mode is lower than an off breakdown voltage that is a breakdown voltage when no channel current flows through the N-type MOS transistor. Transfer gate circuit. In claim 2,
The voltage supplied to the first or second line in the second connection mode is higher than a power supply voltage applied to the gate of the N-type MOS transistor in the first connection mode. Transfer gate circuit. In claim 2 or 3,
The voltage supplied to the first or second line in the second connection mode is higher than an on-breakdown voltage, which is the lowest breakdown voltage in the entire operation region of the N-type MOS transistor. A transfer gate circuit. In any one of Claims 1 thru | or 4,
A transfer gate circuit, wherein a channel length and a channel width of the N-type MOS transistor are designed so as to satisfy a current driving capability required in the first connection mode. A plurality of memory cells connected to one of the plurality of word lines; a plurality of bit lines connected to the plurality of memory cells; and a word line decoder for selecting at least one of the plurality of word lines. Having a memory block,
Each of the plurality of memory cells has a transfer gate connected to one of the plurality of bit lines, and the transfer gate has P-type and N-type MOS transistors connected to the word line decoder. ,
When the plurality of memory cells connected to one of the plurality of word lines are selected, read and erase modes differ from the word line decoder to the gates of the P-type and N-type MOS transistors, respectively. A logic voltage is applied to turn on both the P-type MOS transistor and the N-type MOS transistor. In the program mode, the word line decoder applies the same logic voltage to the gates of the P-type and N-type MOS transistors. The integrated circuit device is applied to turn on the P-type MOS transistor and turn off the N-type MOS transistor. In claim 6,
The maximum voltage supplied to the bit line connected to the selected memory cell in the program mode is lower than an off breakdown voltage which is a breakdown voltage when no channel current flows through the N-type MOS transistor. Circuit device. In claim 6 or 7,
The maximum voltage supplied to the bit line connected to the selected memory cell in the program mode is higher than the power supply voltage applied to the gate of the N-type MOS transistor in the read and erase modes. Circuit device. In claim 6 or 7,
The maximum voltage supplied to the bit line connected to the selected memory cell in the program mode is higher than the on breakdown voltage, which is the lowest breakdown voltage in the entire operation region of the N-type MOS transistor. Integrated circuit device. In any one of Claims 6 thru | or 9.
The one word line is hierarchized into one main word line and a plurality of sub word lines,
The integrated circuit device, wherein the word line decoder is a sub word line decoder provided between the one main word line and one of the plurality of sub word lines. In claim 10,
Each of the plurality of memory cells includes
A write / read transistor and an erase transistor formed on a semiconductor substrate;
A floating gate shared by the gates of the write / read transistor and the erase transistor;
A control gate formed in the semiconductor substrate, and formed in an impurity region formed at a position where the floating gate is opposed to the insulating layer through an insulating layer;
An integrated circuit device, wherein the transfer gate is connected between the write / read transistor and the bit line. In claim 11,
When the semiconductor substrate is P-type, an N-type deep layer well formed on the semiconductor substrate, a P-type surface layer well formed on the N-type deep layer well, and the P-type on the N-type deep layer well A triple well structure formed by an N-type annular surface well surrounding the surface well, and the P-type surface well and the outermost impurity region formed in the N-type annular surface well;
The control gate, the write / read transistor and the N-type MOS transistor are formed in the P-type surface layer well,
The N-type annular surface well has two long side regions,
The erase transistor is formed in one of the two long side regions,
Next to the other of the two long side regions, an N-type band-shaped surface layer well is formed,
An integrated circuit device, wherein the P-type MOS transistor is formed in the N-type strip surface layer well. In claim 11 or 12,
The memory cell array block in which the plurality of memory cells are arranged is divided into first and second regions with a central region as a boundary, and main word lines of the plurality of memory cells arranged in the first and second regions are arranged. Two main word line drivers that respectively drive, and two control gate drivers that respectively drive the control gates of the plurality of memory cells arranged in the first and second regions are arranged. An integrated circuit device. In claim 13,
The memory cell array block has a plurality of column blocks divided in a direction in which the plurality of main word lines extend,
The one sub-word line is arranged for each of the plurality of column blocks;
Each of the plurality of column blocks has a memory cell region and a sub word line decoder region further divided in a direction in which the plurality of word lines extend,
The integrated circuit device, wherein the memory cell region and the sub word line decoder region are formed in a common well region formed on the semiconductor substrate. In claim 14,
An integrated circuit device, wherein a transistor forming the sub word line decoder disposed in the sub word line decoder region is formed in the P-type surface layer well and the N-type band surface layer well. An integrated circuit device according to any one of claims 6 to 15,
A display panel driven by the integrated circuit device;
An electronic device comprising: