JP2007127977A - Integrated circuit device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device that supplies various inspection data in a short period of time, and also to provide an electronic apparatus including the device. <P>SOLUTION: A driver IC 10 includes: an input interface circuit 14; a non-volatile data memory 20 where first inspection data are preliminarily stored through the input interface circuit; a data register 600 where second inspection data are stored through the input interface circuit 14 during inspection; a selector 610 for selecting one of the outputs from the non-volatile data memory 20 and the register; and a selector control circuit 640 for controlling to switch the selector 610 according to a selector switching command inputted through the input interface circuit 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  There is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. This display driver is required to reduce the chip size in order to reduce the cost.

  However, the size of a display panel incorporated in a mobile phone or the like is almost constant. Therefore, if a fine process is adopted and the integrated circuit device of the display driver is simply shrunk to reduce the chip size, problems such as difficulty in mounting are caused.

  In addition, when a user mounts a display driver on a liquid crystal panel to manufacture a display device, various adjustments are necessary on the display driver side. For example, by adjusting the display driver according to the specifications of the panel (amorphous TFT, low-temperature polysilicon TFT, QCIF, QVGA, VGA, etc.) and driving conditions, or by adjusting the display characteristics so that there is no variation between the panels. is there. The IC manufacturer also needs to adjust the oscillation frequency and output voltage, switch to redundant memory, etc. during IC inspection.

Conventionally, the adjustment on the user side has been performed by an external E ² PROM (ELECTRICAL ERASABLE PROGRAMABLE READ ONLY MEMORY) and an external trimmer resistance (variable resistance). Switching to a redundant memory on the IC manufacturer side is performed by fusing a fuse element provided in the integrated circuit device.

  However, the external work of the components is complicated for the user, and the trimmer resistor is expensive, large in size, and has the disadvantage of being easily broken. For the IC manufacturer side, the work of cutting the fuse element and the subsequent operation confirmation are also complicated.

  Here, as a non-volatile memory device that can be manufactured at a low cost with a simple manufacturing process as compared with a stacked gate type non-volatile memory device that requires two layers of gates, the non-volatile memory described in Patent Document 1 Storage devices have been proposed. In the nonvolatile memory device described in Patent Document 1, the control gate is an N-type impurity region in the semiconductor layer, and the floating gate electrode is formed of a conductive layer such as a single polysilicon layer (hereinafter referred to as “single-layer gate”). Type non-volatile memory device). Such a single-layer gate type nonvolatile memory device can be formed in the same manner as a process of a normal CMOS transistor because it is not necessary to stack gate electrodes.

The inventors store inspection data in this type of nonvolatile storage device, and supply the inspection data read from the nonvolatile storage device at the time of inspection to the circuit to be inspected in the integrated circuit device for inspection. Tried to carry out.
JP 63-166274 A

  An object of the present invention is not only to supply inspection data from a nonvolatile storage device, but also to supply inspection data from a register that can be directly input by an operator by interruption, so that various inspection data can be supplied in a short time. An integrated circuit device and an electronic apparatus including the integrated circuit device are provided.

  An integrated circuit device according to an aspect of the present invention includes an input interface circuit, a nonvolatile data memory in which first inspection data is stored in advance via the input interface circuit, and the input interface circuit during inspection. In accordance with a data register for storing second test data, a selector for selecting one output of the nonvolatile data memory and the data register, and a selector switching command input via the input interface circuit, the selector And a selector control circuit for switching control.

  In one aspect of the present invention, at the time of inspection, the second inspection data is stored in the data register through the input interface circuit, and the selector control circuit switches and controls the selector according to the selector switching command input through the input interface circuit. . As a result, not only the first test data from the nonvolatile data memory but also the second test data from the data register can be output as an interrupt. Therefore, various inspection data can be supplied in a short time, and the detection rate can be increased.

  In one aspect of the present invention, the input interface circuit has an input terminal to which N (N is an integer of 2 or more) bits of inspection data or a selector switching command is input, and the first and second inspection data Each is N-bit test data, and the selector control circuit performs switching control so that the selector selects the output of the data register based on the output of the logic gate to which the N-bit selector switching command is input. be able to.

  As described above, the logic of the same N-bit selector switching command as that of the inspection data is determined in advance, so that the selector can be switched and controlled by the output of the logic gate to which the N-bit selector switching command is input.

  In one aspect of the present invention, the data register includes first to Nth registers, and the first to Nth registers have the N-bit first register during a first period in which a register write signal is active. Each of the two test data bits is written, and the selector control circuit includes a selector control register, and a second period in which the register output signal becomes active after the first period is based on the output from the logic gate. Output switching data may be written in the selector control register.

  In this way, by dividing the writing period of the second inspection data and the writing period of the output switching data, the second inspection data input via the input interface circuit and the input interface circuit are input. The output switching data generated based on the selector switching command can be written to the respective registers.

  In one aspect of the present invention, the first to Nth registers are each written with N bits of the second check data based on the first operation clock input during the first period. In the selector control register, the output switching data is written based on the second operation clock input during the second period, and in the second period, the first to Nth registers Second inspection data is read, and the output switching data is read from the selector control register, so that the second inspection data can be selected by the selector.

  Thus, the second test data can be written, the output switching data can be written, and the second test data can be selected from the selector, based on the operation clock that is input once for each period.

  In one embodiment of the present invention, a data output circuit is connected to a subsequent stage of the selector, and the data output circuit can include a latch circuit. In this case, the second inspection data selected by the selector based on the latch signal that becomes active in synchronization with the third operation clock input during the third period after the second period is stored in the second inspection data. It can be latched by a latch circuit.

  In one aspect of the present invention, the first to Nth registers and the selector control register are reset when a macro cell selection signal for selecting a macro cell including the data register and the selector control circuit changes from active to non-active. be able to.

  By this reset operation, the selector can return to the normal operation of selecting the nonvolatile data memory.

  Here, a delay circuit is provided in the macro cell selection signal supply line, and the delay circuit delays the timing at which the first to Nth registers are reset from the timing at which the selector control register is reset. Is preferred.

  It is possible to prevent a malfunction in which data other than the second inspection data generated by first resetting the first to Nth registers is output from the selector.

  In one aspect of the present invention, the nonvolatile data memory is controlled in operation based on a plurality of logic signals for controlling erase, program and control gates, and the macro cell selection signal is a combination of logics of the plurality of logic signals. May be generated based on

  When the macro cell selection signal is active, the nonvolatile data memory is not used and a plurality of logic signals are not required. A macro cell selection signal can be generated using a plurality of unnecessary logic signals.

  In one embodiment of the present invention, each of the plurality of memory cells provided in the nonvolatile data memory includes a write / read transistor and an erase transistor formed on a semiconductor substrate, and each of the write / read transistor and the erase transistor. A floating gate shared by the gate; and a control gate formed in the semiconductor substrate and formed in an impurity region formed at a position where the floating gate faces through an insulating layer. .

  One embodiment of the present invention also has a “single layer gate” structure with only a floating gate, but differs from the prior art in that writing and erasing are performed by MOS transistors having different channel conductivity types. The withstand voltage against the erase voltage can be improved as compared with the case of erasing at the same location as the write region.

  Another aspect of the present invention defines an electronic device including any of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Integrated Circuit Device FIG. 1 shows a configuration example of the integrated circuit device 10 of the present embodiment. In the present embodiment, the direction from the first side SD1 which is the short side of the integrated circuit device 10 to the third side SD3 facing the first direction D1 is the first direction D1, and the opposite direction of D1 is the third direction D3. Yes. The direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and the opposite direction of D2 is a fourth direction D4. In FIG. 1, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side SD1. May be.

  As shown in FIG. 1, the integrated circuit device 10 of this embodiment includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. In this embodiment, circuit blocks CB1 to CBN are arranged in the D1 direction. Details of the first to Nth circuit blocks CB1 to CBN will be described later.

  Further, the integrated circuit device 10 includes an output side I / F region 12 provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, the first to Nth circuit blocks CB1 to CBN include an input side I / F region 14 (input interface circuit) provided along the side SD2 on the D4 direction side. More specifically, the output-side I / F area 12 (first interface area) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second interface area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks. Note that when the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, at least one of the I / F regions 12 and 14 may be omitted.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). In this embodiment in which the integrated circuit device 10 is a display driver, a programmable ROM block (nonvolatile data memory in a broad sense) is essential, and a logic circuit (gate in a broad sense) to which data from the programmable ROM block goes. At least one of an array block) and a power supply circuit block is essential.

  For example, FIG. 2 shows examples of various types of display drivers and circuit blocks incorporated therein. In a display driver for an amorphous TFT (Thin Film Transistor) panel with a built-in memory (RAM), the circuit blocks CB1 to CBN include a display memory, a data driver (source driver), a scanning driver (gate driver), a programmable ROM block, It includes a logic circuit (gate array circuit), a gradation voltage generation circuit (γ correction circuit), and a power supply circuit block. On the other hand, in a display driver for a low-temperature polysilicon (LTPS) TFT panel with a built-in memory, the scanning driver can be formed on a glass substrate, so that the scanning driver block can be omitted. Also, the memory block can be omitted for an amorphous TFT panel without a memory, and the memory and scan driver blocks can be omitted for a low-temperature polysilicon TFT panel without a memory. Further, for a CSTN (Collar Super Twisted Nematic) panel and a TFD (Thin Film Diode) panel, the block of the gradation voltage generation circuit can be omitted.

  3A and 3B show examples of a planar layout of the integrated circuit device 10 of the display driver of this embodiment. 3A and 3B are examples for an amorphous TFT panel with a built-in memory. FIG. 3A targets a display driver for, for example, QCIF and 32 gradations, and FIG. The display driver for gradation is targeted.

  In FIG. 3A, the programmable ROM 20 is between the power supply circuit PB and the logic circuit LB. In other words, the programmable ROM 20 is adjacent to each block of the power supply circuit PB and the logic circuit LB in the direction D1.

  On the other hand, in FIG. 3B, the block of the programmable ROM 20 is adjacent to the block of the power supply circuit PB in the direction D1.

  This is because the main destination of data read from the programmable ROM 20 is the power supply circuit PB and / or the logic circuit LB. That is, data from the programmable ROM 20 can be supplied to the power supply circuit PB and / or the logic circuit LB through a short path. The data read from the programmable ROM 20 will be described later.

  3A and 3B, in addition to the three blocks described above, memories MB1 to MB4 in which display data is stored, data drivers DB1 to DB4 arranged adjacent to each memory, and gradation voltages The generation circuit GB and one or two scan drivers SB (or SB1, SB2) are included.

  According to the layout arrangement of FIG. 3A, there is an advantage that the column address decoder can be shared between the memory blocks MB1 and MB2 and between the MB3 and MB4. On the other hand, according to the layout arrangement of FIG. 3B, there is an advantage that the wiring pitch of the data signal output lines from the data driver blocks DB1 to DB4 to the output side I / F region 12 can be equalized and the wiring efficiency can be improved. is there.

  Note that the layout arrangement of the integrated circuit device 10 of the present embodiment is limited to FIGS. 3A and 3B as long as the block of the programmable ROM 20 is adjacent to the logic circuit LB and / or the power supply circuit PB in the direction D1. Not. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 4A shows an example of a cross-sectional view along the direction D2 of the integrated circuit device 10 of the present embodiment. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. W is the width of the integrated circuit device 10 in the direction D2.

  In this embodiment, as shown in FIG. 4A, in the direction D2, no other circuit block is interposed between the circuit blocks CB1 to CBN and the output side and input side I / F regions 12 and 14. . Therefore, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 can be satisfied, and a narrow integrated circuit device can be realized. Specifically, the width W in the D2 direction can be set to W <2 mm, and more specifically, W <1.5 mm. In consideration of chip inspection and mounting, it is desirable that W> 0.9 mm. The length LD in the long side direction (see FIGS. 3A and 3B) can be 15 mm <LD <27 mm. The chip shape ratio SP = LD / W can be set to SP> 10, and more specifically, SP> 12.

  The widths of the circuit blocks CB1 to CBN in the D2 direction can be unified to the same width, for example. In this case, the widths of the circuit blocks may be substantially the same. For example, a difference of about several μm to 20 μm (several tens of μm) is within an allowable range. When circuit blocks having different widths exist in the circuit blocks CB1 to CBN, the width WB can be the maximum width among the circuit blocks CB1 to CBN.

  FIG. 4B shows a comparative example in which two or more circuit blocks are arranged along the direction D2. In the D2 direction, a wiring region is formed between the circuit blocks or between the circuit block and the I / F region. Therefore, the width W of the integrated circuit device 500 in the D2 direction (short side direction) becomes large, and a slim elongated chip cannot be realized. Therefore, even if the chip is shrunk using a fine process, the length LD in the D1 direction (long side direction) is also shortened, and the output pitch becomes narrow, which makes mounting difficult.

  In contrast, in the present embodiment, as shown in FIG. 1, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. Further, as shown in FIG. 4A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, the width W in the D2 direction can be narrowed while maintaining the length LD in the D1 direction of the integrated circuit device 10, and an ultra slim slim chip can be realized. As a result, the output pitch can be maintained at, for example, 22 μm or more, and mounting can be facilitated.

  In the present embodiment, since the plurality of circuit blocks CB1 to CBN are arranged along the direction D1, it is possible to easily cope with a change in product specifications and the like. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIGS. 3A and 3B, even when the number of pixels and the number of gradations of the display panel increase or decrease, the number of memory blocks and data driver blocks, the number of times image data is read out in one horizontal scanning period, etc. Just increase or decrease the number. FIGS. 3A and 3B are examples for an amorphous TFT panel with a built-in memory. When developing a product for a low-temperature polysilicon TFT panel with a built-in memory, scanning is performed from among the circuit blocks CB1 to CBN. Just remove the driver block. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, in this embodiment, the influence of the circuit block on the other circuit blocks can be minimized, so that the design efficiency can be improved.

  In the present embodiment, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified with, for example, the width (height) of the data driver block and the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIGS. 3A and 3B, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors is increased or decreased, the direction of the D1 direction of the gradation voltage generation circuit block or the power supply circuit block is changed. This can be dealt with by increasing or decreasing the length.

2. Programmable ROM data 2.1. Inspection Data In the integrated circuit device according to the present embodiment, the data stored in the programmable ROM 20 as the nonvolatile data memory can include the inspection data of the driver IC 10. As this inspection data, for example, connection inspection data between the programmable ROM 20 and the block in the driver IC 10 can be cited. As will be described later, only a part of the data necessary for the inspection can be stored in the programmable ROM 20, and the other part of the inspection data can be input from the outside. For example, only specific data for the minimum connection inspection may be stored in the programmable ROM 20, and data for further increasing the detection rate may be supplied from the outside during the inspection.

2.2. Gradation Voltage Data In the integrated circuit device of this embodiment, the data stored in the programmable ROM 20 as the nonvolatile data memory may be adjustment data for adjusting the gradation voltage. Then, the gradation voltage generation circuit (γ correction circuit) generates a gradation voltage based on the adjustment data stored in the programmable ROM 20. Hereinafter, the operation of the gradation voltage generation circuit (γ correction circuit) will be described.

  FIG. 5 shows a programmable ROM 20, a logic circuit LB, and a gradation voltage generation circuit (γ correction circuit) GB among the circuit blocks shown in FIG.

  Adjustment data for adjusting the gradation voltage is input to the programmable ROM 20 by, for example, a user (display device manufacturer). The adjustment register 126 is provided in the logic circuit LB. The adjustment register 126 can set various setting data that can adjust the gradation voltage. Setting data is output by reading the adjustment data stored in the program ROM 20 to the adjustment register 126. The setting data read from the adjustment register 126 is supplied to the gradation voltage generation circuit GB.

  The gradation voltage generation circuit GB includes a selection voltage generation circuit 122 and a gradation voltage selection circuit 124. The selection voltage generation circuit 122 (voltage division circuit) outputs a selection voltage based on the high power supply voltages VDDH and VSSH generated by the power supply circuit PB. Specifically, the selection voltage generation circuit 122 includes a ladder resistor circuit having a plurality of resistor elements connected in series. A voltage obtained by dividing VDDH and VSSH by the ladder resistor circuit is output as a selection voltage. The gradation voltage selection circuit 124 selects, for example, 64 voltages in the case of 64 gradations from among the selection voltages based on the gradation characteristic setting data supplied from the adjustment register 126, to Output as regulated voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel.

  The adjustment register 126 may include an amplitude adjustment register 130, a tilt adjustment register 132, and a fine adjustment register 134. In the amplitude adjustment register 130, the inclination adjustment register 132, and the fine adjustment register 134, gradation characteristic data is set.

  For example, by reading the 5-bit setting data stored in the programmable ROM 20 to the amplitude adjustment register 130, the voltage levels of the power supply voltages VDDH and VSSH change as shown by B1 and B2 in FIG. The voltage amplitude can be adjusted.

  Further, by reading the setting data stored in the programmable ROM 20 to the inclination adjustment register 132, as shown in B3 to B6 of FIG. The inclination of the characteristic can be adjusted. That is, the resistance values of the resistance elements RL1, RL3, RL10, and RL12 constituting the ladder resistance change based on the 4-bit setting data VRP0 to VRP3 set in the inclination adjustment register 132, and the inclination adjustment as shown in B3 is performed. Is possible.

  Further, by reading the setting data stored in the programmable ROM 20 to the fine adjustment register 134, as shown in B7 to B14 of FIG. Fine adjustment of the characteristics becomes possible. That is, based on the 3-bit setting data VP1 to VP8 set in the fine adjustment register 134, the 8to1 selectors 141 to 148 select one of eight taps of the eight resistance elements RL2, RL4 to RL9, and RL11. Two taps are selected, and the voltages of the selected taps are output as VOP1 to OP8. As a result, fine adjustment as shown in B7 to B14 of FIG.

  The gradation amplifier unit 150 outputs gradation voltages V0 to V63 based on the outputs VOP1 to VOP8 of the 8to1 selectors 142 to 148, VDDH, and VSSH. Specifically, the gradation amplifier unit 150 includes first to eighth impedance conversion circuits (operational amplifiers connected to voltage followers) to which VOP1 to VPOP8 are input. Then, for example, by dividing the output voltage of the adjacent impedance conversion circuit among the first to eighth impedance conversion circuits by resistance, the gradation voltages V1 to V62 are generated.

  By performing the adjustment as described above, it is possible to obtain the optimum gradation characteristic (γ characteristic) according to the type of the display panel, and to improve the display quality. In the present embodiment, the programmable ROM 20 stores adjustment data for obtaining optimum gradation characteristics (γ characteristics) according to the type of display panel. Therefore, it is possible to obtain optimum gradation characteristics (γ characteristics) for each type of display panel, and to improve display quality.

  In the present embodiment, the programmable ROM 20 and the logic circuit block LB are disposed adjacent to each other along the first direction D1. In this way, the adjustment data signal line from the programmable ROM 20 can be connected to the logic circuit block LB through a short path, and therefore an increase in chip area caused by the wiring region can be prevented.

  Furthermore, in this embodiment, as shown in FIG. 3A, the logic circuit block LB and the gradation voltage generation circuit block GB may be arranged adjacent to each other along the direction D1. In this way, since the signal line from the logic circuit block LB can be connected to the gradation voltage generation circuit block GB through a short path, an increase in chip area due to the wiring region can be prevented.

  Note that adjustment data for adjusting the gradation voltage may be stored in a second memory cell array block 22 described later.

2.3. Panel Setting Voltage Data In the integrated circuit device of this embodiment, the data stored in the programmable ROM 20 may be adjustment data for adjusting the panel voltage. The adjustment data for adjusting the panel voltage may be data for adjusting the voltage applied to the counter electrode VCOM, for example.

  FIG. 7 shows a block diagram of a configuration example of a display device including an electro-optical device. The display device of FIG. 7 realizes a function as a liquid crystal device. The electro-optical device realizes a function as a liquid crystal panel.

  The liquid crystal device 160 (display device in a broad sense) includes a liquid crystal panel (display panel in a broad sense) 162 using TFTs as switching elements, a data line driving circuit 170, a scanning line driving circuit 180, a controller 190, and a power supply circuit 192. .

  The gate electrode of the TFT is connected to the scanning line G, the source electrode of the TFT is connected to the data line S, and the drain electrode of the TFT is connected to the pixel electrode PE. A liquid crystal capacitor CL (liquid crystal element) and an auxiliary capacitor CS are formed between the pixel electrode PE and a counter electrode VCOM (common electrode) facing each other with a liquid crystal element (electro-optical material in a broad sense) interposed therebetween. . Then, liquid crystal is sealed between the active matrix substrate on which the TFT, the pixel electrode PE, and the like are formed, and the counter substrate on which the counter electrode VCOM is formed, and according to the applied voltage between the pixel electrode PE and the counter electrode VCOM. The transmittance of the pixel is changed.

  In the present embodiment, the programmable ROM 20 may store adjustment data for adjusting the voltage applied to the counter electrode VCOM. Based on the adjustment data, the voltage of the power supply circuit 192 is adjusted and applied to the counter electrode VCOM. Display quality can be improved by setting the adjustment data for each display panel.

  In the present embodiment, as shown in FIG. 3A, the programmable ROM 20 and the power supply circuit block PB are arranged adjacent to each other along the first direction D1. In this way, the adjustment data signal line from the programmable ROM 20 can be connected to the power supply circuit block PB through a short path, and therefore an increase in chip area due to the wiring region can be prevented.

  Note that data for adjusting the panel setting voltage may be stored in a first memory cell array block 21 described later.

2.4. Other User Setting Information In the integrated circuit device of the present embodiment, the data stored in the programmable ROM 20 is not limited to these. For example, the programmable ROM 20 may store adjustment data for adjusting a given timing as display driver adjustment data. That is, various control signals for controlling the refresh cycle and display timing of the memory may be generated based on the adjustment data. Alternatively, the programmable ROM 20 may store adjustment data for adjusting the startup sequence setting of the integrated circuit device as display driver adjustment data.

  The above adjustment data is programmed by the user, but data adjusted by the IC manufacturer in the IC manufacturing / inspection process may be stored.

3. Programmable ROM
3.1. Overall Configuration of Programmable ROM FIG. 8 shows a programmable ROM 20 arranged in the integrated circuit device 10. The programmable ROM 20 roughly includes a memory cell array block 200 and a control circuit block 202. The memory cell array block 200 and the control circuit block 202 are adjacent to each other in the direction D1 that is the long side direction of the integrated circuit device 10.

  The memory cell array block 200 is provided with a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL extend along the direction D2 which is the short side direction of the integrated circuit device 10. The plurality of bit lines BL extend along the direction D1 which is the long side direction of the integrated circuit device 10. The reason is as follows.

  The storage capacity of the programmable ROM 20 can be increased or decreased for each model depending on the specifications on the user side. In the present embodiment, the increase or decrease in storage capacity is dealt with by changing the number of word lines WL. That is, the length of the word line WL is constant even when the storage capacity is changed. As a result, the number of memory cells connected to one word line WL is fixed. If the number of word lines WL is increased, the storage capacity of the program ROM 20 is increased. Even if the storage capacity of the program ROM 20 is increased, the memory cell array block 200 does not become longer in the short side direction (D2 direction) of the integrated circuit device 10. Therefore, the slim shape described in FIG. 1 can be maintained.

  As another reason, even if the storage capacity of the programmable ROM 20 is increased or decreased, the control circuit block 202 does not become longer in the short side direction (D2 direction) of the integrated circuit device 10. Therefore, the slim shape described in FIG. 1 can be maintained. In FIG. 9 as a comparative example, the memory cell array block 200 becomes longer in the short side direction (D2 direction) of the integrated circuit device 10 as a result of increasing the storage capacity of the program ROM 20. In this case, the circuit design of the control circuit block 202 must be redone. However, this is not necessary in the layout of FIG. 8 of the present embodiment in which the layout of FIG. 9 as a comparative example is rotated by 90 °. Therefore, even when the storage capacity of the programmable ROM 20 is increased or decreased, the design efficiency of the control circuit block 202 can be improved.

  As yet another reason, the bit line BL extends along the direction D1 which is the long side direction of the integrated circuit device 10, and the control circuit block 202 can be disposed on the extended line of the bit line BL. One function of the control circuit block 202 is to detect data read through the bit line BL by a sense amplifier and supply it to other circuit blocks. With the above-described layout, data read from the memory cell array block 200 can be supplied to the control circuit block 202 through a short path as compared with the comparative example of FIG.

3.2. Single Layer Gate Memory Cell FIG. 10 is a plan view of a single layer gate memory cell MC arranged in the memory cell array block 200 shown in FIG. FIG. 11 is an equivalent circuit diagram of a single-layer gate memory cell MC.

  In FIG. 10, this memory cell MC has a control gate portion 210, a write / read transistor 220, and an erase transistor 230, and a floating gate FG formed of polysilicon extends in these three regions. . As shown in FIG. 11, the memory cell MC has a transfer gate 240 provided between the drain of the write / read transistor 220 and the bit line BL. The transfer gate 240 connects / disconnects the drain of the write / read transistor 220 and the bit line BL according to the logic of the sub word line SWL and the logic of the inverted sub word line XSWL. The transfer gate 240 includes a P-type MOS transistor Xfer (P) and an N-type MOS transistor Xfer (N). When the word lines are not hierarchized, the transfer gate 240 is controlled by each logic of the word line and the inverted word line.

  The single-layer gate is an N-type (second conductivity type in a broad sense) impurity layer NCU in which a control gate CG is formed in a P-type well PWEL of a semiconductor substrate (for example, P-type, first conductivity type in a broad sense). This means that only one polysilicon floating gate FG is formed. That is, the two-layer gate of the control gate CG and the floating gate FG is not formed of polysilicon. A coupling capacitor is formed by the control gate CG and the floating gate FG facing the control gate CG.

  One embodiment of the present invention also has a “single layer gate” structure with only a floating gate, but differs from the prior art in that writing and erasing are performed by MOS transistors having different channel conductivity types. Thus, the advantage of performing writing and erasing with different MOS transistors is as follows. Erasing is performed by applying a voltage to a portion with small capacitive coupling and setting the portion with large capacitive coupling to 0 V, thereby extracting electrons injected into the floating gate by the FN tunnel current. As a conventional single layer gate type nonvolatile memory device, there is a type in which writing and erasing are performed by the same MOS transistor (same location). In a single-layer gate type nonvolatile memory device, the capacity between the control gate and the floating gate electrode needs to be larger than the capacity of the writing area, so the capacity of the writing area is designed to be small. ing. That is, when erasing, a large voltage for erasing must be applied to a portion having a small capacitive coupling.

  However, in particular, in the case of a fine nonvolatile memory device, a sufficient breakdown voltage cannot be ensured with respect to the voltage applied at the time of erasing, and the MOS transistor may be destroyed. Therefore, in the programmable ROM block according to the present embodiment, writing and erasing are performed by different MOS transistors, and the channel conductivity types of the respective MOS transistors are different. If, for example, a P-channel type MOS transistor is formed as the MOS transistor for erasing, the MOS transistor for erasing is formed on the N-type well. Therefore, at the time of erasing, a voltage up to the junction breakdown voltage of the N-type well and the substrate (semiconductor layer) can be applied. As a result, the withstand voltage against the erasing voltage can be improved as compared with the case where erasing is performed at the same location as the writing region, miniaturization is achieved and reliability is improved.

  In the integrated circuit device 10 of the present embodiment, there are an LV (Low Voltage) system (for example, 1.8 V), an MV system (Middle Voltage) system (for example, 3 V), and an HV (High Voltage) system (for example, 20 V). However, the memory cell MC has an MV-type withstand voltage structure. The write / read transistor 220 and the N-type MOS transistor Xfer (N) are MV N-type MOS transistors, and the erase transistor 230 and the P-type MOS transistor Xfer (P) are MV P-type MOS transistors.

  FIG. 12 shows a data write (program) operation to the memory cell MC. For example, 8V is applied to the control gate CG, and for example, 8V is applied to the drain of the write transistor 220 via the bit line BL and the transfer gate 240. The potential of the source of the write / read transistor 220 and the P-type well PWEL is 0V. Thereby, hot electrons are generated in the channel of the write / read transistor 220, and the electrons are drawn into the floating gate of the write / read transistor 220. As a result, the threshold value Vth of the write / read transistor 220 becomes higher than the initial state as shown in FIG.

  On the other hand, at the time of erasing, as shown in FIG. 14, the control gate CG is grounded, for example, and the potential of the N-type well NWEL of the erasing transistor 230 is 20 V (erasing voltage), for example. Thus, since a high voltage is applied between the control gate CG and the N-type well NWEL, electrons in the floating gate FG are drawn to the N-type well NWEL side. Data is erased by this FN (Fowler-Nordheim) tunnel current. At this time, as shown in FIG. 15, the threshold value Vth of the write / read transistor 220 is a negative threshold value lower than the initial state. At the time of erasing, 20V (erase voltage) is also applied to the P-type impurity layer (source / drain) of the erase transistor 230 to ensure a breakdown voltage at the PN junction.

  At the time of data reading, as shown in FIGS. 16 and 17, the control gate CG is grounded, and for example, 1 V is applied to the drain of the write / read transistor 220. At this time, the potential of the source of the write / read transistor 220 and the P-type well PWEL is 0V. In the write state shown in FIG. 16, since the floating gate FG has an excess of electrons, no current flows through the channel. On the other hand, in the erased state shown in FIG. 17, since the floating gate FG has excess holes, electrons flow through the channel. Data can be read with or without the current.

In the programmable ROM 20 of the present embodiment, as described above, the user mainly stores adjustment data instead of the conventional E ² PROM or trimmer resistor, or the IC manufacturer stores the adjustment data at the manufacturing / inspection stage. Used as a memory. For this reason, it is sufficient to compensate the number of rewrites about 5 times.

3.3. Memory cell array block 3.3.1. Planar Layout FIG. 18 is an enlarged plan view showing the memory cell array block 200 and a part thereof. In the memory cell array block 200, a formation region 250 of the main word line driver MWLDrv and the control gate line driver CGDrv is provided at the center position in the short side direction (D2 direction) of the integrated circuit device 10. With this formation region 250 as a boundary, the memory cell array block 200 is divided into two parts, a first region and a second region. In the present embodiment, eight column blocks are provided in each of the first and second regions, and a total of 16 column blocks 0 to 15 are provided. Eight memory cells MC are arranged in the D2 direction in one column block. In the present embodiment, the length W of the short side of the integrated circuit device 10 shown in FIG. 3A is set to 800 μm, and the memory cell MC accommodated in the length W is based on the length of one memory cell MC in the D2 direction. The number of memory cells is 16 columns × 8 memory cells. In order to increase or decrease the storage capacity of the programmable ROM 20, the number of word lines may be increased or decreased. In addition, two main word line drivers MWLDrv and two control gate line drivers CGDrv are provided, one for each of the divided areas. One main word line driver MWLDrv and control gate line driver CGDrv may be provided at the end of the memory array block 200.

  In FIG. 18, a total of 34 main word lines MWL driven by one main word line driver MWLDrv are provided. Two are test main word lines T1 and T0 connected to memory cells for test bits of the IC manufacturer, and the remaining 32 are user main word lines MWL0 to MWL31. Further, a control gate line CG (N-type impurity layer NCU shown in FIG. 10) driven by one control gate line driver CGDrv extends in parallel with the main word line MWL.

  Each of the 16 column blocks 0 to 15 has a memory cell region 260 and a sub word line decoder region 270. The sub word line decoder area 270 is provided with a sub word line decoder SWLDec connected to each main word line MWL. In the area of the control circuit block 202, a column driver CLDrv is provided for each sub word line decoder area 270. The output lines of the column driver CLDrv are commonly connected to all the sub word line decoders SWLDec arranged in each sub word line decoder region 270.

  A sub word line SWL and an inverted sub word line XSWL extend from one sub word line decoder SWLDec toward the adjacent memory cell region 260. In one column block, for example, eight memory cells MC commonly connected to the sub word line SWL and the inverted sub word line XSWL are arranged in the memory cell region 260.

  In the layout shown in FIG. 18, one main word line MWL is selected by the main word line driver MWLDrv, and one column block is selected by the column decoder CLDrv, so that one sub word line decoder SWLDec is selected. The Eight memory cells MC connected to the selected sub word line decoder SWLDec are selected cells, and data is programmed (written) or read. When erasing data, a plurality of memory cells (memory cells subordinate to two main word lines MWL in this embodiment) having at least an erasing transistor on at least the common N-type well NWEL1-1 are used as a minimum unit. Erased.

3.3.2. FIG. 18 shows a well layout common to the memory cell region 260 and the sub word line decoder region 270. Three wells are used to form one memory cell MC in the memory cell region 260. One is a P-type well PWEL (surface well of the first conductivity type in a broad sense) extending in a direction (D2 direction) along the main word line MWL, and the other is an annular shape surrounding the P-type well PWEL. An N-type well NWEL1 (second conductivity type annular surface layer well in a broad sense), and another one extends in a direction (D2 direction) along the main word line MWL at the side of the annular N-type well NWEL1. This is the N-type well NWEL2 (second conductivity type belt-shaped surface layer well in a broad sense). Note that one long side region of the annular N-type well NWEL1 is NWEL1-1, and the other long side region (NWEL2 side) is NWEL1-2.

  One memory cell MC is formed on three wells (PWEL, NWEL1, NWEL2) over the length region L of one memory cell shown in FIG. NWEL1 (particularly NWEL1-1) and NWEL2 are shared by two memory cells adjacent in the direction D1 in FIG. In the length region L in each memory cell region 260, as shown in FIG. 18, eight memory cells MC commonly connected to one sub word line decoder SWLDec are formed.

  In FIG. 18, a P-type impurity ring 280 (a first conductivity type impurity ring in a broad sense) surrounding each of the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 is provided. This will be described later. To do.

  In FIG. 18, the above-described three wells (PWEL, NWEL1, NWEL2) are also formed in the sub word line decoder region 270. However, the formation region of the transistors constituting the sub word line decoder SWLDec is on the P-type well PWEL and the strip-like N-type well NWEL2 shown as dot regions in FIG. 18, and is not formed on the annular N-type well NWEL1.

3.3.3. FIG. 19 is a planar layout of two memory cells MC adjacent to each other in FIG. FIG. 20 is a cross-sectional view of one memory cell MC, showing the CC ′ cross-section of FIG. Note that the cross section indicated by the broken line in the direction D2 among the broken lines CC ′ in FIG. 19 is omitted in FIG. Further, in the CC ′ fracture line of FIG. 19, there is a portion where the dimension in the D1 direction and the dimension in the D1 direction of FIG.

  In FIG. 19, two memory cells MC are mirror-arranged in plan view. As described above, the memory cell MC is formed across three wells (PWEL, NWEL1, and NWEL2) as shown in FIG. As shown in FIG. 20, a deep N-type well DNWEL (second conductivity type deep well in a broad sense) is provided in the lower layer inside the outer edge region of the annular N-type well NWEL1 and the lower layer of the strip-shaped N-type well NWEL2. ing. As shown in FIG. 20, since three wells (PWEL, NWEL1, NWEL2) on the deep layer N-type well DNWEL are provided with P-type or N-type impurity regions (in the broad sense, the outermost layer impurity region), The memory cell MC of the embodiment has a triple well structure. Thereby, the P-type substrate Psub and the P-type well PWEL can be set to different potentials. Note that not only the programmable ROM 20 is formed on the P-type substrate Psub, but also other circuit blocks are formed, and there is a need for application of a back gate voltage. Therefore, the potential of the P-type substrate Psub is not necessarily fixed to the ground potential. Not always.

  As shown in FIGS. 19 and 20, a floating gate FG made of polysilicon is formed on one long side region NWEL1-1 of the annular N-type well NWEL1 and an upper layer of the P-type well PWEL via an insulating film (not shown). Is formed. The floating gate FG functions as a common gate for the write / read transistor 220 formed in the PWEL and the erase transistor 230 formed in one long side region NWEL1-1 of the annular N-type well NWEL1. Further, an N-type impurity region NCU is formed in a P-type well PWEL region facing the floating gate FG via an insulating film. The N-type impurity region NCU is applied with a control gate voltage VCG and functions as a control gate CG.

  The P-type well PWEL is provided with an N-type MOS transistor Xfer (N) of the transfer gate 240 shown in FIG. Further, a P-type MOS transistor Xfer (P) of the transfer gate 240 is provided in the strip-shaped N-type well NWEL2. As shown in FIG. 19, a plurality of P-type MOS transistors Xfer (P) are provided, and these are connected in parallel to secure the gate width and secure the drive capability.

  In the other long side region NWEL1-2 of the annular N-type well NWEL1, only an N-type impurity region is provided, and no active element is provided. The other long side region NWEL1-2 is provided only to be connected to the one long side region NWEL1-1 and surround the P-type well PWEL in an annular shape. This is because if the other long side region NWEL1-2 is not formed, the P-type well PWEL cannot be electrically separated from the P-type substrate Psub even if the deep N-type well DNWEL is arranged.

  In the present embodiment, the P-type well PWEL, which is the upper layer of the deep N-type well DNWEL, is separated from the outer annular N-type well NWEL1. This separation space G1 is for securing a withstand voltage of 20 V between the annular N-type well NWEL1 to which 20 V is applied during erasure and the P-type well PWEL set to the VSS potential. In the present embodiment, the distance G1 of the separation space is set to 1 μm. If the withstand voltage is secured between the annular N-type well NWEL1 and the P-type well PWEL, the separation space G1 is not necessary. For example, if the design rule is 0.25 μm, the separation space G1 is not necessary, but in the design rule of 0.18 μm, the withstand voltage may be secured by the separation space G1.

  Next, a separation space G2 is also provided between the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2. In particular, the deep N-type well DNWEL is not disposed in the space G2 in order to electrically isolate the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2. Instead, a deep P-type well DPWEL (first conductivity type annular deep well) is formed. The deep layer P-type well DPWEL has a slightly higher impurity concentration than the P-type substrate Psb and a lower concentration than the surface P-type well PWEL, so that the breakdown voltage between the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 It is provided to raise. The deep P-type well DPWEL is annularly arranged so as to surround the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 in FIG.

  In addition, in the present embodiment, a P-type impurity layer (P-type ring, first conductivity type impurity ring in a broad sense) 280 is arranged in a ring shape in plan view on the surface layer of the separation space G2. The formation region of the P-type ring 280 surrounds both the annular N-type well NWEL1 and the strip-shaped N-type well NWEL2 as shown in FIG.

  Providing the P-type ring 280 prevents the potential in the separation space G2 from being inverted by turning on the parasitic transistor even if the metal wiring that can serve as the gate of the parasitic transistor straddles the separation space G2. It is. In this embodiment, the length of the separation space G2 is 4.5 μm, and the width of the P-type ring 280 located at the center of the separation space G2 is 0.5 μm. However, from the viewpoint of preventing the potential inversion, the polysilicon layer and the first layer metal wiring that can be the gate of the parasitic transistor are not formed across the separation space G2. The metal wiring of the second layer or higher is designed to be able to straddle the separation space G2.

  FIG. 21 can be given as a modification of FIG. In FIG. 21, the annular deep layer P-type well DPWEL is not provided in the separation space G2, but an annular surface layer P-type well SPWEL (first conductivity type annular surface well in a broad sense) is provided instead. The P-type ring 280 is formed in an annular surface layer P-type well SPWEL. A space G1 (for example, 1 μm) between the other long side region NWEL1-1 of the annular N-type well NWEL1 and the surface layer P-type well SPWEL is provided to ensure a withstand voltage of 20 V for the same reason as described above.

3.4. Control Circuit Block Next, the control circuit block 202 shown in FIG. 8 will be described. FIG. 22 is a block diagram of the control circuit block 202, and FIG. 23 is a layout diagram of the control circuit block 202. The control circuit block 202 is a circuit block for controlling data programming (writing), reading and erasing to the memory cells MC in the memory cell array block 200. As shown in FIG. 22, the control circuit block 202 includes a power supply circuit 300, a control circuit 302, an X predecoder 304, a Y predecoder 306, a sense amplifier circuit 308, a data output circuit 310, a program driver 312, and a data input circuit. 314 and the column driver 316 (CLDrv) described above. The input / output buffer 318 shown in FIG. 23 includes the data output circuit 310 and the data input circuit 314 shown in FIG. The power supply circuit 300 includes a VPP switch 300-1, a VCG switch 300-2, and an ERS (erase) switch 300-3.

  As shown in FIG. 23, the memory cell array block 200 and the control circuit block 202 are adjacent in the D1 direction. The data read from the memory cell array block 200 passes through the control circuit block 202 and the input / output buffer 318 in the control circuit block 202 in the direction (D1) in which the bit line BL of the memory cell array block 200 extends. Direction).

  Here, as described with reference to FIGS. 3A and 3B, the programmable ROM 20 is arranged adjacent to the block of the logic circuit LB or the power supply circuit PB, which is the data transfer destination, in the D1 direction. . In addition, if the control circuit block 202 of the programmable ROM 20 is arranged adjacent to the block of the logic circuit LB or the power supply circuit PB, which is the data transfer destination, in the D1 direction, data is supplied through a shorter path. it can.

4). Inspection using programmable ROM and data register 4.1. Data Register Unit In this embodiment, as shown in FIG. 24, in addition to the programmable ROM 20, a data register 600 for storing inspection data from the outside is provided. The data register 600 is connected to a selector 610 provided between the sense amplifier circuit 308 and the data output circuit 310 shown in FIG. 22, and one output data of the sense amplifier circuit 308 and the data register 600 is selected by the selector 610. And sent to the data output circuit 310.

  The selector 610 receives N = 8 first to Nth 1-bit selectors 610- to which N (N is an integer of 2 or more) bits, for example, each bit of the sense amplifier outputs SA0-SA7 of N = 8 bits is input. 0-610-7. The data register 600 also has N = 8, for example, first to Nth flip-flops (registers) 600-1 to 600-7, and each bit output Q is sent to the 1-bit selectors 610-0 to 610-7. Each is entered.

  The output of the AND gate 620-k to which the data Dink and the register write signal RRS are input is input to the data terminal D of the kth flip-flop 600-k (k = 0 to 7). That is, the data Dink is input to the data terminal D of the kth flip-flop 600-k only when the register write signal RRS is active (high active in this embodiment). Here, the data Din0 to Din7 are inspection data or command data input from the outside via the input side interface area 14 shown in FIG. 1, and the inspection data is written in the flip-flop 600-k.

  The outputs of the AND gates 630 to which the operation clock OPCK and the register write signal RRS are input are commonly input to the clock terminals C of the flip-flops 600-0 to 600-7. That is, the operation clock OPCK is input to the clock terminal C of the kth flip-flop 600-k only when the register write signal RRS is active.

  FIG. 24 further includes a selector control circuit 640 that controls switching of the selector 610. In the present embodiment, the selector control circuit 640 includes a selector control register 642 and three AND gates 644, 646, 648. Eight input data Din0 to Din7 are input to the AND gate (logic gate in a broad sense) 644. That is, the output of the AND gate 644 becomes “1” only when all the data Din0 to Din7 are “1” as the selector switching command.

  An output line of an AND gate 646 to which an AND gate 644 and a register output signal ROS are input is connected to a D terminal of the selector control register (for example, flip-flop) 642. That is, the selector switching data “1” is input to the D terminal of the selector control register 642 only when all the data Din0 to Din7 are “1” as the selector switching command and the register output signal ROS is active. Is done.

  An output line of an AND gate 648 to which the register output signal ROS and the operation clock signal OPCK are input is connected to the C terminal of the selector control register 643. That is, the operation clock OPCK is input to the C terminal of the selector control register 642 only when the register output signal ROS is active.

  In this embodiment, in order to reset the flip-flops 600-0 to 600-7 and 642, a macro cell selection signal MS for selecting a macro cell including the data register 610 and the register control circuit 640 is used. In the present embodiment, when the macro cell selection signal MS changes from active (High) to non-active (Low), the flip-flops 600-0 to 600-7 and 642 are reset. Here, if the timing when the flip-flops 600-0 to 600-7 are reset is earlier than the timing when the flip-flop 642 as the selector control register is reset, the data after the flip-flops 600-0 to 600-7 are set. Is output from the selector 610. Therefore, a delay circuit 650 is provided so that the macro cell selection signal MS arrives at the reset terminals of the flip-flops 600-0 to 600-7 with a delay.

  A data output circuit 310 shown in FIG. 22 is provided following the selector 610. The data output circuit 310 includes a latch circuit 310-1 that is enabled by a latch signal and latches the output of each bit selector 610-k. The data output circuit 310 has an output transistor 310-2 in which P-type and N-type transistors are connected in series at the output stage. The output of the OR circuit 310-4 to which the output of the inverter 310-3 for inverting the data output signal and the output of the latch circuit 310-1 are input is input to the gate of the P-type transistor. Further, the output of the AND gate 310-5 to which the data output signal and the output of the latch circuit 310-1 are input is input to the gate of the N-type transistor.

4.2. Inspection Method Next, an inspection method using both the programmable ROM 20 and the data register 600 will be described with reference to the timing chart of FIG. Since the output of the selector control register 642 is LOW when using the data of the programmable ROM 20, the selector 610 selects the outputs SA0 to SA7 of the sense amplifier circuit 308 in FIG. The sense amplifier outputs SA0 to SA7 are output via the data output circuit 310. In this inspection, for example, all 0 and all 1 are output as the sense amplifier outputs SA0 to SA7, and for example, the connection inspection between the programmable ROM 20 and the logic circuit LB or the power supply circuit PB can be performed.

  Here, there is a case where the detection rate is low in the connection inspection of only the data stored in advance in the programmable ROM 20. In this case, it is possible to store new inspection data in the programmable ROM 20 at the time of inspection, but the data writing time to the programmable ROM 20 is relatively long (in this embodiment, for example, 1.6 ms / byte is a development target).

  Therefore, it is possible to input additional inspection data from the outside and perform the inspection without going through the programmable ROM 20. That is, in this embodiment, additional inspection data from the outside is stored in the data register 600 instead of the programmable ROM 20.

4.2.1. Write period of test data to data register (first period)
When the test data is written in the data register 600, the logic circuit LB, based on an external command, the erasing (ER) logic signal, the program (PR) logic signal, and the control gate (CG) logic originally used for the programmable ROM 20 As shown in FIG. 25, the signal is set to a signal peculiar to “write to data register”. Based on the logic of these three logic signals, as shown in FIG. 25, only the register write signal RRS among the four types of signals RRS, ROS, RS, and DOS becomes active (HIGH).

  Next, 8-bit write data Din0 to Din7 are input to the driver IC 10 via N = 8 input terminals of the input side interface region 14 shown in FIG. As shown in FIG. 24, data Dink is supplied to the data terminal D of the k-th (k = 0 to 7) flip-flop 600-k as the output of the k-th AND gate 620-k. Become. Subsequently, as shown in FIG. 25, the first operation clock OPCK1 after the macro cell selection signal MS becomes active is supplied to the clock terminals C of all the flip-flops 600-0 to 600-7 via the AND gate 630. Is input. Then, 8-bit write data Din0 to Din7 are written to the flip-flops 600-0 to 600-7 at the rising edge of the first operation clock OPCK1, and output from the output terminal Q. However, since the data selector 610 has selected the sense amplifier output at this time, the outputs from the flip-flops 600-0 to 600-7 are not output via the data selector 610.

4.2.2. Sense amplifier / register output switching setting period (second period)
In the next SA (sense amplifier) / Reg (register) output switching setting period, the erase (ER) logic signal, the program (PR) logic signal, and the control gate (CG) logic signal change as shown in FIG. Thereby, in this SA / Reg switching period, the register write signal RRS changes to Low and the register output signal ROS changes to High.

  In this SA / Reg switching period, 8-bit write selector switching commands Din0 to Din7 are input to the driver IC 10 through N = 8 input terminals of the input side interface region 14 shown in FIG. In this embodiment, the selector switching commands Din0 to Din7 shown in FIG. 25 are set to All High. The selector switching commands Din0 to Din7 are input to the AND gate 644 of the selector control circuit 640, and the output of the AND gate 644 becomes High. Since the register output signal ROS is also High, the data High is supplied to the data terminal D of the flip-flop 642 of the selector control circuit 640. The selector switching commands Din0 to Din7 described above are not supplied to the flip-flops 600-1 to 600-7 of the data register 600. This is because the register write signal RRS is Low and is blocked by the AND gates 620-0 to 620-7.

  Subsequently, as shown in FIG. 25, the second operation clock OPCK 2 after the macro cell selection signal MS becomes active is input to the clock terminal C of the flip-flop 642 via the AND gate 648. The output switching data (High) from the AND gate 646 is written to the flip-flop 642 by the rising edge of the second operation clock OPCK2, and the output switching data (High) is sent from the flip-flop 642 to each bit selector 610-0. To 610-7. As a result, each of the bit selectors 610-0 to 610-7 switches to select the output from the output terminals Q of the flip-flops 600-0 to 600-7 instead of the sense amplifier outputs SA0 to SA7.

4.2.3. Data read period (third period)
In the next data read period, the erase (ER) logic signal, the program (PG) logic signal, and the control gate (CG) logic signal change as shown in FIG. As a result, the register output signal ROS changes to LOW, and the data output signal DOS changes to HIGH.

  In this data read period, the inspection data written in the flip-flops 600-0 to 600-7 is replaced with the output from the programmable ROM 20 via the bit selectors 610-0 to 610-7. This is supplied to the data output circuit 310 by the latch signal RS which becomes HIGH in synchronization with the operation clock OPCK3 of the eye.

  Here, a circuit (not shown) that generates the latch signal RS generates the latch signal RS based on the three logic signals ER, PG, and CG and the operation clock OPCK. In the present embodiment, in the data read period (third period) in which the three logic signals ER, PG, and CG are all LOW, the latch signal RS is supplied over the period in which the third operation clock OPCK3 is HIGH. Become HIGH.

  In FIG. 24, the third operation clock OPCK3 is also input to the AND gates 630 and 648. Since the other inputs RRS and ROS of the AND gates 630 and 648 are both LOW, the flip-flop The operation in 600-0 to 600-7, 642 is not changed between the second period and the third period.

  In the data output circuit 310, since the latch signal RS and the data output signal DOS are both High during the data read period as shown in FIG. 25, the test data from each of the bit selectors 610-0 to 610-7 is latched. 1 and latched when the latch signal RS falls to Low. Based on the logic of the output terminal Q of the latch circuit 310-1, the output transistor 310-2 is driven to output inspection data.

  In this way, instead of the programmable ROM 20 having a low writing speed, the data register 600 capable of rewriting data in a short time such as nano-order is handled like a RAM, so that the inspection time can be improved while improving the defect detection rate. It can be greatly shortened.

5. Electronic Device FIGS. 26A and 26B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic device may include components other than those shown in FIGS. 26A and 26B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  26A and 26B, the host device 410 is, for example, an MPU (Micro Processor Unit), a baseband engine (baseband processor), or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. An image processing controller (display controller) 420 in FIG. 26B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  The display panel 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. The display panel 400 can be constituted by an active matrix panel using switching elements such as TFTs and TFDs. Note that the display panel 400 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel.

  In the case of FIG. 26A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 26B, the integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input-side I / F) described at least once together with different terms having a broader meaning or the same meaning (first interface region, second interface region, etc.) (Area, etc.) can be replaced with the different terms anywhere in the specification or drawings. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

  For example, in the present invention, the memory cell MC constituting the programmable ROM (nonvolatile data memory) may have a single layer gate structure using a well instead of the impurity layer NCU. Further, the gate is not necessarily limited to a single-layer gate, and may be a two-layer gate.

  In addition, the first conductivity type of the semiconductor substrate on which the programmable ROM is mounted can be an N type.

It is a figure which shows the structural example of the integrated circuit device of this embodiment. It is a figure which shows the example of various types of display drivers and the circuit block which it incorporates. 3A and 3B are diagrams showing an example of a planar layout of the integrated circuit device of this embodiment. 4A and 4B are diagrams illustrating examples of cross-sectional views of the integrated circuit device. It is a block diagram which shows the relationship between programmable ROM, a logic circuit, and a gradation voltage generation circuit among the circuit blocks shown to FIG. 3 (A). 6A, 6B, and 6C are characteristic diagrams showing gradation voltages adjusted by the circuit of FIG. It is a block diagram of the structural example of the display apparatus containing an electro-optical apparatus. It is a figure which shows the layout of the programmable ROM block in an integrated circuit device. It is a figure which shows the layout of the comparative example with respect to FIG. It is a top view of the memory cell of the single layer gate arrange | positioned in programmable ROM. FIG. 11 is an equivalent circuit diagram of the memory cell shown in FIG. 10. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a program (write) principle in a memory cell. It is a figure explaining transition of the threshold value of the write / read transistor after programming. FIG. 11 shows a cross section taken along line B-B ′ of FIG. It is a figure explaining transition of the threshold value of the write / read transistor after erasure. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a principle of reading data from a memory cell in a write state. FIG. 11 is a cross-sectional view taken along the line A-A ′ of FIG. 10, illustrating a principle of reading data from a memory cell in an erased state. It is a top view of the memory cell array block of programmable ROM. It is a top view of two adjacent memory cells. It is C-C 'sectional drawing of FIG. It is a figure which shows the modification of FIG. It is a block diagram of programmable ROM. It is a figure which shows the planar layout of the whole programmable ROM. It is a circuit diagram of a data register, a selector, and a selector control circuit. It is a timing chart which shows the inspection method using the circuit shown in FIG. 26A and 26B are diagrams each illustrating a configuration example of an electronic device.

Explanation of symbols

  CB1 to CBN ... 1st to Nth circuit blocks, 10 ... integrated circuit device, 12 ... output side I / F area, 14 ... input side I / F area, 20 ... programmable ROM (nonvolatile data memory), 21 ... 1st memory cell block, 22 ... 2nd memory cell block, 23 ... Memory cell block, 24 ... Memory cell block, 200 ... Memory cell array block, 202 ... Control circuit block, 210 ... Control gate part, 220 ... Write / Read transistor 230 ... Erase transistor 240 ... Transfer gate 250 ... Main word line / control gate line driver region 260 ... Memory cell region 270 ... Sub word line decoder region 280 ... P-type ring 300 ... Power supply circuit 302 ... Control circuit, 304 ... X Decoder, 306 ... Y predecoder, 308 ... Sense amplifier circuit, 310 ... Data output circuit, 312 ... Program driver, 314 ... Data input circuit, 318 ... Input / output buffer, 600 ... Data register, 600-1 to 600- 7 ... 1st to Nth registers (flip-flops), 610 ... selector, 610-0 to 610-7 ... bit selector, 620 ... logic gate (AND gate), 640 ... selector control circuit, 642 ... selector control register 644 ... Logic gate (AND gate), BL ... Bit line, CG (NCU) ... Control gate, FG ... Floating gate, LB ... Logic circuit (gate array), MC ... Memory cell, NWEL1 ... Ring N-type well, NWEL2 ... strip N-type well, PB ... power supply circuit block , PWEL ... P-type well, Xfer (P) ... transfer gate of the PMOS, Xfer (N) ... transfer gate of the NMOS, WL ... word line

Claims (10)

An input interface circuit;
A non-volatile data memory in which first inspection data is stored in advance via the input interface circuit;
A data register for storing second inspection data via the input interface circuit at the time of inspection;
A selector for selecting one output of the nonvolatile data memory and the data register;
A selector control circuit for switching the selector according to a selector switching command input via the input interface circuit;
An integrated circuit device comprising: In claim 1,
The input interface circuit has an input terminal to which N (N is an integer of 2 or more) bits of inspection data or a selector switching command is input.
Each of the first and second inspection data is N-bit inspection data;
The integrated circuit device, wherein the selector control circuit performs switching control so that the selector selects an output of the data register based on an output of a logic gate to which an N-bit selector switching command is input. In claim 2,
The data register includes first to Nth registers, and each bit of the second check data of N bits is stored in the first to Nth registers during a first period in which a register write signal is active. Is written respectively
The selector control circuit includes a selector control register, and output switching data is written to the selector control register based on an output from the logic gate in a second period in which a register output signal becomes active after the first period. An integrated circuit device. In claim 3,
The first to Nth registers are each written with N bits of the second test data based on the first operation clock input during the first period,
In the selector control register, each bit of the selector switch command of N bits is written based on the second operation clock input during the second period,
In the second period, the second inspection data is read from the first to Nth registers, and the output switching data is read from the selector control register, and the second data is read by the selector. An integrated circuit device characterized by selecting inspection data. In claim 4,
A data output circuit is connected to the subsequent stage of the selector, and the data output circuit includes a latch circuit,
Based on a latch signal that becomes active in synchronization with a third operation clock input during a third period after the second period, the second inspection data selected by the selector is input to the latch circuit. An integrated circuit device that is latched. In any of claims 3 to 5,
The integrated circuit wherein the first to Nth registers and the selector control register are reset when a macro cell selection signal for selecting a macro cell including the data register and the selector control circuit changes from active to non-active. Circuit device. In claim 6,
A delay circuit is provided in the macro cell selection signal supply line, and the delay circuit delays the timing at which the first to Nth registers are reset from the timing at which the selector control register is reset. Integrated circuit device. In claim 6 or 7,
The nonvolatile data memory is controlled based on a plurality of logic signals for controlling erase, program and control gates,
The integrated circuit device, wherein the macro cell selection signal is generated based on a combination of logics of the plurality of logic signals. In any one of Claims 1 thru | or 8.
Each of the plurality of memory cells provided in the nonvolatile data memory is
A write / read transistor and an erase transistor formed on a semiconductor substrate;
A floating gate shared by the gates of the write / read transistor and the erase transistor;
An integrated circuit device comprising: a control gate formed in an impurity region formed in the semiconductor substrate, the floating gate being formed at a position facing the floating gate via an insulating layer. An integrated circuit device according to any one of claims 1 to 9,
A display panel driven by the integrated circuit device;
An electronic device comprising: