JP4718703B2 - Automatic phase detection method in ATM main signal phase adjustment circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a main signal phase adjustment circuit used in an ATM digital transmission apparatus, and more particularly to a main signal phase adjustment circuit capable of automatically detecting an output frame phase.
[0002]
[Prior art]
Conventionally, a main signal phase adjustment circuit used in an ATM digital transmission apparatus is realized by giving an output phase in binary from an external terminal of an LSI.
[0003]
[Problems to be solved by the invention]
In the conventional main signal phase adjustment circuit described above, since the phase to be transmitted is given in binary by the external terminal of the LSI, the external terminal of the LSI increases, and the phase value to be set is calculated in advance and set to the external terminal. There was a problem that had to be placed.
[0004]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a main signal phase adjustment circuit in which the external terminals of an LSI are reduced.
[0005]
Another object of the present invention is to provide a main signal phase adjustment circuit that does not require the phase to be transmitted to be calculated and set in advance.
[0006]
[Means for Solving the Problems]
The present invention relates to a main signal phase adjustment circuit, which adjusts the frame phase of an ATM main signal to a frame phase that can be received by a reception buffer provided in an LSI of a next-stage package, and sends it out. the periodic cell detection result notification signal indicating a whether receivable frame range of the frame phase the reception buffer of the ATM main signal received by the receiving buffer received from the receive buffer, wherein the periodic cell detection result notification Phase setting value generation means for setting the output frame phase of the ATM main signal to be in the middle of the capacity of the reception buffer based on the signal is provided.
[0007]
Further, the phase setting value generation means of the present invention includes a count timing generation means for dividing the in-package frame phase signal and outputting the divided frame phase signal, a counter means for counting the divided frame phase signal, and the period And a phase determination unit that calculates a frame phase that is in the middle of the capacity of the reception buffer within the receivable frame phase range indicated by the cell detection result notification signal from the output signal of the counter unit.
[0008]
The phase determining means of the present invention latches the output signal of the counter at a timing when the periodic cell detection result notification signal changes from a state indicating outside the receivable frame phase range to a state indicating within the receivable frame phase range. 1 latch means, and a second latch for latching the output signal of the counter at a timing when the periodic cell detection result notification signal is changed from a state indicating the within the receivable frame phase range to a state indicating the outside of the receivable frame phase range. Means, a subtracter for subtracting the output signal of the counter means latched by the first latch means from the output signal of the counter means latched by the second latch means, and an output signal of the subtractor A first adder for adding the signal shifted right by 1 bit and the LSB of the output signal of the subtractor; and the output of the first latch circuit A second adder for adding a signal to the output signal of the first adder, and a selection switching means for selecting and outputting either the output signal of the second adder or the output signal of the counter It is characterized by providing.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the main signal phase adjustment circuit of this embodiment. As shown in FIG. 1, the main signal phase adjustment circuit of the present embodiment includes a main signal processing unit 1 in the LSI 20 on the previous stage PKG, a periodic cell insertion unit 2 that delays the main signal, and a periodic cell insertion unit 2. A frame phase adjustment unit 3 that transfers the delayed main signal to a frame phase that can be received by the bit buffer unit 5 in the LSI 30 of the subsequent stage PKG, and a period that is notified from the periodic cell detection unit 6 in the LSI 30 of the subsequent stage PKG. The phase setting value generation unit 4 determines the optimum output frame phase of the frame phase adjustment unit 3 based on the detection result notification signal S8 of the fixed pattern on the cell.
[0010]
FIG. 2 is a block diagram showing an internal configuration of the phase setting value generation unit 4. As shown in FIG. 2, the phase setting value generation unit 4 uses a count timing generation unit 7 that generates a count-up timing from the frame phase signal S14 in its own PKG, and the timing generated by the count timing generation unit 7. From the counter unit 8 that counts and the phase determination unit 9 that determines the optimum output frame phase of the frame phase adjustment unit 3 based on the detection result notification signal S8 output from the periodic cell detection unit 6 of the LSI 30 of the post-stage PKG. Composed.
[0011]
Next, the operation of this embodiment will be described in detail with reference to the drawings. FIG. 3 is an explanatory diagram showing the relationship between the output phase signal output from the phase setting value generation unit 4 and the output frame phase of the frame phase adjustment unit 3.
[0012]
The frame phase adjustment unit 3 can receive the main signal delayed by the periodic cell insertion unit 2 by the bit buffer unit 5 in the LSI 30 of the subsequent stage PKG by controlling the phase signal S7 output from the phase setting value generation unit 4. Change to frame phase. At this time, the phase setting value generation unit 4 generates an optimum phase setting value based on the periodic cell detection determination in the periodic cell detection unit 6, but the periodic cell detection determination in the periodic cell detection unit 6 requires several frames. Takes time.
[0013]
In order to achieve the matching, the count timing generation unit 7 divides the frame phase signal S14 in the PKG by n to generate a divided frame phase signal S15 and outputs it to the counter unit 8. The counter unit 8 performs counting using the divided frame phase signal S15 as a clock, and outputs a counter output signal 16 to the phase determination unit 9. The phase determination unit 9 outputs the counter output signal S16 input from the counter unit 8 to the frame phase adjustment unit 3 as the phase signal S7.
[0014]
When the counter output signal S16 is input as the phase signal S7, the frame phase adjustment unit 3 decodes the counter output signal S16 and outputs an output frame phase signal S10 obtained by delaying the input frame phase signal S6 by one clock.
[0015]
Next, the operation of the phase determination unit 9 of the phase setting value generation unit 4 will be described. FIG. 4 is a time chart showing the operation of the phase determination unit 9 of the phase setting value generation unit 4. It is assumed that the read phase of the bit buffer unit 5 of the LSI 30 is at a position delayed by 17 clocks with respect to the input frame phase signal S6 of the frame phase adjustment unit 3, and the capacity of the bit buffer unit 5 is 6 bits. explain.
[0016]
As described above, when the output frame phase signal S10 of the frame phase adjustment unit 3 is sequentially delayed by one clock with respect to the input frame phase signal S6, as shown in FIG. 5 capacity range. At this time, the periodic cell detection unit 6 detects the periodic cell at the head of the frame phase.
[0017]
Then, the periodic cell is correctly detected within the capacity range of the bit buffer unit 5, and the periodic cell is not detected otherwise. Therefore, the periodic cell detection unit 6 outputs a detection result notification signal S8 as shown in FIG.
[0018]
The phase determination unit 9 latches the counter output signal S16 when the detection result notification signal S8 changes from NG to OK (Lo to Hi) and the counter output signal S16 when the detection result notification signal S8 changes from OK to NG (Hi to Lo). Then, the output frame phase signal S10 of the frame phase adjustment unit 3 which is the middle of the capacity of the bit buffer unit 5 is calculated from the value.
[0019]
FIG. 5 is a block diagram illustrating an internal configuration of the phase determination unit 9. Here, the calculation operation of the phase determination unit 9 will be described in detail with reference to FIG. The latch 11 holds the counter output signal S16 of the counter unit 8 at the latch timing output from the latch / switch timing generation unit 10 when the detection result notification signal S8 changes from NG to OK.
[0020]
The latch 12 holds the counter output signal S16 of the counter unit 8 at the latch timing output from the latch / switch timing generation unit 10 when the detection result notification signal S8 changes from OK to NG. The subtractor 13 obtains the capacity of the bit buffer unit 5 by subtracting the value of the latch 11 from the value of the latch 12, and is “6” in this example. The adder 14 adds the lower 1 bit of the output of the subtracter 13 and the remaining bits, thereby obtaining an intermediate position of the bit buffer capacity.
[0021]
Here, a calculation example of the adder 14 will be described with reference to FIG. “0110” of the output of the subtractor 13 is shifted by 1 bit to the LSB side to obtain “011” which is a half value of the bit buffer capacity, and “0” of the LSB bit is added to “011”. Rounds up when a fractional part occurs.
[0022]
Returning to FIG. 5, the adder 15 adds the minimum value of the output phase of the frame phase adjustment unit 3 that can be received by the LSI 30 (the value of the latch 11) to the middle of the capacity of the bit buffer unit 5 obtained by the above calculation. The position value is added, and the optimum value of the output phase of the frame phase adjustment unit 3 that can be received by the LSI 30 is obtained.
[0023]
In the present embodiment, as shown in FIG. 4, the delay 14 of the output frame phase signal S10 of the frame phase adjustment unit 3 is an optimum value. The 2: 1 SEL 16 switches the phase signal S 7 output from the phase determination unit 9 from the output of the counter unit 8 to the output of the adder 15 in response to the SEL switching signal from the latch / switch timing generation unit 10.
[0024]
As described above, in the present embodiment, since the position of the output phase of the frame phase adjustment unit 3 is an intermediate point of the capacity of the bit buffer unit 5 in the LSI 30 at the next stage, the LSI 30 can perform stable reception without error. It becomes possible.
[0025]
【The invention's effect】
The main signal phase adjustment circuit of the present invention can reduce the number of external terminals of the LSI and can reduce the size of the LSI. The reason is that the phase setting value conventionally given from the external terminal can be automatically determined and set in the LSI.
[0026]
Further, the main signal phase adjustment circuit of the present invention has an effect that it is not necessary to determine and set the transmission phase in advance, and the operability can be improved. The reason for this is that the phase setting value conventionally given from the external terminal can be automatically determined and set within the LSI.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing an internal configuration of a phase setting value generation unit.
FIG. 3 is a term chart showing a relationship between a phase signal output from a phase set value generation unit and an output phase of a phase adjustment unit;
FIG. 4 is a time chart illustrating the operation of a phase determination unit.
FIG. 5 is a block diagram showing an internal configuration of a phase determination unit.
6 is an explanatory diagram showing a calculation process of an adder 14. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Main signal processing part 2 Periodic cell insertion part 3 Frame phase adjustment part 4 Phase setting value generation part 5 Bit buffer part 6 Periodic cell detection part 7 Count timing generation part 8 Counter part 9 Phase determination part 10 Latch, switching timing generation part 11 , 12 Latch unit 13 Subtractor 14, 15 Adder 16 2: 1SEL
20, 30 LSI
S1 Main signal processing unit input main signal S2 Main signal processing unit input frame phase signal S3 Periodic cell insertion unit input main signal S4 Periodic cell insertion unit frame phase signal S5 Frame phase adjustment unit input main signal S6 Frame phase adjustment unit input frame phase signal S7 Phase signal S8 Detection result notification signal S9 Frame phase adjuster output main signal S10 Frame phase adjuster output output frame phase signal S11 Periodic cell detector input main signal S12 Periodic cell detector input frame phase signal S13 Bit buffer read frame phase S14 Frame phase signal S15 Divided frame phase signal S16 Counter output signal

Claims (3)

In the main signal phase adjustment circuit for adjusting the frame phase of the ATM main signal to a frame phase that can be received by a reception buffer provided in the LSI of the next stage package, the frame of the ATM main signal received by the reception buffer receiving a periodic cell detection result notification signal indicating whether or not receivable frame range of phase the receive buffer from the reception buffer, the output frame phase of the ATM main signal on the basis of the periodic cell detection result notification signal is the A main signal phase adjustment circuit comprising phase setting value generation means for setting the intermediate capacity of a reception buffer . The phase setting value generation means is a count timing generation means for dividing the frame phase signal in the package and outputting the divided frame phase signal; a counter means for counting the divided frame phase signal; and the periodic cell detection result 2. A phase determination unit that calculates a frame phase that is intermediate between the capacities of the reception buffers within a receivable frame phase range indicated by a notification signal from an output signal of the counter unit. Main signal phase adjustment circuit.   The phase determination means is a first latch that latches the output signal of the counter at a timing when the periodic cell detection result notification signal is changed from a state indicating outside the receivable frame phase range to a state indicating within the receivable frame phase range. And a second latch means for latching the output signal of the counter at a timing when the periodic cell detection result notification signal changes from a state indicating within the receivable frame phase range to a state indicating outside the receivable frame phase range; A subtracter for subtracting the output signal of the counter means latched by the first latch means from the output signal of the counter means latched by the second latch means; A first adder for adding the shifted signal and the LSB of the output signal of the subtractor; the output signal of the first latch circuit; A second adder for adding the output signal of the first adder; and a selection switching means for selecting and outputting one of the output signal of the second adder and the output signal of the counter. 3. The main signal phase adjusting circuit according to claim 2, wherein

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