JPS62205578A - Timing control circuit - Google Patents

Abstract

PURPOSE:To obtain a clock with an optimum phase by comparing the number of errors of a reproducing digital signal with a frame cycle, reversing a counting direction when the number of errors is increased, and selecting a delay signal according to the counted value. CONSTITUTION:An error detection circuit 22 detects the error of the reproducing digital signal, outputs an error pulse, a counter 7 counts every frame and latches to the first latch circuit 8. The second latch circuit 9 latches the output A of the circuit 8 by delaying by one frame. The outputs A, B of the circuits 8, 9 are compared by a comparator 10, when A>B, namely, the generation of the errors is increased, the counting direction is reversed, and when A<B, namely, the generation of the errors is reduced, the counting direction is maintained. An up down counter 13 performs the addition and the subtraction of preset data at a constant cycle, supplies to a decoder 14 and selects the delay signal. Thereby, the dislocation in a latch timing is automatically secured and the clock with the optimum phase can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a magnetic recording and reproducing device for recording and reproducing digital signals, and more particularly to a timing control circuit that controls the data and clock timing of demodulated digital signals.

[Prior Art] A conventional timing control circuit of this type is shown in FIG. The reproduced digital signal demodulated by the equalizer is supplied to the latch circuit 5 and the resonator l. The reproduced digital signal includes a data signal and a clock signal, and the clock signal is separated from the reproduced digital signal by the resonator 1, amplified and shaped by the amplifier 2 and the PLL circuit 3, and supplied to the delay circuit 4. The delay circuit 4 has a plurality of gates Gl, G1 . , G5 are connected in series, and PL
The clock signal output from the L circuit 3 is sent to the gate G1,
G2. , , is sequentially delayed as shown in the timing chart of FIG. These gates G1. G2
．． , , is selected as appropriate and the latch circuit 5
Data 4i! of the reproduced digital signal is determined by the timing of the output of the selected gate that is supplied to the clock terminal of the gate. 3
- is latched by the latch circuit 5.

In this way, the clock signal and data 4'f are separated from the first raw digital signal and output.

[Problems to be Solved] Incidentally, if the delay time of the gate G changes due to a rise in temperature or the like, the latch timing of the latch circuit 6 will deviate from the optimum point. In this case, it is necessary to switch to the output of another gate G. However, in conventional timing control circuits, the contacts are fixed, making it extremely difficult to switch the gates.

The latch timing can be changed relatively easily by changing the resonant frequency of the resonator, but this has the disadvantage that the output level of the clock component from the resonator changes.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a timing control circuit that can select an appropriate delay signal and automatically guarantee a shift in lunch timing.

[Means for Solving Problems] In order to achieve the above object, the present invention separates a clock signal from a reproduced digital signal, further delays this clock signal in multiple stages, and converts data from the reproduced digital signal using the delayed signal in appropriate stages. In the timing control circuit for extracting a signal, (a) an error detection circuit that detects an error in extracting the data signal; (b) a counter that counts the number of error detections of this error detection circuit; and (C) a count value of this counter. (d) a second latch circuit that latches the retention result of the first latch circuit at the constant cycle; and (e) retention of the first launch circuit. a comparison circuit that compares the holding result of the second latch circuit with the holding result of the second latch circuit; If the number is larger than that, the counting direction is reversed, while the first
(g) an up/down counter that holds the counting direction when the holding result of the second latch circuit is smaller than the holding result of the second latch circuit and performs addition or subtraction at the constant cycle; and a decoder that selects the delayed signal by decoding the counted value of .

[Embodiments] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a timing control circuit according to an embodiment of the present invention, and the same parts as those of the conventional timing control circuit shown in FIG. 5 described above are given the same reference numerals.

A reproduced digital signal reproduced from a magnetic tape (not shown) and demodulated by an equalizer is supplied to the antenna 5 and the resonator l. A clock signal is separated from the reproduced digital signal by the resonator 1, the amplifier 2, and the PLL circuit 3, and is supplied to the delay line DLY via the buffer 6.

The output of each tap of this delay line DLY is a Nantes gate 15, 16, . ,．． 19 is supplied to the first input terminal. Namely, Noah Gate 15.16. ,．． 1st of 19
Clock signals with different d-embeddings are supplied to the input terminals. On the other hand, Noah Game) 15.16. ,．． The second input terminal of the decoder 19 is connected to each output terminal of the decoder 14, and therefore, by setting one of the output terminals of the decoder 14 to "L" and the other to "H", the output terminal is set to "L". A clock signal is output from the NOR gate connected to. Noah Gate 15.16,,. The outputs of 19 are wired-OR connected and supplied to each clock terminal of the latch 5, the signal processing circuit 21, and the error detection circuit 22 via the buffer 20. The latch circuit 5 latches the data signal included in the reproduced digital signal at the timing of the supplied clock signal and supplies it to the signal processing circuit 21.

The signal processing circuit 21 converts the serial data supplied from the latch circuit 5 into a parallel data and outputs it as data, and also supplies it to the error detection circuit 22 . In addition,
The signal processing circuit 21 also detects 5YNC. ~Generally, the reproduced data signal has an error detection code added to it to detect errors during reproduction3, and an error detection circuit 2
2 detects whether an error has occurred in the data supplied from the signal processing circuit 21, and if an error is detected, supplies an error pulse to the clock terminal of the counter 7.

The counter 7 counts these error pulses during one frame and supplies the counting result to the first latch circuit 8. The first latch circuit 8 latches the counting result for each frame and supplies it to the comparator 10 and the second latch circuit 9.

Similarly, the second latch circuit 9 latches the latch result of the first latch circuit 8 for each frame and supplies it to the comparator IO.

The comparator 10 compares the latching results of both latch circuits 8 and 9, and outputs "H" when A<B, that is, the latching result of the first latch circuit 8 is smaller than the latching result of the second latch circuit 9. do. This output is supplied to the first input terminal of the exclusive event gate 11. The output of this exclusive evenor gate 11 is supplied to the up/down terminal U/D of the up/down counter 13, and
Each frame is latched by the latch circuit 12, and the latched result is supplied to the second input terminal of the exclusive event gate 11.

The up/down counter 13 adds/subtracts the preset data set at the same time as the power is turned on for each frame according to the addition/subtraction instructions supplied from the exclusive event gate 11, and supplies the counting results to the decoder 14. In this example, there are 5 Noah gates, so the counter 13 is in quinary, but the maximum count number of the counter 13 is changed depending on the number of Noah gates.

In the above configuration, the reproduced digital signal demodulated by the equalizer is supplied to the latch circuit 5 and the resonator l. As a result, the clock signal is separated from the reproduced digital signal by the resonator 1, this clock signal is amplified and shaped by the amplifier 2 and the PLL circuit 3, and is further supplied to the delay line DLY via the buffer 6.

As a result, the clock signal whose phase is sequentially delayed from each tap of the delay line DLY is output to the NOR gates 15, 16 to 19.
is applied to the first input terminal of.

On the other hand, these Noah Gate 15.16. ,．． A decode signal obtained by decoding the count value of the up/down counter 13 is supplied from the decoder 14 to the second input terminal of the NOR gates 15, 16, . 19 is selected, and the delayed clock signal from the selected NOR gate is supplied to the latch circuit 5 via the buffer 20, and the data signal included in the reproduced digital signal is latched at the timing of the tarlock signal. The data signal latched by the latch circuit 5 is converted into parallel data by the signal processing circuit 21 and output.

On the other hand, if an error occurs during signal reproduction, it is detected by the error detection circuit 22 and an error pulse is output. The error pulses are counted by the counter 7 for each frame, and the counting results are latched by the first latch circuit 8 in each frame.

The output A of the first latch circuit 8 is similarly latched by the second latch circuit 9 frame by frame with a delay of one frame.

The outputs A and B of both latch circuits 8.9 are compared by a comparator 10. In this case, A>B indicates that the error occurrence is increasing, and A<B indicates that the error occurrence is decreasing. When A<B, the output of the comparator 10 becomes "L", and when A<B, the output of the comparator 10 becomes "H". On the other hand, the output of this exclusive evenor gate 11 is latched by a latch circuit 12 for each frame, and is supplied to the second input terminal of the exclusive evenor gate 11.Comparison at this time The relationship between the output of the circuit 10, the output of the latch circuit 12, and the output of the exclusive event gate 11 is shown in FIG. 2. The part surrounded by the broken line in the figure becomes the count mode of the up/down counter 13 in the next frame. The down counter 13 performs addition or subtraction of preset data set at power-on according to this mode, and supplies the count result to the decoder 14.

Next, the operation of this embodiment will be further explained using FIG.

Assume that the output of the up-down counter 13 is at a value Nl greater than the point No at which the number of errors is the minimum, as shown in FIG.

At this time, if the up/down counter 13 is in a count-up state, the number of errors occurring will increase after frame (2), so the A<B output of the comparator 10 becomes L, which is input to the first input terminal of the gate 11. Konoto S game) 1
The second input terminal of gate 1 is H because the up-down counter 13 is in the count-up state, and from FIG. Invert. Therefore, the clock delay state is reduced and the number of errors in the first frame is reduced. Therefore, A of comparator lO
<B output becomes H.

At this time, the inputs of gate 11 are H and L, and its output is L.
Therefore, the up/down counter 13 maintains a countdown state and the number of errors continues to decrease.

The output of up/down counter 13 is the minimum error point No.
When N2 is reached, the operation is as follows.

When the up/down counter -13 is in a countdown state, the number of errors increases after one frame, so the A<B output of the comparator 10 becomes L.

Here, since the up/down counter 13 is in a countdown state, the second input terminal of the gate 11 is at L, and the output of the gate hll is at H. Therefore, the up/down counter 13 is reversed to count up and the clock is delayed! I'' reverses from decreasing to increasing. Therefore, the number of errors in the first frame is reduced, and the A<B output of the comparator IO becomes H. At this time, since both il and the second input terminal of the game controller 11 are at H, its output becomes H, and the quantator 13 maintains a count-up state and the number of errors continues to decrease. In this way, the minimum point of error is automatically searched for.

Incidentally, FIG. 4 shows the count value of the up/down counter 13 and the timing of data input and clock input to the latch 5.

[Effects of the Invention] As described below, the present invention compares the number of errors in reproduced digital signals at each frame period.

If the number of errors increases, the phase of the clock is shifted in the opposite direction from the conventional one, so a clock with an optimal phase can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a timing control circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the up/down control signal of the up/down counter 13 and the error increase/decrease output signal of the comparator 10. , FIG. 3 is a graph showing the relationship between the count value (clock phase) of the up-down counter 13 and the number of error occurrences, and FIG. 4 is a graph showing the relationship between the data input and clock input of the latch circuit 5 with respect to the count value of the up-down counter 13. timing chart shown,
FIG. 5 is a block IA showing the configuration of a conventional timing control circuit, and FIG. 6 is a timing chart for explaining the operation of the timing control circuit. 7: Counter 8: First latch circuit 9: Second latch circuit IO: Comparator 13 near-down counter

Claims (1)

[Scope of Claims] A timing control circuit for separating a clock signal from a reproduced digital signal, further delaying this clock signal in multiple stages, and extracting a data signal from the reproduced digital signal using the delay signal in an appropriate stage, comprising: (a) the above-mentioned method; (b) a counter that counts the number of error detections of this error detection circuit; (c) a first latch circuit that latches the counted value of this counter at a constant cycle; (d) a second latch circuit that latches the holding result of the first latch circuit at the constant cycle; (e) the holding result of the first latch circuit and the holding result of the second latch circuit; (f) according to the comparison result of this comparison circuit, when the holding result of the first latch circuit is larger than the holding result of the second latch circuit, the counting direction is reversed; Said first
(g) an up/down counter that maintains the counting direction and performs addition or subtraction at the constant period when the holding result of the second latch circuit is smaller than the holding result of the second latch circuit; A timing control circuit comprising: a decoder that decodes a count value of a counter and selects the delayed signal.