JP2891535B2 - Digital phase locked loop decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATION The present invention relates to a digital phase locked loop
Related to a decoder.

(Conventional technology and its disadvantages)

The present invention is an application for decoding Manchester encoded data. A signal transition in the Manchester encoded data exists at each intermediate cell location, and the direction of the transition represents the value of the encoded binary bit.

Such a decoder is described in U.S. Pat. No. 4,584,695. This decoder uses a multi-phase driver clock circuit that supplies a clock signal out of phase with the other. One clock output signal is used as the driver clock and provides a sample clock signal at four times the data rate or eight times the data rate in fast clock mode, and the PLL reference clock is the received data signal. Determine whether you are ahead or behind. Therefore,
This known decoder has the disadvantage that relatively fast and inexpensive techniques, such as CMOS, are not suitable for use, requiring a very fast clock signal.

Accordingly, it is an object of the present invention to provide a digital phase locked loop decoder which eliminates the above disadvantages.

[Means for solving the problem]

The present invention has solved the above problems as follows.
According to the present invention, clock signal supply means for supplying a first clock signal at a predetermined nominal rate and first delay line means for delaying the clock signal by a controllable delay time to generate a second clock signal And second delay line means for receiving the second clock signal and supplying a plurality of delay clock signals having respective phase delay times to the signal, and the delay clock signal and the input data signal;
Sampling means for providing a plurality of signal samples of the input data signal in response; phase comparison logic means for providing a counter control signal for controlling operation of the counter means in response to the plurality of signal samples; and the counter means Feedback means connected between the first delay line means and the first delay line means for controlling the controllable delay time, and a decoded output data signal connected to the sampling means and corresponding to a decoded output data signal corresponding to the input data signal And a data output means for supplying a second clock signal at a nominal rate, wherein the second clock signal is controlled in phase to correspond to one selected phase of the plurality of delayed clock signals. A digital phase locked loop decoder for decoding a data signal is provided.

〔Example〕

FIG. 1 is a diagram showing characteristics of Manchester encoded data. Waveform A is a periodic clock signal, and waveform B is NR
Z (non-return to zero) data, waveform C is the corresponding Manchester encoded data signal, and line D is the value of the data bit. Manchester encoded data signal C can be generated by modulo-2 (exclusive OR) adding NRZ data signal B and clock signal A. The Manchester encoded signal consists of bit cells having a duration equal to the data rate, with a transition between each bit cell indicating the value of the data bit. Therefore,
A rising transition indicates a "1" bit, and a falling transition is a "0" bit. A bit-in-bit transition between two bit cells only occurs when two consecutive data bits are equal.

FIG. 2 illustrates a data transmission system in which input data on line 10 is provided to a transmitter 12 and converts the data to a Manchester encoded signal for transmission to a receiver 16 over a transmission channel 14. Receiver 16 decodes the received Manchester encoded signal and provides an output clock signal on line 18 and an output data signal on line 20.

This embodiment of the transmitter 12 uses a system clock signal (FIG. 1A) at a frequency of 10 MHz (bit cells occur at 100 ns (nanosecond) intervals). However, noise and distortion induced in the transmission channel 14 cause signal degradation,
This causes jitter in the intermediate bits and transitions in the bits as shown in FIG. 1C. If the amplitude of the jitter exceeds 25 ns, it becomes impossible to distinguish between the intermediate bit transition and the mid-bit transition, so that the maximum allowable jitter is ± 25 ns (50 ns peak-to-peak).

The data in this embodiment is transmitted in the form of a message consisting of a 62 bit preamble, a 2 bit frame start flag signal, and a data field of 46 to 1500 data bytes in length. The 62-bit preamble is an alternating 1010 pattern in the Manchester code that does not include bit transitions.

FIGS. 3A and 3B show the Manchester decoder 30 forming part of the receiver 16 (FIG. 2). The decoder 30 includes a data / clock recovery unit 32 using a digital PLL (phase locked loop), a delay correction unit 34 for controlling the initial setting for the delay line, and the first 48 bits of the 62-bit preamble part of the received message. And a preamble timer unit 36 that clocks a training period corresponding to the preamble timer.

Decoder 30 receives the received data signal RD from line 40, the carrier sense signal CRS on line 42 that becomes active when energy is detected in transmission channel 14 at the start of message reception, and the locally generated 10 MHz clock signal on line 44. Receive.

The data / clock recovery unit 32 will be described first. 10MHz
The clock input line 44 is connected via a line 50 to a tapped delay line unit 52 capable of setting a delay up to 100 ns. The structure of the delay line unit 52 will be described with reference to FIG. The output of delay line unit 52 to output line 54 is a phase locked loop clock signal (PLL clock). PL is selected by selecting an appropriate tap of the delay line unit 52.
The phase of the L clock signal is 0 ° corresponding to a delay of 0 ns to 100 ns
Can be adjusted to ~ 360 °.

Line 54 is connected to delay line unit 58 by line 56, to the input of delay unit 62 by line 60, and to the input of delay device 66 by line 64. Delay line units 58 and 62 are 50ns and 25ns respectively
Includes tapped delay lines with up to a selectable delay, which are similar in structure to delay line unit 52. The output of the delay line unit 58 is connected to the clock output line 18 and the line 68 connected to the clock input of the FF 70. Delay line unit
The output of 62 is connected to line 72 which is connected to the clock input of FF74. The output of delay device 66 is connected via line 76 to the clock input of FF 78. The output signals of lines 68, 72 and 76 are respectively
CLK1, CLK2, REF clock, CLK3. The data inputs of the FFs 70, 74, 78 are all connected to the RD signal input 40 carrying the received Manchester encoded data, and the FFs 70, 74, 78 are triggered on the rising edges of the supplied clock signals CLK1, CLK2, CLK3 respectively. You. The output signals of the FFFs 70, 74, 78 on the output lines 80, 82, 84, respectively, are referred to as samples Q1, Q2, Q3. The output line 80 of the FF 70 is connected to the output data line 20.

Output lines 80, 82, 84 of FF70, 74, 78 are phase comparison logic circuits
Connected to 86, circuit 86 also receives as input a PLL clock signal which is also connected to line 54 via line 88.

The phase comparison logic circuit 86 controls the periodic fine up / down counter circuit 96 with control signals FINE INH and U
It has three output lines 90, 92 and 94 for supplying / D. Circuit 96 receives the PLL clock signal connected to line 88 via line 98 and the enable signal INTEGR on line 100, which is the output line of preamble timer section 36. The predetermined value of LENGTH is supplied to the counter circuit 96 via a line 101 which is an output of the data correction unit 34, and the carrier sense signal CRS is supplied to the counter circuit 96 via a line 102.

The 7-bit width output count signal of the counter circuit 96 is line 10
The signal is fed back to one input of the multiplexer 104 via 3 and its output is connected to the delay line circuit 52 via a 7-bit wide line 106. Multiplexer 104 further receives a second 7-bit wide input from delay corrector 34 via line 107 and has a select control input connected to line 42 having carrier sense signal CRS via line 110. Data / clock recovery 32 includes a digital phase locked loop.

10 MHz connected to line 44 via line 122
Includes a counter 120 for counting clock signals. The counter 120 is supplied from a register 124 or reset to a starting value S which is tied to the counter logic. The counter 120 is loaded with a starting value S under the control of a signal LOAD provided at the output of an OR gate 126 which receives as input the carrier sense signal CRS connected to line 42 via line 128;
A phase comparison output signal is received from phase comparator 130 via line 132.

Phase comparator 130 has a delay having the output signal of delay line circuit 52 via line 133, an input connected to line 44 via line 136, and an output connected to phase comparator 130 via line 138. A delayed 10 MHz clock signal is received via circuit 134.

The output of phase comparator 130 is connected to latch circuit 142 via line 140.
The latch circuit 142 latches the 7-bit width output count signal of the counter 120. The value latched by the latch circuit 142 is supplied to the delay correction unit 3 via a 7-bit width line 146.
4 is the value LENGTH provided as output.

The preamble timer section 36 includes a counter 150 having a count input connected to line 44 for receiving up to a 10 MHz clock signal via line 152, and a clear input for receiving the inverted carrier sense signal CRS via line 154. Counter 150
Has a 6-bit output connected to a 6-bit wide output line 156 connected to the decoder 158. The output of decoder 158 is connected via line 160 to the set input of flag circuit 162, the output of which provides signal INTEGR on line 100. Flag circuit 162 receives the clear signal via line 164 connected to receive inverted carrier signal CRS on line 44.

4 includes delay cells 172-1 and 172-2, respectively.
172-N, each of which includes a delay line 170 having a plurality (N) of delay cells 172, each of which has a decoder 30
As with an S integrated circuit chip, it has an equivalent structure as formed by buffer cells or AND gates. The 10 MHz clock signal on line 50 is applied to the first delay cell 172-1.
1 input. The output of delay cell 172 is an N-selector having an A-bit wide address provided on line 106.
N-bit wide line 174 connected to one input of switch 176
Connected to. The output of the selector switch 176 is connected to the output line 54 of the delay line circuit 52. One of the N input lines is connected to output line 54 according to the address provided on line 106.

The value of N of the 0 to 100 ns delay line 52 is 128, and A is 7. The 7-bit address selects one of the 182 delay line taps and
4 provides delayed output. A bit address value is X
In the case of, the output of the delay cell number X is a selector switch
Connected to 176 outputs.

The delay line circuits 58 and 62 are similar in structure to the circuit 52, and differ only in the values of the parameters N and A. Therefore, the value of N of the 0 to 50 ns delay line circuit 58 is 64 and A is 6. 0 to 25 ns delay line circuit 62
Are 32 and A is 5.

The periodic up / down counter circuit 96 of FIG. 5 receives control signals FINE, U / D and INTEGR on lines 90, 94 and 100, respectively, and an addition generator 180 which receives the value of signal LENGTH on a 7-bit wide line 101. including. The sum generator generates CAPPY IN (C
-IN) signal and a 10-bit wide STEP signal on the 10-bit wide output line 182. The lines 182 and 184 are connected to the adder circuit 186. Adder circuit 186 outputs signal CAPPY OUT on line 190,
A 10-bit wide output signal is provided on line 188. Lines 188 and 190 are 7
It is connected via a bit line 194 to an underflow / overflow detection circuit 192 for inputting a 7-bit value of LENGTH from the 7-bit line 101. Sensing circuit 192 provides a 10-bit wide output signal on line 198 to the data input of 10-bit FF block 200, which also receives the PLL clock signal on line 98 as a clock input and inhibits the INH signal on line 92 As signal, line 102
Received as a reset signal. The 10-bit wide output line 202 is connected to the feedback line 204 which is an input of the adder 186. The 7 high order bit line of the output line 202 is connected to the 7 bit wide line 103 and the signal PLL OUT fed back to the multiplexer 104 (FIG. 3A).
Is output. The periodic up / down counter circuit 96 is implemented in an adder 186 whose output is fed back to a set of its inputs. The adder 186 adds the output of the FF 200 to the 10-bit output value STEP of the addition generator 180. Therefore, STE is required every PLL clock cycle.
The value of P is added to or subtracted from the counter output. When the signal U / D on line 94 indicates down, STEP is subtracted from the counter output. The internal data width of the counter circuit 96 is 10
Bits, but the external interface uses only the seven most significant bits of those bits. One step increase in the external 7-bit external output on line 103 corresponds to one tap increase in delay line 52 (FIG. 3A).

The result of the addition / subtraction of the adder 186 is checked by the underflow / overflow detection circuit 192. If the values are all less than zero and U / D is down, an underallo occurs and the circuit 192 exchanges the value with the value of the value LENGTH on line 194. Also, if the value is greater than LENGTH, U / D
Is up, an overflow condition occurs and the detection circuit
192 exchanges the result with all zeros. In short, the counter circuit 96 cycles between 0 and LENGTH.

Line 96 is the INH input is the phase comparison logic circuit 86-FIG. 3B)
Is activated when a valid up or down decision cannot be made, such as when the transmission channel 14 is noisy. When the signal CRS is inactive, the counter circuit 96 is reset. Therefore, the PLL 108 is inactive when no data is received on the transmission channel 14.

The counter circuit 96 is determined by the size of the STEP 3
Can be counted at two different speeds. Two of them are the fast speed for PLL108 during the training period,
The other is the lowest possible speed when the PLL is locked after training. The value of STEP sets the size of the step and controls the speed of the counter circuit 96. The speed of the counter circuit 96 during the training mode is independent of the absolute value of the delay cell on the delay line 52. This is achieved during the training period by using the value of LENGTH in the occurrence of the STEP, as shown in Table 1, but is achieved by the addition occurrence 180. When PLL 108 is locked, counter circuit 96 counts at the lowest possible rate independent of the value of LENGTH.

The negative value of STEP (two's complement) inverts all 10 bits,
Obtained by activating signal CARRY IN (C-IN) on line 184. FIG. 6 shows the occurrence of C-IN and each bit of STEP. Symbol L0 indicates the least significant bit of LENGTH, and L6 indicates the most significant bit. The first two lines in FIG. 6 show the division of LENGTH by 16, and the next two lines show the division by 32. Therefore, the least significant bit L0 of LENGTH does not appear in FIG.

Next, the operation of the digital phase locked loop decoder 30 will be described. It consists of three phases. If no data is being received, the signal CRS is inactive and the delay modifier 34 is continuously active to compensate for the change in the actual delay of the delay lines 52, 58, 62 (FIG. 3A). The decoder 30 has an advantage that it operates when a large absolute delay change occurs (for example, due to a change in temperature or power supply or a variation between integrated circuit chips). When the reception of data is detected, the signal CRS becomes active and enters the training mode. The training period is continued at 48 bits determined by the preamble timer unit 36. During the training period, three received data samples per bit are used. These samples use three clock signals CLK1, CLK2, CLK3 having the same clock rate as the data rate (10 MHz). Each of the three clock signals is 90 ° out of phase with the previous phase. This 90 ° phase shift is applied to the calibrated delay lines 52,58
This is accomplished by delaying the sample clock by a fixed compensation delay 62. Three clock signals CLK1, C
LK2, CLK3 are sample signals Q1, Q supplied from FF70, 74, 78.
2, involved in generating a window corresponding to Q3.
During the training period of PLL108, not only the sample of the current window but also the sample of the previous window is used,
This assists in determining whether the phase of the PLL reference clock (PLL clock) is advanced or delayed compared to the phase of the received data signal RD. This has the advantage of minimizing errors that may be made in determining the amount of jitter in the received data as compared to using only the current window.

Therefore, the PLL decoder 30 adjusts the phase of the PLL clock signal for training until the phase of the inter-bit transition matches the reference clock (CLK2). PL when in phase
L108 is locked. The phase comparison logic 86 is based on the reference (RE
F) Determine whether the phase of the clock is advanced or delayed. If the phase of the REF clock is advanced, the counter circuit 96 counts
To go down. If the REF clock is delayed, the counter circuit 96 counts up. To determine the correct counting direction, phase comparison logic 86 uses three consecutive samples Q1, Q2, Q3 of signal RD. Sample 2 shows the value of RD at the rising edge of the REF clock. Sample 3 shows the value of the signal RD 25 ns before the rising edge of the REF clock, and sample 1 is equal to the value of the signal RD 25 ns after the rising edge of the REF clock. The phase comparison logic circuit 86 ignores the transition of the signal RD that does not occur in the windows Q1 to Q3. In some situations,
The counting direction is the current sample Q1, Q2, Q3 and the previous sample Q1.
Depends on 0, Q20, Q30.

During the third phase operation (after the training period), the counter circuit 96 operates at the lowest fixed rate according to the value of LENGTH.

The operation of the delay correction section 34 is shown in FIG. 3A, and can compensate for fluctuations in the delay line that occur as a result of power supply and temperature changes and as a result of changes between devices such as integrated circuits. As described above, the delay correction unit 34 operates when the signal CRS is inactive. The delay correcting unit 34 is used for correcting the delay of the 0 to 100 ns delay line circuit 52 provided in the data / clock recovery unit 32. This has the advantage that if separate delay lines are used for the delay correction unit 34 and the data / clock recovery unit 32, errors that may result from small delays between the corresponding cells of the two delay lines are prevented. Having. Delay circuit
134 compensates for the inherent delay of the delay line circuit 52. Therefore, the delay circuit 134 is connected to the selector switch 176 (the fourth
It has a delay equal to the intrinsic delay of FIG.

Multi-tap delay line 170 included in circuit 52 from line 44
(FIG. 4) is supplied with a 10 MHz clock signal. The output tap selected by the switch 176 supplies a signal to the output line 54 and further to the phase comparison circuit 130 via the line 133,
Another input 138 of circuit 130 receives the 10 MHz clock signal delayed by compensation delay circuit 134. The 10 MHz clock signal is also provided to counter 120 via line 122. counter
The count output of 120 is now line 108, multiplexer 104
And one of the taps of the delay line 170 for connection to the address input of the switch 176 via line 106 and to the phase comparator 130 via lines 54 and 133. As long as the phases do not match, the counter 120 increments and a further phase comparison is performed. When the phase comparison circuit 130 detects a phase match, the value LENGTH of the counter 120 is latched by the latch circuit 142, and the counter 120 is reset to a starting value S that is loaded in response to a signal provided through the OR gate 126. You. Therefore,
Latch circuit 142 is always 100n corresponding to 360 ° phase shift
Store the value LENGTH, which represents the number of delay cells 172 giving a delay equal to s clock periods. When the CRS signal becomes active, the current value of LENGTH stored in the latch circuit 142 is used for the operation of the data / clock recovery unit 32.

Thus, during the next phase operation (training period), counter circuit 96 will respond to a 360 ° PLL clock phase shift.
Period between the 0 and 7 bit values of LENGTH.

As mentioned above, data / clock recovery circuit 32 is capable of three phase adjustment speeds. The adjustment speed depends on the magnitude of the difference between the RD (received data) signal and the REF clock signal. If there is a large phase difference, a large adjustment speed is used. When PLL 108 is locked and the phase of the REF clock and the transition between RD bits match, the center of the window defined by samples Q1-Q3 is centered on the transition between bits. The window should capture all inter-bit transitions and prevent the PLL from locking inter-bit transitions that may occur during data reception. The width of the window is determined for both these purposes. The window should be as narrow as possible to prevent mid-bit transitions from entering the window. Conversely, to capture all inter-bit transitions, the window should be wider than the expected maximum jitter of inter-bit transitions. The best width according to this embodiment is 50
ns. This width is used for both mid-bit and inter-bit transitions.
Allows for a jitter amplitude of up to 25 ns and achieves its purpose. After the first 48 preamble bits counted by the preamble timer 36, the preamble timer 36 ends the training period, the PLL 108 is locked, and the phase adjustment is performed at the minimum speed.

Windows are 50 ns and 25 n using delay line circuits 58 and 62
The clock signal on line 54 is made by delaying the PLL clock by s. The delay values of the delay lines 58 and 62 are supplied irrespective of the absolute value of the delay of the delay cells constituting the delay lines. The value of LENGTH stored in latch circuit 142 corresponds to a 360 ° phase shift or a 100 ns delay. Thus the value LENGTH / 2 is 5
Corresponding to a 0 ns delay, this value is provided as a 6-bit input signal to delay line 58 via 6-bit wide line 210. Value LENGTH
/ 4 corresponds to 25 ns, which value is provided via line 212 to delay line 62 as a 5-bit input signal. Delay circuit 66 compensates for the inherent delay of delay line circuits 58,62. That is, the inherent delay of the switch is equal to the switch 1 supplied to the delay line circuits 58 and 62.
This corresponds to 76 (FIG. 4). Accordingly, the PLL clock on line 54 is delayed by this
Supply CLK3. When the PLL decoder adjusts the phase of the PLL clock so that the phase of the bit transition of the REF clock matches the phase of the bit transition of the RD signal, the inherent switch delay is compensated as described above.

FIG. 7 is a block diagram of the phase comparison logic circuit 86, which has a 3-bit wide output line 222 connected to a logic circuit 224 that can be implemented in this machine, and lines 80,8.
Signals Q1, Q2, Q3 representing the current window sample from 2,84
And a clocked storage element 220 that receives Memory element 220
Supplies the previous window samples Q10, Q20, Q30 to the logic circuit 224 via the 3-bit wide line 222.

FIG. 8 shows the interpretation of the window information. The two transitions of the window (corresponding to samples 010 and 101) only occur if they cause noise or spurious pseudo-level shifts.

The data / clock recovery unit 32 has four operation stages as follows.

A. PL until the transition between bits is captured by the window
Adjust L108.

STEP = Use LENGTH / 16 B. Adjust PLL 108 until the inter-bit transition is captured by two consecutive windows.

STEP = Use LENGTH / 16 C. PLL108 until the average jitter value is in the center of the window
Adjust

STEP = Use LENGTH / 32 D. PLL108 only to compensate for frequency fluctuation of received data
Adjust This stage is entered after the 48-bit preamble timer unit 36 times out.

STEP value = 1/8 During the first 48 preamble bits, if PLL 108 is not yet locked, no window has captured a transition. Therefore, the previous window information Q10, Q20, Q30 generated from the storage element 220 (FIG. 7) is used. By using both the current and previous windows,
The reliability of determining whether there is jitter in the transition of the RD signal is considerably improved. During the first 48 preamble bits corresponding to stages A, B, C, logic circuit 224 uses Table 2. Thus, “X” represents “irrelevant”.

Opposite stability level of current window and previous window (000
111 or 111 000) does not produce up / down information. Therefore, the PLL 108 is adjusted in the fixed direction (up). Normally these codes only occur at the beginning of a message when the PLL is completely off (stage A). However, during subsequent stages of operation (eg, when the PLL is down-adjusting), accidental 00011 or 111000 can occur due to jitter peaks. In this case, it is not desired to adjust in the up direction. PLL should not be adjusted. An explanation machine described later with reference to FIG. 9 determines whether or not 000 111 or 111 000 is accidental.
If it is a coincidence, the inhibit count becomes active (INH = 1). If the transitions detected in the previous and current windows are opposite, only the current window is used. In that case, the current window is decoded in Table 3.

If one window detects the transition and the other does not, the information in both windows is used. There are 16 possibilities of one transition occurring in two consecutive windows, and the counting direction (U or D) is determined by first considering the jitter-free signal, adding 20 ns to the transition, and adding 6 ns to one transition in two windows. Isting all the possibilities of bit code,
A 6-bit code and a signal containing jitter are used to determine the range of possible windows. The position of the possible range for the transition of the jitter-free signal determines the required counting direction. Table 4 is a list of all valid codes, and the resulting count directions to decode in stages A, B, and C.

In FIG. 4, if there are two transitions in a single window,
Since it is illegal code, it is not shown in the figure.
Decoded to U / D = X, INH = 1.

Also, the code 000 11 in Table 4 where U / D = U, INH = 0
The decoding of 1 and 111 000 is performed by the explanation machine having the explanation of FIG. The explanation machine is the phase comparison logic circuit 86 (3A
FIG. 7) is a part of the logic circuit 224 (FIG. 7) included in FIG. The output of the interpreter of signal FLAG indicates whether the code is accidental. If the signal FLAG = 1, the code is accidental. The explanation device is controlled by Q1, Q2, and Q3 in FIG. Signal FLAG
Is set by the uninhibited signal DOWN (U / D = D and INH = 0). It is reset by three consecutive signals DOWN or INH signal. DO in the explanatory diagram of FIG. 9 is U / D = DB
And INH = 0. The interpreter steps through the entire PLL clock signal. If the code 000 111 or 111000 is accidental (FLAG = 1), INH becomes active. Otherwise,
The signal INH passes.

After the first 48 preamble bits, the preamble timer section 36 outputs the active signal INTEGR and enters the D stage of the decoding operation. During stage D, decoding is performed by table 5.

The signal fine on line 90 (FIGS. 3B, 5) controls the magnitude of the addition or subtraction step of counter circuit 96. The signal fine is generated by an interpreter included in logic circuit 224 (FIG. 7). FIG. 10 is an explanatory view of an explanation machine.
If both the current and previous windows contain a valid transition, the signal fine is set. If the signal fine CRS is inactive (CRS = 0), it is reset between messages.

The reception of data will be described with reference to FIG. This is PLL1
This happens when 08 is locked. As described above, the value of a data bit in a Manchester code is indicated by the polarity of the plurality of inter-bit transitions. The rising edge of the intermediate bit transition indicates “1”, and the falling edge indicates “0”. Therefore,
The second half of the bit cell is the Manchester encoded data
It has the same value as the bit. Data recovery occurs by latching the second half of the Manchester bit cell. The best latch point is determined by the highest jitter of the inter-bit transition followed by the intra-bit transition. at the worst case,
The transition between bits has a theoretical maximum jitter of +25 ns, and-
A mid-bit transition with 25 ns jitter follows. Both transitions occur simultaneously. Jitter smaller than +/- 25 ns should be allowed (e.g. +/- 24 ns), and the data is valid for 2 ns. The best data latch period (middle of this 2 ns) is the bit-to-bit transition (3 /
4) 25 ns after the occurrence of (Fig. 11). Delay line circuit 58 (third
The output CLK1 in FIG. A) samples the RD (received data) signal 25 ns after the occurrence of the inter-bit transition, so Q1 is equal to the recovered data.

Thus, there has been described a digital locked loop decoder for decoding Manchester encoded data which has the advantage of using a clock signal having a frequency equal to the data rate. Thus, this has the advantage that no high frequency sampling clock signal is required.
This again has the advantage that the decoder can be implemented in a low power, low cost reliable device such as CMOS.

[Brief description of the drawings]

FIG. 1 is a waveform diagram of Manchester encoded data, FIG. 2 is a block diagram of a data transmission system, and FIGS. 3A and 3B are digital phase locked clocks for decoding Manchester encoded data according to the present invention. FIG. 3 is a block diagram of a loop decoder. FIG. 4 is a block diagram of a delay line circuit used in the decoder of FIGS. 3A and 3B, and FIG. 5 is a block diagram of a periodic up / down counter used in the circuit of FIGS. 3A and 3B. FIG. 6 is a table diagram useful for understanding the operation of the periodic up / down counter, FIG. 7 is a block diagram of the phase comparison logic circuit of FIG. 3B, and FIG. FIG. 9 is an explanatory diagram for a flag signal, FIG. 10 is an explanatory diagram for a fine signal, and FIG. 11 is a waveform diagram showing a data recovery operation. In the figure, 12 ... transmitter, 16 ... receiver, 14 ... transmission channel, 30 ... decoder, 32 ... data / block recovery unit, 34
…… Delay correction section, 36 …… Preamble timer section, 52, 58,
62 ... Delay line unit, 66 ... Delay device, 70,74,78 ... F
F, 86 ... Phase comparison logic circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Richard Krysov 2253 S.J.V. Skotan Paganini Drift, Netherlands 60 (56) References JP-A-60-227541 (JP, A) JP-A-63-191433 (JP, A) JP-A-64-91530 (JP, A) JP-A-1-170118 (JP, A) JP-A-64-13820 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 5/12

Claims (1)

(57) [Claims] 1. A digital phase locked loop decoder for decoding an input data signal (RD) generated at a predetermined nominal rate, said clock signal providing a first clock signal at said predetermined nominal rate. Supplying means (44) for delaying the clock signal by a controllable delay time,
A first delay line means (52) for generating a second clock signal (PLL clock); and a plurality of delay clock signals (CLK) having the respective phase delay times for receiving the second clock signal.
1, CLK2, CLK3) (58, 62, 6)
6) and sampling means (70) for supplying a plurality of signal samples (Q1, Q2, Q3) of the input data signal in response to the delayed clock signals (CLK1, CLK2, CLK3) and the input data signal (RD). , 74, 78), and a counter control signal (fine, fine) for controlling the operation of the counter means (96) in response to the second clock signal (PLL clock) and the plurality of signal samples (Q1, Q2, Q3). I
Phase comparison logic means (86) for supplying NH, U / D), the counter means (96), and the first delay line means (52)
Feedback means (103, 104) connected between the control means and the controllable delay time; and a decode output data signal connected to the sampling means (70, 74, 78) and corresponding to the input data signal (RD). And a second clock signal (PLL clock) corresponding to a selected one (CLK2) phase of the plurality of delayed clock signals (CLK1, CLK2, CLK3). A) a digital phase locked loop decoder for controlling the phase.