JP2002290385A - Automatic phase detection system in main signal phase adjustment circuit in atm - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a main signal phase adjustment circuit in the ATM that is downsized with enhanced operability. SOLUTION: The main signal phase adjustment circuit in the embodiment shown in Figure 1 comprises a main signal processing section 1 in an LSI 20 in a pre-stage PKG, a periodic cell insertion section 2 that delays a main signal, a frame phase adjustment section 3 that transfers the main signal delayed by the periodic cell insertion section 2 to a phase of a frame receptible by a bit buffer section 5 in an LSI 30 in a post-stage PKG, and a phase setting value generating section 4 that decides an optimum output frame phase of the frame phase adjustment section 3 on the basis of a fixed pattern detection result notice signal S8 on a period cell informed from a period cell detection section 6 in the LSI 30 of the post-stage PGK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main signal phase adjustment circuit used in an ATM digital transmission apparatus, and more particularly to a main signal phase adjustment circuit capable of automatically detecting a frame phase to be output.

[0002]

2. Description of the Related Art Conventionally, a main signal phase adjusting circuit used in an ATM digital transmission apparatus outputs an output phase of an LSI.
Is provided in binary form from the external terminal of.

[0003]

In the conventional main signal phase adjusting circuit described above, the phase to be transmitted is given in binary by the external terminal of the LSI, so that the number of external terminals of the LSI increases.
There is a problem that a phase value to be set must be calculated in advance and set to an external terminal.

[0004] The present invention has been made in view of the above problems, and an object of the present invention is to provide a main signal phase adjustment circuit in which the number of external terminals of an LSI is reduced.

It is another object of the present invention to provide a main signal phase adjusting circuit which does not need to calculate and set a phase to be transmitted in advance.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a main signal phase adjusting circuit for adjusting a frame phase of an ATM main signal to a frame phase receivable by a receiving buffer provided in an LSI of a next stage package. A main cell phase adjusting circuit for transmitting a periodic cell detection result notification signal indicating whether or not the frame phase of the ATM main signal received by the reception buffer is within the receivable frame range of the reception buffer. It is characterized by having a phase setting value generating means for determining the output frame phase of the received ATM main signal.

Further, the phase setting value generating means of the present invention comprises: count timing generating means for dividing the frame phase signal in the package and outputting a divided frame phase signal; and counter means for counting the divided frame phase signal. A phase determination unit for calculating an optimum frame phase from an output signal of the counter unit within a receivable frame phase range indicated by the periodic cell detection result notification signal.

Further, the phase determining means of the present invention outputs the output signal of the counter at a timing when the periodic cell detection result notification signal changes from a state outside the receivable frame phase range to a state indicating the receivable frame phase range. First latch means for latching, and a second latch means for latching the output signal of the counter at a timing at which the periodic cell detection result notification signal changes from a state indicating within the receivable frame phase range to a state indicating outside the receivable frame phase range. A second latch means, a subtractor for subtracting the output signal of the counter means latched by the first latch means from the output signal of the counter means latched by the second latch means, A first adder for adding the signal obtained by shifting the output signal right by one bit and the LSB of the output signal of the subtractor; A second adder for adding the output signal of the circuit and the output signal of the first adder; and selecting and outputting one of the output signal of the second adder and the output signal of the counter. And a selection switching means.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the main signal phase adjustment circuit of the present embodiment. As shown in FIG. 1, the main signal phase adjustment circuit according to the present embodiment includes a main signal processing unit 1 in an LSI 20 on a preceding stage PKG, a periodic cell insertion unit 2 for delaying a main signal, and a periodic cell insertion unit 2. The cycle notified from the frame phase adjuster 3 that replaces the delayed main signal with the frame phase that can be received by the bit buffer unit 5 in the LSI 30 of the subsequent PKG, and the cycle cell detector 6 in the LSI 30 of the subsequent PKG. A phase setting value generator 4 that determines the optimum output frame phase of the frame phase adjuster 3 based on the detection result notification signal S8 of the fixed pattern on the cell.

FIG. 2 is a block diagram showing the internal configuration of the phase set value generator 4. As shown in FIG. 2, the phase setting value generation unit 4 uses a count timing generation unit 7 that generates a count-up timing from the frame phase signal S14 in its own PKG, and a timing generated by the count timing generation unit 7. Counter unit 8 that counts
And a phase determination unit 9 that determines the optimum output frame phase of the frame phase adjustment unit 3 based on the detection result notification signal S8 output from the periodic cell detection unit 6 of the LSI 30 of the subsequent PKG.

Next, the operation of the present embodiment will be described in detail with reference to the drawings. FIG. 3 is an explanatory diagram illustrating a relationship between an output phase signal output from the phase setting value generation unit 4 and an output frame phase of the frame phase adjustment unit 3.

The frame phase adjuster 3 controls the phase signal S7 output from the phase set value generator 4 to convert the main signal delayed by the periodic cell inserter 2 into the LSI 3 of the subsequent PKG.
The bit buffer unit 5 within 0 shifts to a receivable frame phase. At this time, the phase setting value generation unit 4
The optimal phase setting value is generated based on the periodic cell detection determination in the periodic cell detector 6.
It takes several frames to determine the periodic cell detection.

In order to achieve the matching, the count timing generator 7 divides the frame phase signal S14 in the PKG by n to generate a divided frame phase signal S15 and outputs it to the counter unit 8. The counter unit 8 counts using the frequency-divided frame phase signal S15 as a clock, and outputs a counter output signal 16 to the phase determination unit 9. The phase judging unit 9 outputs the counter output signal S1 input from the counter unit 8.
6 is output to the frame phase adjuster 3 as the phase signal S7.

When the counter output signal S16 is input as the phase signal S7, the frame phase adjuster 3 decodes the counter output signal S16 and outputs the input frame phase signal S16.
6 is output frame phase signal S delayed by 1 clock
10 is output.

Next, the phase determining section 9 of the phase set value generating section 4
FIG. 4 illustrates the operation of the phase setting value generation unit 4.
FIG. 4 is a time chart illustrating the operation of the phase determination unit 9 of FIG.
Note that the read phase of the bit buffer unit 5 of the LSI 30 is based on the input frame phase signal S6 of the frame phase adjustment unit 3.
In the following description, it is assumed that the bit buffer unit 5 is at a position delayed by 17 clocks and the capacity of the bit buffer unit 5 is 6 bits.

As described above, when the output frame phase signal S10 of the frame phase adjustment section 3 is sequentially delayed by one clock with respect to the input frame phase signal S6, as shown in FIG. This is within the capacity range of the bit buffer unit 5. At this time, the cycle cell detector 6 detects the cycle cell at the head of the frame phase.

Then, within the capacity range of the bit buffer section 5, the detection of the periodic cell is correctly performed, and otherwise, the periodic cell is not detected. Therefore, the periodic cell detector 6
It outputs a detection result notification signal S8 as shown in FIG.

In the phase determination section 9, the detection result notification signal S8
Latches the counter output signal S16 when the signal changes from NG to OK (Lo to Hi) and the counter output signal S16 when the signal changes from OK to NG (Hi to Lo). Is calculated by calculating the output frame phase signal S10 of the frame phase adjustment unit 3, which is intermediate between the two.

FIG. 5 is a block diagram showing the internal configuration of the phase determination unit 9. Here, the calculation operation of the phase determination unit 9 will be described in detail with reference to FIG. When the detection result notification signal S8 changes from NG to OK, the latch 11 holds the counter output signal S16 of the counter unit 8 at the latch timing output from the latch / switching timing generation unit 10.

The latch 12 outputs the detection result notification signal S8
When the value changes from K to NG, the counter output signal S16 of the counter unit 8 at that time is held at the latch timing output from the latch / switching timing generation unit 10. The subtracter 13 obtains the capacity of the bit buffer unit 5 by subtracting the value of the latch 11 from the value of the latch 12.
In this example, it is "6". The adder 14 adds the lower one bit of the output of the subtractor 13 and the remaining bits, thereby obtaining an intermediate position of the bit buffer capacity.

Here, an operation example of the adder 14 will be described with reference to FIG. The output “0110” of the subtractor 13 is LSB
Shifts one bit to the right side to obtain “011”, which is a half value of the bit buffer capacity, and “0” of the LSB bit.
Is added to “011” to round up when a fraction below the decimal point occurs.

Returning to FIG. 5, the adder 15
The value at the intermediate position of the capacity of the bit buffer unit 5 obtained by the above operation is added to the minimum value (the value of the latch 11) of the output phase of the frame phase adjustment unit 3 that can be received by
In step 30, the optimum value of the output phase of the receivable frame phase adjuster 3 is determined.

In this embodiment, as shown in FIG.
The delay 14 of the output frame phase signal S10 of the frame phase adjuster 3 has an optimum value. The 2: 1 SEL 16 converts the phase signal S7 output from the phase determination unit 9 according to the SEL switching signal from the latch / switch timing generation unit 10 into:
The output of the counter 8 is switched to the output of the adder 15.

As described above, in the present embodiment, the position of the output phase of the frame phase adjustment unit 3 is
Since it becomes the middle point of the capacity of the bit buffer unit 5 at 0, the LSI 30 can perform stable reception without error.

[0025]

According to the present invention, the main signal phase adjusting circuit is an LSI.
The external terminals can be reduced, and the external shape of the LSI can be reduced in size. The reason is that the phase setting value conventionally provided from the external terminal can be automatically determined and set in the LSI.

Further, the main signal phase adjusting circuit of the present invention does not need to determine and set the transmission phase in advance, and has an effect that operability can be improved. The reason is that the phase setting value conventionally given from the external terminal is
This is because it can be automatically determined and set internally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an internal configuration of a phase setting value generation unit.

FIG. 3 is a term chart illustrating a relationship between a phase signal output from a phase setting value generation unit and an output phase of a phase adjustment unit.

FIG. 4 is a time chart illustrating an operation of a phase determination unit.

FIG. 5 is a block diagram illustrating an internal configuration of a phase determination unit.

FIG. 6 is an explanatory diagram showing an operation process of an adder 14;

[Explanation of symbols]

 Reference Signs List 1 Main signal processing unit 2 Periodic cell insertion unit 3 Frame phase adjustment unit 4 Phase setting value generation unit 5 Bit buffer unit 6 Periodic cell detection unit 7 Count timing generation unit 8 Counter unit 9 Phase determination unit 10 Latch, switching timing generation unit 11 , 12 Latch unit 13 Subtractor 14, 15 Adder 16 2: 1 SEL 20, 30 LSI S1 Main signal processing unit input main signal S2 Main signal processing unit input frame phase signal S3 Periodic cell insertion unit input main signal S4 Periodic cell insertion unit Frame phase signal S5 Frame phase adjuster input main signal S6 Frame phase adjuster input frame phase signal S7 Phase signal S8 Detection result notification signal S9 Frame phase adjuster output main signal S10 Frame phase adjuster output output frame phase signal S11 Periodic cell detection Input main signal S12 Periodic cell detector input frame Phase signal S13 bit buffer reading frame phase S14 frame phase signal S15 divided frame phase signal S16 counter output signal

Claims (3)

[Claims] 1. A main signal phase adjustment circuit for adjusting a frame phase of an ATM main signal to a frame phase receivable by a reception buffer provided in an LSI of a next package and transmitting the received signal. A phase setting value for receiving a periodic cell detection result notification signal indicating whether or not the frame phase of the ATM main signal is within the receivable frame range of the reception buffer from the reception buffer and determining an output frame phase of the ATM main signal. A main signal phase adjustment circuit comprising a generation unit. 2. The phase setting value generating means includes: a count timing generating means for dividing a frame phase signal in a package and outputting a divided frame phase signal; a counter means for counting the divided frame phase signal; 2. The main signal phase adjustment according to claim 1, further comprising: a phase determination unit that calculates an optimum frame phase from an output signal of the counter unit within a receivable frame phase range indicated by the periodic cell detection result notification signal. circuit. 3. The phase determination means latches the output signal of the counter at a timing when the periodic cell detection result notification signal changes from a state indicating outside the receivable frame phase range to a state indicating the receivable frame phase range. First
And second latching means for latching the output signal of the counter at a timing when the periodic cell detection result notification signal changes from a state indicating within the receivable frame phase range to a state indicating out of the receivable frame phase range. A subtractor for subtracting the output signal of the counter means latched by the first latch means from the output signal of the counter means latched by the second latch means; A first adder that adds the bit-shifted signal and the LSB of the output signal of the subtractor, and a second adder that adds the output signal of the first latch circuit and the output signal of the first adder. 3. The adder according to claim 2, further comprising: a selection switch that selects and outputs one of the output signal of the second adder and the output signal of the counter. Signal phase adjustment circuit.