JP4699811B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor light emitting device Download PDF

Info

Publication number
JP4699811B2
JP4699811B2 JP2005167319A JP2005167319A JP4699811B2 JP 4699811 B2 JP4699811 B2 JP 4699811B2 JP 2005167319 A JP2005167319 A JP 2005167319A JP 2005167319 A JP2005167319 A JP 2005167319A JP 4699811 B2 JP4699811 B2 JP 4699811B2
Authority
JP
Japan
Prior art keywords
layer
emitting device
semiconductor light
manufacturing
eutectic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005167319A
Other languages
Japanese (ja)
Other versions
JP2006344682A (en
Inventor
巌 東海林
Original Assignee
スタンレー電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by スタンレー電気株式会社 filed Critical スタンレー電気株式会社
Priority to JP2005167319A priority Critical patent/JP4699811B2/en
Publication of JP2006344682A publication Critical patent/JP2006344682A/en
Application granted granted Critical
Publication of JP4699811B2 publication Critical patent/JP4699811B2/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly to a method for manufacturing a semiconductor light emitting device in which an LED chip is mounted on a submount substrate.

  A semiconductor light emitting device having a structure in which a light emitting diode (LED) chip is mounted on a submount substrate has been proposed. For example, a reflective metal layer is formed on a Si substrate, and a semiconductor light emitting device is bonded thereon. Al, Ag, etc. are known as metals having high reflectivity for visible light and near ultraviolet light. In particular, the reflectance of Ag is high. If a reflective metal layer of Ag, Al or the like is formed on the submount substrate and an LED chip is bonded thereon, light emitted from the LED chip and incident on the reflective metal layer can be efficiently reflected.

  Japanese Patent Laid-Open No. 2001-44491 proposes that a group III-V compound LED formed on a GaAs substrate is bonded to a conductive substrate having a reflective layer, and the GaAs substrate is peeled off to improve the luminance of the LED.

  Japanese Patent Laid-Open No. 2001-189490 proposes a manufacturing method in which an LED is grown on a temporary substrate of GaAs or InP, adhered to a permanent substrate having a metal adhesive layer that also serves as a reflective layer, and the temporary substrate is removed.

  Blue light emitting semiconductor light emitting devices using III-V compound (nitride) semiconductors containing N as a V group element such as GaN, GaAlN, InGaN, InAlGaN, etc. are widely known. The group III element of the nitride semiconductor is Ga, Al, In, or a combination thereof. When a light emitting diode (LED) emitting blue light is covered with a wavelength conversion layer containing a fluorescent material, white light can be emitted. White light can also be used for applications such as lighting.

  The nitride semiconductor layer is generally grown on a substrate made of a different material such as sapphire or SiC. The sapphire substrate is insulative, but the SiC substrate can be conductive and electrodes can be formed thereon.

 In recent years, as the output of light-emitting diodes has increased, the market has expanded from the display field used in the past to lighting fields such as special lighting, general lighting, and automobile lighting. At the same time, the LED die size has been increasing from about □ 300 μm to □ 1 mm and □ 2 mm. However, with the increase in die size, problems such as uneven light emission, current supply failure, and element heat generation have become apparent. The configuration in which the LED chip is placed on the submount substrate is also suitable for high output.

  When the LED chip is mounted on a package, the heat resistant temperature may be equal to or lower than the eutectic temperature. There are cases where the joint surface of the package is so rough that it is inappropriate to mount it directly. Even in such a case, the problem can be avoided by temporarily bonding the LED chip onto the submount substrate and mounting the submount substrate on the package with Ag paste or epoxy resin.

  Au—Sn eutectic bonding is used for bonding the LED chip and the submount substrate. Au—Sn eutectic bonding requires heating and melting the eutectic material layer to a eutectic temperature of 280 ° C. or higher. In order not to adversely affect the LED element, it is desired to complete the eutectic bonding in a short time. Therefore, eutectic bonding is performed by applying a peak temperature higher than the eutectic temperature, for example, 300 ° C. or higher, typically 305 ° C. or higher. During eutectic bonding, the reflective properties of the reflective metal layer may be degraded, and eutectic material ball-up may occur. Ball-up refers to a phenomenon in which Au-Sn once liquefied above the eutectic temperature partially rises due to segregation when it solidifies due to cooling.

  Japanese Patent Laid-Open No. 2002-270905 proposes that a plurality of light emitting elements are formed on a sapphire substrate, and the light emitting elements are mounted on one submount element formed of a silicon substrate via bumps. By integrating a plurality of light emitting elements, a large amount of emitted light can be obtained, and a silicon substrate with better heat dissipation than a sapphire substrate promotes heat dissipation, improves the decrease in light emission efficiency due to heat generation, and improves light emission efficiency. An excellent illumination light source can be obtained.

  Japanese Patent Application Laid-Open No. 2004-296846 proposes to provide a ball-up preventing metal laminate including a Ti layer and a Ni layer on a submount substrate. Furthermore, it is proposed to provide a barrier layer between the eutectic material layer and the electrode layer of the LED chip.

JP 2001-44491 A JP 2001-189490 A JP 2002-270905 A JP 2004-296846 A

  An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device, in which an LED chip is mounted on a submount substrate, and a high light output can be efficiently provided.

  Another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device capable of eutectic bonding an LED chip on a submount substrate and ensuring the flatness of a reflective metal layer.

According to one aspect of the present invention, a step of preparing an LED chip having a eutectic electrode layer, a step of preparing a submount substrate on which a multilayer electrode layer including a reflective metal layer mainly composed of Ag is formed, A thermal history is applied to a submount substrate having a laminated electrode layer, which is a combination of constant temperature constant temperature preheating and peaked peak preheating, and the peak temperature of the peaked preheating is 150 ° C. or higher and 300 ° C. or lower. a step of, on the sub-mount substrate of applying the thermal history, placing the LED chip having the eutectic electrode layer, a method of manufacturing a semiconductor light-emitting device having a step of performing eutectic bonding, there is provided .

  It has been found that the flatness of the reflective metal layer can be ensured by applying a thermal history to the reflective metal layer before eutectic bonding.

  1A, 1B, and 1C are a configuration example of a light-emitting diode (LED) chip 1, a configuration example of a submount substrate 2, and a configuration example of a submount LED in which the LED chip 1 is eutectic bonded on the submount substrate 2. Show.

  As shown in FIG. 1A, the LED chip 1 is an indium gallium nitride (InGaN) light emitting diode with the trade name XTin, available from, for example, Cree, North Carolina, USA. On an n-type silicon carbide SiC single crystal substrate 11 doped with nitrogen (N), an n-type nitride semiconductor (InGaN) layer 12a, a nitride semiconductor (InGaN) multiple quantum well (MQW) active layer 12b, a p-type nitride A nitride semiconductor (InGaN) layer 12 is formed by epitaxially growing a physical semiconductor (InGaN) layer 12c. The SiC substrate has a tapered side surface, the upper surface is about 300 μm × 300 μm, and the bottom surface is about 200 μm × 200 μm. On the p-type nitride semiconductor layer 12c, an anode electrode 13 of Au—Sn eutectic material, which is a non-translucent material, is formed by sputtering, and an Au cathode electrode having a diameter of 105 μm is formed on the back surface of the n-type SiC single crystal substrate 11. 14 is formed. The total thickness is about 115 μm. The composition of the Au—Sn eutectic material is Au: Sn = about 80 wt%: about 20 wt%. Light is extracted from the SiC substrate 11 side.

  As shown in FIG. 1B, the submount substrate 2 includes a Ti layer 23 having a thickness of 0.2 μm, a Si layer 21 having a silicon oxide film 22 having a thickness of 0.1 μm formed by, for example, thermal oxidation, A Cu layer 24 having a thickness of 0.2 μm is formed by sputtering, and a Ni layer 25 having a thickness of 2 μm and an Ag layer 26 having a thickness of 2 μm are formed thereon by plating. The Ag layer has a function of a reflective electrode.

  The Ti layer 23 functions as an adhesion layer that improves adhesion to the silicon oxide layer 22. The Cu layer 24 constitutes an underlayer for plating. The Ti layer 23 and the Ni layer 25 have a function of preventing ball-up during eutectic bonding described later. The Ag layer 26 is a reflective metal layer.

  As shown in FIG. 1C, the Au-Sn anode electrode 13 is placed on the Ag layer 26 of the submount substrate 2 and the LED chip 1 is attached to the submount substrate 2 by applying pressure and heat. Either thermocompression bonding or eutectic bonding using flux. In any case, the eutectic bonding in which the Au—Sn anode electrode 13 reaches the eutectic temperature and melts to become a eutectic is performed. From the viewpoint of mass productivity, it is advantageous to perform eutectic bonding using a flux. In the experiment described below, flux was used. If the LED chip is heated too much, damage such as increased crystal defects, re-diffusion of impurities, diffusion of electrode material into the crystal, and alloying may occur. In order to reduce the damage, it is desired to raise the temperature in a short time, shorten the peak temperature holding time, and reduce the heat accumulation time. The peak temperature needs to be higher than the eutectic temperature. In the case of Au—Sn junction, the peak temperature is preferably about 305 ° C. or higher.

  If the Ti layer 23 and the Ni layer 25 are not formed, so-called ball-up occurs in which the Au—Sn eutectic locally rises when the temperature drops. The Ti layer 23 and the Ni layer 25 have a function as a ball-up preventing layer that prevents ball-up when the Ag layer 26 and the Au—Sn anode electrode 13 are eutectic bonded.

  The inventor formed the LED chip 1 and the submount substrate 2 shown in FIGS. 1A and 1B, and performed eutectic bonding using a flux as shown in FIG. 1C. As shown in FIG. 3A, the temperature profile of eutectic bonding was set at a temperature rising rate of 112 ° C./min, a peak temperature of 305 ° C., a peak temperature duration of about 5 seconds, and a temperature decreasing rate of 93.3 ° C./min. The initial value of the surface roughness of the plated Ag layer 26 in FIG. 1B was arithmetic average roughness Ra = 0.075 μm, 10-point average roughness Rz = 0.46 μm according to the Lm JIS standard (JIS B0601-1982). .

  The surface roughness of the Ag layer 26 on the surface of the submount substrate outside the LED chip bonded portion after eutectic bonding was Ra = about 0.1 μm and Rz> 2 μm. It can be seen that the surface roughness of the Ag layer 26 is considerably increased.

  If the surface roughness of the Ag layer 26 that functions as a reflective electrode increases due to eutectic bonding, the reflectance of the Ag layer 26 decreases, and the external extraction efficiency of light emitted from the LED is likely to decrease. It is desired to suppress a decrease in the reflectance of the Ag layer 26. The cause of the increase in the surface roughness of the Ag layer outside the eutectic joint is considered to be the effect of the heat treatment of the eutectic joint. Even if a strong stimulus is given at once, there is a great influence. If a weak stimulus is given in advance, tolerance to a stronger stimulus may be increased.

  The present inventor examined the effect of preheating the Ag layer 26 before eutectic bonding. As shown in FIG. 1C, with the LED chip 1 overlaid on the submount substrate 2, immediately before eutectic bonding, as shown in FIG. Then, eutectic bonding was tried. The surface roughness of the Ag layer 26 after eutectic bonding was Ra = 0.076 μm. Compared with the surface roughness Ra = 0.1 μm of the Ag layer 26 without preheating, the surface roughness after eutectic bonding is equivalent to the surface roughness before eutectic bonding (about 1). %, The difference is less than 2% is equivalent). Therefore, I changed the preheating conditions. By providing a preheating with a peak shape overlaid with a preheating at a constant temperature, the degree of freedom in setting conditions will increase. The constant temperature preheat was fixed at about 180 ° C. for about 125 seconds, and the peak temperature of the peaked preheat was set to several.

  2B, 2C, 2D show the temperature profile of the preheat experimented. FIG. 2B shows that after applying a constant temperature preheat of about 180 ° C. for about 125 seconds, the temperature was increased at an initial temperature increase rate of 300 ° C./min and then at a temperature increase rate of 105 ° C./min. It is a heat history that gives a peak preheat that is held for 6 seconds, and thereafter drops at an initial temperature drop rate of 106 ° C./minute, then a temperature drop rate of 360 ° C./minute, and further at 68 ° C./minute. FIG. 2C is a thermal history that gives a peak preheat that gives a constant temperature preheat of about 180 ° C. and about 125 seconds, then raises the temperature, holds the peak temperature at about 290 ° C. for about 5 seconds, and then lowers the temperature. FIG. 2D shows a thermal history that gives a peak preheat that gives a constant temperature preheat of about 180 ° C. and about 125 seconds, then raises the temperature, holds it at a peak temperature of about 305 ° C. for about 5 seconds, and then lowers the temperature. The peak temperature 305 ° C. of the thermal history in FIG. 2D is the same as the peak temperature 305 degrees of the temperature profile of the eutectic junction.

  FIG. 3B is a table collectively showing the surface roughness Ra after eutectic bonding of each sample. When no thermal history is given, the surface roughness Ra of the Ag layer 26 is about 0.1 μm as described above, which is a change of + 33% compared to the initial value of 0.075 μm. The surface roughness after eutectic bonding of the sample given a constant temperature of 150 ° C. and preheating for 30 minutes in FIG. 2A is changed by + 1% as described above.

  The surface roughness of the Ag layer 26 after eutectic bonding of the sample to which the thermal history of FIG. 2B (peak temperature of about 260 ° C.) was applied was Ra = 0.043 μm. The surface roughness Ra is about 57% (change of −43%) of the initial value, and it can be seen that the surface roughness is reduced and the flatness is greatly improved. The surface roughness of the Ag layer 26 after eutectic bonding of the sample to which the thermal history of FIG. 2C (peak temperature of about 290 ° C.) was applied was Ra = 0.072 μm. Compared to the case of FIG. 2B, the surface roughness is deteriorated, but it is still about 96% (change of −4%) of the initial value, and the surface roughness is reduced compared to the initial state. The surface roughness of the Ag layer 26 after eutectic bonding of the sample to which the thermal history of FIG. 2D (peak temperature of about 305 ° C.) was applied was Ra = 0.092 μm. The surface roughness is suppressed as compared with the surface roughness Ra when the thermal history is not applied, which is about 0.1 μm. However, the surface roughness Ra is about 123% (+ 23%) of the initial value, which is larger than the initial value.

  It can be seen that the surface roughness deteriorates as the peak temperature of the thermal history is increased above about 260 ° C. It can be said that the peak temperature of the thermal history is preferably set to be equal to or lower than the peak temperature of the temperature profile of the eutectic bonding. The peak temperature of the thermal history will more preferably be 300 ° C. or lower, and even more preferably 290 ° C. or lower. However, it is preferably 150 ° C. or higher.

  From the above experimental results, when performing eutectic bonding including the reflective metal layer and the eutectic metal layer, the flatness of the reflective metal layer is obtained by preheating the reflective metal layer at a peak temperature below the eutectic bonding temperature. It was found that the decrease was suppressed. More preferably, preheating is applied at a peak temperature that is 5 ° C. or more lower than the eutectic bonding temperature.

  In addition, although preheating was performed with the LED chip 1 overlaid on the submount substrate 2, the surface roughness of the reflective metal layer in the region where the LED chip 1 is not present is unlikely to be affected by the LED chip. . The same result can be expected even if the pre-mount substrate 2 is preheated alone.

  Other configuration requirements may be changed in various ways. Although the submount substrate is composed of a silicon substrate provided with a silicon oxide film, the submount substrate may be made conductive. While the reflective metal layer is formed on the submount substrate and the anode electrode of the LED chip is formed of a eutectic material, a eutectic material layer may be used separately from the anode electrode.

  FIG. 4A shows a case where a conductive submount substrate is used instead of the insulating submount substrate. For example, an Au layer 32 is vapor-deposited on both surfaces of a conductive substrate 31 made of Si to which n-type or p-type impurities are added at a high concentration, and alloyed at 400 ° C. in a nitrogen atmosphere. The thickness of the Au layer 32 is, for example, 150 to 600 nm. By alloying, the conductive substrate 31 and the Au layer 32 are eutectic and integrated to form an ohmic contact. For this reason, the Au layer 32 does not peel from the conductive substrate 31. The conductive substrate 31 can be formed of a material other than Si, such as Cu, which is conductive, has high thermal conductivity, and is alloyed with Au.

  On one Au layer 32, a reflective metal layer 35 such as a Ti layer 33, a Ni layer 34, Ag, or Al is deposited by an electron beam evaporation method (EB method) or the like. The Ti layer 33 has a thickness of 100 to 200 nm, the Ni layer 34 has a thickness of 50 to 150 nm, and the reflective metal layer 35 has a thickness of 0.6 to 2 μm, for example. Instead of the Ni layer 34, a NiV layer may be formed. The same effect of preventing ball up will be obtained. The case of forming a Ti / Ni / Ag metal laminate has been described. Cr / Ni / Ag, TiW / Ag, Ti / NiV / Ag, Cr / NiV / Ag, Ti / Ni / AgNdCu, Cr / Ni / AgNdCu , TiW / AgNdCu, Ti / Ni / AgBi, Cr / Ni / AgNdCu, TiW / AgNdCu, Ti / Ni / AgBi, Cr / Ni / AgBi, TiW / AgBi, etc. could be used. Instead of the Ag layer, an Ag alloy layer containing Se, Pd or the like can also be used. As a film forming method, an appropriate method can be used among sputtering, EB vapor deposition, plating, resistance heating and the like.

FIG. 4B shows another configuration example of the LED chip. A GaN-based nitride semiconductor buffer layer 42 is grown on the sapphire substrate 41 at a temperature lower than the temperature at which it can be epitaxially grown, and after annealing, an n-type GaN-based nitride semiconductor layer 43 is epitaxially grown thereon. . A nitride semiconductor active layer 44 having a multiple quantum well (MQW) structure in which a plurality of well layers W are sandwiched between barrier layers is formed on the n-type nitride semiconductor layer 43, and a p-type nitride semiconductor layer 45 is formed thereon. Form. In order to form an electrode in the n-type layer, the p-type layer 45 and part of the MQW structure 44 are removed by etching. Thereafter, electrodes are formed on the p-type layer 45 and the n-type layer 43. As the n-type impurity, Si, Ge, C, Se, Te or the like can be used. Zn, Mg, Be, Ca, Sr, Ba, etc. can be used as the p-type impurity. In the MQW structure, for example, the well layer and the barrier layer can be formed by selecting the composition x of the nitride semiconductor In x Ga 1-x N.

  When the LED chip shown in FIG. 4B is used, wiring is formed on the submount substrate. For example, it is possible to use a submount substrate as disclosed in Japanese Patent Application No. 2004-141380 [Best Mode for Carrying Out the Invention], particularly in FIGS. 4-6 and 7 and their related descriptions. it can.

  Note that although an LED using a nitride semiconductor has been described as an example, the LED is not limited to a nitride semiconductor. As long as the LED is eutectic-bonded with the reflective metal layer, the same effect as in the embodiment can be expected. For example, GaAs and InP described in the embodiments of Patent Documents 1 and 2 may be used as a substrate.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, substitutions, combinations, and the like can be made.

1A to 1C are cross-sectional views illustrating manufacturing steps of a semiconductor light emitting device in which an LED chip is mounted on a submount substrate. 2A to 2D are graphs showing temperature profiles of preheating. FIG. 3A is a graph showing the temperature profile of eutectic bonding, and FIG. 3B is a table showing the roughness of the surface of the reflective metal layer after eutectic bonding in the comparative example and the example. 4A and 4B are sectional views showing a submount substrate and an LED chip according to a modification.

Explanation of symbols

11 SiC substrate 12 Nitride semiconductor layer 13 Anode electrode (Au—Sn eutectic layer)
14 Cathode electrode 21 Si substrate 22 Silicon oxide layer 23 Ti layer 24 Cu layer 25 Ni layer 26 Reflective metal layer (Ag layer)
31 Si substrate 32 Au layer 33 Ti layer 34 Ni layer 35 Reflective metal layer 41 Sapphire substrate 42 (low temperature growth) nitride semiconductor buffer layer 43 n-type nitride semiconductor layer 44 nitride semiconductor MQW structure 45 p-type nitride semiconductor layer

Claims (10)

  1. Preparing an LED chip having a eutectic electrode layer;
    Preparing a submount substrate on which a laminated electrode layer including a reflective metal layer mainly composed of Ag is formed;
    The submount substrate having the laminated electrode layer has a thermal history that is a combination of constant temperature constant temperature preheating and peaked peak preheating, and the peak temperature of the peaked preheat is 150 ° C. or higher and 300 ° C. or lower. Applying, and
    A step of the submount substrate, and placing the LED chip having the eutectic electrode layer performs a eutectic bonding of applying the thermal history,
    A method of manufacturing a semiconductor light emitting device having
  2.   2. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein an arithmetic average roughness Ra of the surface of the laminated electrode layer after application of the thermal history is equal to or less than Ra before application of the thermal history.
  3. The method of manufacturing a semiconductor light-emitting device 5 ° C. or more lower claim 1 or 2, wherein the peak temperature is higher than the peak temperature of the eutectic bonding of the peak-shaped preheating of the thermal history.
  4. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the eutectic junction has a peak temperature profile with a peak temperature of 300 ° C. or higher.
  5. 5. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein a peak temperature of the peak preheat of the thermal history is 290 ° C. or lower.
  6. The laminated electrode layer, a method of manufacturing a semiconductor light-emitting device of any one of claims 1 to 5, which includes a ball-up prevention layer.
  7. The method for manufacturing a semiconductor light emitting device according to claim 6, wherein the ball-up prevention layer includes an adhesion layer of Ti, Cr, or an alloy including any one of Ti and Cr.
  8. 8. The method of manufacturing a semiconductor light emitting device according to claim 7, wherein the ball-up prevention layer includes an upper layer of Ni or an alloy containing Ni formed above the adhesion layer.
  9. The LED chip has a SiC substrate, a nitride semiconductor layer epitaxially grown thereon, a method of manufacturing a semiconductor light-emitting device of any one of claims 1-8.
  10. The step of applying the thermal history, in a superposed state and the LED chip and the submount substrate, performed immediately before the eutectic bonding step, the semiconductor light-emitting device of any one of claims 1-9 Production method.
JP2005167319A 2005-06-07 2005-06-07 Manufacturing method of semiconductor light emitting device Expired - Fee Related JP4699811B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005167319A JP4699811B2 (en) 2005-06-07 2005-06-07 Manufacturing method of semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005167319A JP4699811B2 (en) 2005-06-07 2005-06-07 Manufacturing method of semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JP2006344682A JP2006344682A (en) 2006-12-21
JP4699811B2 true JP4699811B2 (en) 2011-06-15

Family

ID=37641442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005167319A Expired - Fee Related JP4699811B2 (en) 2005-06-07 2005-06-07 Manufacturing method of semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JP4699811B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4836769B2 (en) * 2006-12-18 2011-12-14 スタンレー電気株式会社 Semiconductor light emitting device and manufacturing method thereof
JP2013062297A (en) * 2011-09-12 2013-04-04 Rohm Co Ltd Semiconductor light-emitting device and manufacturing method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335014A (en) * 2001-03-29 2002-11-22 Lumileds Lighting Us Llc A GaInN FLIP CHIP LIGHT EMITTING DEVICE HAVING HIGH REFLECTANCE OHMIC CONTACT
JP2004087705A (en) * 2002-08-26 2004-03-18 Juki Corp Die bonding equipment and method
JP2004296846A (en) * 2003-03-27 2004-10-21 Stanley Electric Co Ltd Semiconductor light emitting element and its fabricating process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335014A (en) * 2001-03-29 2002-11-22 Lumileds Lighting Us Llc A GaInN FLIP CHIP LIGHT EMITTING DEVICE HAVING HIGH REFLECTANCE OHMIC CONTACT
JP2004087705A (en) * 2002-08-26 2004-03-18 Juki Corp Die bonding equipment and method
JP2004296846A (en) * 2003-03-27 2004-10-21 Stanley Electric Co Ltd Semiconductor light emitting element and its fabricating process

Also Published As

Publication number Publication date
JP2006344682A (en) 2006-12-21

Similar Documents

Publication Publication Date Title
US8907366B2 (en) Light emitting diodes including current spreading layer and barrier sublayers
US5990500A (en) Nitride compound semiconductor light emitting element and its manufacturing method
US7112456B2 (en) Vertical GaN light emitting diode and method for manufacturing the same
US8384118B2 (en) LED assembly having maximum metal support for laser lift-off of growth substrate
US7319248B2 (en) High brightness light emitting diode
TWI292227B (en) Light-emitting-dioed-chip with a light-emitting-epitaxy-layer-series based on gan
TWI288486B (en) Light-emitting diode and method for manufacturing the same
JP5676396B2 (en) Substrate removal method for high light extraction LED
US7906785B2 (en) Vertical type nitride semiconductor light emitting device and method of manufacturing the same
TWI506811B (en) Light emitting devices having current blocking structures and methods of fabricating light emitting devices having current blocking structures
TW552723B (en) Group III nitride compound semiconductor light-emitting element
TWI399865B (en) Allngap led having reduced temperature dependence
JP4857310B2 (en) Semiconductor light emitting device and manufacturing method thereof
US7704770B2 (en) Light emitting diode by use of metal diffusion bonding technology and method of producing light emitting diode
US20040248377A1 (en) Method for manufacturing vertical gan light emitting diodes
JP2013070111A (en) Semiconductor light-emitting device
JP3912044B2 (en) Method for manufacturing group III nitride compound semiconductor light emitting device
US20060270075A1 (en) Method of manufacturing light emitting diodes
EP1941555B1 (en) SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH ELECTRODE FOR N-POLAR InGaAlN SURFACE
US7190005B2 (en) GaN LED with solderable backside metal
CN101828274B (en) Nickel tin bonding system with barrier layer for semiconductor wafers and devices
TWI479674B (en) Method for handling a semiconductor wafer assembly
TWI243488B (en) Electrical contact-area for optoelectronic semiconductor-chip and its production method
JP2006196919A (en) Light-emitting device
JP2010186829A (en) Method for manufacturing light emitting element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080428

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101026

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101026

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110301

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110303

R150 Certificate of patent or registration of utility model

Ref document number: 4699811

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees