JP4692539B2 - Manufacturing method of multilayer electronic component - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer electronic component such as a multilayer ceramic capacitor.

  For example, a multilayer ceramic electronic component such as a multilayer ceramic capacitor is manufactured as follows, for example. That is, a green sheet is formed on a flexible support by a doctor blade method using ceramic paint, and an electrode pattern is formed thereon by screen printing. The ceramic paint contains ceramic powder, organic binder, plasticizer, solvent and the like. The electrode paste for forming an electrode pattern contains conductive powders such as palladium, silver, and nickel.

  The green sheets on which the electrode patterns are formed are stacked in a predetermined number and then pressed, and a ceramic green chip is obtained through a cutting process. The ceramic green chip is subjected to binder removal processing and firing processing to become a ceramic sintered body, terminal electrodes are formed, and a multilayer ceramic electronic component is completed.

  However, when a green sheet is laminated or when a green sheet laminate is cut, a stacking shift or a cutting shift may cause a short circuit failure. For this reason, a method for preventing a stacking shift or a cutting shift is desired. For example, in Patent Document 1 below, a cutting mark is formed at the intersection of the planned cutting line in the stacked body in order to prevent stacking shift and cutting shift. The cutting mark is often formed of, for example, an electrode paste for forming an electrode pattern.

  However, with the conventional cutting mark, even when the cutting mark is cut as designed along the cutting mark, the cutting mark remains on the cut green chip. After that, wet polishing such as barrel polishing to round the corners of the green chip may be performed, but at that time, the green chip should be uniformly polished for the electrode paste portion consisting of the cutting marks. There are inconveniences such as being unable to.

In addition, the terminal electrode is formed after the green chip is baked. However, during the plating process, the plating solution may enter the chip from the electrode portion formed by the cutting mark, which may cause chip cracking or short circuit failure.
JP-A-6-314630

  The present invention has been made in view of such a situation, and an object of the present invention is a multilayer electronic component that can easily detect cutting misalignment and laminating misalignment, and does not cause inconvenience during wet polishing or plating. It is to provide a manufacturing method.

In order to achieve the above object, a manufacturing method of a multilayer electronic component according to the present invention includes
Preparing a plurality of green sheets each having an internal electrode pattern formed thereon;
A step of forming a cutting mark at the intersection of the first cutting planned line and the second cutting planned line together with the internal electrode pattern on the green sheet;
A step of laminating a green sheet in which the internal electrode pattern and the cutting mark are formed to obtain a laminate;
Cutting the laminated body along the first planned cutting line and the second planned cutting line, and a method for manufacturing a multilayer electronic component comprising:
In the case where the cutting mark does not cause a cutting shift in both the first planned cutting line and the second planned cutting line, the cutting mark does not remain on the chip after cutting,
The cutting mark is left on the cut chip when the cutting mark has a cutting deviation in one or both of the first scheduled cutting line and the second scheduled cutting line.

  In the method according to the present invention, when green sheets are stacked as designed and cut as designed, no cut mark is left on a good green chip obtained after cutting. Therefore, when a good quality green chip is wet-polished, there is no cut mark made of an electrode paste, so that the green chip can be uniformly polished. Further, when the terminal electrode is formed after the green chip is fired, the plating solution does not enter the chip from the electrode portion formed by the cutting mark during the plating process.

  In addition, when the green sheets are not stacked as designed or when the green sheets are not cut as designed, a cut mark remains on the defective green chip obtained after cutting. For example, even if the first planned cutting line is not shifted, if the cutting is performed while being shifted along any of the other second planned cutting lines, the cutting mark remains on the chip after cutting. In reverse, the cutting mark remains on the cut chip. Therefore, by performing an appearance inspection of the green chip, it is possible to easily and easily detect a green chip stacking fault or a cutting fault.

Preferably, the cutting mark has a first protruding portion that does not fit in a line width of the first scheduled cutting line, and a second protruding portion that does not fit in the second scheduled cutting line,
The first projecting portion has a mark shape that fits within a line width of the second scheduled cutting line, and the second projecting portion fits within a line width of the first scheduled cutting line.
Preferably, a line width of the first protruding portion in the cutting mark is a dimension equal to or smaller than a line width of the second scheduled cutting line, and a line width of the second protruding portion is a line of the first scheduled cutting line. It is the dimension below the width. In such a relationship, when the green sheets are stacked as designed and cut as designed, no cut mark remains on a good green chip obtained after cutting.
Alternatively, the cut mark may have a mark shape that falls within the range of the intersection of the first planned cut line and the second planned cut line. In this case, a cutting mark remains on the chip after cutting only when cutting deviation occurs in both the first cutting planned line and the second cutting planned line.

  Preferably, the cutting mark formed at the intersection of the first planned cutting line and the second planned cutting line has a cross shape. The cross-shaped mark is easy to manufacture and easy to see, and can effectively prevent stacking and cutting shifts.

  Alternatively, the cutting mark formed at the intersection of the first planned cutting line and the second planned cutting line is a circle, and the diameter of the circle is the same as that of the first planned cutting line and the second planned cutting line. It may be larger than the line width and less than or equal to the dimension of √2 of the line width. Even such a cut mark has the same effect as the cross-shaped mark. Further, the cut mark may be a rhombus.

  Preferably, a cutting mark formed at an intersection of the first scheduled cutting line and the second scheduled cutting line is different from a cutting mark formed at another intersecting section with respect to the first scheduled cutting line and the second cutting. They are connected by a contact mark with a line width less than the line width of the planned line. By connecting the cut marks located at the intersections with the contact marks, the cut marks can be easily seen, and stacking deviation and cutting deviation can be effectively prevented. In addition, when a stacking shift or a cutting shift occurs, not only a cutting mark positioned at the intersection but also a communication mark appears on the outer surface of the chip after cutting, so that a defect can be detected more easily.

  Preferably, the cutting mark is formed at an intersection of the first planned cutting line and the second planned cutting line that does not cross the internal electrode pattern. The cutting mark may be formed at an intersection between the first planned cutting line that does not cross the internal electrode pattern and the second planned cutting line that crosses the internal electrode pattern. By forming the cutting marks at the intersections of these planned cutting lines, the cutting marks can be easily seen, and stacking shifts and cutting shifts can be effectively prevented. Further, when a stacking shift or a cutting shift occurs, a cut mark located at the intersection appears in all the layers of the stacked green sheets, so that a defect can be detected more easily.

  Preferably, the cutting mark is simultaneously formed by the same means as the internal electrode pattern. Formation of a cutting mark is facilitated. Preferably, the method further includes a step of wet polishing a chip formed after cutting the laminate. In the method of the present invention, no cut mark remains on a good green chip during wet polishing, and inconveniences based thereon can be prevented.

  Although the line width of the planned cutting line depends on the cutting method, it corresponds to the thickness of the cutting blade when cutting with the cutting blade.

Hereinafter, the present invention will be described based on embodiments shown in the drawings.
FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor manufactured by a method according to an embodiment of the present invention.
2 is a perspective view of a green laminate obtained in the process of manufacturing the multilayer ceramic capacitor shown in FIG.
3 is a cross-sectional view of the main part of the green laminate shown in FIG.
FIG. 4A is a plan view of a green sheet showing an example of electrode patterns and cutting marks attached to the green sheet,
FIG. 4B is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to another green sheet to be laminated;
FIG. 5 is a plan view showing the relationship between the planned cutting line and the cutting mark,
6 is an enlarged plan view of the main part of FIG.
FIG. 7 is a perspective view of a non-defective green chip when cut as designed,
FIG. 8 is a plan view showing the relationship between the planned cutting line and the cutting mark when the cutting is not carried out as designed but shifted from the cutting mark;
FIG. 9 is a perspective view of a defective green chip having a cutting deviation cut at the IX portion shown in FIG.
FIG. 10 is a perspective view of a defective green chip having a cutting deviation cut at a portion X shown in FIG.
FIG. 11A is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to the green sheet according to another embodiment of the present invention,
FIG. 11B is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to another green sheet to be laminated;
FIG. 12 is a plan view showing a relationship between a planned cutting line and a cutting mark;
FIG. 13 is a plan view showing a relationship between a planned cutting line and a cutting mark according to another embodiment of the present invention.
First embodiment

  First, an overall configuration of a multilayer ceramic capacitor will be described as an embodiment of a multilayer electronic component manufactured by a method according to an embodiment of the present invention.

  As shown in FIG. 1, the multilayer ceramic capacitor 2 according to this embodiment includes a capacitor body 4, a first terminal electrode 6, and a second terminal electrode 8. The capacitor body 4 has a first internal electrode layer 12 and a second internal electrode layer 13, and these internal electrode layers 12, 13 are interposed between the first inner dielectric layer 10 and the second inner dielectric layer 11. Are stacked alternately.

  The capacitor body 4 has outer dielectric layers 14 on both end faces in the stacking direction. One of the first internal electrode layers 12 that are alternately stacked is electrically connected to the inside of the first terminal electrode 6 that is formed outside the first end of the capacitor body 4. The other second internal electrode layer 13 that is alternately stacked is electrically connected to the inside of the second terminal electrode 8 formed outside the second end of the capacitor body 4. .

  The materials of the first and second inner dielectric layers 10 and 11 and the outer dielectric layer 14 are not particularly limited, and are made of a dielectric material such as calcium titanate, strontium titanate and / or barium titanate. . The thickness of each inner dielectric layer 10, 11 is not particularly limited, but is generally several μm to several tens μm. Further, the thickness of the outer layer portion composed of the outer dielectric layer 14 is not particularly limited, but is preferably in the range of 10 to 200 μm.

  The material of the terminal electrodes 6 and 8 is not particularly limited, but usually at least one of Ni, Pd, Ag, Au, Cu, Pt, Rh, Ru, Ir, or an alloy thereof can be used. Usually, Cu, Cu alloy, Ni, Ni alloy, etc., Ag, Ag—Pd alloy, In—Ga alloy, etc. are used. The thickness of the terminal electrodes 6 and 8 is not particularly limited, but is usually about 10 to 50 μm.

The shape and size of the multilayer ceramic capacitor 2 may be appropriately determined according to the purpose and application. When the multilayer ceramic capacitor 2 has a rectangular parallelepiped shape, it is usually about vertical (0.2 to 5.7 mm) × horizontal (0.1 to 5.0 mm) × thickness (0.1 to 3.2 mm).
Next, the manufacturing method of the multilayer ceramic capacitor 2 as one embodiment of the present invention will be described.

  First, the green laminated body 4a shown in FIG. 2 is formed. In order to form the green laminate 4a, as shown in FIG. 3, a first green sheet 10a on which a first internal electrode pattern 12a is formed and a second green sheet 11a on which a second internal electrode pattern 13a is formed. Are alternately laminated to form a green laminated body 4a.

  The dielectric paste for forming the green sheets 10a and 11a is usually composed of an organic solvent-based paste or an aqueous paste obtained by kneading ceramic powder and an organic vehicle. In the present embodiment, these pastes are preferably organic solvent-based pastes.

  The organic vehicle is obtained by dissolving a binder in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from usual various binders such as ethyl cellulose and polyvinyl butyral.

  The internal electrode paste for forming the internal electrode patterns 12a, 13a is composed of various conductive metals and alloys, or various oxides, organometallic compounds, resinates, etc. that become conductive materials after firing, and the above-mentioned organic materials. Prepare by kneading with vehicle. The internal electrode paste may contain a ceramic powder as a co-material as necessary. The common material has an effect of suppressing the sintering of the conductive powder in the firing process.

  The green sheets 10a and 11a are formed by a doctor blade method using the above-described dielectric paste. Further, in order to form the internal electrode patterns 12a and 13a on the respective surfaces of the green sheets 10a and 11a, screen printing or the like may be performed using the internal electrode paste.

  The first green sheet 10a in the green laminate 4a is a portion that will eventually become the first inner dielectric layer 10 shown in FIG. 1, and the second green sheet 11a is finally the second green sheet shown in FIG. This is a portion that becomes the inner dielectric layer 11. The first internal electrode pattern 12a is a portion that will eventually become the first internal electrode layer 12 shown in FIG. 1, and the second internal electrode pattern 13a is finally the second internal electrode shown in FIG. This is the portion that becomes the layer 13.

  In FIG. 3, the number of the internal electrode layers 12 a and 13 a in the green laminated body 4 a is reduced for ease of illustration, but it can be freely set from several to several hundred layers.

  As shown in FIGS. 2 and 3, green sheets 14a to be the outer dielectric layers 14 are stacked at both ends in the stacking direction Z of the green stacked body 4a. The thickness in the stacking direction Z of the green stacked body 4a corresponds to the thickness of the capacitor body 4 shown in FIG. 1 after firing.

  As shown in FIGS. 2 and 3, in the green laminate 4a, the first internal electrode pattern 12a and the second internal electrode pattern 13a are along the longitudinal direction X (hereinafter also referred to as the X axis) of the patterns 12a and 13a. This is a recurrence pattern of straight lines that are shifted by a half pattern.

  Further, when viewed along the longitudinal direction Y (hereinafter also referred to as the Y axis) of the green laminated body 4a that is perpendicular to both the longitudinal direction X of the patterns 12a and 13a and the stacking direction Z (hereinafter also referred to as the Z axis). The first internal electrode pattern 12a and the second internal electrode pattern 13a are separated linear patterns having the same pitch length.

  As shown in FIG. 2, the first internal electrode pattern 12a and the second internal electrode pattern 13a have regions that are not formed at both end positions along the Y axis of the green laminate 4a. End cut-off portion 26 is obtained.

  In the present embodiment, the green laminated body 4a is cut along the planned cutting line 30 shown in FIGS. As shown in FIG. 5, when viewed from the XY plane of the green laminate 4a, the planned cutting line 30 includes a first planned cutting line 30x parallel to the X axis and a second planned cutting line 30y parallel to the Y axis. And formed into a matrix, and after dividing along the planned cutting line 30 (30x, 30y), the green chip 4b is obtained.

  As shown in FIG. 4A, FIG. 4B, and FIG. 5, in order to form the cutting planned line 30 at an accurate position when viewed from the XY plane of the green laminated body 4a, the green sheets 10a and 11a have internal electrode patterns. Along with 12a or 13a, a cutting mark M1 is formed at a predetermined position. These cut marks M1 can be simultaneously formed by the printing method using the same electrode paste when the internal electrode pattern 12a or 13a is formed by the printing method.

  In this embodiment, these cutting marks M1 have a cross shape and are formed at the intersections between the first planned cutting line 30x and the second planned cutting line 30y. These cutting marks M1 may also be formed on the green sheet 14a itself.

  As shown in FIG. 6, the cutting mark M1 includes a first protruding portion 32 that does not fit in the line width W2 of the first scheduled cutting line 30x and a second protruding portion 34 that does not fit in the second scheduled cutting line 30y. It is a letter shape. Moreover, the cross-shaped cutting mark M1 in which the first projecting portion 32 fits within the line width W2 of the second scheduled cutting line 30y and the second projecting portion 34 fits within the line width W2 of the first scheduled cutting line 30x. It is. The line width W2 of the planned cutting lines 30x and 30y is a width corresponding to the thickness W2a of the cutting tool 40, and is equal to or greater than the thickness W2a of the cutting tool 40. However, the width of the cutting mark M1 is narrower than the thickness W2a of the cutting tool 40.

  The line width W2 of these planned cutting lines 30x and 30y is smaller than the width W4 between the electrode patterns 12a (13a is the same, and will be omitted hereinafter). The cutting tool 40 for cutting along the planned cutting lines 30x and 30y is not particularly limited, and for example, a rotary blade is exemplified. However, the cutting tool 40 is not necessarily a mechanical cutting tool, such as a laser beam. It may be cut by energy light.

  The line width W1 of the cutting marks M1 itself is the same as the line width of the first protruding portion 32 and the line width of the second protruding portion 34, but is equal to or smaller than the line width W2 of the planned cutting lines 30x and 30y. Width. In this embodiment, the representative length W3 of the cross-shaped cutting mark M1 itself is designed to be smaller than the width W4 between the electrode patterns 12a, but it is not necessarily required to be small. For example, the cross-shaped cut marks M1 may be connected to each other by a contact mark Mb. The line width of the contact mark Mb is preferably equal to or less than the line width W1 of the cutting mark M1 itself.

  These cutting marks M1 are formed at the intersection of the first planned cutting line 30x and the second planned cutting line 30y that do not cross the electrode pattern 12a, and the first planned cutting line 30x and the electrode pattern that do not cross the electrode pattern 12a. It may also be formed at the intersection with the second planned cutting line 30y crossing 12a. By forming the cutting marks M1 at the intersections of these planned cutting lines 30x and 30y, the cutting marks M1 can be easily seen, and stacking and cutting shifts can be effectively prevented. In addition, when a stacking shift or a cutting shift occurs, the cut mark M1 located at the intersection appears in all the layers of the stacked green sheets 10a and 11a, so that a defect can be detected more easily. .

  The green laminated body 4a with such a cutting mark M1 is cut by a cutting tool 40 such as a rotary blade along the planned cutting line 30 (30x, 30y) to form individual green chips 4b. As shown in FIG. 7, when there is no cutting misalignment, the internal electrode patterns 12a and 13a are arranged in an orderly symmetrical shape in the X, Y, and Z directions inside the green chip 4b.

  However, it is assumed that the actual first cutting line 30xa is formed along the cutting mark M1 as shown in the IX portion of FIG. 8, for example, but the second cutting line 30ya is formed so as to be shifted from the cutting mark M1. If there is no cut mark M1, it cannot be distinguished from the normally cut green chip 4b as shown in FIG.

  In the present embodiment, when the second cutting line 30ya is formed so as to be shifted from the cutting mark M1, the first protruding portion 32 in the mark M1 shown in FIG. 8 remains on the cutting surface of the chip 4b, and as shown in FIG. The mark M1 is exposed.

  Further, for example, as shown in part X of FIG. 8, it is assumed that the actual second cutting line 30ya is formed along the cutting mark M1, but the first cutting line 30xa is formed so as to be shifted from the cutting mark M1. In that case, the second projecting portion 34 of the mark M1 shown in FIG. 8 remains on the cut surface of the chip 4b, and the mark M1 is exposed as shown in FIG.

  In the present embodiment, the green chip 4b from which the mark M1 has been exposed can be easily identified, and only the good green chip 4b is subjected to binder removal processing and firing processing to obtain a sintered body chip. Various conditions for the binder removal treatment and the firing treatment are not particularly limited, and the firing temperature is, for example, 1000 to 1400 ° C.

  Thereafter, an electrode paste to be the first and second terminal electrodes 6 and 8 shown in FIG. 1 is applied to the sintered body chip, and a baking process is performed. There are no particular limitations on the temperature conditions during the baking process.

  In the method according to the present embodiment, when the green sheets 10a and 11a are stacked as designed and cut as designed, the cut mark M1 does not remain on the non-defective green chip 4b obtained after cutting. Therefore, when the good green chip 4b is wet-polished, the green chip 4b can be uniformly polished because there is no cut mark M1 made of the electrode paste. Further, when the terminal electrode is formed after the green chip 4b is fired, the plating solution does not enter the chip from the electrode portion formed by the cutting mark M1 during the plating process.

If the green sheets are not stacked as designed or cut as designed, as described above, the cutting mark M1 remains on the defective green chip obtained after cutting. . Therefore, by performing an appearance inspection of the green chip 4b, it is possible to easily and easily detect a stacking failure or a cutting failure of the green chip 4b.
Second embodiment

  As shown in FIGS. 11A, 11B, and 12, in the method of the present embodiment, the cutting mark M2 formed at the intersection of the first planned cutting line 30x and the second planned cutting line 30y has a circular shape. . The diameter W3a of the circular mark M2 is larger than the line width W2 of the first scheduled cutting line 30x and the second scheduled cutting line 30y, and is equal to or smaller than the dimension of √2 of the line width W2. .

  However, this circular mark M2 also has a first protruding portion 32 that does not fit within the line width W2 of the first planned cutting line 30x and a second protruding portion 34 that does not fit within the second scheduled cutting line 30y. Even such a cut mark M2 has the same effect as the cross-shaped mark M1.

  Moreover, as shown in FIG. 13, the cutting mark M3 may be a rhombus. Even in that case, the cutting mark M3 includes the first protruding portion 32 that does not fit in the line width W2 of the first scheduled cutting line 30x and the second protruding portion 34 that does not fit in the second scheduled cutting line 30y. The representative length W3b of the diamond-shaped cut mark M3 is preferably equal to or less than the representative length W3 of the cross-shaped cut mark M1 in the first embodiment. Even such a cut mark M3 has the same effects as the cross-shaped mark M1.

  The present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the present invention.

For example, the cut mark may have a mark shape that falls within the range of the intersection of the first planned cut line 30x and the second planned cut line 30y. That is, the line width of the cut mark is equal to or less than the line width of the first planned cut line 30x and the second planned cut line 30y, and the mark itself does not necessarily have a portion protruding from the range of the intersection. Also good. In this case, a cutting mark remains on the chip after cutting only when cutting deviation occurs in both the first cutting planned line and the second cutting planned line.
Further, the method of the present invention can be applied not only to a multilayer ceramic capacitor but also to other electronic components.

FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor manufactured by a method according to an embodiment of the present invention. FIG. 2 is a perspective view of a green multilayer body obtained in the process of manufacturing the multilayer ceramic capacitor shown in FIG. 3 is a cross-sectional view of a main part of the green laminate shown in FIG. FIG. 4A is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to the green sheet. FIG. 4B is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to another stacked green sheet. FIG. 5 is a plan view showing the relationship between the planned cutting line and the cutting mark. 6 is an enlarged plan view of the main part of FIG. FIG. 7 is a perspective view of a non-defective green chip when cut as designed. FIG. 8 is a plan view showing a relationship between a planned cutting line and a cutting mark when the cutting is performed with a deviation from the cutting mark, not as designed. FIG. 9 is a perspective view of a defective green chip having a cutting deviation cut at a portion IX shown in FIG. FIG. 10 is a perspective view of a defective green chip having a cutting shift cut at a portion X shown in FIG. FIG. 11A is a plan view of a green sheet showing an example of electrode patterns and cutting marks attached to the green sheet according to another embodiment of the present invention. FIG. 11B is a plan view of a green sheet showing an example of an electrode pattern and a cutting mark attached to another green sheet to be laminated. FIG. 12 is a plan view showing the relationship between the planned cutting line and the cutting mark. FIG. 13 is a plan view showing a relationship between a planned cutting line and a cutting mark according to another embodiment of the present invention.

Explanation of symbols

2 ... multilayer ceramic capacitor 4 ... capacitor body 4a ... green laminate 4b ... green chip 6 ... first terminal electrode 8 ... second terminal electrode 10 ... first inner dielectric layer 10a ... first green sheet 11 ... second inner side Dielectric layer 11a ... second green sheet 12 ... first internal electrode layer 12a ... first internal electrode pattern 13 ... second internal electrode layer 13a ... second internal electrode pattern 30 ... planned cutting line 30x ... first planned cutting line 30y ... 2nd scheduled cutting line 32 ... 1st protrusion part 34 ... 2nd protrusion part 40 ... Cutting tool M1, M2, M3 ... Cutting mark

Claims (10)

Preparing a plurality of green sheets each having an internal electrode pattern formed thereon;
A step of forming a cutting mark at the intersection of the first cutting planned line and the second cutting planned line together with the internal electrode pattern on the green sheet;
A step of laminating a green sheet in which the internal electrode pattern and the cutting mark are formed to obtain a laminate;
Cutting the laminated body along the first planned cutting line and the second planned cutting line, and a method for manufacturing a multilayer electronic component comprising:
In the case where the cutting mark does not cause a cutting shift in both the first planned cutting line and the second planned cutting line, the cutting mark does not remain on the chip after cutting,
If any of / or cutting shifted in both of the first cutting line and the second cutting line has occurred, the cutting mark cut after the chip is Ri residue,
The cutting mark has a first protruding portion that does not fit in a line width of the first scheduled cutting line, and a second protruding portion that does not fit in the second scheduled cutting line;
The first projecting portion has a mark shape that fits within the line width of the second planned cutting line, and the second projecting portion fits within the line width of the first planned cutting line,
The line width of the first projecting portion in the cutting mark is a dimension not more than the line width of the second scheduled cutting line, and the line width of the second projecting portion is not more than the line width of the first scheduled cutting line. Dimensions,
The method of manufacturing a multilayer electronic component, wherein the cutting mark is simultaneously formed by the same means as the internal electrode pattern using an internal electrode paste for forming the internal electrode pattern .   2. The method for manufacturing a multilayer electronic component according to claim 1, wherein the cut mark has a mark shape that falls within a range of an intersection of the first planned cut line and the second planned cut line. The method for manufacturing a multilayer electronic component according to claim 1 , wherein a cut mark formed at an intersection of the first planned cutting line and the second planned cutting line is a cross shape. The cutting mark formed at the intersection of the first planned cutting line and the second planned cutting line is circular, and the diameter of the circular shape is the line width of the first planned cutting line and the second planned cutting line. 2. The method for manufacturing a multilayer electronic component according to claim 1 , wherein the size is larger than that and equal to or smaller than a dimension of √2 of the line width. The cutting mark formed at the intersection of the first planned cutting line and the second planned cutting line is different from the cutting mark formed at the other intersecting part of the first planned cutting line and the second planned cutting line. The method for manufacturing a multilayer electronic component according to any one of claims 1 to 4, wherein the multilayer electronic component is connected by a communication mark having a line width equal to or smaller than the line width. The method of manufacturing a multilayer electronic component according to claim 1 , wherein the cutting mark is formed at an intersection of the first planned cutting line and the second planned cutting line that does not cross the internal electrode pattern. The stacked electron according to claim 6, wherein the cutting mark is also formed at an intersection of the first planned cutting line that does not cross the internal electrode pattern and the second planned cutting line that crosses the internal electrode pattern. A manufacturing method for parts. The method for manufacturing a multilayer electronic component according to claim 1 , further comprising a step of wet polishing a chip formed after cutting the multilayer body. The method of manufacturing a multilayer electronic component according to claim 1, wherein the line width of the planned cutting line corresponds to the thickness of the cutting blade. The method for manufacturing a multilayer electronic component according to claim 1, further comprising a step of firing the cut chip and forming a terminal electrode.

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