JP4689659B2 - Semiconductor memory and signal processing apparatus - Google Patents

Description

  The present invention relates to a semiconductor memory and a signal processing device applicable to a motion vector detection circuit. Specifically, the semiconductor memory includes a plurality of storage areas, and a calculation unit that writes back data that has been calculated using the data read from the corresponding storage areas and the input data to the storage areas. Since the storage area and the calculation means are formed integrally on the semiconductor chip, the semiconductor chip can be prevented from being enlarged.

  In image processing, motion vector detection is one of important elements, and a typical method is a block matching method. This is to evaluate the correlation between a certain pixel block (reference block) constituting a part of a certain frame and the same shape pixel block (candidate block) at various positions in a frame at different times. A relative positional shift with the highest candidate block is regarded as a motion vector in the reference block.

  Here, an area that assumes a candidate block is a search range. For the evaluation of the correlation, the sum total of each pixel in the block of the absolute difference value of the pixel data between the corresponding pixels of the reference block and the candidate block, that is, the sum of absolute differences is often used. A sum of absolute differences (correlation values) corresponding to the number of pixels in the search range is obtained for one reference block, which is a correlation value table. In the correlation value table, the place where the sum of absolute differences is smallest, that is, where the correlation is high is regarded as a motion vector in units of pixels. In practice, this processing has a very heavy calculation load, and various measures are taken with respect to the shape and size of the block, the pixel position used for the calculation, and the like.

  For example, according to the multi-port memory device described in Patent Document 1, a shift register that sets a pixel group of a search memory in block matching is provided, and pixel data is simultaneously read in parallel from these shift registers, This is a technical idea in which the pixel data is output to the PE array. As a result, a plurality of pixel data can be simultaneously read from unrelated addresses from one search memory and output to the PE array.

JP 2000-242554 A (page 8, FIGS. 1 and 7)

  By the way, in the conventional block matching, a PE (Processing Element) in which a difference absolute value arithmetic unit and a plurality of registers as storage elements are combined or an adder is further combined is often used. By flowing data between PEs arranged in an array in parallel and in a pipeline, a plurality of difference absolute value sums are calculated in parallel, or after obtaining the difference absolute values, the sum is summed by an adder, and the difference absolute value sum ( A collection of correlation values), that is, a correlation value table is generated.

  In this case, as shown in FIG. 7 of Patent Document 1, since a register is used as a storage element, the number of constituent elements is large and the occupation area is widened, and each PE has a plurality of (for example, two to three) registers. As a result, the occupation area of the PE as a whole increases. Therefore, there is a problem that the semiconductor chip is increased in size.

  Therefore, an object of the present invention is to provide a semiconductor memory and a signal processing device that can prevent an increase in the size of a semiconductor chip.

The semiconductor memory according to the present invention reads data stored in an input means for inputting data, a plurality of storage areas, and data stored in the storage area, and uses the read data and data input by the input means to perform predetermined processing. And a reading means for reading the data stored in the storage area. At least the storage area and the calculating means are provided on a semiconductor chip. The plurality of storage areas are formed in an integrated manner, and the memory areas are arranged in a matrix, and the calculation means includes a plurality of calculation units that perform bit-unit calculations. it's also disposed aligned with the pitch of the columns of the memory cells.

According to the semiconductor memory of the present invention, the storage area and the computing means are formed integrally on the semiconductor chip. For example, the storage area is composed of memory cells arranged in a matrix, and the computing means is composed of a plurality of computing units that perform bit-wise computations. In this case, the plurality of arithmetic units are arranged in alignment with the column pitch of the memory cell. As a result, the occupied area can be reduced as compared with the conventional case in which a register is used as a memory element, and an increase in the size of the semiconductor chip can be prevented. Further, it is possible to efficiently supply the addition data from the arithmetic unit to the memory cell and supply the storage data from the memory cell to the arithmetic unit.

The signal processing device according to the present invention is a device for processing a signal, wherein the input means for inputting the signal, a plurality of storage areas, a signal stored in the storage area is read, the read signal and the above-mentioned Computation means for writing back a signal obtained by performing a predetermined computation using a signal input by the input means to the storage area, and readout means for reading the signal stored in the storage area, and at least the above The storage area and the calculation means are integrated on a semiconductor chip, and the plurality of storage areas include memory cells arranged in a matrix, and the calculation means includes a plurality of calculation units that perform bit-unit calculations. becomes, the plurality of operation portions is the even Ru comprising a semiconductor memory which are arranged aligned to the pitch of the columns of the memory cells.

According to the signal processing apparatus of the present invention, the storage area and the calculation means are integrated on the semiconductor chip , the plurality of storage areas are formed of memory cells arranged in a matrix, and the calculation means performs a calculation in bit units. A semiconductor memory including a plurality of arithmetic units is provided. In this semiconductor memory, a plurality of arithmetic units are arranged in alignment with the pitch of the column of memory cells. Thereby, the enlargement of the semiconductor chip used for the device can be prevented. Further, it is possible to efficiently supply the addition data from the arithmetic unit to the memory cell and supply the storage data from the memory cell to the arithmetic unit.

  According to the present invention, the semiconductor memory includes a plurality of storage areas, and a calculation unit that writes back data that has been calculated using data read from the corresponding storage areas and input data to the storage areas. At least the storage area and the calculation means are integrally formed on the semiconductor chip. With this configuration, it is possible to reduce the occupied area and prevent an increase in the size of the semiconductor chip as compared with the conventional case where a register is used as a memory element.

  Further, according to the present invention, the plurality of arithmetic units in bit units constituting the arithmetic means are arranged in alignment with the column pitch of the memory cells arranged in a matrix constituting the semiconductor memory. It is possible to efficiently supply additional data from the memory cell to the memory cell and supply storage data from the memory cell to the arithmetic unit.

  Further, according to the present invention, the data for clearing or presetting the storage area is generated, and the storage area is cleared or preset by this data without inputting data for clearing or presetting from the outside. The semiconductor memory can be easily cleared or preset, and by devising the data for presetting, for example, a specific motion vector such as (0, 0) can be easily detected in a flat picture portion.

  Further, according to the present invention, when the calculation result by the plurality of addition units constituting the calculation means overflows, the maximum value is set in a predetermined area of the storage area corresponding to the plurality of addition units. It is possible to prevent a motion vector detection error in which an erroneously small value is stored as a correlation value in a predetermined area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of a motion compensated prediction encoding apparatus 100 as an embodiment.

  The encoding apparatus 100 has an input terminal 101 for inputting image data (frame data constituting a moving image) Di, image data Di supplied to the input terminal 101, and prediction supplied from a motion compensation circuit 110 described later. A subtractor 102 that calculates a difference with image data, a DCT circuit 103 that performs DCT (discrete cosine transform) on the difference data obtained by the subtractor 102, and a DCT coefficient obtained by the DCT circuit 103 A quantization circuit 104 that performs quantization and an output terminal 105 that outputs encoded data Do obtained by the quantization circuit 104 are provided.

  The encoding apparatus 100 also performs an inverse quantization circuit 106 that performs inverse quantization on the encoded data Do obtained by the quantization circuit 104, and performs inverse DCT on the output data of the inverse quantization circuit 106. An inverse DCT circuit 107 that obtains difference data, and an adder 108 that adds the difference data obtained by the inverse DCT circuit 107 and the predicted image data obtained by the motion compensation circuit 110 to restore the original image data; A frame memory 109 for storing the image data restored by the adder 108.

  Also, the encoding apparatus 100 reads the image data stored in the frame memory 109, performs motion compensation based on a motion vector MV from a motion vector detection circuit 111 described later, and then performs the subtractor 102 and the addition as described above. A motion compensation circuit 110 that supplies the image data 108 as predicted image data, and a motion vector detection circuit 111 that detects the motion vector MV of the image data Di supplied to the input terminal 101 and supplies the motion vector MV to the motion compensation circuit 110. Yes.

  The operation of the motion compensated predictive coding apparatus 100 shown in FIG. 1 will be described.

  Image data Di input to the input terminal 101 is supplied to the subtractor 102 and the motion vector detection circuit 111. The subtractor 102 calculates the difference between the image data Di and the predicted image data supplied from the motion compensation circuit 110.

  The difference data obtained by the subtracter 102 is supplied to the DCT circuit 103 and subjected to discrete cosine transform. The DCT coefficient obtained by the DCT circuit 103 is supplied to the quantization circuit 104 and quantized. The encoded data Do obtained by the quantization circuit 104 is output to the output terminal 105.

  Also, the encoded data Do obtained by the quantization circuit 104 is supplied to the inverse quantization circuit 106 and inversely quantized, and the output data of the inverse quantization circuit 106 is further supplied to the inverse DCT circuit 107 to perform inverse DCT. The difference data is restored. The difference data and the prediction data from the motion compensation circuit 110 are added by the adder 108 to restore the original image data, and the restored image data is stored in the frame memory 109.

  In the motion compensation circuit 110, in a certain frame, image data stored in the frame memory 109 is read in the previous frame, and motion compensation is performed based on the motion vector MV from the motion vector detection circuit 111. Predictive image data is obtained. As described above, the predicted image data is supplied to the subtractor 102 to obtain difference data, and is also supplied to the adder 108 to restore the image data.

  Next, details of the motion vector detection circuit 111 will be described.

  In the motion vector detection circuit 111, a motion vector is detected by a block matching method. As shown in FIG. 2, the motion vector is obtained by moving the candidate block of the search frame within a predetermined search range and detecting the candidate block that most closely matches the reference block of the reference frame. is there.

  In the block matching method, as shown in FIG. 3A, one image, for example, one frame image of horizontal H pixels and vertical V lines is subdivided into blocks of P pixels × Q lines as shown in FIG. 3B. . In the example of FIG. 3B, P = 5 and Q = 5. c is the central pixel position of the block.

  4A to 4C show the positional relationship between a reference block having c as the central pixel and a candidate block having c ′ as the center. The reference block having c as the central pixel is a reference block of interest in the reference frame, and the candidate block of the search frame that matches the reference block is located at the position of the block centering on c ′ in the search frame. In the block matching method, a motion vector is detected by finding a candidate block that most closely matches a reference block within a search range.

  In the case of FIG. 4A, motion vectors of +1 pixel in the horizontal direction and +1 line in the vertical direction, that is, (+1, +1) are detected. In FIG. 4B, a motion vector MV of (+3, +3) is detected, and in FIG. 4C, a motion vector of (+2, −1) is detected. The motion vector is obtained for each reference block of the reference frame.

  Assuming that the motion vector search range is ± S pixels in the horizontal direction and ± T lines in the vertical direction, the reference block has a center c ′ at a position shifted ± S horizontally and ± T vertically from the center c. Need to be compared to a candidate block with

  FIG. 5 shows that when the position of the center c of a reference block having a reference frame is R, it is necessary to compare with (2S + 1) × (2T + 1) candidate blocks of the search frame to be compared. That is, all candidate blocks in which c ′ exists at the position of the first grid in FIG. 5 are comparison targets. FIG. 5 shows an example in which S = 4 and T = 3.

  Detecting the minimum value among evaluation values obtained by comparison within the search range (that is, sum of absolute values of frame differences, sum of squares of frame differences, or sum of absolute values of frame differences, etc.) Thus, a motion vector is detected. The search range in FIG. 5 is an area where the center of the candidate block is located, and the size of the search range including the entire candidate block is (2S + P) × (2T + Q).

  FIG. 6 shows the configuration of the motion vector detection circuit 111.

  The motion vector detection circuit 111 includes a controller 121 that controls the operation of the entire circuit, an input terminal 122 that receives image data Di of a reference frame, and a frame memory 123 that accumulates the image data Di as image data of a search frame. And have. Operations such as writing and reading of the frame memory 123 are controlled by the controller 121.

The motion vector detection circuit 111 has a plurality of difference absolute value calculators 124 _{-1 to} 124 _-N . Here, N is the number of a plurality of candidate blocks existing in the search range for one reference pixel in a certain reference block. The plurality of computing units 124 _{-1 to} 124 _-N commonly input pixel data constituting the image data Di input to the input terminal 122 as pixel data Dr of the reference block, and also search range for the reference block. The pixel data Dc _{−1 to} Dc _−N of a plurality of candidate blocks existing in is respectively input, and the difference absolute value between the pixel data of the reference block and the pixel data of the candidate block is calculated.

In this case, in the calculators 124 _{-1 to} 124 _-N , as shown in FIG. 7, a one-to-N matching calculation is performed between one reference pixel and N search range pixels. Here, the position of the search range pixel with respect to this reference pixel changes according to the position of the reference pixel in the reference block. For example, the hatched positions indicate the positions of N search range pixels with respect to one pixel at the upper left of the reference block.

The motion vector detection circuit 111 includes a plurality of adders 125 _{−1 to} 125 _−N and a semiconductor memory 126 for generating a correlation value table having a plurality of storage areas 126 _{−1 to} 126 _−N . . A plurality of adders 125 _-1 to 125 _-N, a plurality of computing units 124 are calculated by _-1 to 124 _-N and the resulting difference to absolute value and inputs each, a plurality of storage areas 126 of the semiconductor memory 126 _- Each of the stored data stored in _{1 to} 126- _N is input, and the absolute difference value is added to the stored data.

In this way, each of the addition data obtained by the plurality of adders 125 _{−1 to} 125 _−N is written back to the plurality of storage areas 126 _{−1 to} 126 _−N of the semiconductor memory 126 as storage data. The writing and reading operations of the semiconductor memory 126 are controlled by the controller 121.

For each reference block of the reference frame, the controller 121 calculates a difference absolute value in a plurality of difference absolute value calculators 124 _{-1 to} 124 _-N , and calculates a sum in a plurality of adders 125 _{-1 to} 125 _-N . write back data summation to a plurality of storage areas 126 _-1 - 126 _-N semiconductor memory 126, performs only the block pixels, into a plurality of storage areas 126 _-1 - 126 _-N semiconductor memory 126, each Control is performed so that a correlation value corresponding to each of a plurality of candidate blocks existing in the search range for the reference block is obtained.

The image data Di input to the input terminal 122 is a series of pixel data of each line. Therefore, the pixel data Dr of the reference block input to the calculators 124 _{-1 to} 124 _-N is not continuous for each reference block, but is a predetermined number of pixel data of a plurality of reference blocks. Yes. For example, when the reference block is composed of P pixels × Q lines as shown in FIG. 3B, the pixel data of a certain line constitutes a different reference block for each P pixel. Focusing on a reference block, the pixel data of the reference block are all input only after the pixel data of the Q line is input.

As described above, since the pixel data Dr of the reference block input to the calculators 124 _{-1 to} 124 _-N includes a predetermined number of pieces of pixel data of the plurality of reference blocks, the plurality of differences described above are used. calculation of the absolute value calculator 124 _-1 to 124 absolute differences in _-N, operations included adding in a plurality of adders 125 _-1 to 125 _-N, a plurality of storage areas 126 _-1 - 126 _-N semiconductor memory 126 The addition data is written back in a time-sharing manner corresponding to the plurality of reference blocks. Then, each time the pixel data of the Q line is input, the process proceeds to processing of a plurality of new reference blocks.

Further, the motion vector detection circuit 111 corresponds to each of a plurality of candidate blocks existing in the search range for the reference block obtained in the plurality of storage areas 126 _{-1 to} 126 _-N of the semiconductor memory 126 for each reference block. A correlation value table evaluator 127 that detects the motion vector MV corresponding to the reference block based on the correlation value (sum of absolute differences), and an output terminal 128 that outputs the motion vector MV detected by the evaluator 127; have. The evaluator 127 detects the position of the candidate block that generates the minimum correlation value as the motion vector MV.

  The operation of the motion vector detection circuit 111 shown in FIG. 6 will be described.

The image data Di input to the input terminal 122 is input in common to the plurality of difference absolute value calculators 124 _{-1 to} 124 _-N as pixel data Dr of the reference block. The image data Di input to the input terminal 122 is supplied to the frame memory 123 and stored as image data of the search frame.

Further, pixel data Dc _{−1 to} Dc _−N of a plurality of candidate blocks existing in the search range for the reference block are input from the frame memory 123 to the plurality of difference absolute value calculators 124 _{−1 to} 124 _−N , respectively. The pixel data Dc _{−1 to} Dc _−N of the candidate blocks are set to pixel positions corresponding to the pixel data Dr of the reference block, respectively. In the calculators 124 _{-1 to} 124 _-N , difference absolute values between the pixel data Dr and the pixel data Dc _{-1 to} Dc _-N are respectively calculated.

Further, the difference absolute value obtained by the calculation of a plurality of arithmetic units 124 _-1 to 124 _-N are respectively input to the plurality of adders 125 _-1 to 125 _-N. Furthermore, this plurality of adders 125 _-1 to 125 _-N, stored data stored in the plurality of storage areas 126 _-1 - 126 _-N semiconductor memory 126 are input. As will be described later, each of the plurality of storage areas 126 _{-1 to} 126 _-N includes a storage unit for a plurality of reference blocks. As described above, the storage data input to the plurality of adders 125 _{-1 to} 125 _-N is read from the storage unit corresponding to the reference block including the pixel data Dr.

In the plurality of adders 125 _{-1 to} 125 _-N , absolute difference values are added to the stored data. Then, each of the addition data obtained by the plurality of adders 125 _{−1 to} 125 _−N is written back to the plurality of storage areas 126 _{−1 to} 126 _−N of the semiconductor memory 126 as storage data. In this case, the data is written back to the storage unit corresponding to the reference block including the pixel data Dr.

Calculation of the difference absolute values in the plurality of difference absolute value calculator 124 _-1 to 124 _-N described above, calculation of the included adding in a plurality of adders 125 _-1 to 125 _-N, a plurality of storage areas 126 of the semiconductor memory 126 _- The writing back of the addition data to _{1 to} 126 _-N is performed for each reference block of the reference frame for the pixels in the block. Thereby, in each of the plurality of storage areas 126 _{-1 to} 126 _-N of the semiconductor memory 126, for each reference block, a correlation value (sum of absolute differences) corresponding to each of the plurality of candidate blocks existing in the search range for the reference block. Is obtained. The correlation value table evaluator 127 obtains the correlation value corresponding to each of the plurality of candidate blocks existing in the search range for each reference block obtained in the plurality of storage areas 126 _{−1 to} 126 _−N of the semiconductor memory 126. The data are sequentially read and supplied to the correlation value table evaluator 127. In the evaluator 127, the position of the candidate block that generates the minimum correlation value is detected as the motion vector MV for each reference block. As described above, the motion vector MV in each reference block detected by the evaluator 127 is sequentially output to the output terminal 128.

In the present embodiment, the plurality of adders 125 _{-1 to} 125 _-N and the semiconductor memory 126 are integrated, and the plurality of adders 125 _{-1 to} 125 _-N are configured in units of bits. Are added to the column pitch of the semiconductor memory 126.

FIG. 8 shows a detailed configuration of the adder 125 _-1 and the storage area 126 _-1 of the semiconductor memory 126 corresponding thereto. Although not described, the adders 125 _{-2 to} 125 _-N and the corresponding storage areas 126 _{-2 to} 126 _-N of the semiconductor memory 126 are configured in the same manner.

8, the storage area 126 _-1, n pieces in the column direction, the row direction X + 1 memory cells (Memory Cell) 130 are arranged in a matrix. In this case, a memory unit for one reference block is configured by n memory cells 130 in each row extending in the column direction.

  FIG. 9 shows a configuration example of the memory cell 130. The memory cell 130 has a two-port configuration having a first port for writing and reading and a second port dedicated for reading.

  A P-type MOS transistor Q1 and an N-type MOS transistor Q3, which are load elements, are connected in series between a power source and a ground to form a CMOS inverter 11, and a P-type MOS transistor Q2 and an N-type MOS transistor, which are load elements, A CMOS inverter 12 is formed by connecting the type MOS transistor Q4 in series between the power source and the ground. The outputs of the CMOS inverters 11 and 12, that is, the potentials of the storage nodes N1 and N2, are the inputs of the other CMOS inverters 12 and 11, that is, the gate inputs of the N-type MOS transistors Q4 and Q3.

  The storage node N1 of the CMOS inverter 11 is connected to the terminal 14 via an access transistor Q5 whose gate is connected to the terminal 13. On the other hand, the storage node N2 of the CMOS inverter 12 is connected to the terminal 15 via an access transistor Q6 whose gate is connected to the terminal 13. The word line WL is connected to the terminal 13, the bit line BL is connected to the terminal 14, and the bit line / BL (/ BL represents BL bar) is connected to the terminal 15.

  N-type MOS transistors Q7 and Q8 are connected in series, one end thereof is grounded, and the other end is connected to the terminal 16. The gate of transistor Q7 is connected to storage node N1, and the gate of transistor Q8 is connected to terminal 17. A read-only bit line BRL is connected to the terminal 16, and a read-only word line WRL is connected to the terminal 17.

  In such a memory cell 130, data “1” or “0” is stored in the memory cell portion formed by the pair of CMOS inverters 11 and 12. Then, read and write data transfer is performed between the memory cell portion and the bit lines BL and / BL via the access transistors Q5 and Q6. Further, read data transfer is performed between the memory cell portion and the read-only bit line BRL via the access transistor Q8.

  The configuration example of the memory cell 130 shown in FIG. 9 is based on an SRAM (Static Random Access Memory) cell, but other memory cells such as DRAM (Dynamic Random Access Memory), FeRAM (Ferro-electric), and the like. Random Access Memory (Random Access Memory), MRAM (Magnetic Random Access Memory) or the like may be used as a base.

Returning to FIG. 8, word lines WL _{0 to} WL _X and read-only word lines WRL _{0 to} WRL _X are arranged along the memory cells 130 in each row aligned in the column direction. As described above, the word lines WL _{0 to} WL _X are connected to the terminal 13 of the memory cell 130, and the read-only word lines WRL _{0 to} WRL _X are connected to the terminal 17 of the memory cell 130.

In addition, bit lines BL _{0 to} BL _n−1 , / BL ₀ to / BL _n−1 and read-only bit lines BRL _{0 to} BRL _n−1 are arranged along the memory cells 130 in each column aligned in the row direction. Has been. As described above, the bit lines BL _{0 to} BL _n−1 are connected to the terminal 14 of the memory cell 130, and the bit lines / BL ₀ to / BL _n−1 are connected to the terminal 15 of the memory cell 130, Lines BRL _{0 to} BRL _n−1 are connected to the terminal 16 of the memory cell 130.

It is necessary to precharge the bit lines BRL _{0 to} BRL _n-1 before entering the read mode using the read _- only bit lines BRL _{0 to} BRL _n-1 . For this purpose, the bit line BRL ₀ is connected to the power supply via the P-type MOS transistor Q41. A precharge control signal / φ _RPC (/ φ _RPC represents φ _RPC bar, and is an inverted version of the precharge control signal φ _RPC ) is input to the gate of the transistor Q41. The bit lines BRL _{1 to} BRL _n−1 are similarly configured.

Further, to each column memory cell 130 arranged in the row direction of the memory area 126 _-1 in response, the sense amplifier SA ₀ ~SA _n-1 are arranged. The sense amplifiers SA _{0 to} SA _n-1 are connected to bit lines BL _{0 to} BL _n-1 and / BL ₀ to / BL _n-1 , respectively. As a result, the bit line pairs BL ₀ , / BL _{0 to} BL _n−1 , / BL _n−1 and the sense amplifiers SA _{0 to} SA _{n− are transferred} from the memory cells 130 of each column aligned in the row direction of the storage area 126 _{−1. The} stored data MD _{0 to} MD _n-1 are read out via ₁ .

Here, the configuration of the sense amplifier SA ₀ will be described in detail.

Bit line BL ₀ is connected to the gate of N-type MOS transistor Q22 via P-type MOS transistor Q21. Bit line / BL ₀ is connected to the gate of N-type MOS transistor Q24 via P-type MOS transistor Q23. The sources of the transistors Q22 and Q24 are connected to each other, and the connection point is grounded via the N-type MOS transistor Q25. The gates of the transistors Q21 and Q23 are supplied with a read control signal / φ _R (/ φ _R represents φ _R bar, which is an inverted version of the read control signal φ _R ). An equalize control signal / φ _EQ (/ φ _EQ represents a φ _EQ bar and is an inverted version of the equalize control signal φ _EQ ) is input to the gate.

The drain of the transistor Q22 is connected to a power supply via a parallel circuit of P-type MOS transistors Q26 and Q27, and the drain of the transistor Q24 is connected to a power supply via a parallel circuit of P-type MOS transistors Q28 and Q29. The drain of transistor Q22 is connected to the gate of transistor Q29, and the drain of transistor Q24 is connected to the gate of transistor Q27. An equalize control signal / φ _EQ is input to the gates of transistors Q26 and Q28.

It is necessary to equalize (precharge) the bit line pair BL ₀ and / BL ₀ before entering the read mode. Therefore, the bit line BL ₀ is connected to the power supply via the P-type MOS transistor Q31, the bit line / BL ₀ is connected to the power supply via the P-type MOS transistor Q32, and the bit lines BL ₀ and / BL ₀ are connected to the power supply. It is connected via a type MOS transistor Q33. An equalize control signal / φ _EQ is input to the gates of transistors Q31 to Q33.

The configuration of the sense amplifiers SA _{2 to} SA _{n-1 is} the same as the configuration of the sense amplifier SA ₀ described above.

In addition, as described above, each of the n memory cells 130 in each row extending in the column direction constitutes a storage unit for one reference block. Before starting to sequentially write the addition data of the reference block in the predetermined storage unit, it is necessary to clear the storage data of the memory cell 130 constituting the predetermined storage unit. Therefore, “0” data is generated corresponding to each of the bit line pairs BL ₀ , / BL _{0 to} BL _n−1 , / BL _n−1 , and this data is supplied to the memory cell 130 as write data. It has a configuration to do.

That is, the bit line BL ₀ is grounded via the N-type MOS transistor Q51. A clear control signal φ _CLR is input to the gate of the transistor Q51. The bit line pairs BL ₁ , / BL _{1 to} BL _n−1 , / BL _n−1 are similarly configured.

The adder 125 _-1 includes n adders 140 _{0 to} 140 _n-1 for adding each of n bits, and these n adders 140 _{0 to} 140 _{n-1 are included.} It is arranged aligned to the pitch of the columns of the memory area 126 _-1.

Each of A-side input terminal of the adder 140 _{0-140 7-bit} data D ₀ to D ₇ of the 8-bit difference absolute value from the difference absolute value calculator 124 _-1 is input. Further, the input terminals on the A side of the adders 140 _{8 to} 140 _n−1 are grounded and “0” is input. On the other hand, the input terminal of each of the B-side of the adder 140 ₀ ~140 _n-1, the memory cells arranged in the row direction of the memory area 126 _-1 to correspond to each of these adding section 140 ₀ ~140 _n-1 From 130, storage data MD _{0 to} MD _n-1 read out via bit line pairs BL ₀ , / BL _{0 to} BL _n-1 , / BL _n-1 and sense amplifiers SA _{0 to} SA _n-1 are stored. Each is entered.

The non-inverting output terminal S of the adder 140 ₀ is connected to the gate of the N-type MOS transistor Q11. Then, the drain of the transistor Q11 is connected to the bit line / BL ₀ connected to the memory cell 130 arranged in the row direction corresponding to the adder 140 _0. On the other hand, the inverted output terminal / S of the addition section 140 ₀ (/ S represents the S bar) is connected to the gate of the N-type MOS transistor Q12. The drain of the transistor Q12 is connected to the bit line BL ₀ connected to the memory cell 130 arranged in the row direction corresponding to the adder 140 _0.

The sources of the transistors Q11 and Q12 are connected to each other, and the connection point is grounded via a series circuit of N-type MOS transistors Q13 and Q14. The write control signal φ _W is input to the gate of the transistor Q14, and the carry output C _{MSB of the} MSB (Most Significant Bit) obtained at the carry output terminal C _OUT of the adder 140 _n-1 is input to the gate of the transistor Q13. It is input via the inverter 141.

The configuration of the output terminals S and / S side of the adders 140 _{1 to} 140 _{n−1 is} the same as the configuration of the output terminal S and / S side of the adder 140 ₀ described above.

Further, the carry input terminal C _IN of the adder 140 ₀ is a state of being grounded, "0" is input. The carry output terminals C _OUT of the adders 140 _{0 to} 140 _n-2 are connected to the adders 140 _{1 to} 140 _n−1 , respectively. Thus, the adders 140 _{0 to} 140 _n−1 constitute an _n- bit adder.

Bit line / BL ₀ is grounded through N-type MOS transistors Q61 and Q62. Then, a clear control signal / φ _CLR (/ φ _CLR represents φ _CLR bar, which is an inverted version of the clear control signal φ _CLR ) is input to the gate of the transistor Q61, and the gate of the transistor 62 is input to the gate of the transistor Q61. The MSB carry output C _MSB obtained at the carry output terminal C _OUT of the adder 140 _n-1 is input.

The operation of the adder 125 _-1 and the storage area 126 _-1 shown in FIG. 8 will be described.

  First, the memory unit of one reference block is constituted by n memory cells 130 in each row extending in the column direction. The operation of clearing the memory data of the memory cells 130 constituting the predetermined memory unit will be described. .

When clearing the stored data of the memory cell 130 constituting a predetermined storage unit, the write control signal φ _W and the clear control signal φ _CLR are active, that is, “1”, the read control signal φ _R and the equalize control signal φ _EQ Is inactive, that is, “0”, and among the word lines WL _{0 to} WL _X , a word line corresponding to a predetermined storage unit is activated.

In this case, the clear control signal φ _CLR is activated and the transistor Q51 is turned on. Therefore, data “0” is generated, and this data is output to the bit lines BL _{0 to} BL _n−1 . Therefore, by activating a word line corresponding to a predetermined storage unit, data “0” is written in n memory cells 130 constituting the predetermined storage unit, and the stored data is cleared. .

Then, the stored data MD ₀ ~MD _n-1 stored in a predetermined storage unit, the 8-bit difference absolute value D ₀ to D _7, the adder 125 _-1 (the adding unit 140 ₁ to 140 _{n- The operation} of adding in ₁ ) and writing back the addition data AD _{0 to} AD _n−1 obtained by the adder 125 ₋₁ to the predetermined storage unit will be described.

To and has stored data MD ₀ to MD _n-1 that is stored in a predetermined storage unit, if Komu adding the difference absolute value D ₀ to D ₇ of the 8-bit first, equalization control signal phi _EQ is active, or "1 The write control signal φ _W , the read control signal φ _R and the clear control signal φ _CLR are inactive, that is, set to “0”, and the bit line pairs BL ₀ , / BL _{0 to} BL _n−1 , / BL _{n -1} equalization (precharge) is performed.

In this case, the bit line pair BL _0, with respect to / BL _0, all the equalization control signal phi _EQ is active transistor Q31~Q33 is turned on, the potential of the power supply to the bit line BL ₀ and the bit line / BL ₀ is When applied, the bit line BL ₀ and the bit line / BL ₀ have the same potential. The same applies to the other bit line pairs BL ₁ , / BL _{1 to} BL _n−1 , / BL _n−1 .

In this state where the bit line pairs BL ₀ , / BL _{0 to} BL _n−1 , / BL _n−1 are equalized, the read control signal φ _R is active, that is, “1”, and the write control signal φ _W , equalize control signal φ _EQ and clear control signal φ _CLR are inactive, that is, set to “0”, and among the word lines WL _{0 to} WL _X , a word line corresponding to a predetermined storage unit is activated. .

As a result, the storage data MD _{0 to} MD _n-1 of the _n memory cells 130 constituting the predetermined storage unit are respectively converted into bit line pairs BL ₀ , / BL _{0 to} BL _n-1 , / BL _n-1 and The signals are read out through the sense amplifiers SA _{0 to} SA _n−1 and input to the B-side input terminals of the adders 140 _{0 to} 140 _n−1 , respectively. Therefore, 8-bit difference absolute values D _{0 to} D ₇ are added to the storage data MD _{0 to} MD _n−1 stored in the predetermined storage unit.

Then, when the addition output in the adders 140 _{0 to} 140 _n−1 , that is, the addition data AD _{0 to} AD _n−1 becomes valid, the write control signal φ _W is active, that is, “1”, and the read control is performed. The signal φ _R , the equalize control signal φ _EQ and the clear control signal φ _CLR are inactive, that is, “0”, and among the word lines WL _{0 to} WL _X , a word line corresponding to a predetermined storage unit is activated. The

In this case, when the addition data S ₀ is “1” for the addition unit 140 ₀ , the transistor Q 11 is turned on, the transistor Q 12 is turned off, and “0” is output to the bit line / BL _0. since, among the n memory cells 130 which constitute the predetermined storage unit, in the memory cell 130 corresponding to the addition unit 140 _0, data of "1" is stored. On the other hand, when the addition data S ₀ is “0” for the addition unit 140 ₀ , the transistor Q 11 is turned off, the transistor Q 12 is turned on, and “0” is output to the bit line BL _0. of the n memory cells 130 which constitute the predetermined storage unit, a memory cell 130 corresponding to the addition unit 140 _0, data of "0" is stored.

The same applies to the other addition units 140 _{1 to} 140 _n−1 . As a result, the addition data AD _{0 to} AD _n−1 obtained by the adder 125 ₋₁ is written back to n memory cells 130 constituting a predetermined storage unit.

In addition, when overflow occurs in the adding operation, the carry output C _{MSB of the} MSB obtained at the carry output terminal C _OUT of the adder 140 _n-1 is “1”, so that the transistor Q13 is turned off, The addition data AD _{0 to} AD _n-1 is not written into the n memory cells 130 constituting the predetermined storage unit.

Instead, in this case, since the transistor Q61 is turned on and the transistor Q62 is also turned on, a signal of “0” is output to each of the bit lines / BL ₀ to / BL _n−1 . Therefore, data “1” is written in each of the n memory cells 130 constituting the predetermined storage unit. That is, the maximum value is stored in the predetermined storage unit.

  Next, an operation for reading out final addition data corresponding to a certain reference block stored in a predetermined storage unit, that is, a correlation value (difference absolute value sum) will be described.

First, the precharge control signal / φ _RPC is active, that is, “1”, and the read-only bit lines BRL _{0 to} BRL _n−1 are precharged. In this case, the transistor Q41 is turned on, and the power supply potential is applied to each of the read-only bit lines BRL _{0 to} BRL _n−1 .

In this state where the read-only bit lines BRL _{0 to} BRL _n−1 are precharged, the read-only word line corresponding to a predetermined storage unit is activated among the read-only word lines WRL _{0 to} WRL _X. Is done. Thus, the stored data Σ ₀ ~Σ _n-1 of the n memory cells 130 which constitute the predetermined storage section is obtained in a read-only bit line BRL ₀ ~BRL _n-1, respectively. Here, the stored data Σ _{0 to} Σ _n−1 constitute an _n- bit correlation value (difference absolute value sum).

As described above, in the present embodiment, the difference absolute values are accumulated using the adders 125 _{-1 to} 125 _-N and the semiconductor memory 126 for generating the correlation value table. , A correlation value (sum of absolute differences) corresponding to each of a plurality of candidate blocks existing in the search range with respect to the reference block is obtained, as compared with a conventional method using a register as a storage element, The occupied area can be reduced, and an increase in the size of the semiconductor chip can be prevented.

Further, the adders 125 _{-1 to} 125 _-N and the semiconductor memory 126 for generating the correlation value table are integrated, and a plurality of adders 140 _{0 to} 140 in bit units constituting the adders 125 _{-1 to} 125 _-N , respectively. since _n-1 are arranged aligned to the pitch of the columns of the semiconductor memory 126 (see FIG. 8), the adder 125 data AD ₀ summing from _-1 to 125 _-N to the semiconductor memory 126 to AD _n-1 And the storage data MD ₀ to MD _n-1 from the semiconductor memory 126 to the adders 125 _{-1 to} 125 _-N can be efficiently performed.

Further, the semiconductor memory 126 includes a first port for writing and reading provided in association with the plurality of addition units 140 _{0 to} 140 _n−1 and a second port dedicated for reading. Yes (see FIG. 8), the correlation values Σ _{0 to} Σ _n−1 corresponding to a certain reference block from the semiconductor memory 126 can be read independently from the addition.

  Further, when clearing the stored data of the memory cell 130 that constitutes a predetermined storage portion of the semiconductor memory 126, the transistor Q51 is turned on to generate “0” data for clearing, and this data is stored in the memory cell 130. The semiconductor memory 126 is supplied as write data, and the semiconductor memory 126 can be easily cleared without inputting data for clearing from the outside.

In addition, when the calculation results by the plurality of adders 140 _{0 to} 140 _n−1 constituting the adders 125 _{−1 to} 125 _−N respectively overflow, a semiconductor corresponding to the plurality of adders 140 _{0 to} 140 _n−1. The maximum value is stored (set) in a predetermined storage unit of the memory 126, and an erroneously small value is stored as a correlation value in the predetermined storage unit, thereby preventing a motion vector detection error from occurring.

In the above embodiment, in the storage areas 126 _{-1 to} 126 _-N of the semiconductor memory 126, the bit lines BL _{0 to} BL _n-1 are grounded via the transistor Q51, and a clear control signal is supplied to the gate of the transistor Q51. / φ _CLR is input, and when the clear control signal φ _CLR is activated, “0” data is written to n memory cells 130 constituting a predetermined storage unit and is cleared ( (See FIG. 8).

Here, as shown by a broken line in FIG. 8, the bit lines / BL ₀ to / BL _n-1 are grounded via the transistor Q52, and the clear control signal / φ _CLR is input to the gate of the transistor Q52. In this case, when the clear control signal φ _CLR is activated, data “1” is generated by the transistor Q52, and data “1” is written to n memory cells 130 constituting a predetermined storage unit.

Therefore, transistors Q51 and Q52 are provided corresponding to the bit line pairs BL ₀ , / BL _{0 to} BL _n−1 , / BL _n−1 , respectively, and either of them is selectively connected to the bit line. When the clear control signal φ _CLR is activated, predetermined data may be preset in the n memory cells 130 constituting the predetermined storage unit. By devising this preset data, for example, a specific motion vector such as (0, 0) can be easily detected in a flat pattern portion. The preset setting may be determined in advance at the time of designing the semiconductor device. Therefore, it is assumed that the preset is set by a contact layer program or the like.

Also, in the above-described embodiment, the adder 125 _-1 to 125 _-N and it is obtained by integrating the semiconductor memory 126 of the correlation value table generating further difference absolute value calculator 124 _-1 to 124 _{- N} and the correlation value table evaluator 127 may also be integrated.

  In the above embodiment, the memory cell 130 has a 2-port configuration (see FIG. 9). However, the memory cell may not have a 2-port configuration, and the semiconductor memory 126 as a whole has a 2-port configuration. May be. Further, even if the semiconductor memory 126 does not have a two-port configuration, for example, correlation values (table data) are read during a blanking period in a video signal, or a plurality of identical functional blocks are interleaved between fields or frames. For example, the addition and the reading of the correlation value may be performed in different periods in the same port.

In the above-described embodiment, the addition using the adders 125 _{-1 to} 125 _-N and the semiconductor memory 126 is applied to the addition of the absolute difference value in the motion vector search. It can also be applied to similar additions in processing.

In the above-described embodiment, the adders 125 _{-1 to} 125 _-N and the semiconductor memory 126 for generating the correlation value table are integrated, but other subtracters, multipliers, dividers, etc. A unit in which an arithmetic unit and a semiconductor memory are integrated can be similarly configured, and data can be exchanged efficiently between the arithmetic unit and the semiconductor memory.

  In the above-described embodiment, the motion vector detection circuit 111 is applied to the motion compensated predictive coding apparatus 100. However, it is needless to say that the present invention can be similarly applied to other apparatuses using motion vectors.

  In the above-described embodiment, the motion vector is detected by the block matching method. However, the present invention is not limited to the block matching method, and other pixel value matching such as a representative point block matching method. It can also be applied to methods based on.

  The present invention is suitable for application to a motion vector detection circuit.

It is a block diagram which shows the structure of the motion compensation prediction encoding apparatus as embodiment. It is a figure for demonstrating the block matching method for a motion detection. It is a figure for demonstrating the block matching method for a motion detection. It is a figure for demonstrating the block matching method for a motion detection. It is a figure for demonstrating the block matching method for a motion detection. It is a block diagram which shows the structure of a motion vector detection circuit. It is a figure for demonstrating 1 to N matching calculation with one reference pixel and N search range pixels. It is a figure which shows the structure which integrated the semiconductor memory and the adder. It is a figure which shows the structure of a memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Motion compensation prediction encoding apparatus, 101 ... Input terminal, 102 ... Subtractor, 103 ... DCT circuit, 104 ... Quantization circuit, 105 ... Output terminal, 106 ... Inverse quantization circuit, 107 ... Inverse DCT circuit, 108 ... Adder, 109 ... Frame memory, 110 ... Motion compensation circuit, 111 ... Motion vector detection circuit, 121 ... Controller , 122 ... input terminal, 123 ... frame memory, 124 _{-1 to} 124 _-N ... difference absolute value calculator, 125 _{-1 to} 125 _-N ... adder, 126 ... correlation value Semiconductor memory for table, 126 _{-1 to} 126 _-N ... storage area, 127 ... correlation value table evaluator, 128 ... output terminal, 130 ... memory cell, 140 _{0 to} 140 _n-1 ... Adding unit

Claims (6)

An input means for inputting data;
Multiple storage areas;
Arithmetic means for reading out the data stored in the storage area, and writing back the data obtained by performing a predetermined arithmetic operation using the read data and data input by the input means to the storage area;
A reading means for reading data stored in the storage area,
At least the storage area and the arithmetic means are formed integrally on a semiconductor chip ,
The plurality of storage areas are composed of memory cells arranged in a matrix,
The arithmetic means comprises a plurality of arithmetic units that perform arithmetic operations in bit units,
The plurality of arithmetic units are semiconductor memories arranged in alignment with the column pitch of the memory cells . It said plurality of operation portions, addition, subtraction, multiplication, and a semiconductor memory according to at least one operation in the row cormorants請 Motomeko one of division. Generates data for clearing the storage area, the semiconductor memory according to 請 Motomeko 1 Ru further comprising a means for clearing the storage area by said data. Generates data for presetting the storage area, the semiconductor memory according to 請 Motomeko 1 Ru further comprising means for presetting the storage area by said data. If the calculation result by the plurality of summing unit constituting the operation means is an overflow, according to 請 Motomeko 1 Ru further comprising means for setting a maximum value in a predetermined area of the storage area corresponding to the plurality of the adder Semiconductor memory. A device for processing signals,
An input means for inputting the signal, a plurality of storage areas, a signal stored in the storage area, and a signal obtained by performing a predetermined calculation using the read signal and the signal input by the input means. Computation means for writing back to the storage area and read means for reading out signals stored in the storage area, and at least the storage area and the computation means are formed integrally on a semiconductor chip. ,
The plurality of storage areas are composed of memory cells arranged in a matrix,
The arithmetic means comprises a plurality of arithmetic units that perform arithmetic operations in bit units,
It said plurality of operation portions, signal processing apparatus Ru comprising a semiconductor memory which are arranged aligned to the pitch of the columns of the memory cells.

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