JP4536310B2 - Motion vector detection device and motion compensated prediction encoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a motion vector detection device.andMotion compensated predictive coding deviceIn placeRelated. Specifically, the absolute value of the difference is accumulated using an adder and a semiconductor memory for generating a correlation value table, and the correlation corresponding to each of a plurality of candidate blocks existing in the search range for the reference block is stored in this semiconductor memory. The present invention relates to a motion vector detection device and a motion compensation predictive coding device that can prevent an increase in size of a semiconductor chip by obtaining a value.
[0002]
[Prior art]
In image processing, motion vector detection is one of important elements, and a typical method is a block matching method. This is to evaluate the correlation between a certain pixel block (reference block) constituting a part of a certain frame and the same shape pixel block (candidate block) at various positions in a frame at different times. A relative positional shift with the highest candidate block is regarded as a motion vector in the reference block.
[0003]
Here, an area that assumes a candidate block is a search range. For the evaluation of the correlation, the sum total of each pixel in the block of the absolute difference value of the pixel data between the corresponding pixels of the reference block and the candidate block, that is, the sum of absolute differences is often used. A sum of absolute differences (correlation values) corresponding to the number of pixels in the search range is obtained for one reference block, which is a correlation value table. In the correlation value table, the place where the sum of absolute differences is smallest, that is, where the correlation is high is regarded as a motion vector in units of pixels. In practice, this processing has a very heavy calculation load, and various measures are taken with respect to the shape and size of the block, the pixel position used for the calculation, and the like.
[0004]
[Problems to be solved by the invention]
In conventional block matching, a PE (Processing Element) in which a difference absolute value arithmetic unit and a plurality of registers as storage elements are combined, or an adder is further combined is often used. By flowing data between PEs arranged in an array in parallel and in a pipeline, a plurality of difference absolute value sums are calculated in parallel, or after obtaining the difference absolute values, the sum is summed by an adder, and the difference absolute value sum ( A collection of correlation values), that is, a correlation value table is generated.
[0005]
In this case, since a register is used as a storage element, the number of constituent elements is large and the occupation area is widened. Further, since each PE has a plurality of (for example, two to three) registers, the occupation area is widened as a whole PE. . Therefore, there is a problem that the semiconductor chip is increased in size.
Therefore, an object of the present invention is to provide a motion vector detection device and the like that can prevent an increase in the size of a semiconductor chip.
[0006]
[Means for Solving the Problems]
  The motion vector detection device according to the present invention is a motion vector detection device that detects a motion vector from a reference frame and a search frame that move back and forth in time, and commonly inputs pixel data of a reference block extracted from the reference frame. In addition, pixel data of a plurality of candidate blocks existing in the search range for the reference block, which are extracted from the search frame, are respectively input, and an absolute difference value between the pixel data of the reference block and the pixel data of the candidate block is calculated. A plurality of difference absolute value calculators, a semiconductor memory for generating a correlation value table having a plurality of adders and a plurality of storage areas, and a difference absolute value obtained by calculating with the plurality of difference absolute value calculators. Each of the storage data stored in a plurality of storage areas of the semiconductor memory, Adding a plurality of adders and repeatedly storing the addition data obtained by the plurality of adders in a plurality of storage areas of the semiconductor memory a predetermined number of times, A controller for controlling a region to obtain a correlation value corresponding to each of the plurality of candidate blocks, and a correlation value corresponding to each of the plurality of candidate blocks obtained in the plurality of storage regions of the semiconductor memory. And a correlation value table evaluator for detecting a motion vector corresponding to the reference block, and the adder reads a value stored in the storage area and calculates the difference absolute value calculator to the read value. Add the absolute value of the difference obtained byIncludedWrite back the stored data to the above storage areaHowever, when the result of the addition operation overflows, the maximum value is set in the storage area of the semiconductor memory corresponding to the adder.
[0007]
  In the present invention, the plurality of difference absolute value calculators calculate the difference absolute values of the pixel data of the plurality of candidate blocks and the pixel data of the reference block. The plurality of adders read stored data stored in the plurality of storage areas of the semiconductor memory for generating the correlation value table. Thereafter, the plurality of adders add each of the difference absolute values obtained by the calculation by the plurality of difference absolute value calculators to the read storage data. Then, each of the addition data obtained by the plurality of adders is stored in a plurality of storage areas of the semiconductor memory.Here, the adder sets a maximum value in the storage area of the semiconductor memory corresponding to the adder when the result of the addition operation overflows. Thereby, it is possible to prevent a motion vector detection error in which an erroneously small value is stored as a correlation value in the storage area of the semiconductor memory.
[0008]
The above-described difference absolute value calculation, addition calculation, and storage operation are repeated a predetermined number of times, for example, in the case of the block matching method, a number of times equal to the number of pixel data constituting the reference block. Correlation values (sum of absolute differences) corresponding to each of a plurality of candidate blocks existing in the search range for the reference block are obtained. Then, the correlation value table evaluator detects a motion vector corresponding to the reference block based on the correlation value corresponding to each of the plurality of candidate blocks obtained in the semiconductor memory in this way.
[0009]
Thus, by using a semiconductor memory that is smaller and denser than the register as the memory element, the occupied area can be reduced, and the increase in size of the semiconductor chip can be prevented.
[0010]
  It should be noted that at least a plurality of adders and semiconductor memories are integrated, and a plurality of adders in bit units constituting the adder are provided.,Semiconductor memoryMemory cells arranged in a matrixThus, the addition data is supplied from the adder to the semiconductor memory and the storage data is supplied from the semiconductor memory to the adder efficiently.
[0011]
Further, since the semiconductor memory has a first port for writing and reading and a second port dedicated for reading provided in association with the above-described plurality of addition units, data stored in the semiconductor memory, for example, correlation Reading of values can be performed independently of adding.
[0012]
In addition, by generating data for clearing or presetting the semiconductor memory and clearing or presetting the semiconductor memory with this data, the semiconductor memory can be easily cleared without inputting data for clearing or presetting from the outside. Or, it can be preset, and by devising data for presetting, for example, a specific motion vector such as (0, 0) can be easily detected in a flat picture portion.
[0013]
In addition, when the calculation result by a plurality of adders constituting the adder overflows, the maximum value is set in a predetermined area of the semiconductor memory corresponding to the plurality of adders, thereby erroneously setting the predetermined area of the semiconductor memory. It is possible to prevent a small value from being stored as a correlation value.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a motion compensated prediction encoding apparatus 100 as an embodiment.
The encoding apparatus 100 has an input terminal 101 for inputting image data (frame data constituting a moving image) Di, image data Di supplied to the input terminal 101, and prediction supplied from a motion compensation circuit 110 described later. A subtractor 102 that calculates a difference with image data, a DCT circuit 103 that performs DCT (discrete cosine transform) on the difference data obtained by the subtractor 102, and a DCT coefficient obtained by the DCT circuit 103 A quantization circuit 104 that performs quantization and an output terminal 105 that outputs encoded data Do obtained by the quantization circuit 104 are provided.
[0015]
The encoding apparatus 100 also performs an inverse quantization circuit 106 that performs inverse quantization on the encoded data Do obtained by the quantization circuit 104, and performs inverse DCT on the output data of the inverse quantization circuit 106. An inverse DCT circuit 107 that obtains difference data, and an adder 108 that adds the difference data obtained by the inverse DCT circuit 107 and the predicted image data obtained by the motion compensation circuit 110 to restore the original image data; A frame memory 109 for storing the image data restored by the adder 108.
[0016]
Also, the encoding apparatus 100 reads the image data stored in the frame memory 109, performs motion compensation based on a motion vector MV from a motion vector detection circuit 111 described later, and then performs the subtractor 102 and the addition as described above. A motion compensation circuit 110 that supplies the image data 108 as predicted image data, and a motion vector detection circuit 111 that detects the motion vector MV of the image data Di supplied to the input terminal 101 and supplies the motion vector MV to the motion compensation circuit 110. Yes.
[0017]
The operation of the motion compensated predictive coding apparatus 100 shown in FIG. 1 will be described.
Image data Di input to the input terminal 101 is supplied to the subtractor 102 and the motion vector detection circuit 111. The subtractor 102 calculates the difference between the image data Di and the predicted image data supplied from the motion compensation circuit 110.
[0018]
The difference data obtained by the subtracter 102 is supplied to the DCT circuit 103 and subjected to discrete cosine transform. The DCT coefficient obtained by the DCT circuit 103 is supplied to the quantization circuit 104 and quantized. The encoded data Do obtained by the quantization circuit 104 is output to the output terminal 105.
[0019]
Also, the encoded data Do obtained by the quantization circuit 104 is supplied to the inverse quantization circuit 106 and inversely quantized, and the output data of the inverse quantization circuit 106 is further supplied to the inverse DCT circuit 107 to perform inverse DCT. The difference data is restored. The difference data and the prediction data from the motion compensation circuit 110 are added by the adder 108 to restore the original image data, and the restored image data is stored in the frame memory 109.
[0020]
In the motion compensation circuit 110, in a certain frame, image data stored in the frame memory 109 is read in the previous frame, and motion compensation is performed based on the motion vector MV from the motion vector detection circuit 111. Predictive image data is obtained. As described above, the predicted image data is supplied to the subtractor 102 to obtain difference data, and is also supplied to the adder 108 to restore the image data.
[0021]
Next, details of the motion vector detection circuit 111 will be described.
In the motion vector detection circuit 111, a motion vector is detected by a block matching method. As shown in FIG. 2, the motion vector is obtained by moving the candidate block of the search frame within a predetermined search range and detecting the candidate block that most closely matches the reference block of the reference frame. is there.
[0022]
In the block matching method, as shown in FIG. 3A, one image, for example, one frame image of horizontal H pixels and vertical V lines is subdivided into blocks of P pixels × Q lines as shown in FIG. 4B. . In the example of FIG. 3B, P = 5 and Q = 5. c is the central pixel position of the block.
[0023]
4A to 4C show the positional relationship between a reference block having c as the central pixel and a candidate block having c ′ as the center. The reference block having c as the central pixel is a reference block of interest in the reference frame, and the candidate block of the search frame that matches the reference block is located at the position of the block centering on c ′ in the search frame. In the block matching method, a motion vector is detected by finding a candidate block that most closely matches a reference block within a search range.
[0024]
In the case of FIG. 4A, motion vectors of +1 pixel in the horizontal direction and +1 line in the vertical direction, that is, (+1, +1) are detected. In FIG. 4B, a motion vector MV of (+3, +3) is detected, and in FIG. 4C, a motion vector of (+2, −1) is detected. The motion vector is obtained for each reference block of the reference frame.
[0025]
Assuming that the motion vector search range is ± S pixels in the horizontal direction and ± T lines in the vertical direction, the reference block has a center c ′ at a position shifted ± S horizontally and ± T vertically from the center c. Need to be compared to a candidate block with
[0026]
FIG. 5 shows that when the position of the center c of a reference block having a reference frame is R, it is necessary to compare with (2S + 1) × (2T + 1) candidate blocks of the search frame to be compared. That is, all candidate blocks in which c ′ exists at the position of the first grid in FIG. 5 are comparison targets. FIG. 5 shows an example in which S = 4 and T = 3.
[0027]
Detecting the minimum value among evaluation values obtained by comparison within the search range (that is, sum of absolute values of frame differences, sum of squares of frame differences, or sum of absolute values of frame differences, etc.) Thus, a motion vector is detected. The search range in FIG. 5 is an area where the center of the candidate block is located, and the size of the search range including the entire candidate block is (2S + P) × (2T + Q).
[0028]
FIG. 6 shows the configuration of the motion vector detection circuit 111.
The motion vector detection circuit 111 includes a controller 121 that controls the operation of the entire circuit, an input terminal 122 that receives image data Di of a reference frame, and a frame memory 123 that accumulates the image data Di as image data of a search frame. And have. Operations such as writing and reading of the frame memory 123 are controlled by the controller 121.
[0029]
In addition, the motion vector detection circuit 111 includes a plurality of difference absolute value calculators 124._-1~ 124_-Nhave. Here, N is the number of a plurality of candidate blocks existing in the search range for one reference pixel in a certain reference block. Multiple computing units 124_-1~ 124_-NThe pixel data constituting the image data Di inputted to the input terminal 122 is commonly inputted as the pixel data Dr of the reference block, and the pixel data Dc of a plurality of candidate blocks existing in the search range for the reference block._-1~ Dc_-NAre inputted, and the absolute difference between the pixel data of the reference block and the pixel data of the candidate block is calculated.
[0030]
In this case, the arithmetic unit 124_-1~ 124_-NIn FIG. 7, a one-to-N matching operation between one reference pixel and N search range pixels is performed. Here, the position of the search range pixel with respect to this reference pixel changes according to the position of the reference pixel in the reference block. For example, the hatched positions indicate the positions of N search range pixels with respect to one pixel at the upper left of the reference block.
[0031]
The motion vector detection circuit 111 includes a plurality of adders 125._-1~ 125_-NAnd a plurality of storage areas 126_-1~ 126_-NAnd a semiconductor memory 126 for generating a correlation value table. Multiple adders 125_-1~ 125_-NIs a plurality of computing units 124._-1~ 124_-NThe difference absolute values obtained by the calculation are input, and a plurality of storage areas 126 of the semiconductor memory 126 are input._-1~ 126_-NEach of the stored data stored in is input and the absolute difference value is added to the stored data.
[0032]
Thus, the plurality of adders 125_-1~ 125_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NIs written back as stored data. The writing and reading operations of the semiconductor memory 126 are controlled by the controller 121.
[0033]
For each reference block of the reference frame, the controller 121 calculates a difference absolute value in the plurality of difference absolute value calculators 124-1 to 124-N, and adds a plurality of adders 125._-1~ 125_-NOf addition in the plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NThe addition data is written back to the pixels in the block, and a plurality of storage areas 126 in the semiconductor memory 126 are written._-1~ 126_-NIn addition, control is performed so that correlation values corresponding to the plurality of candidate blocks existing in the search range for each reference block are obtained.
[0034]
The image data Di input to the input terminal 122 is a series of pixel data of each line. Therefore, the arithmetic unit 124_-1~ 124_-NThe pixel data Dr of the reference block input to is not continuous for each reference block, but is a predetermined number of pixel data of a plurality of reference blocks. For example, when the reference block is composed of P pixels × Q lines as shown in FIG. 3B, the pixel data of a certain line constitutes a different reference block for each P pixel. Focusing on a reference block, the pixel data of the reference block are all input only after the pixel data of the Q line is input.
[0035]
Thus, the arithmetic unit 124_-1~ 124_-NSince the pixel data Dr of the reference block input to the reference block is a predetermined number of pieces of pixel data of the plurality of reference blocks, the plurality of difference absolute value calculators 124 described above._-1~ 124_-NOf the absolute difference value at, a plurality of adders 125_-1~ 125_-NOf addition in the plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NThe addition data is written back in a time-sharing manner corresponding to the plurality of reference blocks. Then, each time the pixel data of the Q line is input, the process proceeds to processing of a plurality of new reference blocks.
[0036]
The motion vector detection circuit 111 also has a plurality of storage areas 126 in the semiconductor memory 126 for each reference block._-1~ 126_-NA correlation value table evaluator that detects the motion vector MV corresponding to the reference block based on the correlation value (sum of absolute differences) corresponding to each of the plurality of candidate blocks existing in the search range for the reference block obtained in 127 and an output terminal 128 for outputting the motion vector MV detected by the evaluator 127. The evaluator 127 detects the position of the candidate block that generates the minimum correlation value as the motion vector MV.
[0037]
The operation of the motion vector detection circuit 111 shown in FIG. 6 will be described.
The image data Di input to the input terminal 122 is a plurality of absolute difference calculators 124 as pixel data Dr of the reference block._-1~ 124_-NAre input in common. The image data Di input to the input terminal 122 is supplied to the frame memory 123 and stored as image data of the search frame.
[0038]
Also, pixel data Dc of a plurality of candidate blocks existing in the search range for the reference block from the frame memory 123._-1~ Dc_-NIs a plurality of absolute difference calculators 124_-1~ 124_-NRespectively. Pixel data Dc of this candidate block_-1~ Dc_-NAre pixel positions corresponding to the pixel data Dr of the reference block. Calculator 124_-1~ 124_-NThen, the pixel data Dr and the pixel data Dc_-1~ Dc_-NThe difference absolute value is calculated.
[0039]
Also, a plurality of computing units 124_-1~ 124_-NThe difference absolute value obtained by the calculation in step S1 is a plurality of adders 125._-1~ 125_-NIs input. The plurality of adders 125_-1~ 125_-NIncludes a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NThe stored data stored in is input respectively. As will be described later, a plurality of storage areas 126_-1~ 126_-NEach includes a storage unit for a plurality of reference blocks. As described above, the plurality of adders 125_-1~ 125_-NThe storage data input to is read from the storage unit corresponding to the reference block including the pixel data Dr.
[0040]
Multiple adders 125_-1~ 125_-NThen, the absolute difference value is added to each stored data. In this way, the plurality of adders 125_-1~ 125_-NEach of the addition data obtained in the above is stored in a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NIs written back as stored data. In this case, the data is written back to the storage unit corresponding to the reference block including the pixel data Dr.
[0041]
The plurality of difference absolute value calculators 124 described above._-1~ 124_-NOf the absolute difference value at, a plurality of adders 125_-1~ 125_-NOf addition in the plurality of storage areas 126 of the semiconductor memory 126_-1~ 126_-NThe addition data is written back to each reference block of the reference frame by the number of pixels in the block. Thereby, a plurality of storage areas 126 of the semiconductor memory 126 are obtained._-1~ 126_-NFor each reference block, a correlation value (sum of absolute differences) corresponding to each of a plurality of candidate blocks existing in the search range for the reference block is obtained. The correlation value table evaluator 127 includes a plurality of storage areas 126 of the semiconductor memory 126._-1~ 126_-NThe correlation values corresponding to each of the plurality of candidate blocks existing in the search range for each reference block are sequentially read out and supplied to the correlation value table evaluator 127. In the evaluator 127, the position of the candidate block that generates the minimum correlation value is detected as the motion vector MV for each reference block. As described above, the motion vector MV in each reference block detected by the evaluator 127 is sequentially output to the output terminal 128.
[0042]
In this embodiment, a plurality of adders 125 are used._-1~ 125_-NAnd the semiconductor memory 126 are integrated, and a plurality of adders 125 are integrated._-1~ 125_-NThe plurality of adders in units of bits constituting the memory are arranged in alignment with the column pitch of the semiconductor memory 126.
[0043]
FIG. 8 shows the adder 125_-1And the storage area 126 of the semiconductor memory 126 corresponding thereto_-1The detailed structure of the part is shown. Although not described, the adder 125_-2~ 125_-NAnd the storage area 126 of the semiconductor memory 126 corresponding thereto_-2~ 126_-NThis part is similarly configured.
[0044]
In FIG. 8, the storage area 126_-1In this, n memory cells 130 in the column direction and X + 1 memory cells 130 in the row direction are arranged in a matrix. In this case, a memory unit for one reference block is configured by n memory cells 130 in each row extending in the column direction.
[0045]
FIG. 9 shows a configuration example of the memory cell 130. The memory cell 130 has a two-port configuration having a first port for writing and reading and a second port dedicated for reading.
[0046]
A P-type MOS transistor Q1 and an N-type MOS transistor Q3, which are load elements, are connected in series between a power source and a ground to form a CMOS inverter 11, and a P-type MOS transistor Q2 and an N-type MOS transistor, which are load elements, A CMOS inverter 12 is formed by connecting the type MOS transistor Q4 in series between the power source and the ground. The outputs of the CMOS inverters 11 and 12, that is, the potentials of the storage nodes N1 and N2, are the inputs of the other CMOS inverters 12 and 11, that is, the gate inputs of the N-type MOS transistors Q4 and Q3.
[0047]
The storage node N1 of the CMOS inverter 11 is connected to the terminal 14 via an access transistor Q5 whose gate is connected to the terminal 13. On the other hand, the storage node N2 of the CMOS inverter 12 is connected to the terminal 15 via an access transistor Q6 whose gate is connected to the terminal 13. The word line WL is connected to the terminal 13, the bit line BL is connected to the terminal 14, and the bit line / BL (/ BL represents BL bar) is connected to the terminal 15.
[0048]
N-type MOS transistors Q7 and Q8 are connected in series, one end thereof is grounded, and the other end is connected to the terminal 16. The gate of transistor Q7 is connected to storage node N1, and the gate of transistor Q8 is connected to terminal 17. A read-only bit line BRL is connected to the terminal 16, and a read-only word line WRL is connected to the terminal 17.
[0049]
In such a memory cell 130, data “1” or “0” is stored in the memory cell portion formed by the pair of CMOS inverters 11 and 12. Then, read and write data transfer is performed between the memory cell portion and the bit lines BL and / BL via the access transistors Q5 and Q6. Further, read data transfer is performed between the memory cell portion and the read-only bit line BRL via the access transistor Q8.
[0050]
The configuration example of the memory cell 130 shown in FIG. 9 is based on an SRAM (Static Random Access Memory) cell, but other memory cells such as a DRAM (Dynamic Random Access Memory), an FeRAM (Ferro-electric), and the like. Random Access Memory (Random Access Memory), MRAM (Magnetic Random Access Memory) or the like may be used as a base.
[0051]
Returning to FIG. 8, along the memory cells 130 in each row aligned in the column direction, the word line WL₀~ WL_X, And read-only word line WRL₀~ WRL_XIs arranged. As described above, the word line WL₀~ WL_XAre connected to the terminal 13 of the memory cell 130 and read-only word line WRL.₀~ WRL_XIs connected to the terminal 17 of the memory cell 130.
[0052]
In addition, the bit lines BL are arranged along the memory cells 130 in each column aligned in the row direction.₀~ BL_n-1, / BL₀~ / BL_n-1, And read-only bit line BRL₀~ BRL_n-1Is arranged. As described above, the bit line BL₀~ BL_n-1Is connected to the terminal 14 of the memory cell 130 and the bit line / BL₀~ / BL_n-1Are connected to the terminal 15 of the memory cell 130 and read-only bit line BRL.₀~ BRL_n-1Is connected to the terminal 16 of the memory cell 130.
[0053]
This read-only bit line BRL₀~ BRL_n-1Before entering the read mode by the bit line BRL₀~ BRL_n-1Must be precharged. Therefore, the bit line BRL₀Are connected to a power source via a P-type MOS transistor Q41. The gate of the transistor Q41 has a precharge control signal / φ_RPC(/ Φ_RPCIs φ_RPCRepresents the precharge control signal φ_RPCIs inverted). Bit line BRL₁~ BRL_n-1It is configured in the same way.
[0054]
In addition, the memory area 126_-1Sense amplifier SA corresponding to each column of memory cells 130 arranged in the row direction.₀~ SA_n-1Is arranged. Each sense amplifier SA₀~ SA_n-1Are bit lines BL respectively.₀~ BL_n-1, / BL₀~ / BL_n-1It is connected to the. As a result, the storage area 126_-1Bit line pair BL from memory cells 130 in each column aligned in the row direction₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1Storage data MD via₀~ MD_n-1Is read out.
[0055]
Here, the sense amplifier SA₀Details of the configuration of this part will be described.
Bit line BL₀Is connected to the gate of the N-type MOS transistor Q22 via the P-type MOS transistor Q21. Also, bit line / BL₀Is connected to the gate of the N-type MOS transistor Q24 via the P-type MOS transistor Q23. The sources of the transistors Q22 and Q24 are connected to each other, and the connection point is grounded via the N-type MOS transistor Q25. The gates of the transistors Q21 and Q23 are connected to the read control signal / φ._R(/ Φ_RIs φ_RRepresents the bar, and the read control signal φ_RAnd the equalization control signal / φ is applied to the gate of the transistor Q25._EQ(/ Φ_EQIs φ_EQRepresents the equalization control signal φ_EQIs inverted).
[0056]
The drain of the transistor Q22 is connected to a power supply via a parallel circuit of P-type MOS transistors Q26 and Q27, and the drain of the transistor Q24 is connected to a power supply via a parallel circuit of P-type MOS transistors Q28 and Q29. The drain of transistor Q22 is connected to the gate of transistor Q29, and the drain of transistor Q24 is connected to the gate of transistor Q27. The equalization control signal / φ is applied to the gates of the transistors Q26 and Q28._EQIs entered.
[0057]
Before entering the read mode, the bit line pair BL₀, / BL₀Must be equalized (precharged). Therefore, the bit line BL₀Is connected to the power supply via a P-type MOS transistor Q31, and the bit line / BL₀Is connected to the power supply via a P-type MOS transistor Q32 and the bit line BL₀, / BL₀Are connected via a P-type MOS transistor Q33. The equalization control signal / φ is applied to the gates of the transistors Q31 to Q33._EQIs entered.
Sense amplifier SA₂~ SA_n-1The configuration of this part is also the above-described sense amplifier SA.₀This is the same as the configuration of the part.
[0058]
Further, as described above, each of the n memory cells 130 in each row extending in the column direction forms a storage unit for one reference block. Before starting to sequentially write the addition data of the reference block in the predetermined storage unit, it is necessary to clear the storage data of the memory cell 130 constituting the predetermined storage unit. Therefore, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Corresponding to each of the above, data “0” is generated, and this data is supplied to the memory cell 130 as write data.
[0059]
That is, the bit line BL₀Are grounded via an N-type MOS transistor Q51. The clear control signal φ is supplied to the gate of the transistor Q51._CLRIs entered. Bit line pair BL₁, / BL₁~ BL_n-1, / BL_n-1This part is also configured in the same manner.
[0060]
Also, adder 125_-1Are n adders 140 for adding each bit of n bits.₀~ 140_n-1These n adders 140₀~ 140_n-1Is the memory area 126_-1It is arranged in line with the pitch of the column.
[0061]
Adder 140₀~ 140₇The difference absolute value calculator 124 is connected to each A-side input terminal._-18-bit difference absolute value bit data from₀~ D₇Is entered. Also, the adding unit 140₈~ 140_n-1Each A side input terminal is grounded, and "0" is input. Meanwhile, the adding unit 140₀~ 140_n-1These adders 140 are connected to the input terminals on the B side.₀~ 140_n-1Corresponding to each of the storage areas 126_-1From the memory cells 130 arranged in the row direction of the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1Data MD read via₀~ MD_n-1Are entered respectively.
[0062]
Adder 140₀The non-inverting output terminal S is connected to the gate of the N-type MOS transistor Q11. The drain of the transistor Q11 is connected to the adding unit 140.₀Corresponding to the bit lines / BL connected to the memory cells 130 arranged in the row direction.₀Connected to. On the other hand, the adding unit 140₀Inverted output terminal / S (/ S represents S bar) is connected to the gate of N-type MOS transistor Q12. The drain of the transistor Q12 is connected to the adding unit 140.₀Corresponding to the bit line BL connected to the memory cells 130 arranged in the row direction.₀Connected to.
[0063]
The sources of the transistors Q11 and Q12 are connected to each other, and the connection point is grounded via a series circuit of N-type MOS transistors Q13 and Q14. A write control signal φ is applied to the gate of the transistor Q14._WIs added to the gate of the transistor Q13._n-1Carry output terminal C_OUTMSB (Most Significant Bit) carry output C_MSBIs input via the inverter 141.
Adder 140₁~ 140_n-1The configuration of the output terminals S, / S side of the adder 140 is also described above.₀This is the same as the configuration on the output terminals S, / S side.
[0064]
Also, the adding unit 140₀Carry input terminal C_INIs grounded and "0" is input. Also, the adding unit 140₀~ 140_n-2Carry output terminal C_OUTRespectively, adder 140₁~ 140_n-1It is connected to the. Thus, the adding unit 140₀~ 140_n-1Constitutes an n-bit adder.
[0065]
Also, bit line / BL₀Are grounded via N-type MOS transistors Q61 and Q62. The clear control signal / φ is applied to the gate of the transistor Q61._CLR(/ Φ_{C LR}Is φ_CLRRepresents the bar and the clear control signal φ_CLRIs added to the gate of the transistor 62._n-1Carry output terminal C_OUTMSB carry output C obtained_MSBIs entered.
[0066]
Adder 125 shown in FIG._-1And storage area 126_-1The operation of this part will be described.
First, the memory portion of one reference block is constituted by n memory cells 130 in each row extending in the column direction. The operation of clearing the memory data of the memory cells 130 constituting the predetermined memory portion will be described. .
[0067]
When clearing the storage data of the memory cell 130 constituting the predetermined storage unit, the write control signal φ_WAnd clear control signal φ_CLRIs active, that is, “1”, and the read control signal φ_RAnd equalize control signal φ_EQIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, a word line corresponding to a predetermined storage unit is activated.
[0068]
In this case, the clear control signal φ_CLRIs activated and the transistor Q51 is turned on. Therefore, data “0” is generated, and this data is stored in the bit line BL.₀~ BL_n-1Is output. Therefore, by activating a word line corresponding to a predetermined storage unit, data “0” is written in n memory cells 130 constituting the predetermined storage unit, and the stored data is cleared. .
[0069]
Next, storage data MD stored in a predetermined storage unit₀~ MD_n-18 bits of absolute difference D₀~ D₇, Adder 125_-1(Adder 140₁~ 140_n-1) And adder 125_-1Addition data AD obtained in₀~ AD_n-1The operation of writing back to the predetermined storage unit will be described.
[0070]
Storage data MD stored in a predetermined storage unit₀~ MD_n-18 bits of absolute difference D₀~ D₇First, equalize control signal φ_EQIs active, that is, “1”, and the write control signal φ_WRead control signal φ_RAnd clear control signal φ_CLRIs inactive, ie, “0”, and the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Is equalized (precharged).
[0071]
In this case, the bit line pair BL₀, / BL₀Is equalized control signal φ_EQIs activated, all of the transistors Q31 to Q33 are turned on, and the bit line BL₀And bit line / BL₀The power supply potential is applied to the bit lines BL.₀And bit line / BL₀Are at the same potential. Other bit line pairs BL₁, / BL₁~ BL_n-1, / BL_n-1The same applies to.
[0072]
In this way, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1In the state where equalization is performed, the read control signal φ_RIs active, that is, “1”, and the write control signal φ_W, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, a word line corresponding to a predetermined storage unit is activated.
[0073]
Thereby, the storage data MD of the n memory cells 130 constituting the predetermined storage unit₀~ MD_n-1Are bit line pairs BL₀, / BL₀~ BL_n-1, / BL_n-1And sense amplifier SA₀~ SA_n-1And the adder 140₀~ 140_n-1Are respectively input to the B side input terminals. Therefore, the stored data MD stored in the predetermined storage unit₀~ MD_n-18 bits of absolute difference D₀~ D₇Is added.
[0074]
Then, the adding unit 140₀~ 140_n-1Addition output at, that is, addition data AD₀~ AD_n-1When becomes effective, write control signal φ_WIs active, that is, “1”, and the read control signal φ_R, Equalize control signal φ_EQAnd clear control signal φ_CLRIs inactive, ie, “0”, and the word line WL₀~ WL_XAmong these, a word line corresponding to a predetermined storage unit is activated.
[0075]
In this case, the adding unit 140₀The additional data S for the part₀Is "1", the transistor Q11 is on, the transistor Q12 is off, and the bit line / BL₀Since “0” is output to the memory cell 130, the adding unit 140 out of the n memory cells 130 constituting the predetermined storage unit.₀Data “1” is stored in the memory cell 130 corresponding to. Meanwhile, the adding unit 140₀The additional data S for the part₀Is "0", the transistor Q11 is off, the transistor Q12 is on, and the bit line BL₀Since “0” is output to the memory cell 130, the adding unit 140 out of the n memory cells 130 constituting the predetermined storage unit.₀Data “0” is stored in the memory cell 130 corresponding to.
[0076]
Other adder 140₁~ 140_n-1The same applies to the portion of. Thus, the adder 125_-1Addition data AD obtained in₀~ AD_n-1Is written back to n memory cells 130 constituting a predetermined storage unit.
[0077]
In addition, in the case of overflow in the adding operation, the adding unit 140_n-1Carry output terminal C_OUTMSB carry output C obtained_MSBBecomes “1”, the transistor Q13 is turned off, and the additional data AD₀~ AD_n-1However, the data is not written into the n memory cells 130 constituting the predetermined storage unit.
[0078]
Instead, in this case, in addition to the transistor Q61 being turned on, the transistor Q62 is also turned on, so that the bit line / BL₀~ / BL_n-1In this case, a signal of “0” is output. Therefore, data “1” is written in each of the n memory cells 130 constituting the predetermined storage unit. That is, the maximum value is stored in the predetermined storage unit.
[0079]
Next, an operation when reading final addition data corresponding to a certain reference block, that is, a correlation value (difference absolute value sum) stored in a predetermined storage unit will be described.
First, precharge control signal / φ_RPCIs active, ie, “1”, and the read-only bit line BRL₀~ BRL_n-1Is precharged. In this case, the transistor Q41 is turned on, and the read-only bit line BRL₀~ BRL_n-1The potential of the power supply is applied to each of the above.
[0080]
In this way, the read-only bit line BRL₀~ BRL_n-1Read-only word line WRL in the precharge state₀~ WRL_XAmong these, the read-only word line corresponding to the predetermined storage unit is activated. As a result, the storage data Σ of the n memory cells 130 constituting the predetermined storage unit₀~ Σ_n-1Are read-only bit lines BRL, respectively.₀~ BRL_n-1Is obtained. Here, the stored data Σ₀~ Σ_n-1Constitutes an n-bit correlation value (difference absolute value sum).
[0081]
As described above, in the present embodiment, the adder 125_-1~ 125_-NAnd the semiconductor memory 126 for generating the correlation value table, the difference absolute value is accumulated, and the correlation value (difference) corresponding to each of a plurality of candidate blocks existing in the search range for the reference block is stored in the semiconductor memory 126. (Absolute value sum) is obtained, and the occupied area can be made smaller and the size of the semiconductor chip can be prevented from increasing as compared with a conventional case where a register is used as a memory element.
[0082]
Also, adder 125_-1~ 125_-NAnd the semiconductor memory 126 for generating the correlation value table are integrated into the adder 125._-1~ 125_-NA plurality of addition units 140 in bit units constituting each of₀~ 140_n-1Are arranged in alignment with the column pitch of the semiconductor memory 126 (see FIG. 8)._-1~ 125_-NData AD from the memory to the semiconductor memory 126₀~ AD_n-1And the adder 125 from the semiconductor memory 126_-1~ 125_-NStorage data MD₀~ MD_n-1Can be efficiently supplied.
[0083]
Further, the semiconductor memory 126 includes the plurality of addition units 140 described above.₀~ 140_n-1And a correlation value corresponding to a reference block from the semiconductor memory 126, which has a first port for writing and reading and a second port dedicated for reading (see FIG. 8). Σ₀~ Σ_n-1Can be read independently of the addition.
[0084]
Further, when clearing the stored data of the memory cell 130 that constitutes a predetermined storage portion of the semiconductor memory 126, the transistor Q51 is turned on to generate “0” data for clearing, and this data is stored in the memory cell 130. The semiconductor memory 126 is supplied as write data, and the semiconductor memory 126 can be easily cleared without inputting data for clearing from the outside.
[0085]
Also, adder 125_-1~ 125_-NA plurality of adders 140 respectively constituting₀~ 140_n-1When the result of calculation by overflows, the plurality of addition units 140₀~ 140_n-1The maximum value is stored (set) in a predetermined storage unit of the semiconductor memory 126 corresponding to the above, and an erroneously small value is stored as a correlation value in the predetermined storage unit, resulting in a motion vector detection error. Can be prevented.
[0086]
In the above embodiment, the storage area 126 of the semiconductor memory 126 is used._-1~ 126_-NThen, the bit line BL₀~ BL_n-1Is grounded via the transistor Q51, and the clear control signal / φ is applied to the gate of the transistor Q51._CLRThe clear signal φ_CLRIn FIG. 8, “0” data is written and cleared in n memory cells 130 constituting a predetermined storage section when the signal is activated (see FIG. 8).
[0087]
Here, as shown by the broken line in FIG.₀~ / BL_n-1Is grounded via the transistor Q52, and the clear control signal / φ is applied to the gate of the transistor Q52._CLRClear signal φ_CLRWhen “1” is activated, data “1” is generated by the transistor Q52, and data “1” is written in n memory cells 130 constituting a predetermined memory portion.
[0088]
Therefore, the bit line pair BL₀, / BL₀~ BL_n-1, / BL_n-1Transistors Q51 and Q52 are provided corresponding to each of these, and one of them is selectively connected to the bit line, and the clear signal φ_CLRWhen data is activated, predetermined data may be preset in n memory cells 130 constituting a predetermined storage unit. By devising this preset data, for example, a specific motion vector such as (0, 0) can be easily detected in a flat pattern portion. The preset setting may be determined in advance at the time of designing the semiconductor device. Therefore, it is assumed that the preset is set by a contact layer program or the like.
[0089]
In the above-described embodiment, the adder 125_-1~ 125_-NAnd a semiconductor memory 126 for generating a correlation value table are integrated._-1~ 124_-NAlternatively, the correlation value table evaluator 127 may be integrated.
[0090]
In the above embodiment, the memory cell 130 has a 2-port configuration (see FIG. 9). However, the memory cell may not have a 2-port configuration, and the semiconductor memory 126 as a whole has a 2-port configuration. May be. Further, even if the semiconductor memory 126 does not have a two-port configuration, for example, correlation values (table data) are read during a blanking period in a video signal, or a plurality of identical functional blocks are interleaved between fields or frames. For example, the addition and the reading of the correlation value may be performed in different periods in the same port.
[0091]
In the above-described embodiment, the adder 125_-1~ 125_-NAlthough the addition using the semiconductor memory 126 is applied to the addition of the absolute difference value in the motion vector search, it can be applied to the same addition in other signal processing.
[0092]
In the above-described embodiment, the adder 125_-1~ 125_-NIn addition, the semiconductor memory 126 for generating the correlation value table is integrated. However, a semiconductor memory integrated with other arithmetic units such as a subtractor, a multiplier, and a divider can be configured in the same manner. Data can be exchanged efficiently between the memory and the semiconductor memory.
[0093]
In the above-described embodiment, the motion vector detection circuit 111 is applied to the motion compensated predictive coding apparatus 100. However, it is needless to say that the present invention can be similarly applied to other apparatuses using motion vectors.
[0094]
In the above-described embodiment, the motion vector is detected by the block matching method. However, the present invention is not limited to the block matching method, and other pixel value matching such as a representative point block matching method. It can also be applied to methods based on.
[0095]
【The invention's effect】
  According to this invention,pluralWith adderAnd having a plurality of storage areasSemiconductor memo for correlation value table generationLiUse this semiconductor memory to accumulate absolute differences usingStorage areaIn addition, a correlation value (sum of absolute differences) for each of a plurality of candidate blocks in the search range corresponding to the reference block is obtained, and the occupied area is reduced compared to the conventional case using a register as a storage element. And an increase in size of the semiconductor chip can be prevented.
[0096]
  According to the present invention, at least a plurality of adders and a semiconductor memory are integrated, and a plurality of adders in bit units constituting the adder are provided.,Semiconductor memoryMemory cells arranged in a matrixThus, the addition data from the adder to the semiconductor memory and the storage data from the semiconductor memory to the adder can be efficiently supplied.
[0097]
According to the invention, the semiconductor memory has the first port for writing and reading and the second port dedicated for reading provided in association with the plurality of addition units described above, and the semiconductor Data stored in the memory, for example, correlation values can be read out independently of addition.
[0098]
Further, according to the present invention, data for clearing or presetting the semiconductor memory is generated, and by clearing or presetting the semiconductor memory with this data, without inputting data for clearing or presetting from the outside, The semiconductor memory can be easily cleared or preset, and by devising data for presetting, for example, a specific motion vector such as (0, 0) can be easily detected in a flat picture portion.
[0099]
Further, according to the present invention, when the calculation result by the plurality of adders constituting the adder overflows, a maximum value is set in a predetermined area of the semiconductor memory corresponding to the plurality of adders. It is possible to prevent a motion vector detection error in which an erroneously small value is stored as a correlation value in a predetermined area of the memory.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a motion compensated prediction encoding apparatus as an embodiment.
FIG. 2 is a diagram for explaining a block matching method for motion detection.
FIG. 3 is a diagram for explaining a block matching method for motion detection.
FIG. 4 is a diagram for explaining a block matching method for motion detection.
FIG. 5 is a diagram for explaining a block matching method for motion detection.
FIG. 6 is a block diagram showing a configuration of a motion vector detection circuit.
FIG. 7 is a diagram for explaining a 1: N matching operation between one reference pixel and N search range pixels;
FIG. 8 is a diagram showing a configuration in which a semiconductor memory and an adder are integrated.
FIG. 9 is a diagram showing a configuration of a memory cell.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Motion compensation prediction encoding apparatus, 101 ... Input terminal, 102 ... Subtractor, 103 ... DCT circuit, 104 ... Quantization circuit, 105 ... Output terminal, 106 ... Inverse quantization circuit 107 ... Inverse DCT circuit 108 ... Adder 109 ... Frame memory 110 ... Motion compensation circuit 111 ... Motion vector detection circuit 121 ... Controller 122, input terminals, 123, frame memory, 124_-1~ 124_-N... Difference absolute value calculator, 125_-1~ 125_-N... Adder, 126 ... Semiconductor memory for correlation value table, 126_-1~ 126_-N... Storage area, 127 ... Correlation value table evaluator, 128 ... Output terminal, 130 ... Memory cell, 140₀~ 140_n-1... Adding unit

Claims (4)

A motion vector detection device that detects a motion vector from a reference frame and a search frame that are temporally forward and backward,
The pixel data of the reference block extracted from the reference frame is input in common, and the pixel data of a plurality of candidate blocks existing in the search range for the reference block, which are extracted from the search frame, are input, respectively. A plurality of difference absolute value calculators for calculating a difference absolute value between the data and the pixel data of the candidate block;
A semiconductor memory for generating a correlation value table having a plurality of adders and a plurality of storage areas;
The difference absolute values calculated by the plurality of difference absolute value calculators are added to the storage data stored in the plurality of storage areas of the semiconductor memory using the plurality of adders. And storing each of the addition data obtained by the plurality of adders in the plurality of storage areas of the semiconductor memory a predetermined number of times, and the plurality of candidate blocks in the plurality of storage areas of the semiconductor memory. A controller that controls to obtain a correlation value corresponding to each of the
A correlation value table evaluator that detects a motion vector corresponding to the reference block based on correlation values corresponding to each of the plurality of candidate blocks obtained in the plurality of storage areas of the semiconductor memory;
The above adder
Reading the value stored in the storage area, the read write sum absolute difference value obtained by being calculated by the difference absolute value calculator to the value data to written back into the storage area,
A motion vector detection device , wherein, when an addition operation result overflows, a maximum value is set in a storage area of the semiconductor memory corresponding to the adder .   2. The plurality of bit-by-bit addition units constituting the adder are arranged in alignment with a column pitch of memory cells arranged in a matrix constituting the semiconductor memory. Motion vector detection device.   2. The motion vector detecting device according to claim 1, further comprising means for generating data for clearing the semiconductor memory composed of RAM memory cells and clearing the semiconductor memory by the data. A motion-compensated predictive coding apparatus that detects a motion vector from a reference frame and a search frame that are temporally moved by a motion vector detection circuit and performs motion compensation using the motion vector,
The motion vector detection circuit is
The pixel data of the reference block extracted from the reference frame is input in common, and the pixel data of a plurality of candidate blocks existing in the search range for the reference block, which are extracted from the search frame, are input, respectively. A plurality of difference absolute value calculators for calculating a difference absolute value between the data and the pixel data of the candidate block;
A semiconductor memory for generating a correlation value table having a plurality of adders and a plurality of storage areas;
The difference absolute values calculated by the plurality of difference absolute value calculators are added to the storage data stored in the plurality of storage areas of the semiconductor memory using the plurality of adders. And storing each of the addition data obtained by the plurality of adders in the plurality of storage areas of the semiconductor memory a predetermined number of times, and the plurality of candidate blocks in the plurality of storage areas of the semiconductor memory. A controller that controls to obtain a correlation value corresponding to each of the
A correlation value table evaluator that detects a motion vector corresponding to the reference block based on correlation values corresponding to each of the plurality of candidate blocks obtained in the plurality of storage areas of the semiconductor memory;
The above adder
Reading the value stored in the storage area, the read write sum absolute difference value obtained by being calculated by the difference absolute value calculator to the value data to written back into the storage area,
A motion-compensated predictive coding apparatus , wherein, when an addition operation result overflows, a maximum value is set in a storage area of the semiconductor memory corresponding to the adder .

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