JP4122774B2 - Semiconductor memory device, motion vector detection device, and motion compensated prediction encoding device - Google Patents

Description

【０１００】
なお、本実施の形態では、上述した減算値出力を使用するものであるが、メモリセル１４０の参照データＲＤとしてＹｉを供給し、Ｃ_-1＝０とすることで、演算出力Ｓｉおよびキャリ出力Ｃiは、それぞれ（３）式、（４）式のように得られ、加算値出力を得ることができる。
【０１０１】
【数２】

【０１０２】
次に、演算補助セル１７０について説明する。メモリブロック１２５の演算補助セル１３４ｄの部分には、上述したように候補ブロックおよび参照ブロックの対応する画素データの減算値出力を得るためのｎ個の演算補助セル１５０毎に、演算補助セル１７０が設けられる。すなわち、演算補助セル１３４ｄの部分には、候補ブロックを構成する画素データの個数と等しいｍ個の演算補助セル１７０が設けられる。図２０は、ｍ個の演算補助セル１７０のうちｋ番目（ｋ＝０，１，・・・，ｍ−１）の演算補助セル１７０を示している。
【０１０３】
図２０において、ｎ個の演算補助セル１５０の演算出力Ｓi(i=0,1,・・・,n-1)がそれぞれ入力される入力端子１７１₀，１７１₁，・・・，１７１_n-1は、それぞれイクスクルーシブＯＲゲート（ＥｘＯＲゲート）１７１₀，１７１₁，・・・，１７１_n-1に入力側に接続される。
【０１０４】
また、ｎ−１番目の演算補助セル１５０のキャリ出力/Ｃn-1が入力される入力端子１７３は、ＥｘＯＲゲート１７１₀，１７１₁，・・・，１７１_n-1に共通に接続される。そして、このＥｘＯＲゲート１７１₀，１７１₁，・・・，１７１_n-1の出力側はそれぞれｎビット全加算器１７４の、入力端子ａ₀，ａ₁，・・・，ａ_n-1に接続される。
【０１０５】
また、ｎビット全加算器１７４の入力端子ｂ₀は上述の入力端子１７３に接続されると共に、このｎビット全加算器１７４のｂ₁，・・・，ｂ_n-1は接地される。そして、このｎビット全加算器１７４の出力端子ｏ₀，ｏ₁，・・・，ｏ_n-1は、それぞれ差分絶対値Ｄk(Ｄk₀〜Ｄk_n-1）を出力する出力端子１７５₀，１７５₁，・・・，１７５_n-1に接続される。
【０１０６】
図２０に示す演算補助セル１７０においては、Ｃn-1が１で演算出力Ｓi(i=0,1,・・・,n-1)が正であるときは、この演算出力Ｓi(i=0,1,・・・,n-1)がそのまま差分絶対値Ｄk(i=0,1,・・・,n-1)として得られ、一方Ｃn-1が０で演算出力Ｓi(i=0,1,・・・,n-1)が負であるときは、この演算出力Ｓi(i=0,1,・・・,n-1)の全てのビットがＥｘＯＲゲート１７１₀，１７１₁，・・・，１７１_n-1で反転され、その後ｎビット全加算器１７４でＬＳＢに１が加算されて演算出力Ｓi(i=0,1,・・・,n-1)の絶対値が算出され、これが差分絶対値Ｄk(i=0,1,・・・,n-1)として得られる。
【０１０７】
図２１は、候補ブロックを構成するｋ番目の画素データに対応する差分絶対値Ｄk(i=0,1,・・・,n-1)を得るための演算補助セル１３４ｄの一部構成を示しており、ｎ個の演算補助セル１５０と、１個の演算補助セル１７０で構成される。演算補助セル１３４ｄの部分には、この図２１に示す構成が、候補ブロックを構成する画素データの個数と等しいｍ個だけ存在することになる。
【０１０８】
上述したように、メモリ・セル・アレイ１３１にマトリックス状に配された複数のメモリセル１４０のうち、アドレス・バッファ１３５ａに入力されるロウ・アドレスおよびアドレス・バッファ１３４ｂに入力されるカラム・アドレスによって、候補ブロックを構成するｍ個の画素データをビット毎に記憶しているｍ×ｎ個のメモリセル１４０が同時に選択されることで、演算補助セル１３４ｄではｍ個の画素データに対応する減算や差分絶対演算を同時並行的に行うことができる。
【０１０９】
以下、このように、候補ブロックを構成するｍ個の画素データをビット毎に記憶しているｍ×ｎ個のメモリセル１４０を同時に選択可能とするための構成について説明する。
【０１１０】
図２２Ａは、探索フレームメモリ１２４を構成する１つのメモリブロック１２５に記憶される画素データを模式的に示したものである。説明を簡単にするため、１つのメモリブロック１２５に記憶される画素データは、水平方向に１５画素、垂直方向に１０ラインの画素データであり、各画素データは１ビットデータであるとする。
【０１１１】
図２２Ｂは、各画素データのメモリ・セル・アレイ１３１内の記憶位置を示している。ここでは、升目のそれぞれがメモリセル１４０に対応している。メモリ・セル・アレイ１３１は、参照データのカラム方向（図１０のメモリブロック１２５の構成では、記憶データのカラム方向と同じ、図１２のメモリブロック１２５の構成では、記憶データのロウ方向と同じ）に５０個のメモリセル１４０が並べられた構成となっている。そして、メモリ・セル・アレイ１３１内の複数のメモリセル１４０は、カラム方向に分割され、５つの分割領域１３１ａ〜１３１ｅが形成されている。
【０１１２】
ここで、分割領域１３１ａの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「００」〜「９０」、「０５」〜「９５」および「０ａ」〜「９ａ」が記憶される。また、分割領域１３１ｂの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０１」〜「９１」、「０６」〜「９６」および「０ｂ」〜「９ｂ」が記憶される。また、分割領域１３１ｃの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０２」〜「９２」、「０７」〜「９７」および「０ｃ」〜「９ｃ」が記憶される。
【０１１３】
また、分割領域１３１ｄの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０３」〜「９３」、「０８」〜「９８」および「０ｄ」〜「９ｄ」が記憶される。さらに、分割領域１３１ｅの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０４」〜「９４」、「０９」〜「９９」および「０ｅ」〜「９ｅ」が記憶される。
【０１１４】
上述した複数のセル選択線ＷＬＦ（図９、図１１参照）は、それぞれ各分割領域１３１ａ〜１３１ｅに対応して分割された５本の分割セル選択線ＷＬＦａ〜ＷＬＦｅ（図２２Ｂには図示せず）からなっている。そして、メモリ・セル・アレイ１３１には、各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線を切り換えるための切り換え機構が配されている。例えば、図２２Ｂに示すように、各分割領域１３１ａ〜１３１ｅの間に切り換え機構１８０が配されている。
【０１１５】
図２３は、切り換え機構１８０の構成例を示している。この切り換え機構１８０はＮ型ＭＯＳトランジスタとＰ型ＭＯＳトランジスタとが並列接続されてなるＣＭＯＳトランスファーゲートが使用されて構成される。この切り換え機構１８０は、同一行の分割セル選択線の間に配され、それらを接続するためのトランスファーゲートＴＧ１と、隣接行の分割セル選択線の間に配され、それらを接続するためのトランスファーゲートＴＧ２とからなっている。
【０１１６】
そして、トランスファーゲートＴＧ１のＮ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ２のＰ型ＭＯＳトランジスタのゲートには切り換え制御信号φが供給され、トランスファーゲートＴＧ１のＰ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ２のＮ型ＭＯＳトランジスタのゲートには切り換え制御信号/φ（/φはφバーを表し、切り換え制御信号φが反転されたものである）が供給される。なお、各分割領域１３１ａ〜１３１ｅの間に配される切り換え機構１８０には、それぞれ独立して切り換え制御信号φ，/φが供給される。
【０１１７】
切り換え機構１８０の動作を説明する。φ＝１で、/φ＝０であるとき、トランスファーゲートＴＧ１が導通し、同一行の分割セル選択線同士が接続される状態となる。一方、φ＝０で、/φ＝１であるとき、トランスファーゲートＴＧ２が導通し、隣接行の分割セル選択線同士が接続される状態となる。
【０１１８】
メモリ・セル・アレイ１３１の各分割領域１３１ａ〜１３１ｅの間に、上述したような切り換え機構１８０が配されていることから、任意の候補ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル１４０を同時に選択できる。
【０１１９】
例えば、図２２Ａにハッチングをして示した範囲の候補ブロックに対しては、切り換え機構１８０によって図２２Ｂに破線で示すように接続された各分割領域１３１ａ〜１３１ｅの分割セル選択線ＷＬＦａ〜ＷＬＦｅに、参照データ用ロウ・アドレス・デコーダ１３５（図１０、図１２参照）から“１”のセル選択信号を供給して活性化すると共に、参照データ用カラム・アドレス・デコーダ１３４ａ（図１０、図１２参照）のＩ／Ｏゲート（カラム・スイッチ）により、図２２Ｂでハッチングをして示したメモリセル１４０を選択すればよい。
【０１２０】
また例えば、図２４Ａにハッチングをして示した範囲の候補ブロックに対しては、切り換え機構１８０により図２４Ｂに破線で示すように接続された各分割領域１３１ａ〜１３１ｅの分割セル選択線ＷＬＦａ〜ＷＬＦｅに、参照データ用ロウ・アドレス・デコーダ１３５から“１”のセル選択信号を供給して活性化すると共に、参照データ用カラム・アドレス・デコーダ１３４ａのＩ／Ｏゲート（カラム・スイッチ）により、図２４Ｂでハッチングをして示したメモリセル１４０を選択すればよい。
【０１２１】
このように、Ｉ／Ｏゲート（カラム・スイッチ）によるメモリセル１４０の選択により、矩形または十字形等の任意の形状の候補ブロックに対処することができる。また、１つの分割セル選択線に対応する複数のメモリセル１４０に、画像データを構成する垂直方向の１列分の画素データを記憶しているので、切り換え機構１８０とＩ／Ｏゲート（カラム・スイッチ）の共働により、候補ブロックの位置を水平、垂直の双方向に１画素単位で動かすことができる。
【０１２２】
なお、上述では説明を簡単にするため各画素データは１ビットデータであるとして説明したが、各画素データがｎビットデータ（例えばｎ＝８）である場合には、各画素データを記憶するためにｎ個のメモリセル１４０が必要となり、それらｎ個のメモリセル１４０は例えばカラム方向に連続して配される。
【０１２３】
また、上述した図２２Ｂ、図２４Ｂの例では、各分割セル選択線ＷＬＦａ〜ＷＬＦｅにそれぞれ対応した複数のメモリセル１４０にそれぞれ垂直方向の１列分の画素データが記憶されるものを示したが、各分割セル選択線ＷＬＦａ〜ＷＬＦｅにそれぞれ対応した複数のメモリセル１４０にそれぞれ水平方向の１列分の画素データが記憶されるようにしてもよい。
【０１２４】
また、各分割セル選択線ＷＬＦａ〜ＷＬＦｅにそれぞれ対応した複数のメモリセル１４０に、それぞれ画像データを構成する水平方向または垂直方向のｍ列分（ｍは２以上の整数）の画素データが記憶されるようにしてもよい。この場合、候補ブロックの位置は、水平方向のｍ列分の画素データが記憶されるときには垂直方向にはｍ画素単位で移動でき、また、垂直方向のｍ列分の画素データが記憶されるときには水平方向にはｍ画素単位で移動可能となる。
【０１２５】
図２５Ａは、探索フレームメモリ１２４を構成する１つのメモリブロック１２５に記憶される画素データを模式的に示したものである。説明を簡単にするため、１つのメモリブロック１２５に記憶される画素データは、水平方向に１０画素、垂直方向に１０ラインの画素データであり、各画素データは１ビットデータであるとする。
【０１２６】
図２５Ｂは、各画素データのメモリ・セル・アレイ１３１内の記憶位置を示している。ここでは、升目のそれぞれがメモリセル１４０に対応している。メモリ・セル・アレイ１３１は、参照データのカラム方向（図１０のメモリブロック１２５の構成では、記憶データのカラム方向と同じ、図１２のメモリブロック１２５の構成では、記憶データのロウ方向と同じ）に５０個のメモリセル１４０が並べられた構成となっている。そして、メモリ・セル・アレイ１３１内の複数のメモリセル１４０は、カラム方向に分割され、５つの分割領域１３１ａ〜１３１ｅが形成されている。
【０１２７】
ここで、分割領域１３１ａの連続する第１の行および第２の行のそれぞれの１０個のメモリセルには、それぞれ水平方向の１列分の画素データ「００」〜「０９」および「５０」〜「５９」が記憶される。また、分割領域１３１ｂの連続する第１の行および第２の行のそれぞれの１０個のメモリセルには、それぞれ水平方向の１列分の画素データ「１０」〜「１９」および「６０」〜「６９」が記憶される。また、分割領域１３１ｃの連続する第１の行および第２の行のそれぞれの１０個のメモリセルには、それぞれ水平方向の１列分の画素データ「２０」〜「２９」および「７０」〜「７９」が記憶される。
【０１２８】
また、分割領域１３１ｄの連続する第１の行および第２の行のそれぞれの１０個のメモリセルには、それぞれ水平方向の１列分の画素データ「３０」〜「３９」および「８０」〜「８９」が記憶される。さらに、分割領域１３１ｅの連続する第１の行および第２の行のそれぞれの１０個のメモリセルには、それぞれ水平方向の１列分の画素データ「４０」〜「４９」および「９０」〜「９９」が記憶される。
【０１２９】
上述した複数のセル選択線ＷＬＦ（図９、図１１参照）は、それぞれ各分割領域１３１ａ〜１３１ｅに対応して分割された５本の分割セル選択線ＷＬＦａ〜ＷＬＦｅ（図２５Ｂには図示せず）からなっている。そして、メモリ・セル・アレイ１３１には、各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線を切り換えるための切り換え機構１８０（図２３参照）が配されている。
【０１３０】
このように、各分割セル選択線ＷＬＦａ〜ＷＬＦｅにそれぞれ対応した複数のメモリセル１４０にそれぞれ水平方向の１列分の画素データが記憶されるものにあっても、メモリ・セル・アレイ１３１の各分割領域１３１ａ〜１３１ｅの間に切り換え機構１８０が配されていることから、任意の候補ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル１４０を同時に選択できる。
【０１３１】
例えば、図２５Ａにハッチングをして示した範囲の候補ブロックに対しては、切り換え機構１８０によって図２５Ｂに破線で示すように接続された各分割領域１３１ａ〜１３１ｅの分割セル選択線ＷＬＦａ〜ＷＬＦｅに、参照データ用ロウ・アドレス・デコーダ１３５（図１０、図１２参照）から“１”のセル選択信号を供給して活性化すると共に、参照データ用カラム・アドレス・デコーダ１３４ａ（図１０、図１２参照）のＩ／Ｏゲート（カラム・スイッチ）により、図２５Ｂでハッチングをして示したメモリセル１４０を選択すればよい。
【０１３２】
また例えば、図２６Ａにハッチングをして示した範囲の候補ブロックに対しては、切り換え機構１８０により図２６Ｂに破線で示すように接続された各分割領域１３１ａ〜１３１ｅの分割セル選択線ＷＬＦａ〜ＷＬＦｅに、参照データ用ロウ・アドレス・デコーダ１３５から“１”のセル選択信号を供給すると共に、参照データ用カラム・アドレス・デコーダ１３４ａのＩ／Ｏゲート（カラム・スイッチ）により、図２６Ｂでハッチングをして示したメモリセル１４０を選択すればよい。
【０１３３】
また、上述では、メモリ・セル・アレイ１３１の各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線を切り換えるために、各分割領域１３１ａ〜１３１ｅの間に切り換え機構１８０（図２３参照）が配されるものを示したが、この切り換え機構は他の構成であってもよい。
【０１３４】
図２７は、切り換え機構の他の構成例を示している。この切り換え機構１８０Ａは、各分割領域１３１ａ〜１３１ｅに対応して配される。図２７には、分割領域１３１ｂ，１３１ｃの部分のみ示している。
【０１３５】
この切り換え機構１８０Ａを使用する場合、各セル選択線ＷＬＦ（分割セル選択線ＷＬＦａ〜ＷＬＦｅで構成される）に平行する、セル選択信号を入力するためのグローバル選択線/ＧＷＬ（/ＧＷＬはＧＷＬバーを表し、セル選択信号として“０”が入力される）が必要となる。
【０１３６】
切り換え機構１８０Ａは、ノアゲートおよびアンドゲートが使用されて構成される。すなわち、ロウ方向の奇数行に対しては、入力側がグローバル選択線/ＧＷＬに接続され、その出力側が対応する分割セル選択線に接続されるノアゲートＮＧが配され、一方ロウ方向の偶数行に対しては、入力側がグローバル選択線/ＧＷＬに接続され、その出力側が対応する分割セル選択線に接続されるオアゲートＯＧが配される。そして、ノアゲートＮＧおよびオアゲートＯＧの入力側には切り換え制御信号/φ（/φはφバーを表し、切り換え制御信号φが反転されたものである）が供給される。なお、各分割領域１３１ａ〜１３１ｅに対応して配される切り換え機構１８０Ａには、それぞれ独立して切り換え制御信号/φが供給される。
【０１３７】
切り換え機構１８０Ａを使用した、各分割領域１３１ａ〜１３１ｅにおけるセル選択線の選択動作について説明する。
例えば、図２７において、分割領域１３１ｂでは第２の行の分割セル選択線ＷＬＦｂを選択し、分割領域１３１ｃでは第１の行の分割セル選択線ＷＬＦｃを選択するものとする。
【０１３８】
この場合、第１、第２の行のグローバル選択線/ＧＷＬi，/ＧＷＬi+1にそれぞれセル選択信号として“０”が供給される。また、分割領域１３１ｂの切り換え機構１８０Ａに供給される切り換え制御信号/φjとして“１”が供給される。これにより、第２の行のオアゲートＯＧの出力側には“１”が出力されるため、第２の行の分割セル選択線ＷＬＦｂが活性化された状態となる。
【０１３９】
一方、分割領域１３１ｃの切り換え機構１８０Ａに供給される切り換え制御信号/φjとして“０”が供給される。これにより、第１の行のノアゲートＮＧの出力側には“１”が出力されるため、第１の行の分割セル選択線ＷＬＦｃが活性化された状態となる。
【０１４０】
このように、メモリ・セル・アレイ１３１の各分割領域１３１ａ〜１３１ｅに対して、上述したような切り換え機構１８０Ａが配される場合においても、各分割領域１３１ａ〜１３１ｅの間に上述した切り換え機構１８０が配される場合と同様に、各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線の切り換えを行うことができ、任意の候補ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル１４０を同時に選択できる。
【０１４１】
また、この切り換え機構１８０Ａを使用する場合、セル選択信号の伝送路にトランスファーゲートが配されるものではなく、切り換え機構１８０におけるように、複数のトランスファーゲートＴＧ１，ＴＧ２が伝送路に配されるもののような、セル選択信号の伝送遅延を回避することができる。
【０１４２】
図２８は、切り換え機構のさらに他の構成例を示している。この切り換え機構１８０Ｂも、各分割領域１３１ａ〜１３１ｅに対応して配される。図２８には、分割領域１３１ｂ，１３１ｃの部分のみ示している。
【０１４３】
この切り換え機構１８０Ｂを使用する場合、各セル選択線ＷＬＦ（分割セル選択線ＷＬＦａ〜ＷＬＦｅで構成される）に平行する、セル選択信号を入力するためのグローバル選択線ＧＷＬ（セル選択信号として“１”が入力される）が必要となる。
【０１４４】
切り換え機構１８０Ｂは、ＣＭＯＳトランスファーゲートが使用されて構成される。すなわち、ロウ方向の奇数行に対しては、グローバル選択線ＧＷＬと各分割セル選択線ＷＬＦａ〜ＷＬＦｅとを接続するためのトランスファーゲートＴＧ３が配され、一方ロウ方向の偶数行に対しては、グローバル選択線ＧＷＬと各分割セル選択線ＷＬＦａ〜ＷＬＦｅとを接続するためのトランスファーゲートＴＧ４が配される。
【０１４５】
そして、トランスファーゲートＴＧ３のＮ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ４のＰ型ＭＯＳトランジスタのゲートには切り換え制御信号φが供給され、トランスファーゲートＴＧ３のＰ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ４のＮ型ＭＯＳトランジスタのゲートには切り換え制御信号/φ（/φはφバーを表し、切り換え制御信号φが反転されたものである）が供給される。なお、各分割領域１３１ａ〜１３１ｅに対応して配される切り換え機構１８０Ｂには、それぞれ独立して切り換え制御信号φ，/φが供給される。
【０１４６】
切り換え機構１８０Ｂを使用した、各分割領域１３１ａ〜１３１ｅにおけるセル選択線の選択動作について説明する。
例えば、図２８において、分割領域１３１ｂでは第２の行の分割セル選択線ＷＬＦｂを選択し、分割領域１３１ｃでは第１の行の分割セル選択線ＷＬＦｃを選択するものとする。
【０１４７】
この場合、第１、第２の行のグローバル選択線ＧＷＬi，ＧＷＬi+1にそれぞれセル選択信号として“１”が供給される。また、分割領域１３１ｂの切り換え機構１８０Ｂに供給される切り換え制御信号φ，/φjとしてそれぞれ“０”，“１”が供給される。これにより、第２の行のトランスファーゲートＴＧ４が導通し、グローバル選択線ＧＷＬi+1から分割セル選択線ＷＬＦｃに“１”のセル選択信号が供給されるため、第２の行の分割セル選択線ＷＬＦｂが活性化された状態となる。
【０１４８】
一方、分割領域１３１ｃの切り換え機構１８０Ｂに供給される切り換え制御信号φ，/φjとして“１”，“０”が供給される。これにより、第１の行のトランスファーゲートＴＧ３が導通し、グローバル選択線ＧＷＬiから分割セル選択線ＷＬＦｃに“１”のセル選択信号が供給されるため、第１の行の分割セル選択線ＷＬＦｃが活性化された状態となる。
【０１４９】
このように、メモリ・セル・アレイ１３１の各分割領域１３１ａ〜１３１ｅに対して、上述したような切り換え機構１８０Ｂが配される場合においても、各分割領域１３１ａ〜１３１ｅの間に上述した切り換え機構１８０が配される場合と同様に各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線の切り換えを行うことができ、任意の候補ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル１４０を同時に選択できる。
【０１５０】
また、この切り換え機構１８０Ｂを使用する場合、セル選択信号の伝送路に配されるトランスファーゲートは１個だけとなるため、切り換え機構１８０におけるように、複数のトランスファーゲートＴＧ１，ＴＧ２が伝送路に配されるものに比べて、セル選択信号の伝送遅延を軽減することができる。
【０１５１】
次に、参照フレームの画像データを蓄積するフレームメモリ１２３（図６参照）を説明する。
図２９に示すように、フレームメモリ１２３も、上述したフレームメモリ１２４と同様に、例えば４個のメモリブロック１９１ａ〜１９１ｄから構成されている。メモリブロック１９１ａ〜１９１ｄには、それぞれ、データ入力部、データ出力部が備えられている。データ入力部より画像データＤｉが入力され、データ出力部から画像データＤｏが出力される。これら、メモリブロック１９１ａ，１９１ｂ，１９１ｃ，１９１ｄには、それぞれ、参照フレームの左上、右上、左下、右下の各部分の画素データが記憶される。
【０１５２】
所定の参照ブロックの中心画素の範囲が、参照フレームの左上、右上、左下、右下の各部分にある場合には、それぞれメモリブロック１９１ａ，１９１ｂ，１９１ｃ，１９１ｄのみを活性化させればよく、消費電力を少なく抑えることができる。
【０１５３】
この場合、メモリブロック１９１ａ〜１９１ｄには、上述したフレームメモリ１２４のメモリブロック１２５ａ〜１２５ｄと同様に、参照フレームの左上、右上、左下、右下の各部分の境界部に対応して、重複して画素データが記憶される。このように、メモリブロック１９１ａ〜１９１ｄに重複した画素データを記憶しておくのは、中心画素が境界付近となる参照ブロックの画素データには、その境界部を越えた位置の画素データも必要となるからである。
【０１５４】
図３０は、メモリブロック１９１（１９１ａ〜１９１ｄ）の構成例を示している。
メモリブロック１９１は、複数のメモリセルがマトリックス状に配されたメモリ・セル・アレイ２０１と、記憶データ入出力用ポート（カラム・アドレス・デコーダなどを含む）２０２と、記憶データ用ロウ・アドレス・デコーダ２０３とを有している。
【０１５５】
メモリ・セル・アレイ２０１は、ロウ方向に延びるデータを転送するための複数のビット線ＢＬ，/ＢＬ（/ＢＬはＢＬバーを表している）と、カラム方向に延びる、複数のビット線ＢＬ，/ＢＬに直交する複数のワード線ＷＬと，これらビット線ＢＬ，/ＢＬおよびワード線ＷＬに接続され、マトリックス状に配された複数のメモリセル２１０とからなっている。
【０１５６】
図３１は、図３０に示したメモリブロック１９１のメモリ・セル・アレイ２０１以外の部分の構成を詳細に示したものである。
【０１５７】
記憶データ用カラム・アドレス・デコーダ２０２ａ、アドレスバッファ２０２ｂおよびＩ／Ｏバッファ２０２ｃは、図３０における記憶データ入出力用ポート２０２を構成している。カラム・アドレス・デコーダ２０２ａには、Ｉ／Ｏゲート（カラム・スイッチ）やセンスアンプ等が含まれている。カラム・アドレス・デコーダ２０２ａには、アドレス・バッファ２０２ｂを介してカラム・アドレスが入力される。
【０１５８】
カラム・アドレス・デコーダ２０２ａは、アドレス・バッファ２０２ｂを介して供給されるカラム・アドレスに対応して、メモリ・セル・アレイ２０１のカラム方向の所定の複数のメモリセル２１０に接続される複数のビット線ＢＬ，/ＢＬとの接続を確保し、Ｉ／Ｏバッファ２０２ｃおよびカラム・アドレス・デコーダ２０２ａを通じて、当該カラム方向の所定のメモリセルに対する、記憶データの書き込み、読み出しが可能となるようにする。
【０１５９】
また、記憶データ用ロウ・アドレス・デコーダ２０３には、アドレス・バッファ２０３ａを介してロウ・アドレスが入力される。ロウ・アドレス・デコーダ２０３は、アドレス・バッファ２０３ａを介して供給されるロウ・アドレスに対応して、メモリ・セル・アレイ２０１のロウ方向の所定のメモリセル２１０に接続されるワード線ＷＬを活性化し、Ｉ／Ｏバッファ２０２ｃおよびカラム・アドレス・デコーダ２０２ａを通じて、当該ロウ方向の所定のメモリセル２１０に対する、記憶データの書き込み、読み出しが可能となるようにする。
【０１６０】
また、制御回路２０４は、メモリブロック１９１の上述した各回路の動作を、制御入力に基づいて制御する。なお、後述するが、メモリ・セル・アレイ２０１にマトリックス状に配された複数のメモリセルの領域はワード線ＷＬに沿う方向（カラム方向）に分割された複数の分割領域からなり、複数のワード線ＷＬは、それぞれ複数の分割領域に対応して分割された複数の分割ワード線からなっており、メモリ・セル・アレイ２０１には、各分割領域で同時に活性化される分割ワード線を切り換えるための切り換え機構が配されている。この切り換え機構の制御も、制御回路２０４によって行われる。
【０１６１】
なお、メモリセル２１０は、上述したメモリブロック１２５のメモリセル１４０とは異なり、演算機能部を持っていない。詳細説明は省略するが、このメモリセル２１０は、例えば、上述の図１３に示すＳＲＡＭセル、あるいは上述の図１４に示すＤＲＡＭセルと同様の構成とされる。
【０１６２】
メモリブロック１９１は、任意の参照ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル２１０を同時に選択可能とされている。以下、そのための構成について説明する。
【０１６３】
図３２Ａは、参照フレームメモリ１２３を構成する１つのメモリブロック１９１に記憶される画素データを模式的に示したものである。説明を簡単にするため、１つのメモリブロック１９１に記憶される画素データは、水平方向に１５画素、垂直方向に１０ラインの画素データであり、各画素データは１ビットデータであるとする。
【０１６４】
図３２Ｂは、各画素データのメモリ・セル・アレイ２０１内の記憶位置を示している。ここでは、升目のそれぞれがメモリセル２１０に対応している。メモリ・セル・アレイ２０１は、カラム方向に５０個のメモリセル２１０が並べられた構成となっている。そして、メモリ・セル・アレイ２０１内の複数のメモリセル２１０は、カラム方向に分割され、５つの分割領域２０１ａ〜２０１ｅが形成されている。
【０１６５】
ここで、分割領域２０１ａの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「００」〜「９０」、「０５」〜「９５」および「０ａ」〜「９ａ」が記憶される。また、分割領域２０１ｂの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０１」〜「９１」、「０６」〜「９６」および「０ｂ」〜「９ｂ」が記憶される。また、分割領域２０１ｃの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０２」〜「９２」、「０７」〜「９７」および「０ｃ」〜「９ｃ」が記憶される。
【０１６６】
また、分割領域２０１ｄの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０３」〜「９３」、「０８」〜「９８」および「０ｄ」〜「９ｄ」が記憶される。さらに、分割領域２０１ｅの連続する第１の行、第２の行および第３の行のそれぞれの１０個のメモリセルには、それぞれ垂直方向の１列分の画素データ「０４」〜「９４」、「０９」〜「９９」および「０ｅ」〜「９ｅ」が記憶される。
【０１６７】
上述した複数のワード線ＷＬ（図３０参照）は、それぞれ各分割領域２０１ａ〜２０１ｅに対応して分割された５本の分割ワード線ＷＬａ〜ＷＬｅ（図３２Ｂには図示せず）からなっている。そして、メモリ・セル・アレイ２０１には、各分割領域２０１ａ〜２０１ｅで同時に活性化される分割ワード線を切り換えるための切り換え機構が配されている。例えば、図３２Ｂに示すように、各分割領域２０１ａ〜２０１ｅの間に切り換え機構２２０が配されている。
【０１６８】
図３３は、切り換え機構２２０の構成例を示している。この切り換え機構２２０は、上述したメモリブロック１２５のメモリ・セル・アレイ１３１内に配された切り換え機構１８０（図２３参照）と同様に構成されている。
【０１６９】
この切り換え機構２２０は、Ｎ型ＭＯＳトランジスタとＰ型ＭＯＳトランジスタとが並列接続されてなるＣＭＯＳトランスファーゲートが使用されて構成される。この切り換え機構２２０は、同一行の分割ワード線の間に配され、それらを接続するためのトランスファーゲートＴＧ１と、隣接行の分割ワード線の間に配され、それらを接続するためのトランスファーゲートＴＧ２とからなっている。
【０１７０】
そして、トランスファーゲートＴＧ１のＮ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ２のＰ型ＭＯＳトランジスタのゲートには切り換え制御信号φが供給され、トランスファーゲートＴＧ１のＰ型ＭＯＳトランジスタのゲートおよびトランスファーゲートＴＧ２のＮ型ＭＯＳトランジスタのゲートには切り換え制御信号/φ（/φはφバーを表し、切り換え制御信号φが反転されたものである）が供給される。なお、各分割領域２０１ａ〜２０１ｅの間に配される切り換え機構２２０には、それぞれ独立して切り換え制御信号φ，/φが供給される。
【０１７１】
切り換え機構２２０の動作を説明する。φ＝１で、/φ＝０であるとき、トランスファーゲートＴＧ１が導通し、同一行の分割ワード線同士が接続される状態となる。一方、φ＝０で、/φ＝１であるとき、トランスファーゲートＴＧ２が導通し、隣接行の分割ワード線同士が接続される状態となる。
【０１７２】
メモリ・セル・アレイ２０１の各分割領域２０１ａ〜２０１ｅの間に、上述したような切り換え機構２２０が配されていることから、任意の参照ブロックを構成する全画素データをビット毎に記憶している複数のメモリセル２１０を同時に選択できる。これにより、参照フレームメモリ１２３から探索フレームメモリ１２４に、参照ブロックを構成する全画素データのビットデータを参照データとして同時に供給することが可能となる。
【０１７３】
例えば、図３２Ａにハッチングをして示した範囲の候補ブロックに対しては、切り換え機構２２０によって図３２Ｂに破線で示すように接続された各分割領域２０１ａ〜２０１ｅの分割ワード線ＷＬａ〜ＷＬｅに、記憶データ用ロウ・アドレス・デコーダ２０３（図３１参照）から“１”の信号を供給して活性化すると共に、記憶データ用カラム・アドレス・デコーダ２０２ａ（図３１参照）のＩ／Ｏゲート（カラム・スイッチ）により、図２２Ｂでハッチングをして示したメモリセル２１０を選択すればよい。
【０１７４】
このように、Ｉ／Ｏゲート（カラム・スイッチ）によるメモリセル２１０の選択により、矩形または十字形等の任意の形状の参照ブロックに対処することができる。また、１つの分割ワード線に対応する複数のメモリセル２１０に、画像データを構成する垂直方向の１列分の画素データを記憶しているので、切り換え機構２２０とＩ／Ｏゲート（カラム・スイッチ）の共働により、参照ブロックの位置を水平、垂直の双方向に１画素単位で動かすことができる。
【０１７５】
なお、上述では説明を簡単にするため各画素データは１ビットデータであるとして説明したが、各画素データがｎビットデータ（例えばｎ＝８）である場合には、各画素データを記憶するためにｎ個のメモリセル２１０が必要となり、それらｎ個のメモリセル２１０は例えばカラム方向に連続して配される。
【０１７６】
また、上述した図３２Ｂの例では、各分割ワード線ＷＬａ〜ＷＬｅにそれぞれ対応した複数のメモリセル２１０にそれぞれ垂直方向の１列分の画素データが記憶されるものを示したが、上述したメモリブロック１２５のメモリ・セル・アレイ１３１の場合と同様に、各分割ワード線ＷＬａ〜ＷＬｅにそれぞれ対応した複数のメモリセル２１０にそれぞれ水平方向の１列分の画素データが記憶されるようにしてもよい。
【０１７７】
また、各分割ワード線ＷＬａ〜ＷＬｅにそれぞれ対応した複数のメモリセル２１０に、それぞれ画像データを構成する水平方向または垂直方向のｍ列分（ｍは２以上の整数）の画素データが記憶されるようにしてもよい。この場合、参照ブロックの位置は、水平方向のｍ列分の画素データが記憶されるときには垂直方向にはｍ画素単位で移動でき、また、垂直方向のｍ列分の画素データが記憶されるときには水平方向にはｍ画素単位で移動可能となる。
【０１７８】
また、上述では、メモリ・セル・アレイ２０１の各分割領域２０１ａ〜２０１ｅで同時に活性化される分割ワード線を切り換えるために、各分割領域２０１ａ〜２０１ｅの間に切り換え機構２２０（図３３参照）が配されるものを示したが、この切り換え機構２２０の代わりに、上述したメモリブロック１２５のメモリ・セル・アレイ１３１の場合と同様に、図２７に示す切り換え機構１８０Ａ、あるいは図２８に示す切り換え機構１８０Ｂと同様の構成を採用することもできる。ただしこの場合には、メモリ・セル・アレイ２０１は、各ワード線ＷＬ（分割ワード線ＷＬａ〜ＷＬｅで構成される）に平行する、セル選択信号を入力するグローバルワード線を備えている必要がある。
【０１７９】
なお、詳細説明は省略するが、上述したメモリブロック１９１の構成を、上述したメモリブロック１２５の記憶データ側にも採用してもよい。これにより、任意のブロックを構成する全画素データをビット毎に記憶している複数のメモリセル１４０を同時に選択して当該ブロックを構成する全画素データの同時読み出し、または同時書き込みを行うことが可能となる。
【０１８０】
以上説明したように、本実施の形態においては、メモリブロック１２５を構成するメモリセル１４０に論理演算を行う演算機能部が含まれていると共に（図１５参照）、このメモリブロック１２５に演算データを用いて数値演算を行うための演算補助セル１３４ｄ（図１０，図１２参照）を有するものであり、幅の広いデータ・バスを用いて処理回路にデータを伝送することなく、高速かつ効率的に所望の演算処理を行わせることができる。
【０１８１】
また、メモリブロック１２５において、記憶データの書き込み、読み出しは、複数のビット線ＢＬ，/ＢＬ、複数のワード線ＷＬを用いて行われるのに対して、演算データＤ₀〜Ｄ_m-1の出力は、複数の参照データ入力線ＲＤＬ，/ＲＤＬ、複数の演算データ出力線ＤＡＬ，ＤＢＬおよび複数のセル選択線ＷＬＦを用いて行われるものであり（図９、図１１参照）、記憶データの書き込み、読み出しと、演算データの出力とを独立して行うことができ、全体としてより柔軟で効率的な処理を行うことができる。
【０１８２】
また、探索フレームメモリ１２４を構成するメモリブロック１２５において、メモリ・セル・アレイ１３１のマトリックス状に配された複数のメモリセル１４０の領域が、セル選択線ＷＬＦに沿う方向に分割された複数の分割領域１３１ａ〜１３１ｅからなり、複数のセル選択線ＷＬＦが、それぞれ、複数の分割領域１３１ａ〜１３１ｅに対応して分割された複数の分割セル選択線ＷＬＦａ〜ＷＬＦｅからなり、各分割領域１３１ａ〜１３１ｅで同時に活性化される分割セル選択線を切り換えるための切り換え機構１８０，１８０Ａ，１８０Ｂが配されるものであり（図２２、図２３、図２７、図２８参照）、分割セル選択線単位で階段状に並ぶ複数のメモリセル１４０の演算データを複数の演算データ出力線ＤＡＬ，ＤＢＬに出力して、演算補助セル１３４ｄで処理できる。
【０１８３】
この場合、１つの分割セル選択線に対応する複数のメモリセル１４０に、画像データを構成する垂直方向または水平方向の整数列分（１列分またはｍ列分（ｍは２以上の整数））の画素データが記憶されるものであり、候補ブロックを構成する複数の画素データに対応した演算データを、同時に複数の演算データ出力線ＤＡＬ，ＤＢＬに出力でき、これらを用いた数値演算を複数の演算補助セル１５０，１７０（図１９、図２０参照）で同時並行的に行うことができる。したがって、動きベクトルＭＶを求めるための所定の候補ブロックの複数の画素データに係る複数の差分絶対値Ｄ₀〜Ｄ_m-1を同時に得ることができ、データ処理効率を大幅に向上できる。
【０１８４】
また、メモリブロック１２５の参照データ用カラム・アドレス・デコーダ１３４ａのＩ／Ｏゲート（カラム・スイッチ）によるメモリセル１４０の選択により、矩形または十字形等の任意の形状の候補ブロックに対処できる。また、１つの分割セル選択線に対応する複数のメモリセル１４０に、画像データを構成する垂直方向または水平方向の整数列分の画素データを記憶しているので、切り換え機構１８０（１８０Ａ，１８０Ｂ）とＩ／Ｏゲート（カラム・スイッチ）の共働により、候補ブロックの位置を水平、垂直の双方向に容易に移動できる。
【０１８５】
また、参照フレームメモリ１２３を構成するメモリブロック１９１において、メモリ・セル・アレイ２０１のマトリックス状に配された複数のメモリセル２１０の領域が、ワード線に沿う方向に分割された複数の分割領域２０１ａ〜２０１ｅからなり、複数のワード線ＷＬが、それぞれ、複数の分割領域２０１ａ〜２０１ｅに対応して分割された複数の分割ワード線ＷＬａ〜ＷＬｅからなり、各分割領域２０１ａ〜２０１ｅで同時に選択される分割セル選択線を切り換えるための切り換え機構２２０が配されるものであり（図３２，図３３参照）、分割ワード線単位で階段状に並ぶ複数のメモリセル２１０を同時に選択できる。
【０１８６】
この場合、１つの分割ワード線に対応する複数のメモリセル１４０に、画像データを構成する垂直方向または水平方向の整数列分（１列分またはｍ列分（ｍは２以上の整数））の画素データが記憶されるものであり、参照ブロックを構成する複数の画素データを同時に読み出すことができ、それを探索フレームメモリ１２４に同時に供給でき、処理の高速化を図ることができる。
【０１８７】
また、メモリブロック１９１の記憶データ用カラム・アドレス・デコーダ２０２ａのＩ／Ｏゲート（カラム・スイッチ）によるメモリセル２１０の選択により、矩形または十字形等の任意の形状の参照ブロックに対処できる。また、１つの分割ワード線に対応する複数のメモリセル２１０に、画像データを構成する垂直方向または水平方向の整数列分の画素データを記憶しているので、切り換え機構２２０とＩ／Ｏゲート（カラム・スイッチ）の共働により、参照ブロックの位置を水平、垂直の双方向に容易に移動できる。
【０１８８】
また、探索フレームメモリ１２４は、複数、例えば４個のメモリブロック１２５ａ〜１２５ｄで構成され、これらには探索フレームの左上、右上、左下、右下の各部分の境界部に対応して重複した画素データが記憶されるものであり、所定の候補ブロックの中心画素の範囲が、探索フレームの左上、右上、左下、右下の各部分にある場合には、それぞれメモリブロック１２５ａ，１２５ｂ，１２５ｃ，１２５ｄのみを活性化させればよく、消費電力を少なく抑えることができる。
【０１８９】
また、参照フレームメモリ１２３は、複数、例えば４個のメモリブロック１９１ａ〜１９１ｄで構成され、これらには参照フレームの左上、右上、左下、右下の各部分の境界部に対応して重複した画素データが記憶されるものであり、所定の参照ブロックの中心画素の範囲が、参照フレームの左上、右上、左下、右下の各部分にある場合には、それぞれメモリブロック１９１ａ，１９１ｂ，１９１ｃ，１９１ｄのみを活性化させればよく、消費電力を少なく抑えることができる。
【０１９０】
このように、探索フレームメモリ１２４，参照フレームメモリ１２３においては、それぞれ候補ブロックの画素データに係る演算データ、参照ブロックの画素データを得るために、いずれか１個のメモリブロックのみを活性化すればよく、従って他のメモリブロックに関しては他の処理のために使用することも可能となる。これにより、複雑な処理を効率よく行うことが可能となる。
【０１９１】
また、上述した参照フレームメモリ１２３、探索フレームメモリ１２４を使用して構成される動きベクトル検出回路１１１および動き補償予測符号化装置１００では、動きベクトルＭＶの検出のための処理の高速化、効率化を図ることができる。
【０１９２】
なお、上述実施の形態において、探索フレームメモリ１２４はメモリブロック１２５ａ〜１２５ｄからなり、これらのメモリブロック１２５ａ〜１２５ｄからの差分絶対値Ｄ₀〜Ｄ_m-1をそのまま出力するものであるが、この探索フレームメモリ１２４に、これら差分絶対値Ｄ₀〜Ｄ_m-1を累積する回路、累積値を格納する回路、さらには累積値から動きベクトルＭＶを検出する回路等の回路ブロックを一体的に有する構成とすることも考えられる。これにより、さらに処理の高速化、効率化を図ることができる。
【０１９３】
また、上述実施の形態においては、フレームメモリ１２３，１２４を構成する４個のメモリブロックには、それぞれ左上、右上、左下、右下の各部分の画素データが記憶されるものを示したが、それぞれに記憶される画素データを、データ入力順、あるいは画素位置に応じた複数の位相に対応させてもよい。
【０１９４】
また、上述実施の形態においては、動きベクトル検出回路１１１では、判断回路１２８で、差分絶対値の累積値（絶対値和）に基づいて動きベクトルＭＶを検出するものであったが、二乗和または絶対値のｎ乗和などに基づいて動きベクトルを検出するものも同様に構成することができる。その場合、図６に示す動きベクトル検出回路１１１では、フレームメモリ１２４から直接、差分の二乗値あるいは差分のｎ乗値を得るようにすればよい。
【０１９５】
また、上述実施の形態においては、この発明に係る半導体メモリ装置を、動きベクトル検出回路１１１、動き補償予測符号化装置１００に適用したものを示したが、その他の装置にも同様に適用できることは勿論である。
【０１９６】
【発明の効果】
この発明に係る半導体メモリ装置によれば、メモリブロックを構成するメモリセルに論理演算を行う演算機能部が含まれていると共に、このメモリブロックに演算データを用いて数値演算を行うための演算補助セルを有するものであり、幅の広いデータ・バスを用いて処理回路にデータを伝送することなく、高速かつ効率的に所望の演算処理を行わせることができる。
【０１９７】
また、この発明に係る半導体メモリ装置によれば、記憶データの書き込み、読み出しは、複数のビット線、複数のワード線を用いて行われ、演算データの出力は、複数の参照データ入力線、複数の演算データ出力線および複数のセル選択線を用いて行われるものであり、記憶データの書き込み、読み出しと、演算データの出力とを独立して行うことができ、全体としてより柔軟で効率的な処理が可能となる。
【０１９８】
また、この発明に係る半導体メモリ装置によれば、マトリックス状に配された複数のメモリセルの領域は、セル選択線に沿う方向に分割された複数の分割領域からなり、複数のセル選択線は、それぞれ、上記複数の分割領域に対応して分割された複数の分割セル選択線からなり、メモリブロックは、各分割領域で同時に活性化される分割セル選択線を切り換えるための切り換え機構を有するものであり、マトリックス状に配された複数のメモリセルのセル選択線に沿う方向に、分割セル選択線単位で階段状に並ぶ複数のメモリセルの演算データを演算データ出力線に出力して、演算補助セルで処理することが可能となる。
【０１９９】
この場合、画像データを構成する画素データをマトリックス状に配された複数のメモリセルに適切に配置しておくことで、矩形または十字形等の任意の形状の画素ブロックを構成する複数の画素データに対応した演算データを同時に複数の演算データ出力線に出力でき、これらを用いた数値演算を複数の演算補助セルで一括、同時に行うことができ、データ処理効率の大幅な向上を図ることができ、また当該画素ブロックの位置を容易に変更可能となる。例えば、１つの分割セル選択線に対応する複数のメモリセルに、画像データを構成する垂直方向または水平方向の整数列分の画素データが記憶されることにより、上述の画素ブロックを水平方向または垂直方向に整数画素単位で移動させることができ、一方それと直交する方向に１画素単位で移動させることができる。
【０２００】
また、この発明に係る半導体メモリ装置によれば、複数のメモリブロックで構成されることで、必要なメモリブロックのみを活性化させて使用でき、消費電力を少なく抑えることができる。
【０２０１】
また、この発明に係る半導体メモリ装置によれば、１個または２個以上のメモリブロックの他に、メモリブロックより出力される演算データに基づく処理を行う回路ブロックを有するものであり、さらに処理の高速化、効率化を図ることが可能となる。
【０２０２】
また、この発明に係る動きベクトル検出装置および動き補償予測符号化装置は、この発明に係る半導体メモリ装置を用いるものであり、動きベクトル検出のための処理の高速化、効率化を図ることができる。
【図面の簡単な説明】
【図１】実施の形態としての動き補償予測符号化装置の構成を示すブロック図である。
【図２】動き検出のためのブロックマッチング法を説明するための図である。
【図３】動き検出のためのブロックマッチング法を説明するための図である。
【図４】動き検出のためのブロックマッチング法を説明するための図である。
【図５】動き検出のためのブロックマッチング法を説明するための図である。
【図６】動きベクトル検出回路の構成を示すブロック図である。
【図７】探索フレームの画像データを蓄積するフレームメモリ（探索フレームメモリ）の構成を示す図である。
【図８】探索フレームメモリを構成する各メモリブロック間の画素データの重複を説明するための図である。
【図９】探索フレームメモリを構成するメモリブロックの構成例を示す図である。
【図１０】探索フレームメモリを構成するメモリブロックの構成例を示す図である。
【図１１】探索フレームメモリを構成するメモリブロックの他の構成例を示す図である。
【図１２】探索フレームメモリを構成するメモリブロックの他の構成例を示す図である。
【図１３】ＳＲＡＭセルの構成を示す図である。
【図１４】ＤＲＡＭセルの構成を示す図である。
【図１５】演算機能部を有するメモリセルの構成を示す図である。
【図１６】演算機能部を有する他のメモリセルの構成を示す図である。
【図１７】演算機能部を有する他のメモリセルの構成を示す図である。
【図１８】演算機能部を有するさらに他のメモリセルの構成を示す図である。
【図１９】加算、減算用の演算補助セルの構成を示す図である。
【図２０】差分絶対値演算用の演算補助セルの構成を示す図である。
【図２１】差分絶対値を得るための演算補助セル（１画素データ分）の構成を示す図である。
【図２２】探索フレームの画素データとメモリ・セル・アレイ内の記憶位置を示す図である。
【図２３】分割セル選択線の切り換え機構の構成例を示す図である。
【図２４】探索フレームの画素データとメモリ・セル・アレイ内の記憶位置を示す図である。
【図２５】探索フレームの画素データとメモリ・セル・アレイ内の記憶位置を示す図である。
【図２６】探索フレームの画素データとメモリ・セル・アレイ内の記憶位置を示す図である。
【図２７】分割セル選択線の切り換え機構の他の構成例を示す図である。
【図２８】分割セル選択線の切り換え機構のさらに他の構成例を示す図である。
【図２９】参照フレームの画像データを蓄積するフレームメモリ（参照フレームメモリ）の構成を示す図である。
【図３０】参照フレームメモリを構成するメモリブロックの構成例を示す図である。
【図３１】参照フレームメモリを構成するメモリブロックの構成例を示す図である。
【図３２】参照フレームの画素データとメモリ・セル・アレイ内の記憶位置を示す図である。
【図３３】分割ワード線の切り換え機構の構成例を示す図である。
【符号の説明】
１００・・・動き補償予測符号化装置、１０１・・・入力端子、１０２・・・減算器、１０３・・・ＤＣＴ回路、１０４・・・量子化回路、１０５・・・出力端子、１０６・・・逆量子化回路、１０７・・・逆ＤＣＴ回路、１０８・・・加算器、１０９・・・フレームメモリ、１１０・・・動き補償回路、１１１・・・動きベクトル検出回路、１２１・・・コントローラ、１２２・・・入力端子、１２３，１２４・・・フレームメモリ、１２５，１２５ａ〜１２５ｄ・・・メモリブロック、１２６・・・累積器、１２７・・・相関値テーブル、１２８・・・判断回路、１２９・・・出力端子、１３１・・・メモリ・セル・アレイ、１３１ａ〜１３１ｅ・・・分割領域、１３２・・・記憶データ入出力用ポート、１３２ａ・・・記憶データ用カラム・アドレス・デコーダ、１３２ｂ・・・Ｉ／Ｏバッファ、１３２ｃ・・・アドレス・バッファ、１３３・・・記憶データ用ロウ・アドレス・デコーダ、１３３ａ・・・アドレス・バッファ、１３４・・・参照データ入力用ポート＆演算補助セル、１３４ａ・・・参照データ用カラム・アドレス・デコーダ、１３４ｂ・・・アドレス・バッファ、１３４ｃ・・・Ｉ／Ｏバッファ、１３４ｄ・・・演算補助セル、１３５・・・参照データ用ロウ・アドレス・デコーダ、１３５ａ・・・アドレス・バッファ、１３６・・・制御回路、１４０・・・メモリセル、１４１・・・メモリセル部、１５０・・・演算補助セル、１７０・・・演算補助セル、１８０，１８０Ａ，１８０Ｂ・・・切り換え機構、１９１，１９１ａ〜１９１ｅ・・・メモリブロック、２０１・・・メモリ・セル・アレイ、２０２・・・記憶データ入出力用ポート、２０３・・・記憶データ用ロウ・アドレス・デコーダ、２０４・・・制御回路、２１０・・・メモリセル、２２０・・・切り換え機構[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, a motion vector detection device, and a motion compensated prediction encoding device. Specifically, the memory cell includes a calculation function unit that performs a logical operation using the stored data and the reference data from the reference data input unit, and a numerical value using the calculation data output from the calculation data output unit of the memory cell. A semiconductor memory capable of performing desired arithmetic processing at high speed and efficiently without transmitting data to a processing circuit using a wide data bus by using a configuration having an arithmetic auxiliary cell for performing arithmetic operations. It relates to the device.
[0002]
[Prior art]
The function of the conventional semiconductor memory device is storage of input data, and the calculation and processing of data are performed by other semiconductor devices. On the other hand, by having a memory function, a calculation function, and a processing function in one semiconductor device, there is a possibility that higher-speed calculation and processing can be performed.
[0003]
One example is an SOC (System On Chip) in which a memory and a logic circuit are juxtaposed on a single semiconductor chip. In contrast to this, there is a functional memory such as a CAM (Content Addressable Memory), for example, which has a calculation function in the memory itself.
[0004]
[Problems to be solved by the invention]
The former is still based on the old Neumann architecture, and the memory and logic circuit are integrated into a single chip, which increases the bus width between them and speeds up the clock to speed up processing. It is intended. There is an aspect of suppressing the so-called von Neumann bottleneck with force, and it is not necessarily an excellent solution or avoidance method.
[0005]
On the other hand, in the latter, high speed can be achieved by processing all data simultaneously by parallel processing in SIMD (Single Instruction Stream Multiple Data Stream) format. There may be a problem that a waiting time is required until all data is collected, or that different processing cannot be performed for each partial data. In many cases, the calculation of the entire bits constituting the data, that is, the processing of the entire data, is performed by accumulating repeated operations for each bit.
[0006]
These are not necessarily separated clearly, and there is a possibility that more appropriate processing can be performed by combining good points. For example, if the data required for a certain process is a part of the whole, if you execute partial parallel processing only for those data when they are complete, without waiting for all the data to be complete Good.
[0007]
In addition, since the memory or the memory cell itself has a necessary arithmetic function, data is not transmitted from the memory to the processing circuit using a wide data bus, and all bits can be simultaneously transmitted on the spot. It is also conceivable to perform an operation. Furthermore, by making the writing and reading of the stored data independent of the calculation and processing based on the stored data, it can be expected that more flexible and efficient processing can be performed as a whole.
Therefore, an object of the present invention is to provide a semiconductor memory device or the like that can perform desired arithmetic processing efficiently at high speed.
[0008]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes: Computational auxiliary cells and multiple memory cells arranged in a matrix A semiconductor memory device including one or two or more memory blocks, each of which has a memory cell portion that stores data of “1” or “0”, and a reference for inputting reference data A data input unit, a calculation function unit that performs logical calculation of the stored data stored in the memory cell unit and the reference data from the reference data input unit, and calculation data obtained by calculation in the calculation function unit are output. A calculation data output unit, a cell selection signal input unit for inputting a cell selection signal, and a calculation data output unit for calculating calculation data from the calculation function unit based on the cell selection signal input to the cell selection signal input unit And an output control unit for outputting to the calculation data cell, the calculation auxiliary cell includes a calculation data input unit for inputting calculation data output to the calculation data output unit of the memory cell, and an input to the calculation data input unit. A calculation unit that performs numerical calculation using the input calculation data, and a calculation data output unit that outputs calculation data obtained by the calculation unit A plurality of memory cell regions arranged in a matrix form is composed of a plurality of divided regions, and the memory block is configured such that the cell selection signal input unit of the memory cell belonging to the divided region to be activated receives the cell selection signal. Has a switching mechanism to control the memory cell to input Is.
[0009]
The semiconductor memory device according to the present invention is a semiconductor memory device including one or two or more memory blocks each having a memory cell and an operation auxiliary cell, and the memory block includes a plurality of memory blocks for transferring data. Bit lines, a plurality of word lines orthogonal to the plurality of bit lines, a reference data input line for inputting reference data parallel to the plurality of bit lines, and an operation data parallel to the plurality of bit lines Calculation data output line for outputting a cell, a cell selection line for inputting a cell selection signal parallel to a plurality of word lines, a bit line, a word line, a reference data input line, a calculation data output line and a cell selection A number using a plurality of memory cells connected to a line and arranged in a matrix, and at least a part of operation data output from a plurality of operation data output lines A plurality of operation auxiliary cells for performing an operation, the memory cell being connected to a bit line and a word line, connected to a memory cell portion storing data of “1” or “0” and a reference data input line; A reference data input unit for inputting reference data, an arithmetic function unit for performing logical operation of the stored data stored in the memory cell unit and the reference data from the reference data input unit, and an arithmetic data output line A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit to a calculation data output line; a cell selection signal input unit for inputting a cell selection signal connected to the cell selection line; A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit to a calculation data output line based on the cell selection signal input to the cell selection signal input unit. The regions of the plurality of memory cells arranged in a matrix form are composed of a plurality of divided regions divided in the direction along the word line, and the plurality of cell selection lines correspond to the plurality of divided regions, respectively. The memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region. Is.
[0010]
The semiconductor memory device according to the present invention is a semiconductor memory device including one or two or more memory blocks each having a memory cell and an operation auxiliary cell, and the memory block includes a plurality of memory blocks for transferring data. Bit lines, a plurality of word lines orthogonal to the plurality of bit lines, a reference data input line for inputting reference data, orthogonal to the plurality of bit lines, and operation data orthogonal to the plurality of bit lines Operation data output line for outputting, cell selection line for inputting a cell selection signal orthogonal to a plurality of word lines, bit line, word line, reference data input line, operation data output line and cell selection A number using a plurality of memory cells connected to a line and arranged in a matrix, and at least a part of operation data output from a plurality of operation data output lines A plurality of operation auxiliary cells for performing an operation, and the memory cell is connected to a bit line and a word line, and is connected to a memory cell portion for storing data of “1” or “0” and a reference data input line A reference data input unit for inputting reference data, an arithmetic function unit for performing a logical operation of the stored data stored in the memory cell unit and the reference data from the reference data input unit, and a calculation data output line A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit to a calculation data output line, and a cell selection signal input unit for inputting a cell selection signal connected to the cell selection line And a calculation data output unit for outputting calculation data obtained by calculation by the calculation function unit to the calculation data output line based on the cell selection signal input to the cell selection signal input unit. The regions of the plurality of memory cells arranged in a matrix form are composed of a plurality of divided regions divided in the direction along the bit line, and the plurality of cell selection lines correspond to the plurality of divided regions, respectively. The memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region. Is.
[0011]
A motion vector detection device according to the present invention is a motion vector detection device that detects a motion vector from a reference frame and a search frame that move back and forth in time, and stores a plurality of pixel data constituting the reference frame. 1 memory unit, a second memory unit that stores a plurality of pixel data constituting a search frame, and a plurality of pixel data of a reference block is read out from the first memory unit and used as reference data in the second memory unit. In addition, in the second memory unit, the pixel data of the candidate block is read for each of the plurality of candidate blocks corresponding to the reference block, and the difference for each pixel data between the candidate block and the reference block is calculated. And a pixel for each of a plurality of candidate blocks output from the second memory unit Based on the difference for each over data, motion vector corresponding to the reference block and a motion vector detecting section for detecting a second memory portion, Computational auxiliary cells and multiple memory cells arranged in a matrix The memory cell includes a memory cell portion that stores data of “1” or “0”, a reference data input portion for inputting reference data, and , An arithmetic function unit for performing a logical operation between the stored data stored in the memory cell unit and the reference data from the reference data input unit, and an arithmetic data output for outputting the arithmetic data obtained by the arithmetic function unit Unit, a cell selection signal input unit for inputting a cell selection signal, and based on the cell selection signal input to the cell selection signal input unit, the calculation data from the calculation function unit is output to the calculation data output unit The operation auxiliary cell includes an operation data input unit for inputting operation data output to the operation data output unit of the memory cell, and an operation input to the operation data input unit. And an arithmetic unit that obtains a difference by performing a numerical operation using data A plurality of memory cell regions arranged in a matrix form is composed of a plurality of divided regions, and the memory block is configured such that the cell selection signal input unit of the memory cell belonging to the divided region to be activated receives the cell selection signal. Has a switching mechanism to control the memory cell to input Is.
[0012]
A motion vector detection device according to the present invention is a motion vector detection device that detects a motion vector from a reference frame and a search frame that move back and forth in time, and stores a plurality of pixel data constituting the reference frame. 1 memory unit, a second memory unit that stores a plurality of pixel data constituting a search frame, and a plurality of pixel data of a reference block is read out from the first memory unit and used as reference data in the second memory unit. In addition, in the second memory unit, the pixel data of the candidate block is read for each of the plurality of candidate blocks corresponding to the reference block, and the difference for each pixel data between the candidate block and the reference block is calculated. And a pixel for each of a plurality of candidate blocks output from the second memory unit And a motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each data, and each of the second memory units is composed of one or more semiconductor memory blocks. The memory block includes a plurality of bit lines for transferring data, a plurality of word lines orthogonal to the plurality of bit lines, and a reference data input line for inputting reference data parallel to the plurality of bit lines. Parallel operation data output lines for outputting operation data, cell selection lines for inputting cell selection signals, bit lines, word lines, reference parallel to a plurality of bit lines Calculation data output from a plurality of memory cells connected to the data input line, calculation data output line, and cell selection line and arranged in a matrix, and a plurality of calculation data output lines And a plurality of operation auxiliary cells that obtain a difference by performing a numerical operation using at least a part of the memory cell, and the memory cell is connected to the bit line and the word line and stores data of “1” or “0” Connected to the memory cell portion and the reference data input line, and performs a logical operation on the reference data input portion for inputting reference data, the stored data stored in the memory cell portion, and the reference data from the reference data input portion. Calculation function unit, connected to calculation data output line, calculation data output unit for outputting calculation data obtained by calculation in calculation function unit to calculation data output line, cell selection line, cell selection Based on the cell selection signal input unit for inputting a signal and the cell selection signal input to the cell selection signal input unit, the calculation data obtained by calculation in the calculation function unit is output to the calculation data output line. And an arithmetic data output unit of the order The regions of the plurality of memory cells arranged in a matrix form are composed of a plurality of divided regions divided in the direction along the word line, and the plurality of cell selection lines correspond to the plurality of divided regions, respectively. The memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region. Is.
[0013]
A motion vector detection device according to the present invention is a motion vector detection device that detects a motion vector from a reference frame and a search frame that move back and forth in time, and stores a plurality of pixel data constituting the reference frame. 1 memory unit, a second memory unit that stores a plurality of pixel data constituting a search frame, and a plurality of pixel data of a reference block is read out from the first memory unit and used as reference data in the second memory unit. In addition, in the second memory unit, the pixel data of the candidate block is read for each of the plurality of candidate blocks corresponding to the reference block, and the difference for each pixel data between the candidate block and the reference block is calculated. And a pixel for each of a plurality of candidate blocks output from the second memory unit And a motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each data, and each of the second memory units is composed of one or more semiconductor memory blocks. The memory block includes a plurality of bit lines for transferring data, a plurality of word lines orthogonal to the plurality of bit lines, and a reference data input line for inputting reference data orthogonal to the plurality of bit lines. , Operation data output lines for outputting operation data orthogonal to a plurality of bit lines, cell selection lines for inputting cell selection signals orthogonal to a plurality of word lines, bit lines, word lines, reference Calculation data output from a plurality of memory cells connected to the data input line, calculation data output line, and cell selection line and arranged in a matrix, and a plurality of calculation data output lines And a plurality of operation auxiliary cells that obtain a difference by performing a numerical operation using at least a part of the memory cell, and the memory cell is connected to the bit line and the word line and stores data of “1” or “0” Connected to the memory cell portion and the reference data input line, and performs a logical operation on the reference data input portion for inputting reference data, the stored data stored in the memory cell portion, and the reference data from the reference data input portion. Calculation function unit, connected to calculation data output line, calculation data output unit for outputting calculation data obtained by calculation in calculation function unit to calculation data output line, cell selection line, cell selection Based on the cell selection signal input unit for inputting signals and the cell selection signal input to the cell selection signal input unit, the operation data obtained by the operation of the operation function unit is output to the operation data output line. And a because of the operation data output unit The regions of the plurality of memory cells arranged in a matrix form are composed of a plurality of divided regions divided in the direction along the bit line, and the plurality of cell selection lines correspond to the plurality of divided regions, respectively. The memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region. Is.
[0014]
The motion compensated predictive coding apparatus according to the present invention performs motion compensation using the motion vector detected by the motion vector detecting apparatus described above.
[0015]
In the present invention, a semiconductor memory device is composed of one or more memory blocks each having a memory cell and an operation auxiliary cell. In the arithmetic function unit of the memory cell, a logical operation is performed using the stored data “1” or “0” stored in the memory cell unit and the reference data from the reference data input unit, and the cell selection signal input unit When the cell selection signal is input to the operation data, the operation data obtained by the operation by the operation function unit is output to the operation data output unit. In the operation auxiliary cell, a numerical operation using the operation data output to the operation data output unit of the memory cell is performed, and the operation data is output to the operation data output unit.
[0016]
For example, the arithmetic function unit of the memory cell performs a plurality of logical operations in parallel, and the arithmetic unit of the operation auxiliary cell performs a numerical operation using a plurality of arithmetic data obtained by the plurality of logical operations.
[0017]
In addition, for example, the calculation auxiliary cell includes a first calculation auxiliary cell unit and a second calculation auxiliary cell unit. In the first auxiliary cell unit, a calculation obtained by calculation in the calculation function unit of the memory cell. The first numerical calculation using the data is performed, and the second numerical calculation cell using the calculation data obtained by the calculation in the plurality of first auxiliary cell units is performed in the second calculation auxiliary cell unit. Is called. In this case, when the first numerical calculation is subtraction and the second numerical calculation is an absolute value calculation, an absolute difference value is obtained as calculation data output from the calculation auxiliary cell.
[0018]
As described above, the memory cell constituting the memory block includes an arithmetic function unit for performing a logical operation, and the memory block further includes an arithmetic auxiliary cell for performing a numerical operation using the arithmetic data. It is possible to perform desired arithmetic processing at high speed and efficiently in the memory block without transmitting data to the processing circuit using a wide data bus.
[0019]
For example, the memory block has a plurality of bit lines for transferring data, a plurality of word lines orthogonal to the plurality of bit lines, and a reference for inputting reference data parallel to or orthogonal to the plurality of bit lines. A data input line and a calculation data output line for outputting calculation data and a cell selection line for inputting a cell selection signal that is parallel or orthogonal to a plurality of word lines are arranged. These bit lines and words A plurality of memory cells arranged in a matrix are connected to the line, the reference data input line, the operation data output line, and the cell selection line. Then, numerical calculations are performed in at least some of the calculation data output from the plurality of calculation data output lines in the plurality of calculation auxiliary cells.
[0020]
In this case, writing and reading of stored data are performed using a plurality of bit lines and a plurality of word lines. On the other hand, calculation data is output using a plurality of reference data input lines, a plurality of calculation data output lines, and a plurality of cell selection lines. As a result, writing and reading of stored data and output of calculation data can be performed independently, and as a whole, more flexible and efficient processing is possible.
[0021]
For example, a plurality of memory cell regions arranged in a matrix form include a plurality of divided regions divided in a direction along the cell selection line, and each of the plurality of cell selection lines corresponds to the plurality of divided regions. It consists of a plurality of divided cell selection lines. The memory block has a switching mechanism for switching divided cell selection lines that are activated simultaneously in each divided region. As a result, operation data of a plurality of memory cells arranged in a stepwise manner in divided cell selection line units in the direction along the cell selection line of the plurality of memory cells arranged in a matrix is output to the operation data output line. It is possible to process in the auxiliary cell.
[0022]
In this case, a plurality of pixel data constituting a pixel block of an arbitrary shape such as a rectangle or a cross shape by appropriately arranging the pixel data constituting the image data in a plurality of memory cells arranged in a matrix. Can be simultaneously output to a plurality of operation data output lines, and numerical operations using these can be performed simultaneously in a plurality of operation auxiliary cells, thereby greatly improving the data processing efficiency. In addition, the position of the pixel block can be easily changed.
[0023]
For example, pixel data for integer columns in the vertical direction or horizontal direction constituting the image data is stored in a plurality of memory cells corresponding to one divided cell selection line, so that the above-described pixel block is horizontally or vertically aligned. It can be moved in units of integer pixels in the direction, while it can be moved in units of one pixel in a direction orthogonal thereto.
[0024]
In addition to the above-described one or more memory blocks, a semiconductor memory device having a circuit block that performs processing based on operation data output from the memory block can further increase the processing speed and efficiency. It becomes possible.
[0025]
Note that the semiconductor memory device described above is used in the memory unit of the motion vector detection circuit of the motion vector detection device or motion compensation predictive coding device, so that the processing for motion vector detection can be speeded up and made efficient. .
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a motion compensated prediction encoding apparatus 100 as an embodiment.
The encoding apparatus 100 has an input terminal 101 for inputting image data (frame data constituting a moving image) Di, image data Di supplied to the input terminal 101, and prediction supplied from a motion compensation circuit 110 described later. A subtractor 102 that calculates a difference with image data, a DCT circuit 103 that performs DCT (discrete cosine transform) on the difference data obtained by the subtractor 102, and a DCT coefficient obtained by the DCT circuit 103 A quantization circuit 104 that performs quantization and an output terminal 105 that outputs encoded data Do obtained by the quantization circuit 104 are provided.
[0027]
The encoding apparatus 100 also performs an inverse quantization circuit 106 that performs inverse quantization on the encoded data Do obtained by the quantization circuit 104, and performs inverse DCT on the output data of the inverse quantization circuit 106. An inverse DCT circuit 107 that obtains difference data, and an adder 108 that adds the difference data obtained by the inverse DCT circuit 107 and the predicted image data obtained by the motion compensation circuit 110 to restore the original image data; A frame memory 109 for storing the image data restored by the adder 108.
[0028]
Also, the encoding apparatus 100 reads the image data stored in the frame memory 109, performs motion compensation based on a motion vector MV from a motion vector detection circuit 111 described later, and then performs the subtractor 102 and the addition as described above. A motion compensation circuit 110 that supplies the image data 108 as predicted image data, and a motion vector detection circuit 111 that detects and supplies the motion vector MV of the image data Di supplied to the input terminal 101 to the motion compensation circuit 110. Yes.
[0029]
The operation of the motion compensated predictive coding apparatus 100 shown in FIG. 1 will be described.
Image data Di input to the input terminal 101 is supplied to the subtractor 102 and the motion vector detection circuit 111. The subtractor 102 calculates the difference between the image data Di and the predicted image data supplied from the motion compensation circuit 110.
[0030]
The difference data obtained by the subtracter 102 is supplied to the DCT circuit 103 and subjected to discrete cosine transform. The DCT coefficient obtained by the DCT circuit 103 is supplied to the quantization circuit 104 and quantized. The encoded data Do obtained by the quantization circuit 104 is output to the output terminal 105.
[0031]
Also, the encoded data Do obtained by the quantization circuit 104 is supplied to the inverse quantization circuit 106 and inversely quantized, and the output data of the inverse quantization circuit 106 is further supplied to the inverse DCT circuit 107 and subjected to inverse DCT. The differential data is restored. The difference data and the prediction data from the motion compensation circuit 110 are added by the adder 108 to restore the original image data, and the restored image data is stored in the frame memory 109.
[0032]
In the motion compensation circuit 110, in a certain frame, image data stored in the frame memory 109 is read in the previous frame, and motion compensation is performed based on the motion vector MV from the motion vector detection circuit 111. Predictive image data is obtained. As described above, the predicted image data is supplied to the subtractor 102 to obtain difference data, and is also supplied to the adder 108 to restore the image data.
[0033]
Next, details of the motion vector detection circuit 111 will be described.
In the motion vector detection circuit 111, a motion vector is detected by a block matching method. As shown in FIG. 2, the motion vector is obtained by moving the candidate block of the search frame within a predetermined search range and detecting the candidate block that most closely matches the reference block of the reference frame. is there.
[0034]
In the block matching method, as shown in FIG. 3A, one image, for example, one frame image of horizontal H pixels and vertical V lines is subdivided into blocks of P pixels × Q lines as shown in FIG. 4B. . In the example of FIG. 3B, P = 5 and Q = 5. c is the central pixel position of the block.
[0035]
4A to 4C show the positional relationship between a reference block having c as the central pixel and a candidate block having c ′ as the center. The reference block having c as the central pixel is a reference block of interest in the reference frame, and the candidate block of the search frame that matches the reference block is located at the position of the block centering on c ′ in the search frame. In the block matching method, a motion vector is detected by finding a candidate block that most closely matches a reference block within a search range.
[0036]
In the case of FIG. 4A, motion vectors of +1 pixel in the horizontal direction and +1 line in the vertical direction, that is, (+1, +1) are detected. In FIG. 4B, a motion vector MV of (+3, +3) is detected, and in FIG. 4C, a motion vector of (+2, −1) is detected. The motion vector is obtained for each reference block of the reference frame.
[0037]
Assuming that the motion vector search range is ± S pixels in the horizontal direction and ± T lines in the vertical direction, the reference block has a center c ′ at a position shifted ± S horizontally and ± T vertically from the center c. Need to be compared to a candidate block with
[0038]
FIG. 5 shows that when the position of the center c of a reference block having a reference frame is R, it is necessary to compare with (2S + 1) × (2T + 1) candidate blocks of the search frame to be compared. That is, all candidate blocks in which c ′ exists at the position of the first grid in FIG. 5 are comparison targets. FIG. 5 shows an example in which S = 4 and T = 3.
[0039]
Detecting the minimum value among evaluation values obtained by comparison within the search range (that is, sum of absolute values of frame differences, sum of squares of frame differences, or sum of absolute values of frame differences, etc.) Thus, a motion vector is detected. The search range in FIG. 5 is an area where the center of the candidate block is located, and the size of the search range including the entire candidate block is (2S + P) × (2T + Q).
[0040]
FIG. 6 shows the configuration of the motion vector detection circuit 111.
The motion vector detection circuit 111 includes a controller 121 that controls the operation of the entire circuit, an input terminal 122 to which image data Di is input, a frame memory 123 that stores image data of a reference frame, and image data of a search frame. And a frame memory 124 for accumulation. Operations such as writing and reading of these frame memories 123 and 124 are controlled by the controller 121.
[0041]
When image data of a certain frame is supplied from the input terminal 122 to the frame memory 123 and written, the image data of the previous frame stored in the frame memory 123 is read and supplied to the frame memory 124 for writing. It is.
[0042]
Based on the control of the controller 121, the frame memory 124 is supplied with the pixel data of the reference block from the frame memory 123, and the frame memory 124 receives each of the plurality of candidate blocks in the search range corresponding to the reference block. The difference absolute value between the pixel data of the candidate block and the pixel data of the reference block is calculated and output for each corresponding pixel data.
[0043]
Further, the motion vector detection circuit 111 accumulates an absolute difference value for each pixel data corresponding to each of a plurality of candidate blocks output from the frame memory 124, and a plurality of values obtained by the accumulator 126. A correlation value table 127 that stores the cumulative value for each candidate block as a correlation value;
[0044]
The motion vector detection circuit 111 also detects a motion vector MV based on the correlation value for each of the plurality of candidate blocks stored in the correlation value table 127, and the motion vector detected by the determination circuit 128. And an output terminal 129 for outputting MV. The determination circuit 128 detects the position of the candidate block that generates the minimum correlation value as the motion vector MV.
[0045]
The operation of the motion vector detection circuit 111 shown in FIG. 6 will be described.
Image data Di input to the input terminal 122 is supplied to the frame memory 123 and stored as image data of a reference frame. At this time, the image data of the previous frame stored in the frame memory 123 is read out, supplied to the frame memory 124, and stored as image data of the search frame.
[0046]
Image data of the reference block is supplied from the frame memory 123 to the frame memory 124. In the frame memory 124, for each of a plurality of candidate blocks in the search range corresponding to the reference block, an absolute difference value between the pixel data of the candidate block and the pixel data of the reference block is calculated for each corresponding pixel data. Is output. In this case, when the reference block and the candidate block are configured by P pixels × Q lines (see FIG. 3B), P × Q difference absolute values are obtained for each of the plurality of candidate blocks.
[0047]
As described above, the absolute difference value for each pixel data corresponding to each of the plurality of candidate blocks output from the frame memory 124 is sequentially supplied to the accumulator 126 and accumulated. The accumulated value for each of the plurality of candidate blocks from the accumulator 126 is supplied to the correlation value table 127 and stored as a correlation value. Then, the determination circuit 128 detects the position of the candidate block that generates the minimum correlation value as the motion vector MV based on the correlation value for each of the plurality of candidate blocks stored in the correlation value table 127 in this way.
[0048]
Image data of a plurality of reference blocks in the reference frame is sequentially supplied from the frame memory 123 to the frame memory 124. Therefore, the above-described operation is repeated in the frame memory 124, the accumulator 126, the correlation value table 127, and the determination circuit 128 corresponding to each reference block. Therefore, in the determination circuit 128, the motion vector MV corresponding to each reference block is obtained. Sequentially detected. Thus, the motion vector MV detected by the determination circuit 128 is output to the output terminal 129.
[0049]
Next, details of the frame memory 124 will be described.
As shown in FIG. 7, in the present embodiment, the frame memory 124 is composed of four memory blocks 125a to 125d, but the number of memory blocks constituting the frame memory 124 is limited to four. It is not a thing. Each of the memory blocks 125a to 125d includes a data input unit, a data output unit, a reference data input unit, and a calculation data output unit. In these memory blocks 125a, 125b, 125c, and 125d, pixel data of respective upper left, upper right, lower left, and lower right portions of the search frame are stored.
[0050]
When the range of the center pixel of the predetermined candidate block is in each of the upper left, upper right, lower left, and lower right portions of the search frame, only the memory blocks 125a, 125b, 125c, and 125d may be activated. Power consumption can be reduced.
[0051]
In this case, in each of the memory blocks 125a to 125d, pixel data near the boundaries of the upper left, upper right, lower left, and lower right portions of the search frame are stored redundantly. As described above, the pixel data is stored redundantly in the memory blocks 125a to 125d because the pixel data of the candidate block whose center pixel is in the vicinity of the boundary also needs pixel data at a position beyond the boundary. Because it becomes.
[0052]
FIG. 8 shows the upper left, upper right, lower left, and lower right portions Fa, Fb, Fc, and Fd of the search frames stored in the memory blocks 125a, 125b, 125c, and 125d, respectively. The memory blocks 125a and 125b store pixel data ha and hb that are overlapped in the horizontal direction, the memory blocks 125c and 125d store pixel data hc and hd that are overlapped in the horizontal direction, and the memory blocks 125a and 125c are vertical. Pixel data va and vb overlapping in the direction are stored, and pixel data vb and vd overlapping in the vertical direction are stored in the memory blocks 125b and 125d. The number of overlapping pixels in the horizontal and vertical directions of this pixel data increases as the size of the candidate block in the horizontal and vertical directions increases.
[0053]
FIG. 9 shows a configuration example of the memory block 125 (125a to 125d).
The memory block 125 includes a memory cell array 131 in which a plurality of memory cells are arranged in a matrix, a storage data input / output port (including a column address decoder) 132, a storage data row address, It has a decoder 133, a reference data input port & operation auxiliary cell (including a column address decoder) 134, and a reference data row address decoder 135.
[0054]
The memory cell array 131 includes a plurality of bit lines BL, / BL (/ BL represents a BL bar) for transferring data extending in the row direction, and a plurality of bit lines BL, Reference data input lines RDL and / RDL for inputting reference data parallel to the plurality of word lines WL orthogonal to / BL and the plurality of bit lines BL and / BL (/ RDL represents an RDL bar) And parallel operation data output lines DAL and DBL for outputting operation data parallel to the plurality of bit lines BL and / BL, and a cell selection line WLF for inputting a cell selection signal parallel to the word line WL. These bit lines BL, / BL, word lines WL, reference data input lines RDL, / RDL, operation data output lines DAL, DBL, and cell selection lines WLF are connected in a matrix. It consists of a number of memory cell 140..
[0055]
FIG. 10 shows in detail the configuration of the memory block 125 shown in FIG. 9 other than the memory cell array 131.
The storage data column address decoder 132a, the address buffer 132b, and the I / O buffer 132c constitute the storage data input / output port 132 in FIG. The column address decoder 132a includes an I / O gate (column switch), a sense amplifier, and the like. A column address is input to the column address decoder 132a via the address buffer 132b.
[0056]
The column address decoder 132a corresponds to the column address supplied via the address buffer 132b, and a plurality of bits connected to a plurality of predetermined memory cells 140 in the column direction of the memory cell array 131. The connection with the lines BL and / BL is secured, and the storage data can be written to and read from a predetermined memory cell in the column direction through the I / O buffer 132c and the column address decoder 132a.
[0057]
A row address is input to the stored data row address decoder 133 via the address buffer 133a. The row address decoder 133 activates a word line WL connected to a predetermined memory cell 140 in the row direction of the memory cell array 131 corresponding to the row address supplied via the address buffer 133a. The stored data can be written to and read from the predetermined memory cell 140 in the row direction through the I / O buffer 132c and the column address decoder 132a.
[0058]
Further, the reference data column address decoder 134a, the address buffer 134b, the I / O buffer 134c, and the operation auxiliary cell 134d constitute the reference data input port & operation auxiliary cell 134 in FIG. The column address decoder 134a includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 134a via the address buffer 134b.
[0059]
The column address decoder 134a is connected to a plurality of predetermined memory cells 140 in the column direction of the memory cell array 131 corresponding to the column address supplied via the address buffer 134b. Connections between the operation data output lines DAL and DBL and the plurality of reference data input lines RDL and / RDL are secured. As a result, reference data is input to the predetermined plurality of memory cells 140 in the column direction via the I / O buffer 134c and the column address decoder 134a, and from the predetermined plurality of memory cells 140 in the column direction. The calculation data can be supplied to the calculation auxiliary cell 134d.
[0060]
Further, the row address is input to the reference data row address decoder 135 via the address buffer 135a. The row address decoder 135 is connected to a cell selection line WLF connected to a predetermined memory cell 140 in the row direction of the memory cell array 131 corresponding to the row address supplied via the address buffer 135a. A cell selection signal is supplied and activated. As a result, reference data is input to a predetermined memory cell 140 in the row direction through the I / O buffer 134c and the column address decoder 134a, and further, the row data is input through the column address decoder 134a and the I / O buffer 134c. It is possible to supply the operation data from the predetermined memory cell 140 in the direction to the operation auxiliary cell 134d.
[0061]
The control circuit 136 controls the operation of each circuit of the memory block 125 based on the control input. As will be described later, the region of the plurality of memory cells 140 arranged in a matrix in the memory cell array 131 includes a plurality of divided regions divided in the direction along the cell selection line WLF, and includes a plurality of cell selection lines. The WLF is composed of a plurality of divided cell selection lines divided corresponding to a plurality of divided regions, and the memory cell array 131 switches the divided cell lines activated simultaneously in each divided region. Switching mechanism is arranged. Control of this switching mechanism is also performed by the control circuit 136.
[0062]
FIG. 11 shows another configuration example of the memory block 125 (125a to 125d). In FIG. 11, parts corresponding to those in FIG. 9 are given the same reference numerals. The configuration of the memory block 125 shown in FIG. 11 differs from the configuration of the memory block 125 shown in FIG. 9 in the directions of the reference data input lines RDL and / RDL, the operation data output lines DAL and DBL, and the cell selection line WLF. ing.
[0063]
The memory block 125 includes a memory cell array 131 in which a plurality of memory cells are arranged in a matrix, a storage data input / output port (including a column address decoder) 132, a storage data row address, It has a decoder 133, a reference data input port & operation auxiliary cell (including a column address decoder) 134, and a reference data row address decoder 135.
[0064]
The memory cell array 131 includes a plurality of bit lines BL and / BL for transferring data extending in the row direction, and a plurality of word lines WL extending in the column direction and orthogonal to the plurality of bit lines BL and / BL. Reference data input lines RDL, / RDL for inputting reference data orthogonal to the plurality of bit lines BL, / BL, and DAL for outputting operation data orthogonal to the plurality of bit lines BL, / BL , DBL, a cell selection line WLF orthogonal to the word line WL for inputting a cell selection signal, these bit lines BL, / BL, word line WL, reference data input lines RDL, / RDL, operation data output line The memory cell 140 includes a plurality of memory cells 140 arranged in a matrix connected to the DAL and DBL and the cell selection line WLF.
[0065]
FIG. 12 shows in detail the configuration of a portion other than the memory cell array 131 of the memory block 125 shown in FIG. In FIG. 12, parts corresponding to those in FIG. 10 are given the same reference numerals.
[0066]
The storage data column address decoder 132a, the address buffer 132b, and the I / O buffer 132c constitute the storage data input / output port 132 in FIG. The column address decoder 132a includes an I / O gate (column switch), a sense amplifier, and the like. A column address is input to the column address decoder 132a via the address buffer 132b.
[0067]
The column address decoder 132a corresponds to the column address supplied via the address buffer 132b, and a plurality of bits connected to a plurality of predetermined memory cells 140 in the column direction of the memory cell array 131. The connection with the lines BL and / BL is secured, and the storage data can be written to and read from a predetermined memory cell in the column direction through the I / O buffer 132c and the column address decoder 132a.
[0068]
A row address is input to the stored data row address decoder 133 via the address buffer 133a. The row address decoder 133 activates a word line WL connected to a predetermined memory cell 140 in the row direction of the memory cell array 131 corresponding to the row address supplied via the address buffer 133a. The stored data can be written to and read from the predetermined memory cell 140 in the row direction through the I / O buffer 132c and the column address decoder 132a.
[0069]
The reference data column address decoder 134a, the address buffer 134b, the I / O buffer 134c, and the operation auxiliary cell 134d constitute the reference data input port & operation auxiliary cell 134 in FIG. The column address decoder 134a includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 134a via the address buffer 134b.
[0070]
The column address decoder 134a is connected to a plurality of predetermined memory cells 140 in the row direction of the memory cell array 131 corresponding to the column address supplied via the address buffer 134b. Connections between the operation data output lines DAL and DBL and the plurality of reference data input lines RDL and / RDL are secured. Thus, reference data is input to the predetermined plurality of memory cells 140 in the row direction via the I / O buffer 134c and the column address decoder 134a, and from the predetermined plurality of memory cells 140 in the row direction. The calculation data can be supplied to the calculation auxiliary cell 134d.
[0071]
Further, the row address is input to the reference data row address decoder 135 via the address buffer 135a. The row address decoder 135 is connected to a cell selection line WLF connected to a predetermined memory cell 140 in the column direction of the memory cell array 131 corresponding to the row address supplied via the address buffer 135a. A cell selection signal is supplied and activated. As a result, the reference data is input to the predetermined memory cell 140 in the column direction through the I / O buffer 134c and the column address decoder 134a, and further, the column is transmitted through the column address decoder 134a and the I / O buffer 134c. It is possible to supply the operation data from the predetermined memory cell 140 in the direction to the operation auxiliary cell 134d.
[0072]
The control circuit 136 controls the operation of each circuit of the memory block 125 based on the control input. As will be described later, the region of the plurality of memory cells 140 arranged in a matrix in the memory cell array 131 includes a plurality of divided regions divided in the direction along the cell selection line WLF, and includes a plurality of cell selection lines. The WLF is composed of a plurality of divided cell selection lines divided corresponding to a plurality of divided regions, and the memory cell array 131 switches the divided cell lines activated simultaneously in each divided region. Switching mechanism is arranged. Control of this switching mechanism is also performed by the control circuit 136.
[0073]
Next, the memory cell 140 will be described.
First, a well-known SRAM (Static Random Access Memory) cell and DRAM (Dynamic Random Access Momory) cell will be described.
FIG. 13 shows an exemplary configuration of the SRAM cell. A P-type MOS transistor Q1 and an N-type MOS transistor Q3, which are load elements, are connected in series between a power source and a ground to form a CMOS inverter 11, and a P-type MOS transistor Q2 and an N-type MOS transistor, which are load elements, A CMOS inverter 12 is formed by connecting the type MOS transistor Q4 in series between the power source and the ground. The outputs of the CMOS inverters 11 and 12, that is, the potentials of the storage nodes N1 and N2, are the inputs of the other CMOS inverters 12 and 11, that is, the gate inputs of the N-type MOS transistors Q4 and Q3.
[0074]
The storage node N1 of the CMOS inverter 11 is connected to the bit line BL via an access transistor Q5 whose gate is connected to the word line WL. On the other hand, the storage node N2 of the CMOS inverter 12 is connected to the bit line / BL via an access transistor Q6 whose gate is connected to the word line WL.
[0075]
In the SRAM cell having such a configuration, data “1” or “0” is stored in the memory cell unit 13 including the pair of CMOS inverters 11 and 12. Then, read and write data transfer is performed between the memory cell portion 13 and the bit lines BL and / BL via the access transistors Q5 and Q6.
[0076]
FIG. 14 shows an exemplary configuration of a DRAM cell. Capacitors C1 and C2 are connected in series, and Vcc / 2 (Vcc is a power supply voltage) is applied to the middle point P of each other. The side opposite to the middle point P of the capacitor C1 is a storage node N1, and this storage node N1 is connected to the bit line BL via an access transistor Q7 whose gate is connected to the word line WL. The side opposite to the middle point P of the capacitor C2 is a storage node N2. This storage node N2 is connected to the bit line / BL via an access transistor Q8 whose gate is connected to the word line WL.
[0077]
In the DRAM cell having such a configuration, data “1” or “0” is stored in the memory cell portion 14 including the pair of capacitors C1 and C2. Then, read and write data transfer is performed between the memory cell portion 14 and the bit lines BL and / BL via the access transistors Q7 and Q8.
[0078]
FIG. 15 shows a configuration of the memory cell 140 in the present embodiment.
The storage node N1 of the memory cell portion 141 is connected to the bit line BL via an access transistor Q11 whose gate is connected to the word line WL. On the other hand, the storage node N2 of the memory cell portion 141 is connected to the bit line / BL via an access transistor Q12 whose gate is connected to the word line WL.
[0079]
Here, when the memory cell 140 is based on the SRAM cell, the memory cell unit 141 is configured in the same manner as the memory cell unit 13 of the SRAM cell shown in FIG. 13, for example, and the memory cell 140 is based on the DRAM cell. For example, the memory cell portion 14 of the DRAM cell shown in FIG.
[0080]
In this case, “1” or “0” data is stored in the memory cell portion 141. Then, read and write data transfer is performed between the memory cell portion 141 and the bit lines BL and / BL via the access transistors Q11 and Q12. That is, the reading of the storage data from the memory cell unit 141 and the writing of the storage data to the memory cell unit 141 are performed in the same manner as the memory cells shown in FIGS.
[0081]
The drains of N-type MOS transistors Q13 and Q14 whose gates are connected to the storage nodes N1 and N2 of the memory cell unit 141 are connected to each other, and the source of the MOS transistor Q13 is an input terminal 142a to which reference data RD is input. And the source of the MOS transistor Q14 is grounded. The drains of the N-type MOS transistors Q15 and Q16 whose gates are connected to the storage nodes N1 and N2 of the memory cell portion 141 are connected to each other, the source of the MOS transistor Q15 is connected to the input terminal 142a, and the MOS transistor Q16 Is connected to an input terminal 142b to which reference data / RD (/ RD represents an RD bar and RD is inverted) is input.
[0082]
The input terminal 142a is connected to the reference data input line RDL described above, and the reference data RD is input through the reference data input line RDL. On the other hand, the input terminal 142b is connected to the above-described reference data input line / RDL, and the reference data / RD is input through the reference data input line / RDL.
[0083]
Here, the MOS transistors Q13 to Q18 constitute an arithmetic function unit for obtaining exclusive OR inversion (ExNOR) and logical product (AND) of the storage data stored in the memory cell unit 141 and the reference data RD. ing. An ExNOR output is obtained at the connection point Pa between the MOS transistors Q15 and Q16, and an AND output is obtained at the connection point Pb between the MOS transistors Q13 and Q14.
[0084]
The drain of the N-type MOS transistor Q17 is connected to the connection point Pa between the MOS transistors Q15 and Q16, and the source of the MOS transistor Q17 is connected to the output terminal 143 for outputting the operation data DA. The drain of the N-type MOS transistor Q18 is connected to the connection point Pb of the MOS transistors Q13 and Q14, and the source of the MOS transistor Q18 is connected to the output terminal 144 for outputting the operation data DB. The gates of these MOS transistors Q17 and Q18 are connected to an input terminal 145 to which a cell selection signal CS is input.
[0085]
The output terminal 143 is connected to the calculation data output line DAL described above, and the calculation data DA is supplied to the calculation data output line DAL. On the other hand, the output terminal 143 is connected to the arithmetic data output line DBL described above, and arithmetic data DB is supplied to the arithmetic data output line DBL. Further, the input terminal 145 is connected to the cell selection line WLF described above, and the cell selection signal CS is input through the cell selection line WLF.
[0086]
Here, the MOS transistors Q17 and Q18 constitute a transfer gate as an output control unit, and are turned on when the cell selection signal CS of “1” is supplied to the input terminal 145. In this case, the ExNOR output obtained at the connection point Pa is output to the output terminal 143 as the operation data DA through the MOS transistor Q17. Similarly, the AND output obtained at the connection point Pb is output to the output terminal 144 as the operation data DB through the MOS transistor Q18.
[0087]
As described above, the calculation of the storage data of the memory cell unit 141 and the reference data RD and the output of the calculation data DA and DB can be performed independently of the writing and reading of the storage data, and this storage data is affected. There is nothing.
[0088]
As the memory cell 140 constituting the memory cell block 125 described above, the memory cell having the configuration shown in FIG. 15 is used, but other memory cells having the same arithmetic function unit can be similarly configured. 16 to 18 show examples of other memory cells. In FIGS. 16 to 18, portions corresponding to those in FIG. 15 are denoted by the same reference numerals.
[0089]
The memory cell shown in FIG. 16 has a calculation function unit and an output control unit related to ExNOR calculation. The memory cell shown in FIG. 17 has an arithmetic function unit and an output control unit related to an AND operation.
The memory cell shown in FIG. 18 includes a calculation function unit and an output control unit related to a logical sum inversion (NOR) calculation.
[0090]
The drains of N-type MOS transistors Q19 and Q20 whose gates are connected to the storage nodes N1 and N2 of the memory cell portion 141 are connected, the source of the MOS transistor Q19 is grounded, and the source of the MOS transistor Q20 is the reference data / The RD is connected to the input terminal 142b. The MOS transistor Q19, Q20 constitutes an arithmetic function unit for obtaining the logical sum (NOR) of the stored data stored in the memory cell unit 141 and the reference data RD, and the connection point of the MOS transistors Q19, Q20. A NOR output is obtained for Pb.
[0091]
The drain of the N-type MOS transistor Q21 is connected to the connection point Pc of the MOS transistors Q19 and Q20, and the source of the MOS transistor Q21 is connected to the output terminal 146 for outputting the operation data DC. The gate of the MOS transistor Q21 is connected to an input terminal 145 to which a cell selection signal CS is input. The MOS transistor Q21 forms a transfer gate as an output control unit, and is turned on when the cell selection signal CS of “1” is supplied to the input terminal 145. In this case, the NOR output obtained at the connection point Pc is output to the output terminal 146 as the operation data DC through the MOS transistor Q21.
[0092]
Next, the arithmetic auxiliary cell 134d constituting the memory block 125 will be described.
In the present embodiment, a plurality of calculation auxiliary cells 150 for addition and subtraction shown in FIG. 19 and a plurality of calculation auxiliary cells 170 for difference absolute value calculation shown in FIG. Is done.
[0093]
Of the plurality of memory cells 140 arranged in a matrix in the memory cell array 131, the row address input to the address buffer 135a and the column address input to the address buffer 134b (FIG. 10, FIG. 12), m × n memory cells 140 storing a plurality of pixel data constituting the candidate block for each bit are simultaneously selected. m represents the number of pixel data constituting the candidate block, and n represents the number of bits of the pixel data. In the operation auxiliary cell 134d, operation data DA and DB output to the output terminals 143 and 144 of the m × n memory cells 140 are respectively connected via m × n pairs of operation data output lines DAL and DBL. Supplied at the same time.
[0094]
First, the calculation auxiliary cell 150 will be described. In the portion of the operation auxiliary cell 134d, m × n operation auxiliary cells 150 are provided corresponding to the m × n memory cells 140 described above. FIG. 19 shows an operation auxiliary cell 150 corresponding to the i-th bit data of predetermined pixel data of the candidate block. Here, i = 0, 1,..., N−1, the 0th bit data is LSB (Least Significant Bit), and the n−1th bit data is MSB (Most Significant Bit). .
[0095]
In FIG. 19, the drains of N-type MOS transistors Q31 and Q32 are connected. The drains of the N-type MOS transistors Q33 and Q34 are connected to each other, and the source of the MOS transistor Q34 is grounded. An input terminal 151 to which the operation data DA (ExNOR output) from the corresponding memory cell 140 is input as operation data DAi is connected to the gates of the MOS transistors Q32 and Q34 via a series circuit of inverters IN1 and IN2. The connection points of the inverters IN1 and IN2 are connected to the gates of the MOS transistors Q31 and Q33.
[0096]
The input terminal 152 to which the carry output / Ci-1 (/ Ci-1 represents the Ci-1 bar and the carry output Ci-1 is inverted) from the lower order is input to the MOS transistor In addition to being connected to the source of Q32, it is connected to the respective sources of MOS transistors Q31 and Q33 via an inverter IN3.
[0097]
The input terminal 153 to which the operation data DB (AND output) from the corresponding memory cell 140 is input as the operation data DBi is connected to the input side of the NOR gate 154. The connection point of the MOS transistors Q33 and Q34 is connected to the input side of the NOR gate 154. The output side of the NOR gate 154 is connected to the output terminal 155 from which the carry output / Ci (/ Ci represents the Ci bar and the carry output Ci is inverted) to the higher order is output. . The connection point of the MOS transistors Q31 and Q32 is connected to an output terminal 156 from which the operation data Si is output via an inverter IN4.
[0098]
Here, the subtraction value output between the predetermined pixel data of the candidate block and the pixel data of the reference block corresponding to the predetermined pixel data of the candidate block is obtained by the n arithmetic auxiliary cells 150 corresponding to the predetermined pixel data (n bits) of the candidate block. . That is, the predetermined pixel data of the candidate block is Xi (i = 0, 1,..., N−1), and the pixel data of the corresponding reference block is Yi (i = 0, 1,..., N−1). ) And / Yi (/ Yi represents Yi bar and Yi is inverted) is supplied as the reference data RD of the memory cell 140 described above, and C _-1 By setting = 1, the operation output Si and the carry output Ci are obtained as shown in the equations (1) and (2), respectively, and a subtraction value output is obtained. This subtraction value output is obtained as an offset binary in which the carry output Cn-1 indicates a positive or negative sign.
[0099]
[Expression 1]

[0100]
In this embodiment, the above-described subtraction value output is used, but Yi is supplied as reference data RD of the memory cell 140, and C _-1 By setting = 0, the operation output Si and the carry output Ci are obtained as shown in the equations (3) and (4), respectively, and an added value output can be obtained.
[0101]
[Expression 2]

[0102]
Next, the calculation auxiliary cell 170 will be described. In the portion of the operation auxiliary cell 134d of the memory block 125, the operation auxiliary cell 170 is provided for each of the n operation auxiliary cells 150 for obtaining the subtraction value output of the pixel data corresponding to the candidate block and the reference block as described above. Provided. In other words, in the portion of the calculation auxiliary cell 134d, m number of calculation auxiliary cells 170 equal to the number of pixel data constituting the candidate block are provided. FIG. 20 shows the kth (k = 0, 1,..., M−1) arithmetic auxiliary cell 170 among the m arithmetic auxiliary cells 170.
[0103]
In FIG. 20, input terminals 171 to which the operation outputs Si (i = 0, 1,..., N−1) of n operation auxiliary cells 150 are respectively input. ₀ , 171 ₁ ,..., 171 _n-1 Are exclusive OR gates (ExOR gates) 171 respectively. ₀ , 171 ₁ ,..., 171 _n-1 Connected to the input side.
[0104]
The input terminal 173 to which the carry output / Cn-1 of the (n-1) th auxiliary cell 150 is input is an ExOR gate 171. ₀ , 171 ₁ ,..., 171 _n-1 Connected in common. And this ExOR gate 171 ₀ , 171 ₁ ,..., 171 _n-1 Are respectively connected to the input terminal a of the n-bit full adder 174. ₀ , A ₁ , ..., a _n-1 Connected to.
[0105]
Also, the input terminal b of the n-bit full adder 174 ₀ Is connected to the input terminal 173 and b of the n-bit full adder 174 ₁ , ..., b _n-1 Is grounded. The output terminal o of the n-bit full adder 174 ₀ , O ₁ , ..., o _n-1 Is the difference absolute value Dk (Dk ₀ ~ Dk _n-1 ) To output the output terminal 175 ₀ 175 ₁ , ..., 175 _n-1 Connected to.
[0106]
In the computation auxiliary cell 170 shown in FIG. 20, when Cn-1 is 1 and the computation output Si (i = 0, 1,..., N-1) is positive, this computation output Si (i = 0). , 1,..., N-1) are directly obtained as differential absolute values Dk (i = 0, 1,..., N-1), while Cn-1 is 0 and the computation output Si (i = 0). , 1,..., N−1) are negative, all bits of the operation output Si (i = 0, 1,..., N−1) are converted to ExOR gates 171. ₀ , 171 ₁ ,..., 171 _n-1 And then 1 is added to LSB by the n-bit full adder 174 to calculate the absolute value of the operation output Si (i = 0, 1,..., N−1), which is the difference absolute value Dk ( i = 0,1, ..., n-1).
[0107]
FIG. 21 shows a partial configuration of the operation auxiliary cell 134d for obtaining the absolute difference value Dk (i = 0, 1,..., N−1) corresponding to the kth pixel data constituting the candidate block. It is composed of n calculation auxiliary cells 150 and one calculation auxiliary cell 170. In the part of the arithmetic auxiliary cell 134d, there are m pieces of the configuration shown in FIG. 21 equal to the number of pixel data constituting the candidate block.
[0108]
As described above, among the plurality of memory cells 140 arranged in a matrix in the memory cell array 131, the row address input to the address buffer 135a and the column address input to the address buffer 134b are used. Since the m × n memory cells 140 storing the m pixel data constituting the candidate block for each bit are selected at the same time, the arithmetic auxiliary cell 134d performs subtraction or the like corresponding to the m pixel data. The absolute difference calculation can be performed concurrently.
[0109]
Hereinafter, a configuration for enabling m × n memory cells 140 storing m pixel data constituting a candidate block for each bit in this manner will be described.
[0110]
FIG. 22A schematically shows pixel data stored in one memory block 125 constituting the search frame memory 124. For simplicity of explanation, it is assumed that pixel data stored in one memory block 125 is pixel data of 15 pixels in the horizontal direction and 10 lines in the vertical direction, and each pixel data is 1-bit data.
[0111]
FIG. 22B shows the storage position of each pixel data in the memory cell array 131. Here, each cell corresponds to the memory cell 140. The memory cell array 131 is in the column direction of the reference data (same as the column direction of the stored data in the configuration of the memory block 125 in FIG. 10, and the same as the row direction of the stored data in the configuration of the memory block 125 in FIG. 12). 50 memory cells 140 are arranged side by side. The plurality of memory cells 140 in the memory cell array 131 are divided in the column direction to form five divided regions 131a to 131e.
[0112]
Here, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 131a, the pixel data “00” to “90” for one column in the vertical direction is provided. ”,“ 05 ”to“ 95 ”and“ 0a ”to“ 9a ”are stored. In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 131b, pixel data “01” to “91” corresponding to one column in the vertical direction, respectively. , “06” to “96” and “0b” to “9b” are stored. In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 131c, pixel data “02” to “92” for one column in the vertical direction, respectively. , “07” to “97” and “0c” to “9c” are stored.
[0113]
In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 131d, the pixel data “03” to “93” for one column in the vertical direction, respectively. , “08” to “98” and “0d” to “9d” are stored. Further, each of the ten memory cells in the first row, the second row, and the third row of the divided region 131e has pixel data “04” to “94” for one column in the vertical direction. , “09” to “99” and “0e” to “9e” are stored.
[0114]
The plurality of cell selection lines WLF (see FIGS. 9 and 11) described above are divided into five divided cell selection lines WLFa to WLFe (not shown in FIG. 22B) corresponding to the divided regions 131a to 131e, respectively. ). The memory cell array 131 is provided with a switching mechanism for switching the divided cell selection lines that are simultaneously activated in the divided regions 131a to 131e. For example, as shown in FIG. 22B, a switching mechanism 180 is disposed between the divided regions 131a to 131e.
[0115]
FIG. 23 shows a configuration example of the switching mechanism 180. This switching mechanism 180 is configured using a CMOS transfer gate in which an N-type MOS transistor and a P-type MOS transistor are connected in parallel. This switching mechanism 180 is arranged between the divided cell selection lines in the same row and is arranged between the transfer gate TG1 for connecting them and the divided cell selection lines in the adjacent rows, and is a transfer for connecting them. It consists of a gate TG2.
[0116]
A switching control signal φ is supplied to the gate of the N-type MOS transistor of the transfer gate TG1 and the gate of the P-type MOS transistor of the transfer gate TG2, and the gate of the P-type MOS transistor of the transfer gate TG1 and the N-type of the transfer gate TG2 The gate of the MOS transistor is supplied with a switching control signal / φ (/ φ represents φ bar and is an inverted version of the switching control signal φ). Note that the switching control signals φ and / φ are independently supplied to the switching mechanism 180 disposed between the divided regions 131a to 131e.
[0117]
The operation of the switching mechanism 180 will be described. When φ = 1 and / φ = 0, the transfer gate TG1 becomes conductive, and the divided cell selection lines in the same row are connected to each other. On the other hand, when φ = 0 and / φ = 1, the transfer gate TG2 becomes conductive, and the divided cell selection lines in adjacent rows are connected to each other.
[0118]
Since the switching mechanism 180 as described above is arranged between the divided regions 131a to 131e of the memory cell array 131, all pixel data constituting an arbitrary candidate block is stored for each bit. A plurality of memory cells 140 can be selected simultaneously.
[0119]
For example, for the candidate blocks in the range indicated by hatching in FIG. 22A, the switching mechanism 180 applies the divided cell selection lines WLFa to WLFe of the divided regions 131a to 131e connected as shown by the broken lines in FIG. 22B. The cell selection signal “1” is supplied from the reference data row address decoder 135 (see FIGS. 10 and 12) for activation, and the reference data column address decoder 134a (see FIGS. 10 and 12) is activated. The memory cell 140 shown by hatching in FIG. 22B may be selected by the I / O gate (column switch) of (see).
[0120]
Further, for example, for the candidate blocks in the range shown by hatching in FIG. 24A, the divided cell selection lines WLFa to WLFe of the divided regions 131a to 131e connected by the switching mechanism 180 as shown by the broken lines in FIG. 24B. In addition, a cell selection signal of “1” is supplied from the reference data row address decoder 135 to be activated, and the I / O gate (column switch) of the reference data column address decoder 134a is used to activate the cell. The memory cell 140 indicated by hatching at 24B may be selected.
[0121]
Thus, by selecting the memory cell 140 by the I / O gate (column switch), it is possible to deal with a candidate block having an arbitrary shape such as a rectangle or a cross. Further, since the pixel data for one vertical column constituting the image data is stored in the plurality of memory cells 140 corresponding to one divided cell selection line, the switching mechanism 180 and the I / O gate (column By cooperating with the switch), the position of the candidate block can be moved in units of one pixel in both horizontal and vertical directions.
[0122]
In the above description, each pixel data is described as 1-bit data in order to simplify the description. However, when each pixel data is n-bit data (for example, n = 8), each pixel data is stored. N memory cells 140 are required, and these n memory cells 140 are continuously arranged in the column direction, for example.
[0123]
In the example of FIGS. 22B and 24B described above, the pixel data for one column in the vertical direction is stored in each of the plurality of memory cells 140 corresponding to each of the divided cell selection lines WLFa to WLFe. The pixel data for one column in the horizontal direction may be stored in the plurality of memory cells 140 corresponding to the divided cell selection lines WLFa to WLFe, respectively.
[0124]
Further, pixel data of m columns (m is an integer of 2 or more) in the horizontal direction or the vertical direction constituting the image data is stored in the plurality of memory cells 140 respectively corresponding to the divided cell selection lines WLFa to WLFe. You may make it do. In this case, the position of the candidate block can be moved in units of m pixels in the vertical direction when pixel data for m columns in the horizontal direction is stored, and when the pixel data for m columns in the vertical direction is stored. It can move in units of m pixels in the horizontal direction.
[0125]
FIG. 25A schematically shows pixel data stored in one memory block 125 constituting the search frame memory 124. For simplicity of explanation, it is assumed that pixel data stored in one memory block 125 is pixel data of 10 pixels in the horizontal direction and 10 lines in the vertical direction, and each pixel data is 1-bit data.
[0126]
FIG. 25B shows the storage position of each pixel data in the memory cell array 131. Here, each cell corresponds to the memory cell 140. The memory cell array 131 is in the column direction of the reference data (same as the column direction of the stored data in the configuration of the memory block 125 in FIG. 10, and the same as the row direction of the stored data in the configuration of the memory block 125 in FIG. 12). 50 memory cells 140 are arranged side by side. The plurality of memory cells 140 in the memory cell array 131 are divided in the column direction to form five divided regions 131a to 131e.
[0127]
Here, each of the ten memory cells in the first row and the second row in the divided region 131a has pixel data “00” to “09” and “50” for one column in the horizontal direction, respectively. ~ "59" is stored. In addition, each of the ten memory cells in the first row and the second row in the divided region 131b includes pixel data “10” to “19” and “60” to one column in the horizontal direction, respectively. “69” is stored. The ten memory cells in each of the first row and the second row in the divided region 131c have pixel data “20” to “29” and “70” to “70” to one column in the horizontal direction, respectively. “79” is stored.
[0128]
The ten memory cells in each of the first row and the second row in the divided region 131d have pixel data “30” to “39” and “80” to one column in the horizontal direction, respectively. “89” is stored. Further, each of the ten memory cells in the first row and the second row in the divided region 131e has pixel data “40” to “49” and “90” to “90” to one column in the horizontal direction, respectively. “99” is stored.
[0129]
The plurality of cell selection lines WLF (see FIGS. 9 and 11) described above are divided into five divided cell selection lines WLFa to WLFe (not shown in FIG. 25B) corresponding to the divided regions 131a to 131e, respectively. ). The memory cell array 131 is provided with a switching mechanism 180 (see FIG. 23) for switching divided cell selection lines that are simultaneously activated in the divided regions 131a to 131e.
[0130]
As described above, even in the case where pixel data for one column in the horizontal direction is stored in each of the plurality of memory cells 140 corresponding to each of the divided cell selection lines WLFa to WLFe, each of the memory cell array 131 Since the switching mechanism 180 is arranged between the divided areas 131a to 131e, a plurality of memory cells 140 storing all pixel data constituting an arbitrary candidate block for each bit can be selected simultaneously.
[0131]
For example, for the candidate blocks in the range shown by hatching in FIG. 25A, the switching mechanism 180 applies the divided cell selection lines WLFa to WLFe of the divided regions 131a to 131e connected as shown by the broken lines in FIG. 25B. The cell selection signal “1” is supplied from the reference data row address decoder 135 (see FIGS. 10 and 12) for activation, and the reference data column address decoder 134a (see FIGS. 10 and 12) is activated. The memory cell 140 shown by hatching in FIG. 25B may be selected by the I / O gate (column switch) of (see).
[0132]
Further, for example, for the candidate blocks in the range shown by hatching in FIG. 26A, the divided cell selection lines WLFa to WLFe of the divided regions 131a to 131e connected as shown by the broken line in FIG. In addition, a cell selection signal of “1” is supplied from the reference data row address decoder 135, and hatching is performed in FIG. 26B by the I / O gate (column switch) of the reference data column address decoder 134a. The memory cell 140 shown in FIG.
[0133]
In the above description, the switching mechanism 180 (see FIG. 23) is used between the divided regions 131a to 131e in order to switch the divided cell selection lines that are simultaneously activated in the divided regions 131a to 131e of the memory cell array 131. However, this switching mechanism may have other configurations.
[0134]
FIG. 27 shows another configuration example of the switching mechanism. The switching mechanism 180A is arranged corresponding to each of the divided areas 131a to 131e. FIG. 27 shows only the portions of the divided areas 131b and 131c.
[0135]
When this switching mechanism 180A is used, a global selection line / GWL (/ GWL is a GWL bar) for inputting a cell selection signal parallel to each cell selection line WLF (configured by divided cell selection lines WLFa to WLFe). And “0” is input as the cell selection signal).
[0136]
The switching mechanism 180A is configured using a NOR gate and an AND gate. In other words, for odd rows in the row direction, a NOR gate NG is arranged whose input side is connected to the global selection line / GWL and whose output side is connected to the corresponding divided cell selection line. In this case, an OR gate OG whose input side is connected to the global selection line / GWL and whose output side is connected to the corresponding divided cell selection line is arranged. Then, the switching control signal / φ (/ φ represents φ bar, and the switching control signal φ is inverted) is supplied to the input side of the NOR gate NG and the OR gate OG. Note that the switching control signal / φ is independently supplied to the switching mechanism 180A arranged corresponding to each of the divided regions 131a to 131e.
[0137]
A cell selection line selection operation in each of the divided regions 131a to 131e using the switching mechanism 180A will be described.
For example, in FIG. 27, the divided cell selection line WLFb in the second row is selected in the divided region 131b, and the divided cell selection line WLFc in the first row is selected in the divided region 131c.
[0138]
In this case, “0” is supplied as the cell selection signal to the global selection lines / GWLi and / GWLi + 1 in the first and second rows. Further, “1” is supplied as the switching control signal / φj supplied to the switching mechanism 180A of the divided region 131b. As a result, “1” is output to the output side of the OR gate OG in the second row, so that the divided cell selection line WLFb in the second row is activated.
[0139]
On the other hand, “0” is supplied as the switching control signal / φj supplied to the switching mechanism 180A of the divided region 131c. As a result, “1” is output to the output side of the NOR gate NG in the first row, so that the divided cell selection line WLFc in the first row is activated.
[0140]
Thus, even when the switching mechanism 180A as described above is arranged for each of the divided regions 131a to 131e of the memory cell array 131, the switching mechanism 180 described above between the divided regions 131a to 131e. As in the case where is arranged, the divided cell selection lines that are simultaneously activated in each of the divided regions 131a to 131e can be switched, and all pixel data constituting an arbitrary candidate block can be stored for each bit. A plurality of memory cells 140 can be selected simultaneously.
[0141]
When this switching mechanism 180A is used, a transfer gate is not arranged in the transmission path of the cell selection signal, but a plurality of transfer gates TG1 and TG2 are arranged in the transmission path as in the switching mechanism 180. Such a transmission delay of the cell selection signal can be avoided.
[0142]
FIG. 28 shows still another configuration example of the switching mechanism. This switching mechanism 180B is also arranged corresponding to each of the divided areas 131a to 131e. FIG. 28 shows only the portions of the divided areas 131b and 131c.
[0143]
When this switching mechanism 180B is used, a global selection line GWL (cell selection signal “1” is inputted in parallel with each cell selection line WLF (configured by divided cell selection lines WLFa to WLFe) for inputting a cell selection signal. ”Is input).
[0144]
The switching mechanism 180B is configured using a CMOS transfer gate. That is, a transfer gate TG3 for connecting the global selection line GWL and each of the divided cell selection lines WLFa to WLFe is provided for the odd-numbered rows in the row direction, while the global rows are provided for the even-numbered rows in the row direction. A transfer gate TG4 for connecting the selection line GWL and each divided cell selection line WLFa to WLFe is arranged.
[0145]
Then, a switching control signal φ is supplied to the gate of the N-type MOS transistor of the transfer gate TG3 and the gate of the P-type MOS transistor of the transfer gate TG4, and the N-type of the P-type MOS transistor of the transfer gate TG3 and the transfer gate TG4. The gate of the MOS transistor is supplied with a switching control signal / φ (/ φ represents φ bar and is an inverted version of the switching control signal φ). Note that the switching control signals φ and / φ are independently supplied to the switching mechanisms 180B arranged corresponding to the respective divided regions 131a to 131e.
[0146]
A cell selection line selection operation in each of the divided regions 131a to 131e using the switching mechanism 180B will be described.
For example, in FIG. 28, the divided cell selection line WLFb of the second row is selected in the divided region 131b, and the divided cell selection line WLFc of the first row is selected in the divided region 131c.
[0147]
In this case, “1” is supplied as the cell selection signal to the global selection lines GWLi and GWLi + 1 of the first and second rows. Further, “0” and “1” are supplied as the switching control signals φ and / φj supplied to the switching mechanism 180B of the divided region 131b, respectively. As a result, the transfer gate TG4 in the second row becomes conductive, and a cell selection signal of “1” is supplied from the global selection line GWLi + 1 to the division cell selection line WLFc, so that the division cell selection line in the second row WLFb is activated.
[0148]
On the other hand, “1” and “0” are supplied as the switching control signals φ and / φj supplied to the switching mechanism 180B of the divided region 131c. As a result, the transfer gate TG3 in the first row is turned on, and a cell selection signal of “1” is supplied from the global selection line GWLi to the division cell selection line WLFc, so that the division cell selection line WLFc in the first row is It becomes an activated state.
[0149]
Thus, even when the switching mechanism 180B as described above is arranged for each of the divided regions 131a to 131e of the memory cell array 131, the switching mechanism 180 described above between the divided regions 131a to 131e. As in the case of the arrangement, the divided cell selection lines activated simultaneously in each of the divided regions 131a to 131e can be switched, and all pixel data constituting an arbitrary candidate block is stored for each bit. A plurality of memory cells 140 can be selected simultaneously.
[0150]
In addition, when this switching mechanism 180B is used, only one transfer gate is arranged on the transmission path of the cell selection signal. Therefore, as in the switching mechanism 180, a plurality of transfer gates TG1 and TG2 are arranged on the transmission path. Compared to what is done, the transmission delay of the cell selection signal can be reduced.
[0151]
Next, the frame memory 123 (see FIG. 6) that stores the image data of the reference frame will be described.
As shown in FIG. 29, the frame memory 123 is also composed of, for example, four memory blocks 191a to 191d, similarly to the frame memory 124 described above. Each of the memory blocks 191a to 191d includes a data input unit and a data output unit. Image data Di is input from the data input unit, and image data Do is output from the data output unit. In these memory blocks 191a, 191b, 191c, and 191d, pixel data of respective upper left, upper right, lower left, and lower right portions of the reference frame are stored.
[0152]
When the range of the center pixel of a predetermined reference block is in the upper left, upper right, lower left, and lower right portions of the reference frame, only the memory blocks 191a, 191b, 191c, and 191d may be activated. Power consumption can be reduced.
[0153]
In this case, like the memory blocks 125a to 125d of the frame memory 124 described above, the memory blocks 191a to 191d overlap corresponding to the boundary portions of the upper left, upper right, lower left, and lower right portions of the reference frame. Pixel data is stored. In this way, the overlapping pixel data is stored in the memory blocks 191a to 191d because the pixel data of the reference block whose center pixel is near the boundary also needs pixel data at a position beyond the boundary. Because it becomes.
[0154]
FIG. 30 shows a configuration example of the memory block 191 (191a to 191d).
The memory block 191 includes a memory cell array 201 in which a plurality of memory cells are arranged in a matrix, a storage data input / output port (including a column address decoder, etc.) 202, a storage data row address, And a decoder 203.
[0155]
The memory cell array 201 includes a plurality of bit lines BL, / BL (/ BL represents a BL bar) for transferring data extending in the row direction, and a plurality of bit lines BL, It consists of a plurality of word lines WL orthogonal to / BL and a plurality of memory cells 210 connected to these bit lines BL, / BL and word lines WL and arranged in a matrix.
[0156]
FIG. 31 shows in detail the configuration of the memory block 191 shown in FIG. 30 other than the memory cell array 201.
[0157]
The stored data column address decoder 202a, the address buffer 202b, and the I / O buffer 202c constitute the stored data input / output port 202 in FIG. The column address decoder 202a includes an I / O gate (column switch), a sense amplifier, and the like. The column address is input to the column address decoder 202a via the address buffer 202b.
[0158]
The column address decoder 202a corresponds to a column address supplied via the address buffer 202b, and a plurality of bits connected to a plurality of predetermined memory cells 210 in the column direction of the memory cell array 201. The connection to the lines BL and / BL is secured, and the storage data can be written to and read from a predetermined memory cell in the column direction through the I / O buffer 202c and the column address decoder 202a.
[0159]
Further, the row address is input to the stored data row address decoder 203 via the address buffer 203a. The row address decoder 203 activates a word line WL connected to a predetermined memory cell 210 in the row direction of the memory cell array 201 corresponding to the row address supplied via the address buffer 203a. Thus, the storage data can be written to and read from the predetermined memory cell 210 in the row direction through the I / O buffer 202c and the column address decoder 202a.
[0160]
The control circuit 204 controls the operation of each circuit of the memory block 191 based on the control input. As will be described later, the area of the plurality of memory cells arranged in a matrix in the memory cell array 201 is composed of a plurality of divided areas divided in the direction (column direction) along the word line WL. The line WL is composed of a plurality of divided word lines each divided corresponding to a plurality of divided regions, and the memory cell array 201 is switched to switch divided word lines activated simultaneously in each divided region. Switching mechanism is arranged. This switching mechanism is also controlled by the control circuit 204.
[0161]
Note that, unlike the memory cell 140 of the memory block 125 described above, the memory cell 210 does not have an arithmetic function unit. Although detailed description is omitted, the memory cell 210 has the same configuration as, for example, the SRAM cell shown in FIG. 13 or the DRAM cell shown in FIG.
[0162]
The memory block 191 can simultaneously select a plurality of memory cells 210 that store all pixel data constituting an arbitrary reference block for each bit. Hereinafter, a configuration for that purpose will be described.
[0163]
FIG. 32A schematically shows pixel data stored in one memory block 191 constituting the reference frame memory 123. In order to simplify the description, it is assumed that the pixel data stored in one memory block 191 is pixel data of 15 pixels in the horizontal direction and 10 lines in the vertical direction, and each pixel data is 1-bit data.
[0164]
FIG. 32B shows the storage position of each pixel data in the memory cell array 201. Here, each cell corresponds to the memory cell 210. The memory cell array 201 has a configuration in which 50 memory cells 210 are arranged in the column direction. A plurality of memory cells 210 in the memory cell array 201 are divided in the column direction to form five divided regions 201a to 201e.
[0165]
Here, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 201a, the pixel data “00” to “90” for one column in the vertical direction respectively. ”,“ 05 ”to“ 95 ”and“ 0a ”to“ 9a ”are stored. In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 201b, the pixel data “01” to “91” for one column in the vertical direction, respectively. , “06” to “96” and “0b” to “9b” are stored. In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided region 201c, the pixel data “02” to “92” for one column in the vertical direction, respectively. , “07” to “97” and “0c” to “9c” are stored.
[0166]
In addition, in each of the ten memory cells in the first row, the second row, and the third row in the divided area 201d, the pixel data “03” to “93” for one column in the vertical direction, respectively. , “08” to “98” and “0d” to “9d” are stored. Further, each of the ten memory cells in the first row, the second row, and the third row in the divided region 201e has pixel data “04” to “94” for one column in the vertical direction. , “09” to “99” and “0e” to “9e” are stored.
[0167]
The plurality of word lines WL (see FIG. 30) described above are composed of five divided word lines WLa to WLe (not shown in FIG. 32B) divided corresponding to the divided regions 201a to 201e, respectively. . The memory cell array 201 is provided with a switching mechanism for switching the divided word lines that are simultaneously activated in the divided regions 201a to 201e. For example, as shown in FIG. 32B, a switching mechanism 220 is disposed between the divided areas 201a to 201e.
[0168]
FIG. 33 shows a configuration example of the switching mechanism 220. The switching mechanism 220 is configured in the same manner as the switching mechanism 180 (see FIG. 23) arranged in the memory cell array 131 of the memory block 125 described above.
[0169]
The switching mechanism 220 is configured using a CMOS transfer gate in which an N-type MOS transistor and a P-type MOS transistor are connected in parallel. The switching mechanism 220 is arranged between the divided word lines in the same row and is connected to the transfer gate TG1 for connecting them, and the transfer gate TG2 is arranged between the divided word lines in the adjacent row and is connected to them. It is made up of.
[0170]
A switching control signal φ is supplied to the gate of the N-type MOS transistor of the transfer gate TG1 and the gate of the P-type MOS transistor of the transfer gate TG2, and the gate of the P-type MOS transistor of the transfer gate TG1 and the N-type of the transfer gate TG2 The gate of the MOS transistor is supplied with a switching control signal / φ (/ φ represents φ bar and is an inverted version of the switching control signal φ). Note that switching control signals φ and / φ are independently supplied to the switching mechanism 220 arranged between the divided regions 201a to 201e.
[0171]
The operation of the switching mechanism 220 will be described. When φ = 1 and / φ = 0, the transfer gate TG1 becomes conductive, and the divided word lines in the same row are connected to each other. On the other hand, when φ = 0 and / φ = 1, transfer gate TG2 becomes conductive, and the divided word lines in adjacent rows are connected.
[0172]
Since the switching mechanism 220 as described above is arranged between the divided areas 201a to 201e of the memory cell array 201, all pixel data constituting an arbitrary reference block is stored for each bit. A plurality of memory cells 210 can be selected simultaneously. As a result, the bit data of all the pixel data constituting the reference block can be simultaneously supplied from the reference frame memory 123 to the search frame memory 124 as reference data.
[0173]
For example, for the candidate blocks in the range indicated by hatching in FIG. 32A, the divided word lines WLa to WLe of the divided regions 201 a to 201 e connected as shown by the broken line in FIG. A signal “1” is supplied from the stored data row address decoder 203 (see FIG. 31) to be activated, and the I / O gate (column) of the stored data column address decoder 202a (see FIG. 31) is activated. The memory cell 210 shown hatched in FIG. 22B may be selected by the switch).
[0174]
As described above, by selecting the memory cell 210 by the I / O gate (column switch), it is possible to deal with a reference block having an arbitrary shape such as a rectangle or a cross. Further, since the pixel data for one column in the vertical direction constituting the image data is stored in the plurality of memory cells 210 corresponding to one divided word line, the switching mechanism 220 and the I / O gate (column switch ), The position of the reference block can be moved in units of one pixel in both horizontal and vertical directions.
[0175]
In the above description, each pixel data is described as 1-bit data in order to simplify the description. However, when each pixel data is n-bit data (for example, n = 8), each pixel data is stored. N memory cells 210 are required, and these n memory cells 210 are continuously arranged in the column direction, for example.
[0176]
In the example of FIG. 32B described above, the pixel data for one column in the vertical direction is stored in the plurality of memory cells 210 respectively corresponding to the divided word lines WLa to WLe. As in the case of the memory cell array 131 of the block 125, pixel data for one column in the horizontal direction may be stored in the plurality of memory cells 210 respectively corresponding to the divided word lines WLa to WLe. Good.
[0177]
Also, pixel data of m columns (m is an integer of 2 or more) in the horizontal direction or the vertical direction constituting the image data is stored in the plurality of memory cells 210 respectively corresponding to the divided word lines WLa to WLe. You may do it. In this case, the position of the reference block can be moved in units of m pixels in the vertical direction when pixel data for m columns in the horizontal direction is stored, and when the pixel data for m columns in the vertical direction is stored. It can move in units of m pixels in the horizontal direction.
[0178]
In the above description, the switching mechanism 220 (see FIG. 33) is provided between the divided regions 201a to 201e in order to switch the divided word lines activated simultaneously in the divided regions 201a to 201e of the memory cell array 201. However, instead of the switching mechanism 220, the switching mechanism 180A shown in FIG. 27 or the switching mechanism shown in FIG. 28 is used in the same manner as the memory cell array 131 of the memory block 125 described above. A configuration similar to 180B may be employed. However, in this case, the memory cell array 201 needs to include a global word line for inputting a cell selection signal, which is parallel to each word line WL (configured by divided word lines WLa to WLe). .
[0179]
Although not described in detail, the configuration of the memory block 191 described above may also be employed on the storage data side of the memory block 125 described above. As a result, a plurality of memory cells 140 storing all pixel data constituting an arbitrary block for each bit can be simultaneously selected, and all pixel data constituting the block can be simultaneously read or written. It becomes.
[0180]
As described above, in the present embodiment, the memory cell 140 constituting the memory block 125 includes an arithmetic function unit that performs a logical operation (see FIG. 15), and arithmetic data is stored in the memory block 125. And has a calculation auxiliary cell 134d (see FIGS. 10 and 12) for performing a numerical operation using the wide data bus without transmitting data to the processing circuit at high speed and efficiently. Desired arithmetic processing can be performed.
[0181]
In the memory block 125, writing and reading of storage data are performed using a plurality of bit lines BL and / BL and a plurality of word lines WL, whereas operation data D ₀ ~ D _m-1 Are output using a plurality of reference data input lines RDL, / RDL, a plurality of operation data output lines DAL, DBL, and a plurality of cell selection lines WLF (see FIGS. 9 and 11), and stored data Can be independently written and read out, and the operation data can be output, so that more flexible and efficient processing can be performed as a whole.
[0182]
In the memory block 125 constituting the search frame memory 124, a plurality of divisions in which the areas of the plurality of memory cells 140 arranged in a matrix of the memory cell array 131 are divided in the direction along the cell selection line WLF. Each of the plurality of cell selection lines WLF includes a plurality of divided cell selection lines WLFa to WLFe divided corresponding to the plurality of divided regions 131a to 131e. Switching mechanisms 180, 180A, and 180B for switching the divided cell selection lines that are activated simultaneously are arranged (see FIGS. 22, 23, 27, and 28), and are stepped in units of divided cell selection lines. Are output to a plurality of operation data output lines DAL and DBL to perform the operation. It can be processed by the auxiliary cell 134d.
[0183]
In this case, in the plurality of memory cells 140 corresponding to one divided cell selection line, the vertical or horizontal integer columns (one column or m columns (m is an integer of 2 or more)) constituting the image data. Pixel data is stored, and calculation data corresponding to a plurality of pixel data constituting a candidate block can be simultaneously output to a plurality of calculation data output lines DAL and DBL, and numerical calculations using these can be performed. It can be performed in parallel in the operation auxiliary cells 150 and 170 (see FIGS. 19 and 20). Therefore, a plurality of difference absolute values D relating to a plurality of pixel data of a predetermined candidate block for obtaining the motion vector MV ₀ ~ D _m-1 Can be obtained simultaneously, and the data processing efficiency can be greatly improved.
[0184]
Further, by selecting the memory cell 140 by the I / O gate (column switch) of the reference address column address decoder 134a of the memory block 125, a candidate block having an arbitrary shape such as a rectangle or a cross can be dealt with. In addition, since a plurality of memory cells 140 corresponding to one divided cell selection line store pixel data for integer columns in the vertical direction or horizontal direction constituting the image data, the switching mechanism 180 (180A, 180B). And the I / O gate (column switch) can easily move the position of the candidate block in both the horizontal and vertical directions.
[0185]
Further, in the memory block 191 constituting the reference frame memory 123, a plurality of divided areas 201a in which the areas of the plurality of memory cells 210 arranged in a matrix of the memory cell array 201 are divided in the direction along the word line. The plurality of word lines WL are each composed of a plurality of divided word lines WLa to WLe divided corresponding to the plurality of divided regions 201a to 201e, and are simultaneously selected in each of the divided regions 201a to 201e. A switching mechanism 220 for switching the divided cell selection lines is provided (see FIGS. 32 and 33), and a plurality of memory cells 210 arranged in a stepwise manner can be selected in units of divided word lines.
[0186]
In this case, a plurality of memory cells 140 corresponding to one divided word line are stored in integer columns (one column or m columns (m is an integer of 2 or more)) in the vertical or horizontal direction constituting the image data. Pixel data is stored, and a plurality of pixel data constituting the reference block can be read out simultaneously and supplied to the search frame memory 124 at the same time, so that the processing speed can be increased.
[0187]
Further, by selecting the memory cell 210 by the I / O gate (column switch) of the storage data column address decoder 202a of the memory block 191, a reference block having an arbitrary shape such as a rectangle or a cross can be dealt with. Further, since the pixel data for the integer columns in the vertical direction or the horizontal direction constituting the image data is stored in the plurality of memory cells 210 corresponding to one divided word line, the switching mechanism 220 and the I / O gate ( By cooperating with the column switch, the position of the reference block can be easily moved in both the horizontal and vertical directions.
[0188]
The search frame memory 124 is composed of a plurality of, for example, four memory blocks 125a to 125d, which include overlapping pixels corresponding to the boundary portions of the upper left, upper right, lower left, and lower right portions of the search frame. When data is stored and the range of the center pixel of a predetermined candidate block is in the upper left, upper right, lower left, and lower right portions of the search frame, memory blocks 125a, 125b, 125c, and 125d, respectively. The power consumption can be suppressed to a low level.
[0189]
The reference frame memory 123 includes a plurality of, for example, four memory blocks 191a to 191d, which include overlapping pixels corresponding to the boundary portions of the upper left, upper right, lower left, and lower right portions of the reference frame. When data is stored and the range of the center pixel of a predetermined reference block is in the upper left, upper right, lower left, and lower right portions of the reference frame, the memory blocks 191a, 191b, 191c, and 191d, respectively. The power consumption can be suppressed to a low level.
[0190]
As described above, in the search frame memory 124 and the reference frame memory 123, only one of the memory blocks is activated in order to obtain calculation data related to the pixel data of the candidate block and pixel data of the reference block, respectively. Therefore, other memory blocks can be used for other processing. Thereby, complicated processing can be performed efficiently.
[0191]
Further, in the motion vector detection circuit 111 and the motion compensated prediction encoding apparatus 100 configured using the reference frame memory 123 and the search frame memory 124 described above, the processing for detecting the motion vector MV is speeded up and efficient. Can be achieved.
[0192]
In the above-described embodiment, the search frame memory 124 includes the memory blocks 125a to 125d, and the difference absolute value D from these memory blocks 125a to 125d. ₀ ~ D _m-1 Are output as they are, but the difference absolute value D is stored in the search frame memory 124. ₀ ~ D _m-1 It is also conceivable to have a circuit block such as a circuit for accumulating the signal, a circuit for storing the accumulated value, and a circuit for detecting the motion vector MV from the accumulated value. This can further increase the processing speed and efficiency.
[0193]
In the above-described embodiment, the four memory blocks constituting the frame memories 123 and 124 are shown in which the pixel data of each of the upper left, upper right, lower left, and lower right parts is stored. The pixel data stored in each may correspond to a plurality of phases according to the data input order or pixel position.
[0194]
In the above embodiment, in the motion vector detection circuit 111, the determination circuit 128 detects the motion vector MV based on the accumulated value (absolute value sum) of the difference absolute values. A device that detects a motion vector based on the sum of absolute values of the nth power or the like can be similarly configured. In this case, the motion vector detection circuit 111 shown in FIG. 6 may obtain the square value of the difference or the n-th power value of the difference directly from the frame memory 124.
[0195]
In the above-described embodiment, the semiconductor memory device according to the present invention is applied to the motion vector detection circuit 111 and the motion compensated prediction encoding device 100. However, the present invention can be applied to other devices as well. Of course.
[0196]
【The invention's effect】
According to the semiconductor memory device of the present invention, the memory cell that constitutes the memory block includes the arithmetic function unit that performs the logical operation, and the memory block includes the arithmetic assist unit for performing the numerical operation using the arithmetic data. It has a cell and can perform desired arithmetic processing efficiently at high speed without transmitting data to a processing circuit using a wide data bus.
[0197]
According to the semiconductor memory device of the present invention, the storage data is written and read using a plurality of bit lines and a plurality of word lines, and the operation data is output from a plurality of reference data input lines and a plurality of data lines. The calculation data output line and a plurality of cell selection lines are used, and storage data can be written and read independently, and calculation data output can be performed independently, making the overall more flexible and efficient. Processing is possible.
[0198]
According to the semiconductor memory device of the present invention, the region of the plurality of memory cells arranged in a matrix is composed of a plurality of divided regions divided in the direction along the cell selection line, and the plurality of cell selection lines are Each comprising a plurality of divided cell selection lines divided corresponding to the plurality of divided regions, and the memory block has a switching mechanism for switching divided cell selection lines activated simultaneously in each divided region The operation data of a plurality of memory cells arranged in a stepwise manner in units of divided cell selection lines in the direction along the cell selection line of the plurality of memory cells arranged in a matrix is output to the operation data output line. It is possible to process in the auxiliary cell.
[0199]
In this case, a plurality of pixel data constituting a pixel block of an arbitrary shape such as a rectangle or a cross shape by appropriately arranging the pixel data constituting the image data in a plurality of memory cells arranged in a matrix. Can be output simultaneously to multiple operation data output lines, and numerical operations using these can be performed simultaneously in multiple operation auxiliary cells, greatly improving data processing efficiency. In addition, the position of the pixel block can be easily changed. For example, pixel data for integer columns in the vertical direction or horizontal direction constituting the image data is stored in a plurality of memory cells corresponding to one divided cell selection line, so that the above-described pixel block is horizontally or vertically aligned. It can be moved in units of integer pixels in the direction, while it can be moved in units of one pixel in a direction orthogonal thereto.
[0200]
In addition, according to the semiconductor memory device of the present invention, since it is composed of a plurality of memory blocks, only necessary memory blocks can be activated and used, and power consumption can be reduced.
[0201]
According to the semiconductor memory device of the present invention, in addition to one or two or more memory blocks, the semiconductor memory device has a circuit block that performs processing based on operation data output from the memory block. It is possible to increase speed and efficiency.
[0202]
The motion vector detection device and motion compensation predictive coding device according to the present invention use the semiconductor memory device according to the present invention, and can increase the processing speed and efficiency of motion vector detection. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a motion compensated prediction encoding apparatus as an embodiment.
FIG. 2 is a diagram for explaining a block matching method for motion detection.
FIG. 3 is a diagram for explaining a block matching method for motion detection.
FIG. 4 is a diagram for explaining a block matching method for motion detection.
FIG. 5 is a diagram for explaining a block matching method for motion detection.
FIG. 6 is a block diagram showing a configuration of a motion vector detection circuit.
FIG. 7 is a diagram illustrating a configuration of a frame memory (search frame memory) that stores image data of a search frame.
FIG. 8 is a diagram for explaining duplication of pixel data between memory blocks constituting a search frame memory;
FIG. 9 is a diagram illustrating a configuration example of a memory block configuring a search frame memory.
FIG. 10 is a diagram illustrating a configuration example of a memory block configuring a search frame memory.
FIG. 11 is a diagram illustrating another configuration example of a memory block configuring the search frame memory.
FIG. 12 is a diagram illustrating another configuration example of a memory block configuring the search frame memory.
FIG. 13 is a diagram showing a configuration of an SRAM cell.
FIG. 14 is a diagram showing a configuration of a DRAM cell.
FIG. 15 is a diagram showing a configuration of a memory cell having an arithmetic function unit.
FIG. 16 is a diagram showing a configuration of another memory cell having an arithmetic function unit.
FIG. 17 is a diagram showing a configuration of another memory cell having an arithmetic function unit.
FIG. 18 is a diagram showing a configuration of still another memory cell having an arithmetic function unit.
FIG. 19 is a diagram showing a configuration of an operation auxiliary cell for addition and subtraction.
FIG. 20 is a diagram illustrating a configuration of a calculation auxiliary cell for calculating a difference absolute value.
FIG. 21 is a diagram illustrating a configuration of a calculation auxiliary cell (for one pixel data) for obtaining a difference absolute value.
FIG. 22 is a diagram showing pixel data of a search frame and storage positions in the memory cell array.
FIG. 23 is a diagram illustrating a configuration example of a switching mechanism for a divided cell selection line.
FIG. 24 is a diagram showing pixel data of a search frame and storage positions in the memory cell array.
FIG. 25 is a diagram showing pixel data of a search frame and storage positions in the memory cell array.
FIG. 26 is a diagram showing pixel data of a search frame and storage positions in the memory cell array.
FIG. 27 is a diagram illustrating another configuration example of a switching mechanism for a divided cell selection line.
FIG. 28 is a diagram illustrating still another configuration example of a switching mechanism for a divided cell selection line.
FIG. 29 is a diagram illustrating a configuration of a frame memory (reference frame memory) that stores image data of a reference frame.
FIG. 30 is a diagram illustrating a configuration example of a memory block configuring a reference frame memory.
FIG. 31 is a diagram illustrating a configuration example of a memory block configuring a reference frame memory.
FIG. 32 is a diagram showing pixel data of a reference frame and a storage position in the memory cell array.
FIG. 33 is a diagram illustrating a configuration example of a switching mechanism of divided word lines.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Motion compensation prediction encoding apparatus, 101 ... Input terminal, 102 ... Subtractor, 103 ... DCT circuit, 104 ... Quantization circuit, 105 ... Output terminal, 106 ... Inverse quantization circuit, 107 ... Inverse DCT circuit, 108 ... Adder, 109 ... Frame memory, 110 ... Motion compensation circuit, 111 ... Motion vector detection circuit, 121 ... Controller , 122, input terminals, 123, 124, frame memory, 125, 125 a to 125 d, memory block, 126, accumulator, 127, correlation value table, 128, determination circuit, 129: Output terminal, 131: Memory cell array, 131a to 131e ... Divided area, 132 ... Port for storage data input / output, 132a ... Memory for storage data Address decoder, 132b ... I / O buffer, 132c ... address buffer, 133 ... row address decoder for stored data, 133a ... address buffer, 134 ... reference data Input port & operation auxiliary cell, 134a ... reference data column address decoder, 134b ... address buffer, 134c ... I / O buffer, 134d ... operation auxiliary cell, 135 ... Reference data row address decoder, 135a ... Address buffer, 136 ... Control circuit, 140 ... Memory cell, 141 ... Memory cell section, 150 ... Auxiliary cell, 170 ...・ Auxiliary operation cells, 180, 180A, 180B... Switching mechanism, 191, 191a to 191e. 201 ... Memory cell array, 202 ... Storage data input / output port, 203 ... Storage data row address decoder, 204 ... Control circuit, 210 ... Memory cell, 220 ... switching mechanism

Claims (25)

A semiconductor memory device comprising one or two or more memory blocks, each having an arithmetic auxiliary cell and a plurality of memory cells arranged in a matrix ,
The memory cell
A memory cell portion for storing data of “1” or “0”;
A reference data input unit for inputting reference data;
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit;
A cell selection signal input unit for inputting a cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data from the calculation function unit to the calculation data output unit,
The calculation auxiliary cell is
A calculation data input unit for inputting calculation data output to the calculation data output unit of the memory cell;
A calculation unit that performs numerical calculation using the calculation data input to the calculation data input unit;
A calculation data output unit for outputting calculation data obtained by calculation in the calculation unit ,
The area of the plurality of memory cells arranged in a matrix is composed of a plurality of divided areas.
The memory block
A semiconductor memory device comprising: a switching mechanism for controlling a memory cell so that the cell selection signal input unit of the memory cell belonging to the activation target divided region inputs the cell selection signal . The arithmetic function unit of the memory cell performs a plurality of logical operations in parallel,
2. The semiconductor memory device according to claim 1, wherein the operation unit of the operation auxiliary cell performs a numerical operation using a plurality of operation data obtained by the plurality of logic operations. The calculation auxiliary cell is composed of a first calculation auxiliary cell unit and a second calculation auxiliary cell unit,
The first calculation auxiliary cell unit performs a first numerical calculation using calculation data obtained by calculation in the calculation function unit of the memory cell,
The said 2nd operation auxiliary cell part performs 2nd numerical calculation using the operation data obtained by calculating in the said some said 1st operation auxiliary cell part. Semiconductor memory device. The semiconductor memory device according to claim 3, wherein the first numerical calculation is subtraction, and the second numerical calculation is an absolute value calculation. The semiconductor memory device according to claim 1, further comprising a circuit block that performs processing based on operation data output from the one or more memory blocks. A semiconductor memory device comprising one or more memory blocks,
The memory block
Multiple bit lines,
A plurality of word lines orthogonal to the plurality of bit lines;
A reference data input line for inputting reference data parallel to the plurality of bit lines;
A calculation data output line for outputting calculation data parallel to the plurality of bit lines;
A cell selection line for inputting a cell selection signal parallel to the plurality of word lines;
A plurality of memory cells arranged in a matrix and connected to the bit line, the word line, the reference data input line, the arithmetic data output line, and the cell selection line;
A calculation auxiliary cell that performs numerical calculation using at least a part of the calculation data output from the plurality of calculation data output lines,
The memory cell
A memory cell portion for storing data of “1” or “0”;
A reference data input unit connected to the reference data input line for inputting the reference data;
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit connected to the calculation data output line and outputting the calculation data obtained by calculation in the calculation function unit to the calculation data output line;
A cell selection signal input unit connected to the cell selection line for inputting the cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit ,
The area of the plurality of memory cells arranged in the matrix form is composed of a plurality of divided areas divided in the direction along the word line,
Each of the plurality of cell selection lines includes a plurality of divided cell selection lines divided corresponding to the plurality of divided regions,
2. The semiconductor memory device according to claim 1, wherein the memory block has a switching mechanism for switching the divided cell selection lines that are simultaneously activated in each divided region . The arithmetic function unit of the memory cell performs a plurality of logical operations in parallel,
The semiconductor memory device according to claim 6, wherein the memory cell is connected to a plurality of the operation data output lines for outputting a plurality of operation data obtained by the plurality of logic operations, respectively. . The calculation auxiliary cell is
A plurality of first calculation auxiliary cells each performing a first numerical calculation using the calculation data output from a plurality of memory cells corresponding to a predetermined cell selection line selected among the plurality of cell selection lines; ,
For each predetermined number of the plurality of first calculation auxiliary cells, a plurality of second calculation units that respectively perform a second numerical calculation using calculation data obtained by calculation in the first calculation auxiliary cell for each predetermined number. The semiconductor memory device according to claim 6, further comprising: The first numerical operation is subtraction,
The semiconductor memory device according to claim 8, wherein the second numerical calculation is an absolute value calculation. The switching mechanism is
Arranged between the adjacent first divided region and the second divided region,
The first divided cell selection line of the first divided region is arranged in a direction along the bit line with respect to the first divided cell selection line of the second divided region adjacent to the first divided region. The semiconductor memory device according to claim 6 , further comprising a switch circuit that is selectively connected to the second divided cell selection line at the same position or an adjacent position. The memory block further includes a global selection line for inputting the cell selection signal parallel to the word line for each of a plurality of divided cell selection lines arranged in a direction along the word line,
The switching mechanism is
The cell selection signal is selectively supplied from the global selection line to any one of the first and second division cell selection lines that are arranged corresponding to the respective divided regions and are adjacent in the direction along the bit line. The semiconductor memory device according to claim 6 , further comprising a gate circuit. It claims that the plurality of memory cells corresponding to one divided cell select line for each of the divided regions, characterized in that the vertical or horizontal integer column of the pixel data constituting the image data is stored 6 The semiconductor memory device described in 1. The semiconductor memory device according to claim 6, further comprising a circuit block that performs processing based on operation data output from the one or more memory blocks. A semiconductor memory device comprising one or more memory blocks,
The memory block
Multiple bit lines,
A plurality of word lines orthogonal to the plurality of bit lines;
A reference data input line for inputting reference data orthogonal to the plurality of bit lines;
An operation data output line for outputting operation data orthogonal to the plurality of bit lines;
A cell selection line for inputting a cell selection signal orthogonal to the plurality of word lines;
A plurality of memory cells arranged in a matrix and connected to the bit line, the word line, the reference data input line, the arithmetic data output line, and the cell selection line;
A calculation auxiliary cell that performs numerical calculation using at least a part of the calculation data output from the plurality of calculation data output lines,
The memory cell
A memory cell portion for storing data of “1” or “0”;
A reference data input unit connected to the reference data input line for inputting the reference data;
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit connected to the calculation data output line and outputting the calculation data obtained by calculation in the calculation function unit to the calculation data output line;
A cell selection signal input unit connected to the cell selection line for inputting the cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit ,
The area of the plurality of memory cells arranged in a matrix is composed of a plurality of divided areas divided in the direction along the bit line,
Each of the plurality of cell selection lines includes a plurality of divided cell selection lines divided corresponding to the plurality of divided regions,
2. The semiconductor memory device according to claim 1, wherein the memory block has a switching mechanism for switching the divided cell selection lines that are simultaneously activated in each divided region . The arithmetic function unit of the memory cell performs a plurality of logical operations in parallel,
The semiconductor memory device according to claim 14 , wherein the memory cell is connected to a plurality of the operation data output lines for outputting a plurality of operation data obtained by the plurality of logic operations, respectively. . The calculation auxiliary cell is
A plurality of first calculation auxiliary cells each performing a first numerical calculation using the calculation data output from a plurality of memory cells corresponding to a predetermined cell selection line selected among the plurality of cell selection lines; ,
For each predetermined number of the plurality of first calculation auxiliary cells, a plurality of second calculation units that respectively perform a second numerical calculation using calculation data obtained by calculation in the first calculation auxiliary cell for each predetermined number. The semiconductor memory device according to claim 14 , further comprising: The first numerical operation is subtraction,
The semiconductor memory device according to claim 16 , wherein the second numerical calculation is an absolute value calculation. The switching mechanism is
Arranged between the adjacent first divided region and the second divided region,
The first divided cell selection line of the first divided region is arranged in a direction along the word line with respect to the first divided cell selection line of the second divided region adjacent to the first divided region. The semiconductor memory device according to claim 14 , further comprising a switch circuit that is selectively connected to a second divided cell selection line at the same position or an adjacent position. The memory block further includes a global selection line for inputting the cell selection signal parallel to the bit line for each of a plurality of divided cell selection lines arranged in a direction along the bit line,
The switching mechanism is
The cell selection signal is selectively supplied from the global selection line to either one of the first and second divided cell selection lines that are arranged corresponding to the respective divided regions and are adjacent in the direction along the word line. The semiconductor memory device according to claim 14 , further comprising a gate circuit. The plurality of memory cells corresponding to one divided cell select line for each of the divided regions, claim vertical or horizontal integer column of the pixel data constituting the image data is characterized in that it is stored 14 The semiconductor memory device described in 1. The semiconductor memory device according to claim 14 , further comprising a circuit block that performs processing based on operation data output from the one or more memory blocks. A motion vector detection device that detects a motion vector from a reference frame and a search frame that are temporally forward and backward,
A first memory unit for storing a plurality of pixel data constituting the reference frame;
A second memory unit for storing a plurality of pixel data constituting the search frame;
The pixel data of the reference block is read from the first memory unit and supplied to the second memory unit as reference data, and a plurality of candidate blocks in the search range corresponding to the reference block in the second memory unit A memory control unit that controls the difference between the pixel data of the candidate block and the pixel data of the reference block to be calculated for each corresponding pixel data,
A motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each pixel data with respect to each of the plurality of candidate blocks calculated in the second memory unit;
The second memory unit includes one or two or more semiconductor memory blocks having a plurality of auxiliary cells and a plurality of memory cells arranged in a matrix .
The memory cell
A memory cell portion for storing data of “1” or “0”;
A reference data input unit for inputting the reference data;
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit;
A cell selection signal input unit for inputting a cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit,
The calculation auxiliary cell is
A calculation data input unit for inputting calculation data output to the calculation data output unit of the memory cell;
A calculation unit that obtains the difference by performing a numerical calculation using the calculation data input to the calculation data input unit ,
The area of the plurality of memory cells arranged in a matrix is composed of a plurality of divided areas.
The memory block
A motion vector detection device comprising a switching mechanism for controlling a memory cell so that the cell selection signal input unit of the memory cell belonging to the division region to be activated inputs the cell selection signal . A motion vector detection device that detects a motion vector from a reference frame and a search frame that are temporally forward and backward,
A first memory unit for storing a plurality of pixel data constituting the reference frame;
A second memory unit for storing a plurality of pixel data constituting the search frame;
The pixel data of the reference block is read from the first memory unit and supplied to the second memory unit as reference data, and a plurality of candidate blocks in the search range corresponding to the reference block in the second memory unit A memory control unit that controls the difference between the pixel data of the candidate block and the pixel data of the reference block to be calculated for each corresponding pixel data,
A motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each pixel data with respect to each of the plurality of candidate blocks calculated in the second memory unit;
Each of the second memory units is composed of one or more semiconductor memory blocks,
The semiconductor memory block is
Multiple bit lines,
A plurality of word lines orthogonal to the plurality of bit lines;
A reference data input line for inputting the reference data parallel to the plurality of bit lines;
A calculation data output line for outputting calculation data parallel to the plurality of bit lines;
A cell selection line for inputting a cell selection signal parallel to the plurality of word lines;
A plurality of memory cells arranged in a matrix and connected to the bit line, the word line, the reference data input line, the arithmetic data output line, and the cell selection line;
A calculation auxiliary cell that obtains the difference by performing a numerical calculation using at least a part of the calculation data output from the plurality of calculation data output lines,
The memory cell
A memory cell portion for storing data of “1” or “0”, a reference data input portion connected to the reference data input line for inputting the reference data,
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit connected to the calculation data output line and outputting the calculation data obtained by calculation in the calculation function unit to the calculation data output line;
A cell selection signal input unit connected to the cell selection line for inputting the cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit ,
The area of the plurality of memory cells arranged in the matrix form is composed of a plurality of divided areas divided in the direction along the word line,
Each of the plurality of cell selection lines includes a plurality of divided cell selection lines divided corresponding to the plurality of divided regions,
The motion vector detecting device , wherein the memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region . A motion vector detection device that detects a motion vector from a reference frame and a search frame that are temporally forward and backward,
A first memory unit for storing a plurality of pixel data constituting the reference frame;
A second memory unit for storing a plurality of pixel data constituting the search frame;
The pixel data of the reference block is read from the first memory unit and supplied to the second memory unit as reference data, and a plurality of candidate blocks in the search range corresponding to the reference block in the second memory unit A memory control unit that controls the difference between the pixel data of the candidate block and the pixel data of the reference block to be calculated for each corresponding pixel data,
A motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each pixel data with respect to each of the plurality of candidate blocks calculated in the second memory unit;
Each of the second memory units is composed of one or more semiconductor memory blocks,
The semiconductor memory block is
Multiple bit lines,
A plurality of word lines orthogonal to the plurality of bit lines;
A reference data input line for inputting the reference data orthogonal to the plurality of bit lines;
An operation data output line for outputting operation data orthogonal to the plurality of bit lines;
A cell selection line for inputting a cell selection signal orthogonal to the plurality of word lines;
A plurality of memory cells arranged in a matrix and connected to the bit line, the word line, the reference data input line, the arithmetic data output line, and the cell selection line;
A calculation auxiliary cell that obtains the difference by performing a numerical calculation using at least a part of the calculation data output from the plurality of calculation data output lines,
The memory cell
A memory cell portion for storing data of “1” or “0”, a reference data input portion connected to the reference data input line for inputting the reference data,
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit connected to the calculation data output line and outputting the calculation data obtained by calculation in the calculation function unit to the calculation data output line;
A cell selection signal input unit connected to the cell selection line for inputting the cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit ,
The area of the plurality of memory cells arranged in a matrix is composed of a plurality of divided areas divided in the direction along the bit line,
Each of the plurality of cell selection lines includes a plurality of divided cell selection lines divided corresponding to the plurality of divided regions,
The motion vector detecting device , wherein the memory block has a switching mechanism for switching the divided cell selection lines activated simultaneously in each divided region . A motion-compensated predictive coding apparatus that detects a motion vector from a reference frame and a search frame that are temporally moved by a motion vector detection circuit and performs motion compensation using the motion vector,
The motion vector detection circuit is
A first memory unit for storing a plurality of pixel data constituting the reference frame;
A second memory unit for storing a plurality of pixel data constituting the search frame;
The pixel data of the reference block is read from the first memory unit and supplied to the second memory unit as reference data, and a plurality of candidate blocks in the search range corresponding to the reference block in the second memory unit A memory control unit that controls the difference between the pixel data of the candidate block and the pixel data of the reference block to be calculated for each corresponding pixel data,
A motion vector detection unit that detects a motion vector corresponding to the reference block based on a difference for each pixel data with respect to each of the plurality of candidate blocks calculated in the second memory unit;
The second memory unit includes one or two or more semiconductor memory blocks having a plurality of auxiliary cells and a plurality of memory cells arranged in a matrix .
The memory cell
A memory cell portion for storing data of “1” or “0”;
A reference data input unit for inputting the reference data;
An arithmetic function unit for performing a logical operation using the storage data stored in the memory cell unit and the reference data from the reference data input unit;
A calculation data output unit for outputting calculation data obtained by calculation in the calculation function unit;
A cell selection signal input unit for inputting a cell selection signal;
Based on the cell selection signal input to the cell selection signal input unit, an output control unit that outputs the calculation data obtained by calculation in the calculation function unit to the calculation data output unit,
The calculation auxiliary cell is
A calculation data input unit for inputting calculation data output to the calculation data output unit of the memory cell;
A calculation unit that obtains the difference by performing a numerical calculation using the calculation data input to the calculation data input unit ,
The area of the plurality of memory cells arranged in a matrix is composed of a plurality of divided areas.
The memory block
A motion-compensated predictive coding apparatus comprising: a switching mechanism for controlling a memory cell so that the cell selection signal input unit of the memory cell belonging to the division area to be activated inputs the cell selection signal .

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