JP4687044B2 - Display device and driving method of display device - Google Patents

Description

  The present invention relates to a display device and a driving method of the display device, and in particular, pixel circuits (pixels) having electro-optic elements whose luminance is changed by a flowing current as display elements are arranged in a matrix, and each pixel circuit has an active element. And an active matrix display device in which display driving is performed in units of pixels by the active element and a driving method of the display device.

  In a display device, for example, a liquid crystal display device using a liquid crystal cell as a display element of a pixel, a number of pixels including the liquid crystal cell are arranged in a matrix, and the light intensity is controlled for each pixel according to image information to be displayed. Thus, image display driving is performed. This display drive is the same for an organic EL display device using an electro-optical element whose luminance is changed by a flowing current, for example, an organic EL (electroluminescence) element, as a pixel display element.

  However, in the case of an organic EL display device, since it is a so-called self-luminous display device using an organic EL element which is a self-luminous element as a pixel display element, the light intensity from the light source (backlight) is controlled. Compared with a liquid crystal display device, it has advantages such as high image visibility, no need for a backlight, and high response speed. Further, the light emission luminance of the organic EL element is controlled by the value of the current flowing therethrough, that is, the organic EL element is of a current control type, which is greatly different from a liquid crystal display device in which the liquid crystal cell is of a voltage control type.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although the simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device. For this reason, in recent years, an active matrix in which a current flowing in a light emitting element in a pixel is controlled by an active element similarly provided in the pixel, for example, an insulated gate field effect transistor (generally, a thin film transistor (TFT)). There is a lot of development of methods.

  FIG. 11 is a block diagram showing a schematic configuration of an active matrix organic EL display device. In this active matrix organic EL display device, R (red), G (green), and B (blue) pixel circuits (pixels) 51R, 51G, and 51B including organic EL elements are sequentially arranged in a matrix. A pixel array unit 52 is provided. As these pixel circuits 51R, 51G, and 51B, a pixel circuit having a Vth correction function for correcting variation in threshold voltage Vth of a drive transistor that drives an organic EL element is conventionally known (for example, see Patent Document 1). ).

Special table 2002-514320 gazette

  In the pixel array unit 52, for each of the pixel circuits 51R, 51G, and 51B, the write scan line 53, the first drive scan line 54, the second drive scan lines 55R, 55G, and 55B corresponding to each color, and auto-zero for each row. A line 56 is wired, and a data line 57 is wired for each column. Around the pixel array section 52, a write scanning circuit 58 for driving the write scanning line 53, a first driving scanning circuit 59 for driving the first driving scanning line 54, and second driving scanning lines 55R, 55G, 55B. Are arranged, a second drive scanning circuit 60 that drives the auto-zero line, an auto-zero circuit 61 that drives the auto-zero line 56, and a data line drive circuit 62 that supplies a data signal corresponding to the luminance information to the data line 57.

  The writing scanning circuit 58, the first driving scanning circuit 59, the second driving scanning circuit 60, and the auto zero circuit 61 are all constituted by a shift register and the like, and a common clock pulse CK having a pulse width of 1H (H is a horizontal scanning period). And it operates in synchronization with the clock pulse CKX having the opposite phase.

  The writing scanning circuit 58 starts a scanning operation in response to the writing scanning start pulse WSST, and sequentially outputs the writing scanning signal WS in synchronization with the clock pulses CK and CKX. The first driving scanning circuit 59 starts a scanning operation in response to the driving scanning start pulse DS1ST, and sequentially outputs the first driving scanning signal DS1 in synchronization with the clock pulses CK and CKX. The second driving scanning circuit 60 starts a scanning operation in response to the driving scanning start pulse DS2ST, and sequentially outputs the second driving scanning signal DS2 in synchronization with the clock pulses CK and CKX. The auto zero circuit 61 starts the scanning operation in response to the auto zero start pulse AZST, and sequentially outputs the auto zero signal AZ in synchronization with the clock pulses CK and CKX.

  FIG. 12 is a circuit diagram showing an example of a pixel circuit 51 having a Vth correction function used as the pixel circuits 51R, 51G, and 51B. In FIG. 12, the same parts as those in FIG. . Here, the pixel circuit 51R will be described as an example. However, the pixel circuits 51G and 51B have exactly the same circuit configuration as the pixel circuit 51R.

  As is apparent from FIG. 12, the pixel circuit 51 (51R / 51G / 51B) includes, for example, five switching transistors 72 to 76 in addition to the organic EL element 70 and the drive transistor 71 that drives the organic EL element 70. The configuration has two capacitors 77 and 78. Here, a case where an N-channel field effect transistor, for example, a TFT (thin film transistor) is used as the driving transistor 71 and the switching transistors 72 to 76 will be described as an example. Hereinafter, the driving transistor 71 and the switching transistors 72 to 76 are referred to as TFT 71 and TFTs 72 to 76.

  The organic EL element 70 has, for example, a cathode (cathode) connected to a negative power supply potential, for example, a ground potential GND. The TFT 71 is connected in series to the organic EL element 70, that is, the source is connected to the anode (anode) of the organic EL element 70. The TFT 72 has a source connected to the data line 57 and a gate connected to the write scanning line 53. The TFT 73 has a drain connected to the anode of the organic EL element 70, a source connected to a negative power supply potential, for example, the ground potential GND, and a gate connected to the first drive scanning line 54.

  The TFT 74 has a drain connected to the positive power supply potential Vcc, a source connected to the drain of the TFT 71, and a gate connected to the second drive scanning line 55 (55R / 55G / 55B). The TFT 75 is connected between the gate of the TFT 71 and the drain of the TFT 71, and the gate is connected to the auto zero line 56. The TFT 76 is connected between the drain of the TFT 72 and a fixed potential, for example, the ground potential GND, and the gate is connected to the auto zero line 56. The capacitor 77 is connected between the gate of the TFT 71 and the drain of the TFT 72. The capacitor 78 is connected between the gate of the TFT 71 and the source of the TFT 71 (the anode of the organic EL element 70).

  Here, since organic EL elements often have a rectifying property, they are sometimes called OLEDs (Organic Light Emitting Diodes). Therefore, in FIG. 12 and other figures, a symbol of a diode is used as the OLED. However, in the following description, rectification is not necessarily required for the OLED.

  Subsequently, a circuit operation of the active matrix organic EL display device using the pixel circuit 51 having the above configuration as the pixel circuit 51R / 51G / 51B will be described with reference to a timing chart of FIG.

  In FIG. 13, when driving the pixel circuit 51 in a certain row, the write scanning signal WS supplied from the write scanning circuit 58 to the pixel circuit 51 via the write scanning line 53, and the first driving scanning circuit 59 to the first driving. A first drive scanning signal DS1 applied to the pixel circuit 51 via the scanning line 54, and a second drive scanning signal DS applied to the pixel circuit 51 from the second drive scanning circuit 60 via the second drive scanning line 55 (55R / 55G / 55B). The timing relationship between the drive scanning signal DS2 and the auto zero signal AZ supplied from the auto zero circuit 61 to the pixel circuit 51 via the auto zero line 56 is shown.

  First, in a normal light emission state, the write scan signal WS output from the write scan circuit 58, the first drive scan signal DS1 output from the first drive scan circuit 59, and the auto zero signal AZ output from the auto zero circuit 61 are approximately. The second drive scanning signal DS2 output from the second drive scanning circuit 60 is at a substantially Vcc level (hereinafter referred to as “H” level) at the GND level (hereinafter referred to as “L” level). Therefore, the TFTs 72, 73, 75, and 76 are in an off state, and the TFT 74 is in an on state.

At this time, the TFT 71 which is a drive transistor operates as a constant current source because it is designed to operate in a saturation region. As a result, a constant current Ids given by the following equation (1) is supplied to the organic EL element 70 through the TFT 74 and the TFT 71.
Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² (1)
Here, Vth is the threshold value of the TFT 71, μ is the carrier mobility, W is the channel width, L is the channel length, Cox is the gate capacitance per unit area, and Vgs is the gate-source voltage.

  Next, when the auto-zero signal AZ output from the auto-zero circuit 61 becomes “H” level with the TFT 74 turned on, the TFTs 75 and 76 are turned on. As a result, the gate and drain of the TFT 71 are short-circuited via the TFT 75, and a through current flows through the TFT 71, so that the gate-source potential Vgs of the TFT 71 once becomes higher than the threshold voltage Vth.

  After a certain period, the drive scanning signal DS1 output from the first drive scanning circuit 59 becomes “H” level, so that the TFT 73 is turned on. Thereby, since the anode potential of the organic EL element 70 becomes the ground potential GND, the organic EL element 70 enters a non-light emitting state and enters a non-light emitting period. At this time, the constant current Ids corresponding to the gate-source voltage Vgd flows through the path of the TFT 73 to the ground potential GND.

  At the same time as the driving scanning signal DS1 becomes “H” level, the driving scanning signal DS2 output from the second driving scanning circuit 60 becomes “L” level, whereby the TFT 74 is turned off, and the threshold voltage Vth of the TFT 71 is canceled ( The threshold is canceled during correction. At this time, the TFT 71 operates in a saturation region because the gate and drain are short-circuited via the TFT 75. Further, since the capacitors 77 and 78 are connected in parallel to the gate of the TFT 71, the voltage Vgd between the gate and the drain of the TFT 71 gradually decreases with time.

  After a certain period of time, the gate-source voltage Vgs of the TFT 71 becomes the threshold voltage Vth of the TFT 71. At this time, the capacitor 77 is charged with a voltage of −Vth, and the capacitor 78 is charged with a voltage of Vth. Thereafter, when the auto zero signal AZ output from the auto zero circuit 61 changes from the “H” level to the “L” level with the TFTs 72 and 74 turned off and the TFT 73 turned on, the TFTs 75 and 76 are turned off, and the threshold cancel period Is the end. At this time, the capacitor 77 holds the voltage of −Vth, and the capacitor 78 holds the voltage of Vth.

  Next, when the TFTs 72, 75, and 76 are turned off and the TFTs 73 and 74 are turned on, the writing scanning signal WS output from the writing scanning circuit 58 changes from the “L” level to the “H” level. enter. In this writing period, the TFT 72 is turned on, and the input signal voltage Vin supplied through the data line 57 is written. By writing the input signal voltage Vin, the voltage at the input terminal of the capacitor 77 changes by ΔV. This voltage change amount ΔV is transmitted to the gate of the TFT 71 by coupling by the capacitor 77.

At this time, the gate voltage Vg of the TFT 71 is a value called a threshold voltage Vth, and the coupling amount ΔV is expressed by the following equation (2) according to the capacitance value C1 of the capacitor 77, the capacitance value C2 of the capacitor 78, and the parasitic capacitance value C3 of the TFT 71. To be determined.
ΔV = {C1 / (C1 + C2 + C3)} · Vin (2)
Therefore, if the capacitance values C1 and C2 of the capacitors 77 and 78 are set sufficiently larger than the parasitic capacitance value C3 of the TFT 71, the coupling amount ΔV to the gate of the TFT 71 is not affected by the threshold voltage Vth of the TFT 71. , Determined only by the capacitance values C1 and C2 of the capacitors 77 and 78.

  The writing scanning signal WS output from the writing scanning circuit 58 transits from the “H” level to the “L” level, and the TFT 72 is turned off, so that the writing period of the input signal voltage Vin ends. After the end of the writing period, the drive scanning signal DS1 output from the first drive scanning circuit 59 becomes “L” level while the TFTs 72, 75, and 76 are turned off, so that the TFT 73 is turned off. The TFT 74 is turned on when the drive scanning signal DS2 output from the two-drive scanning circuit 60 becomes “H” level.

  When the TFT 74 is turned on, the drain potential of the TFT 71 rises to the power supply potential Vcc. Since the gate-source voltage Vgs of the TFT 71 is constant, the TFT 71 supplies a constant current Ids to the organic EL element 70. At this time, the anode potential of the organic EL element 70 rises to a voltage Vx at which the constant current Ids flows through the organic EL element 70, and as a result, the organic EL element 70 emits light.

  In the pixel circuit 51 that performs the above-described series of operations, when the light emission time of the organic EL element 70 becomes longer, the IV characteristic of the organic EL element 70 changes. Therefore, the anode potential of the organic EL element 70 also changes. However, since the gate-source potential Vgs of the TFT 71 is maintained at a constant value, the current flowing through the organic EL element 70 does not change. Therefore, even if the IV characteristic of the organic EL element 70 is deteriorated, the constant current Ids always flows through the organic EL element 70, so that the light emission luminance of the organic EL element 70 does not change.

  Further, the threshold voltage Vth of the TFT 71 can be canceled (corrected) by the action of the TFT 75 during the threshold cancellation period. Therefore, since the constant current Ids can always flow through the organic EL element 70 without being affected by the variation in the threshold voltage Vth of the TFT 71, a high-quality image can be obtained.

  By the way, in the pixel circuit 51 having the Vth correction function described above, in order to surely perform Vth correction at the time of black display, as apparent from the timing chart of FIG. 13, the active state of the drive scanning signal DS2 (this example) In this case, the “H” level state) and the active state of the auto zero signal AZ (in this example, the “H” level state) are overlapped for a certain period. By providing this overlap period, as described above, the gate and drain of the TFT 71 are short-circuited via the TFT 75, and a through current flows through the TFT 71. Therefore, the gate-source potential Vgs of the TFT 71 is higher than the threshold voltage Vth. Once it grows.

  As described above, the active states of the drive scanning signal DS2 and the auto-zero signal AZ are overlapped, and the gate-source potential Vgs of the TFT 71 is once made larger than the threshold voltage Vth, and then the drive scanning signal DS2 is changed from the “H” level. By shifting to the “L” level and simultaneously changing the drive scanning signal DS1 from the “L” level to the “H” level, the operation of canceling (correcting) the threshold voltage Vth of the TFT 71 is reliably performed.

  However, in this overlap period, the source potential of the TFT 71 becomes an operating point where the organic EL element 70 is turned on, and the organic EL element 70 emits light. The overlap period is, for example, about several tens of microseconds, which is a short period compared to the 60 Hz field period (16.7 msec), and light emission in the overlap period is also very small. Therefore, this minute emission is not a problem in white display.

  On the other hand, during black display, slight light emission during the overlap period causes black floating. Here, black floating means a phenomenon in which black cannot be displayed as a complete black. FIG. 14 shows the operating voltage during black display. During black display, the gate-source potential Vgs of the TFT 71 is kept at the threshold voltage Vth even during the light emission period in which the drive scanning signal DS2 is at the “H” level. Therefore, the source potential of the TFT 71 is also maintained at the ground potential GND, and the organic EL element 70 does not emit light during the light emission period.

  However, in the overlap period, as shown in FIG. 14, since the through current flows through the TFT 71, the source potential of the TFT 71 rises. Thereby, the organic EL element 70 emits light. The luminance of the organic EL element 70 is determined by the average value of the amount of light emitted within one field. For this reason, the light emission in the overlap period increases the luminance that should be black, resulting in black floating. As a result, the contrast is lowered.

  Incidentally, in the active matrix organic EL display device shown in FIG. 11, the second driving scanning circuit 60 that generates the driving scanning signal DS2 and the auto zero circuit 61 that generates the auto zero signal AZ have a common clock as described above. It is configured by a shift register or the like that performs a shift operation in synchronization with a pulse CK (clock pulse CKX having a reverse phase).

  Thus, by generating the drive scanning signal DS2 and the auto zero signal AZ based on the common clock pulses CK and CKX, the overlap period in each active state of the drive scanning signal DS2 and the auto zero signal AZ is as shown in FIG. As is apparent from the timing chart, the integer multiple of the pulse width (1H) of the clock pulses CK and CKX, which is 1H at the shortest. Depending on the drive frequency of the display device, the 1H period is 20 [μsec] or more, for example, about 30 [μsec].

  On the other hand, the relationship between the overlap period and the black floating luminance is generally expressed as shown in the characteristic diagram of FIG. 16, although it varies depending on characteristics such as the mobility of the transistors constituting the pixel circuit. Specifically, the overlap period is 5 [μsec], the black floating luminance is 0.08 [Nit], 10 [μsec] is 0.16 [Nit], 20 [μsec] is 0.32 [Nit], 30 [Μsec] is 0.48 [Nit].

  Here, in order to realize a contrast of 1000: 1 [= (white luminance) / (black luminance)] with an all white of 200 [Nit], the black floating luminance is 0.20 [Nit] or less as a minimum. Necessary. However, the overlap period in each active state of the drive scanning signal DS2 and the auto-zero signal AZ is 1H at the shortest as described above. Therefore, the black floating luminance is 0.48 [Nit], and the total white is 200 [Nit]. Therefore, a contrast of 1000: 1 cannot be realized.

  Here, the pixel circuit 51 having the circuit configuration shown in FIG. 12 has been described as an example of the pixel circuit having the Vth correction function. However, the pixel circuit having the Vth correction function having another circuit configuration is also described above. There is a problem that black floating occurs at the time of clock display due to abnormal light emission due to the through current flowing in the driving transistor in the wrap period.

  The present invention has been made in view of the above problems, and an object of the present invention is to perform abnormal light emission due to a through current flowing in a drive transistor in an overlap period in each active state of the drive scanning signal DS and the auto-zero signal AZ. It is an object of the present invention to provide a display device and a display device driving method capable of preventing black floating caused by the above and enabling high contrast.

  In order to achieve the above object, according to the present invention, a drive transistor that drives an electro-optical element according to pixel information, a first transistor that controls light emission / non-light emission of the electro-optical element, and a gate transistor of the drive transistor In a display device in which pixel circuits including at least a second transistor for selectively short-circuiting between drains are arranged in a matrix, a first clock pulse serving as a reference for generating a drive scanning signal for driving the first transistor is used. On the other hand, a configuration is adopted in which the phase of the second clock pulse having the same cycle as that of the first clock pulse serving as a reference for generating the auto-zero signal for driving the second transistor is made different.

  Since the second clock pulse has a phase difference with respect to the first clock pulse, the overlap period in each active state of the drive scanning signal and the auto-zero signal becomes shorter than the pulse width of the first clock pulse. That is, the overlap period can be set shorter than in the prior art, which can only be set to an integer multiple of 1H. As a result, it is possible to suppress black float caused by abnormal light emission due to the through current flowing in the drive transistor in the overlap period in each active state of the drive scanning signal and the auto zero signal.

  According to the present invention, it is possible to suppress black floating caused by abnormal light emission due to a through current flowing in the driving transistor in the overlap period in each active state of the driving scanning signal and the auto zero signal, thereby maintaining the black luminance while maintaining the white luminance. Therefore, high contrast can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an active matrix display device according to an embodiment of the present invention. Here, as the active matrix display device according to the present embodiment, electro-optical elements whose luminance changes depending on a flowing current, for example, R, G, and B pixel circuits (pixels) 11R, 11G including an organic EL element as a display element. , 11B will be described by taking as an example the case of an organic EL display device having a pixel array unit 12 in which two-dimensionally arranged in a matrix.

  In the pixel array unit 12, for each of the pixel circuits 11R, 11G, and 11B, the write scanning line 13, the first driving scanning line 14, the second driving scanning lines 15R, 15G, and 15B corresponding to each color, and auto-zero for each row. A line 16 is wired, and a data line 17 is wired for each column. Around the pixel array section 12, a write scanning circuit 18 that drives the write scanning line 13, a first drive scanning circuit 19 that drives the first drive scanning line 14, and second drive scanning lines 15R, 15G, and 15B. Are arranged, a second drive scanning circuit 20 that drives the auto zero line, an auto zero circuit 21 that drives the auto zero line 16, and a data line drive circuit 22 that supplies a data signal corresponding to the luminance information to the data line 17.

  The writing scanning circuit 18, the first driving scanning circuit 19, the second driving scanning circuit 20, and the auto zero circuit 21 are all constituted by a shift register or the like. The writing scanning circuit 18, the first driving scanning circuit 19 and the second driving scanning circuit 20 operate in synchronization with a common clock pulse CK having a pulse width of 1H and a clock pulse CKX having a reverse phase. The auto zero circuit 21 operates in synchronization with clock pulses AZCK and AZCKX having the same cycle as the clock pulses CK and CKX and having a predetermined phase difference with respect to the clock pulses CK and CKX. The phase difference between the clock pulses CK and CKX and the clock pulses AZCK and AZCKX will be described later.

  The writing scanning circuit 18 starts a scanning operation in response to the writing scanning start pulse WSST, and sequentially outputs the writing scanning signal WS in synchronization with the clock pulses CK and CKX. The first driving scanning circuit 19 starts a scanning operation in response to the driving scanning start pulse DS1ST, and sequentially outputs the first driving scanning signal DS1 in synchronization with the clock pulses CK and CKX. The second driving scanning circuit 20 starts a scanning operation in response to the driving scanning start pulse DS2ST, and sequentially outputs the second driving scanning signal DS2 in synchronization with the clock pulses CK and CKX. The auto zero circuit 21 starts the scanning operation in response to the auto zero start pulse AZST, and sequentially outputs the auto zero signal AZ in synchronization with the clock pulses AZCK and AZCKX.

  In the active matrix organic EL display device having such a configuration, the write scanning circuit 18, the drive scanning circuits 19, 20 and the auto zero circuit 21 are arranged on the display panel (substrate) on which the pixel array unit 12 is formed. 12 may be arranged together or may be arranged outside the display panel.

(Pixel circuit 1)
FIG. 2 is a circuit diagram illustrating a configuration of a pixel circuit 1 (hereinafter referred to as “pixel circuit 11A”) having a Vth correction function used as the pixel circuits 11R, 11G, and 11B. This pixel circuit 11A is the pixel circuit 51 itself described in the prior art.

  As apparent from FIG. 2, the pixel circuit 11 </ b> A according to this example includes, for example, five switching transistors 32 to 36 and two capacitors in addition to the organic EL element 30 and the drive transistor 31 that drives the organic EL element 30. 37, 38. Here, the case where an N-channel field effect transistor, for example, a TFT is used as the driving transistor 31 and the switching transistors 32 to 36 will be described as an example. Hereinafter, the driving transistor 31 and the switching transistors 32-36 are referred to as TFT 31 and TFTs 32-36.

  The organic EL element 30 has, for example, a cathode connected to a negative power supply potential, for example, a ground potential GND. The TFT 31 is connected in series to the organic EL element 30, that is, the source is connected to the anode of the organic EL element 70. The TFT 32 is a data write transistor, and has a source connected to the data line 17 and a gate connected to the write scanning line 13. The TFT 33 has a drain connected to the anode of the organic EL element 30, a source connected to a negative power supply potential, for example, a ground potential GND, and a gate connected to the first drive scanning line 14.

  The TFT 34 is a transistor that controls light emission / non-light emission (duty) of the organic EL element 30. The drain is the positive power supply potential Vcc, the source is the drain of the TFT 31, and the gate is the second drive scanning line 15 (15 R / 15 G / 15B). The TFT 35 is connected between the gate of the TFT 31 and the drain of the TFT 31, and the gate is connected to the auto zero line 16. The TFT 36 is connected between the drain of the TFT 32 and a fixed potential, for example, the ground potential GND, and the gate is connected to the auto-zero line 16. The capacitor 37 is connected between the gate of the TFT 31 and the drain of the TFT 32. The capacitor 38 is connected between the gate of the TFT 31 and the source of the TFT 31 (the anode of the organic EL element 30).

  Next, the circuit operation of the active matrix organic EL display device using the pixel circuit 11A having the above configuration as the pixel circuit 11R / 11B / 11B will be described with reference to the timing chart of FIG.

  In FIG. 3, when driving the pixel circuit 11 in a certain row, the write scanning signal WS supplied from the writing scanning circuit 18 to the pixel circuit 11 via the writing scanning line 13, and the first driving scanning circuit 19 to the first driving. A drive scanning signal DS1 supplied to the pixel circuit 11 via the scanning line 14, and a driving scanning signal DS2 supplied from the second driving scanning circuit 20 to the pixel circuit 11 via the second driving scanning line 15 (15R / 15G / 15B). The timing relationship of the auto zero signal AZ supplied from the auto zero circuit 21 to the pixel circuit 11 via the auto zero line 16 and the waveforms of the gate potential and the source potential of the TFT 31 are shown.

  Here, the drive scanning signal DS2 is a pulse signal used to control light emission / non-light emission of the organic EL element 30, that is, the duty, and the auto zero signal AZ is used to correct the threshold voltage Vth of the TFT 31. It is a pulse signal.

  First, in a normal light emission state, the write scan signal WS output from the write scan circuit 18, the drive scan signal DS1 output from the first drive scan circuit 19, and the auto zero signal AZ output from the auto zero circuit 21 are "L". Since the drive scanning signal DS2 output from the second drive scanning circuit 20 is at the “H” level, the TFTs 32, 33, 35, and 36 are turned off, and the TFT 34 is turned on. At this time, the TFT 31, which is a driving transistor, is designed to operate in a saturation region, and thus operates as a constant current source. As a result, the organic EL element 30 is supplied with the constant current Ids given by the above-described formula (1) through the TFT 34 and the TFT 31.

  Next, when the auto-zero signal AZ output from the auto-zero circuit 21 becomes “H” level in a state where the TFT 34 is turned on, the TFTs 35 and 36 are turned on. As a result, the gate and drain of the TFT 31 are short-circuited via the TFT 35, and a through current flows through the TFT 31, so that the gate-source potential Vgs of the TFT 31 once becomes higher than the threshold voltage Vth.

  After a certain period, the drive scanning signal DS1 output from the first drive scanning circuit 19 becomes “H” level, so that the TFT 33 is turned on. Thereby, since the anode potential of the organic EL element 30 becomes the ground potential GND, the organic EL element 30 enters a non-light emitting state and enters a non-light emitting period. At this time, a constant current Ids corresponding to the gate-source voltage Vgd flows through the path of the TFT 33 to the ground potential GND.

  At the same time as the driving scanning signal DS1 becomes “H” level, the driving scanning signal DS2 output from the second driving scanning circuit 20 becomes “L” level, whereby the TFT 34 is turned off, and the threshold voltage Vth of the TFT 31 is canceled ( The threshold is canceled during correction. At this time, the TFT 71 operates in a saturation region because the gate and drain are short-circuited via the TFT 35. Further, since the capacitors 37 and 38 are connected in parallel to the gate of the TFT 31, the voltage Vgd between the gate and the drain of the TFT 31 gradually decreases with the passage of time.

  After a certain period, the gate-source voltage Vgs of the TFT 31 becomes the threshold voltage Vth of the TFT 31. At this time, the capacitor 37 is charged with a voltage of −Vth, and the capacitor 38 is charged with a voltage of Vth. Thereafter, when the TFTs 32 and 34 are turned off and the TFT 33 is turned on and the auto zero signal AZ output from the auto zero circuit 21 transits from the “H” level to the “L” level, the TFTs 35 and 36 are turned off, and the threshold cancel period Is the end. At this time, the capacitor 37 holds the voltage of −Vth, and the capacitor 38 holds the voltage of Vth.

  Next, the write scanning signal WS output from the write scanning circuit 18 with the TFTs 32, 35, and 36 turned off and the TFTs 33 and 34 turned on transitions from the “L” level to the “H” level. enter. In this writing period, the TFT 32 is turned on, and the input signal voltage Vin given through the data line 17 is written. By writing the input signal voltage Vin, the voltage at the input terminal of the capacitor 37 changes by ΔV. This voltage change amount ΔV is transmitted to the gate of the TFT 31 by coupling by the capacitor 37.

  At this time, the gate voltage Vg of the TFT 31 is a value called the threshold voltage Vth, and the coupling amount ΔV is expressed by the equation (2) described above according to the capacitance value C1 of the capacitor 37, the capacitance value C2 of the capacitor 38, and the parasitic capacitance value C3 of the TFT 31. To be determined. Therefore, if the capacitance values C1 and C2 of the capacitors 37 and 38 are set sufficiently larger than the parasitic capacitance value C3 of the TFT 31, the coupling amount ΔV to the gate of the TFT 31 is not affected by the threshold voltage Vth of the TFT 31. , Determined only by the capacitance values C1 and C2 of the capacitors 37 and 38.

  The writing scanning signal WS output from the writing scanning circuit 18 changes from the “H” level to the “L” level, and the TFT 32 is turned off, so that the writing period of the input signal voltage Vin ends. After the writing period ends, the drive scanning signal DS1 output from the first drive scanning circuit 19 becomes “L” level while the TFTs 32, 35, and 36 are turned off, so that the TFT 33 is turned off. The TFT 34 is turned on when the drive scanning signal DS2 output from the two-drive scanning circuit 20 becomes “H” level.

  When the TFT 34 is turned on, the drain potential of the TFT 31 rises to the power supply potential Vcc. Since the gate-source voltage Vgs of the TFT 31 is constant, the TFT 31 supplies a constant current Ids to the organic EL element 30. At this time, the anode potential of the organic EL element 30 rises to a voltage Vx at which the constant current Ids flows through the organic EL element 30, and as a result, the organic EL element 30 emits light.

  In the active matrix type organic EL display device using the pixel circuit 11A that performs the above-described series of operations as the pixel circuit 11R / 11G / 11B, if the light emission time of the organic EL element 30 becomes long, the I− V characteristics change. Therefore, the anode potential of the organic EL element 30 also changes. However, since the gate-source potential Vgs of the TFT 31 is maintained at a constant value, the current flowing through the organic EL element 30 does not change. Therefore, even if the IV characteristic of the organic EL element 30 is deteriorated, the constant current Ids always flows through the organic EL element 30, so that the light emission luminance of the organic EL element 30 does not change.

  In addition, in the threshold cancellation period, the drain and gate of the TFT 31 are short-circuited by the TFT 35, whereby the threshold voltage Vth of the TFT 31 can be canceled (corrected). Therefore, since the constant current Ids can always flow through the organic EL element 30 without being affected by variations in the threshold voltage Vth of the TFT 31, a high-quality image can be obtained.

  Next, the phase difference between the clock pulses CK and CKX and the clock pulses AZCK and AZCKX will be described. The phase difference between the clock pulses CK and CKX and the clock pulses AZCK and AZCKX is set in the phase difference setting circuit 23. Specifically, in the timing chart of FIG. 4, when the phase difference α of the clock pulse AZCK with respect to the clock pulse CK is set to about 30 [μsec], for example, the pulse width (1H) of the clock pulses CK and AZCK is 10 to 29. About [μsec], preferably about 17.5 to 29 [μsec] is set.

  In this way, by making the phases of the clock pulses AZCK and AZCKX different from the clock pulses CK and CKX, the drive scanning signal DS2 (DS2) generated by the second drive scanning circuit 20 based on the clock pulses CK and CKX. −1, DS2-2,...) And autozero signals AZ (AZ-1, AZ-2,...) Generated in the autozero circuit 21 based on the clock pulses AZCK, AZCKX in the active state. Can be set shorter than the conventional shortest overlap period 1H (for example, 30 [μsec]).

  Specifically, when the phase difference α of the clock pulse AZCK with respect to the clock pulse CK is set to about 10 to 29 [μsec], the active state of the drive scanning signal DS2 (in this example, the “H” level state) ) And the active state of the auto zero signal AZ (in this example, the state of the “H” level) is approximately 20 to 1 [μsec]. Here, the reason why the overlap period of at least about 1 [μsec] is necessary is to ensure that the Vth correction (cancel) operation of the TFT 31 is performed. That is, in order to reliably perform the Vth correction operation, the gate-source potential Vgs of the TFT 31 is once made larger than the threshold voltage Vth, and then the drive scanning signal DS2 is changed from the “H” level to the “L” level. It takes a time (overlap period) of at least about 1 [μsec] to shift the drive scanning signal DS1 from the “L” level to the “H” level.

  When the phase difference α is set to about 17.5 to 29 [μsec], the overlap period in each active state of the drive scanning signal DS2 and the auto zero signal AZ is about 12.5 to 1 [μsec]. It becomes. By setting the overlap period to 12.5 [μsec] or less, as apparent from the characteristic diagram of FIG. 16, the drive scan signal DS2 and the auto zero signal AZ flow in the TFT 31 in the overlap period in each active state. The black floating brightness resulting from abnormal light emission due to the through current can be suppressed to 0.20 [Nit] or less. As a result, the black luminance can be lowered while maintaining the white luminance, so that the contrast of the display device (display panel) can be increased, specifically, the contrast of 1000: 1 can be realized with all white 200 [Nit].

Here, the overlap period is set to 12.5 [μsec] or less, but this is a preferable value. If the overlap period is shorter than 1H period, the overlap period is only an integral multiple of 1H. Compared to the conventional technology that could not be set, the black float can be suppressed and a high contrast can be achieved. It is apparent from the characteristic diagram of FIG. 16 that the shorter the overlap period, the greater the effect. However, for the reasons described above, an overlap period of about 1 [μsec] is a minimum necessary for reliably performing Vth correction.

(Pixel circuit 2)
FIG. 5 is a circuit diagram showing a configuration of a pixel circuit 2 having a Vth correction function (hereinafter referred to as “pixel circuit 11B”) used as the pixel circuits 11R, 11G, and 11B. Are denoted by the same reference numerals.

  In the previous pixel circuit 11A, N-channel transistors are used for all of the TFTs 31 to 36, but in the pixel circuit 11B according to this example, P-channel transistors are used only for the TFTs 34 that operate with the second drive scanning signal DS2. The composition is taken. As a result, as shown in the timing chart of FIG. 6, the second drive scanning circuit 20 outputs “L” level (active) in the light emission period and “H” level (non-light emission) as the second drive scanning signal DS2. Active) is output.

  Thus, in the pixel circuit 11B using a P-channel transistor instead of an N-channel transistor as the TFT 34, the basic circuit operation is basically the same as the circuit operation of the pixel circuit 11A.

  Also in the active matrix organic EL display device using the pixel circuit 11B having the above configuration as the pixel circuit 11R / 11B / 11B, the active state of the drive scanning signal DS2 (in this example, the “L” level state) and the auto zero signal AZ When the overlap period in the active state (in this example, the “H” level state) is shorter than 1H, specifically when 1H is set to about 30 [μsec], for example, it is 20 [μsec] or less, preferably 12 By setting to about 5 to 1 [μsec], it is possible to suppress black floating caused by abnormal light emission due to a through current flowing in the TFT 31 in the overlap period in each active state of the drive scanning signal DS and the auto zero signal AZ. it can. As a result, the black luminance can be lowered while maintaining the white luminance, so that a high-contrast display panel can be obtained.

(Pixel circuit 3)
FIG. 7 is a circuit diagram showing a configuration of a pixel circuit 3 having a Vth correction function (hereinafter, referred to as “pixel circuit 11C”) used as the pixel circuits 11R, 11G, and 11B. In FIG. Are denoted by the same reference numerals.

  The pixel circuit 11C according to this example is configured to include four switching TFTs 32 and 34 to 36 in addition to the TFT 31 that is a driving transistor. Only the TFT 31 is composed of a P-channel transistor, and the TFTs 32 and 34 to 36 are composed of N-channel transistors.

  In FIG. 7, the source of the TFT 31 is connected to the positive power supply potential Vcc. The TFT 34 is connected between the drain of the TFT 31 and the anode of the organic EL element 30. The TFT 35 is connected between the gate of the TFT 31 and the drain of the TFT 31. The TFT 36 is connected between the drain of the TFT 32 and the ground potential GND. The capacitor 37 is connected between the gate of the TFT 31 and the drain of the TFT 32. The capacitor 38 is connected between the positive power supply potential Vcc and the drain of the TFT 32.

  In the active matrix organic EL display device using the pixel circuit 11C having the above configuration as the pixel circuit 11R / 11B / 11B, the switching transistor corresponding to the TFT 33 in FIG. 2 does not exist, so the first drive scanning signal DS1 becomes unnecessary. One drive scanning signal DS is used. Therefore, in the active matrix organic EL display device, the first drive scanning circuit 19 that generates the first drive scanning signal DS1 is also unnecessary.

  Also in the pixel circuit 11C having the above configuration, the basic circuit operation for Vth correction is basically the same as the circuit operation of the pixel circuit 11A. FIG. 8 shows the timing relationship between the write scanning signal WS, the driving scanning signal DS, and the auto zero signal AZ, and the waveforms of the gate potential of the TFT 31 and the anode potential of the organic EL element 30.

  Also in the active matrix organic EL display device using the pixel circuit 11C having the above configuration as the pixel circuit 11R / 11B / 11B, the active state of the drive scanning signal DS (in this example, the “H” level state) and the auto zero signal AZ When the overlap period in the active state (in this example, the “H” level state) is shorter than 1H, specifically when 1H is set to about 30 [μsec], for example, it is 20 [μsec] or less, preferably 12 By setting to about 5 to 1 [μsec], it is possible to suppress black floating caused by abnormal light emission due to a through current flowing in the TFT 31 in the overlap period in each active state of the drive scanning signal DS and the auto zero signal AZ. it can. As a result, the black luminance can be lowered while maintaining the white luminance, so that a high-contrast display panel can be obtained.

(Pixel circuit 4)
FIG. 9 is a circuit diagram showing a configuration of a pixel circuit 4 having a Vth correction function (hereinafter referred to as “pixel circuit 11D”) used as the pixel circuits 11R, 11G, and 11B. In FIG. Are denoted by the same reference numerals.

  In the pixel circuit 11B, a P-channel transistor is used only for the TFT 34 and in the pixel circuit 11C only for the TFT 31. However, in the pixel circuit 11D according to this example, in addition to both the TFTs 31 and 34, the TFT 35 that operates with the auto-zero signal AZ. , 36 also employs a configuration using P-channel transistors instead of N-channel transistors.

  In FIG. 9, the TFT 31 and the TFT 34 are connected in series between the anode of the organic EL element 30 and the positive power supply potential Vcc. The TFT 35 is connected between the drain of the TFT 32 and the source of the TFT 31 (the drain of the TFT 34). The TFT 36 is connected between the gate of the TFT 31 and a predetermined fixed potential Vini. The capacitor 37 is connected between the gate of the TFT 31 and the drain of the TFT 32. The capacitor 38 is connected between the positive power supply potential Vcc and the drain of the TFT 32.

  Even in the active matrix organic EL display device using the pixel circuit 11D having the above configuration as the pixel circuit 11R / 11B / 11B, there is no switching transistor corresponding to the TFT 33 in FIG. The first drive scanning circuit 19 that generates the drive scanning signal DS1 is not necessary.

  In the pixel circuit 11D configured as described above, the basic circuit operation for Vth correction is basically the same as the circuit operation of the pixel circuit 11A. FIG. 10 shows the timing relationship of the write scanning signal WS, the driving scanning signal DS, and the auto zero signal AZ, and the waveforms of the gate potential and the source potential of the TFT 31.

  Also in the active matrix organic EL display device using the pixel circuit 11D having the above configuration as the pixel circuit 11R / 11B / 11B, the active state of the drive scanning signal DS (in this example, the “L” level state) and the auto zero signal AZ When the overlap period in the active state (in this example, the “L” level state) is shorter than 1H, specifically when 1H is about 30 [μsec], for example, it is 20 [μsec] or less, preferably 12 By setting to about 5 to 1 [μsec], it is possible to suppress black floating caused by abnormal light emission due to a through current flowing in the TFT 31 in the overlap period in each active state of the drive scanning signal DS and the auto zero signal AZ. it can. As a result, the black luminance can be lowered while maintaining the white luminance, so that a high-contrast display panel can be obtained.

  The pixel circuits 11 </ b> A to 11 </ b> B described above as examples of application are merely examples, and are not limited to these. While controlling the light emission / non-light emission of the organic EL element 30 based on the drive scanning signal DS (DS2), All pixel circuits having a Vth correction function for correcting the Vth of the TFT 31 as a driving transistor based on the auto-zero signal AZ can be used as the pixel circuits 11R / 11B / 11B of the active matrix organic EL display device.

  In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as a pixel display element (electro-optical element) has been described as an example. However, the present invention is not limited to this and flows. The present invention can be applied to all display devices using an electro-optical element whose luminance changes with current as a display element of a pixel.

1 is a block diagram illustrating a configuration of an active matrix organic EL display device according to an embodiment of the present invention. 2 is a circuit diagram showing a configuration of a pixel circuit 1. FIG. 3 is a timing chart for explaining the circuit operation of an active matrix organic EL display device using the pixel circuit 1. 4 is a timing chart showing a phase relationship between a clock pulse CK and a clock pulse AZCK and an overlap relationship between a drive scanning signal DS2 and an auto zero signal AZ. 2 is a circuit diagram showing a configuration of a pixel circuit 2. FIG. 3 is a timing chart for explaining the circuit operation of an active matrix organic EL display device using a pixel circuit 2; 3 is a circuit diagram illustrating a configuration of a pixel circuit 3. FIG. 3 is a timing chart for explaining the circuit operation of an active matrix organic EL display device using a pixel circuit 3; 3 is a circuit diagram illustrating a configuration of a pixel circuit 4. FIG. 3 is a timing chart for explaining circuit operations of an active matrix organic EL display device using a pixel circuit 4; It is a block diagram which shows the outline of a structure of the active matrix type organic electroluminescence display which concerns on a prior art example. It is a circuit diagram which shows an example of a structure of the pixel circuit which concerns on a prior art example. 6 is a timing chart showing a timing relationship among a write scan signal WS, a first drive scan signal DS1, a second drive scan signal DS2, and an auto zero signal AZ. It is a timing chart which shows the operating voltage at the time of black display. 4 is a timing chart showing an overlap relationship between a drive scanning signal DS2 and an auto zero signal AZ with respect to a clock pulse CK. It is a characteristic view which shows the relationship between an overlap period and black floating brightness.

Explanation of symbols

  11A to 11D: Pixel circuit (pixel), 12: Pixel array unit, 13: Write scanning line, 14: First driving scanning line, 15 (15R, 115G, 15B) ... Second driving scanning line, 16: Auto zero line, DESCRIPTION OF SYMBOLS 17 ... Data line, 18 ... Write scanning circuit, 19 ... 1st drive scanning circuit, 20 ... 2nd drive scanning circuit, 21 ... Auto zero circuit, 22 ... Data line drive circuit, 23 ... Phase difference setting circuit, 30 ... Organic EL Element 31 ... Driving transistor (TFT), 32-36 ... Switching transistor, 37, 38 ... Capacitor, WS ... Write scanning signal, DS, DS1, DS2 ... Driving scanning signal, AZ ... Auto zero signal

Claims (4)

A drive transistor for driving the electro-optic element in accordance with an input signal voltage , a first transistor for controlling light emission / non-light emission of the electro-optic element, and a second transistor for selectively short-circuiting between the gate and drain of the drive transistor A pixel array section in which pixel circuits including at least are arranged in a matrix,
A driving scanning circuit for generating a driving scanning signal for driving the first transistor based on a first clock pulse having a pulse width of one horizontal scanning period ;
An auto-zero circuit for generating an auto-zero signal for driving the second transistor based on a second clock pulse having the same period as the first clock pulse and having a predetermined phase difference with respect to the first clock pulse ;
A phase difference setting circuit for setting a phase difference of the second clock pulse with respect to the first clock pulse ;
The active state of the drive scanning signal and the active state of the auto zero signal overlap for a certain period,
The phase difference setting circuit sets an overlap period in each active state of the drive scanning signal and the auto zero signal by setting a time shorter than the pulse width of the first clock pulse as the predetermined phase difference. A display device that is 1 μsec or longer and shorter than a pulse width of the first clock pulse . The display device according to claim 1 , wherein the phase difference setting circuit sets the overlap period to 12.5 μsec or less when a pulse width of the first clock pulse is about 30 μsec . A drive transistor for driving the electro-optic element in accordance with an input signal voltage , a first transistor for controlling light emission / non-light emission of the electro-optic element, and a second transistor for selectively short-circuiting between the gate and drain of the drive transistor A pixel array section in which pixel circuits including at least are arranged in a matrix ,
A driving scanning circuit for generating a driving scanning signal for driving the first transistor based on a first clock pulse having a pulse width of one horizontal scanning period;
An auto-zero circuit for generating an auto-zero signal for driving the second transistor based on a second clock pulse having the same period as the first clock pulse and having a predetermined phase difference with respect to the first clock pulse;
A phase difference setting circuit for setting a phase difference of the second clock pulse with respect to the first clock pulse;
In driving the display device in which the active state of the drive scanning signal and the active state of the auto-zero signal overlap for a certain period ,
By setting a time shorter than the pulse width of the first clock pulse as the predetermined phase difference, an overlap period in each active state of the drive scanning signal and the auto zero signal is 1 μsec or more and the first phase difference is set. A method for driving a display device, which is shorter than a pulse width of a clock pulse . 4. The method of driving a display device according to claim 3 , wherein when the pulse width of the first clock pulse is about 30 [mu] sec, the overlap period is 12.5 [mu] sec or less .

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