JP4684587B2 - Memory card - Google Patents

Description

  The present invention relates to a technology for updating sector data of a memory card, and more particularly to a technology effective when applied to improvement of reliability in a memory card using a nonvolatile semiconductor memory.

  As storage devices such as personal computers and multi-function terminals, memory cards such as multimedia cards and CF (Compact Flash (R)) cards are rapidly spreading.

  With the recent demand for higher performance, as a semiconductor memory mounted on a memory card, for example, a non-volatile memory such as a flash memory that can be electrically erased and rewritten electrically and can hold a large amount of data. It is used.

  The flash memory performs a data erasing operation for each erasing unit (for example, word line unit, block unit), and performs a data writing / reading operation for each read / write unit (for example, sector unit). Yes.

  In addition, in the memory card, there is a technique for managing data by overlappingly storing data in a plurality of memory areas in a flash memory in order to prevent errors such as corruption or loss of important data such as system data. In this case, all the duplicate data is updated when the data is updated.

As a data management technique in this type of flash memory, for example, first address conversion information by an alternative processing function that replaces a memory cell group that does not include a defective memory cell, and an average number of rewrites that replaces a memory cell group that does not include a defective memory cell Second address conversion information obtained by the conversion processing function is stored in a predetermined area of the memory array, and a plurality of first address conversion information and second address conversion information relating to the same memory cell group are stored in time series. (See Patent Document 1).
JP 2004-118407 A

  However, the present inventors have found that the data management technology in the memory card as described above has the following problems.

  In the flash memory, due to the characteristics of the device, when data writing / erasing is repeated, blocks that cannot be written / erased at a certain rate are generated. In particular, when the erase unit is larger than the write / read unit and the data at a specific location is updated frequently, the erase count increases by the number of data writes, and the performance of the flash memory deteriorates early. There is a risk of doing.

  In addition, even if important system data for address management etc. is duplicated and stored in the memory card, all duplicate data is updated at the time of update, so there is a trouble such as power interruption during rewriting of the system data. When this occurs, there is a problem that the system data is garbled or lost, and the memory system configured using the memory card does not operate.

  An object of the present invention is to provide a technique capable of significantly reducing the number of times data is erased and reducing a recognition failure of a memory card due to a data error or the like.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention includes a non-volatile semiconductor memory having a plurality of non-volatile memory cells and capable of storing predetermined information, and a controller for instructing operation of the non-volatile semiconductor memory based on a command issued from the outside. When updating sector data to a block that is an erasing unit of a nonvolatile memory cell, the controller sequentially writes sector data to an empty sector of the block, and when there is no empty sector in the block, the controller After the sector data is erased, the sector data is sequentially written from an arbitrary empty sector.

  The memory card of the present invention further includes a history information table storage unit that stores a history information table that manages the position of the latest sector data stored in the block, and the controller is stored in the history information table storage unit. The position of the latest sector data is managed based on the history information table.

  Further, in the memory card of the present invention, the history information table storage unit is composed of a volatile semiconductor memory.

  In the memory card of the present invention, the controller acquires the position of the latest sector data based on the management information stored in the sector data during the reset process of the memory card, and stores the history information table in the history information table storage unit. Is stored as

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention includes a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells and capable of storing predetermined information, and a controller for instructing operation of the nonvolatile semiconductor memory based on an externally issued command. In the memory card, the controller uses two blocks when updating sector data to a block which is an erasure unit of a nonvolatile memory cell, and the first write uses sector data in an empty sector of one block. , The second write writes sector data to the empty sector of the other block, and the third write alternately writes to the empty sector of the two blocks so that the sector data is written to the empty sector of one block. The sector data is updated sequentially.

  In the memory card of the present invention, the two blocks whose sector data are updated are separated from the target memory cell, word line, bit line, and source line at the time of writing, erasing, and reading. It is made up of blocks each provided in a separate string.

  Furthermore, the memory card of the present invention writes sector data after erasing the sector data of the block when there is no empty sector in the block.

  The memory card of the present invention further includes a history information table storage unit for storing a history information table for managing the position of the latest sector data stored in one of the two blocks. The position of the latest sector data is managed based on the history information table stored in the storage unit.

  Further, in the memory card of the present invention, the history information table storage unit is composed of a volatile semiconductor memory.

  In the memory card of the present invention, the controller acquires the position of the latest sector data based on the management information stored in the sector data during the reset process of the memory card, and stores the history information table in the history information table storage unit. Is stored as

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the number of times of erasing can be greatly reduced, it is possible to suppress the performance degradation of the nonvolatile semiconductor memory.

  (2) Further, even if an error occurs in data, the data before update can be used as backup data, so that the reliability of the memory card can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a block diagram of a storage system according to an embodiment of the present invention, FIG. 2 is a block diagram of a controller provided in a memory card constituting the storage system of FIG. 1, and FIG. 3 is a storage system of FIG. FIG. 4 is an explanatory diagram showing a configuration example of a memory array in the memory cell array of FIG. 3, and FIG. 5 is a memory diagram of FIG. FIG. 6 is an explanatory diagram showing an example of a block configuration in the memory array of FIG. 3, and FIG. 7 is a configuration of a data section provided in the block of FIG. 8 is an explanatory diagram showing an example, FIG. 8 is an explanatory diagram showing a configuration example of the management unit provided in the block of FIG. 6, and FIG. 9 is a relationship between invalid / valid sectors and history information in the block of FIG. FIG. 10 is an explanatory diagram illustrating a configuration example of a history information table stored in a history storage unit provided in the controller of FIG. 2, and FIG. 11 is a flowchart illustrating reset processing in the memory card of FIG. 12 is a flowchart showing a writing process in the memory card of FIG. 1, and FIG. 13 is a flowchart showing a writing error process in the memory card of FIG.

  In this embodiment, as shown in FIG. 1, the storage system includes a memory card 1 including a controller 4 and a nonvolatile semiconductor memory exemplified by a flash memory 3, and a host device 2 is connected to the outside of the memory card 1. It is configured to be connectable. The memory card 1 is used as an external storage medium for a host device 2 such as a digital video camera, a cellular phone, a portable music player, or a personal computer.

  The flash memory 3 is composed of a nonvolatile semiconductor memory capable of electrically rewriting and erasing data. Here, the flash memory 3 is composed of one semiconductor memory, but it is sufficient if the number of the semiconductor memories is one or more.

  As shown in FIG. 2, the controller 4 includes a host-side interface 5, an MPU (MicroProcessing Unit) 6, a buffer interface 7, a data buffer 8, a storage unit-side interface 9, a history detection unit 10, a history generation unit 11, and a history storage. It consists of a part 12 and the like.

  The controller 4 is connected to the host device 2 and controls the flash memory 3. The controller 4 reads out the program or data stored in the flash memory 3 and outputs it to the host device 2 or input from the host device 2. Instructions for program and data write operations.

  The host side interface 5 is an interface between the host device 2 and the MPU 6. The MPU 6 manages all the controls in the controller 4. The buffer interface 7 is an interface between the MPU 6 and the data buffer 8.

  The data buffer 8 is composed of a volatile memory such as SRAM (Static Random Access Memory), and is also used as a work area of the CPU provided in the MPU 6. The storage unit side interface 9 is an interface between the MPU 6 and the flash memory 3 and includes an error detection / correction circuit.

  The history detection unit 10 detects a place where the latest data is stored from the multiplexed data based on the history information RJ (FIG. 8). The history generation unit 11 generates history information RJ indicating the storage location of the latest data, and stores the history information RJ in the flash memory 3. The history storage unit 12 includes a volatile memory such as a RAM (Random Access Memory), for example, reads the history information RJ stored in the flash memory 3, and creates and manages a history information table RT (FIG. 10).

  Note that the history detection unit 10, the history generation unit 11, and the history storage unit 12 are not provided as circuits, and may be replaced by firmware processing by the MPU 6, for example.

  FIG. 3 is an explanatory diagram showing a configuration example of the memory array MA in the flash memory 3.

  In this case, the memory array MA has a configuration in which a plurality of sub bit lines SBL are connected to the global bit line GBL, and a nonvolatile memory cell S is connected to each of the sub bit lines SBL.

  In addition, a plurality of nonvolatile memory cells S connected to the word line WL can be erased at once. This is called a block (erase unit), and a plurality of blocks connected to the sub bit line SBL are called strings. Further, hereinafter, a data writing unit is called a page, and a data storage unit is called a sector, and one or a plurality of sector data (table data) is stored in one block.

  When reading data, a voltage is applied to the selected word line WL, and the data is read from the nonvolatile memory cell S connected to the word line WL via the sub bit line SBL. When data is written, the word line WL and the sub bit line SBL are selected and a voltage is applied, and the data is written to the nonvolatile memory cell S.

  FIG. 4 is an explanatory diagram showing a map configuration of the memory array MA in the flash memory 3.

  As described above, a string is composed of a plurality of blocks. Here, block rewriting of table data (sector data) uses blocks in two strings ST1 and ST2.

  In FIG. 4, the table number TBLNo. 0-No. The case where 199 is stored is shown. Two blocks are allocated to one table data, and one is a primary block PB and the other is a secondary block SB.

  When data rewriting involves erasing a block, erasing / writing is performed on another empty block. The defective registration block FT of the memory array MA is a block area in which a defective block address in a string used for updating table data is registered.

  FIG. 5 is an explanatory diagram showing a data update procedure in a block in the memory array MA.

  The primary block PB and the secondary block SB are respectively configured by a data part D that stores table data and a management part K that stores management information of the block.

  Here, an example in which the number of pages in the primary block PB and the secondary block SB is two is shown. In the primary block PB and the secondary block SB, the data portion D of each block is divided into 8 (sectors CA00 to CA07), and table data is stored in one of them. One management unit K is provided for each page, but one management unit K may be provided for each block.

  The table data is updated by adding the secondary block SB and the data block D divided into eight primary blocks PB sequentially and alternately, and adding the primary block PB and the secondary block SB 16 times in total. Is possible.

  For example, in the figure, when the data part D0 (1) in the primary block PB is updated, it is added to the data part D0 (2) in the secondary block SB. Thereafter, when the data part D0 (2) is updated, it is added to the data part D0 (3) in the primary block PB.

  When the data part D0 (8) in the secondary block SB is updated, the data part D0 (9) in the primary block PB is added.

  FIG. 6 is an explanatory diagram illustrating a configuration example of the primary block PB and the secondary block SB.

  The primary block PB and the secondary block SB are each composed of a data part D and a management part K. The data part D is composed of sectors CA00 to CA07, and the management part K is composed of management parts K1 and K2.

  As shown in FIG. 7, each sector CA00 (to CA07) includes table data and redundant data such as ECC (Error Collecting Code) that protects the table data.

  Further, as shown in FIG. 8, the management unit K1 has a good block code BC, management information KJ, table number TBLNo. The error detection / correction redundancy code CD and the history information RJ are included. The management unit K2 includes the good block code BC, the management information KJ, the error detection / correction redundancy code CD, and the history information RJ. ing.

  The good block code BC is a code for identifying whether the page or the block can be used. The management information KJ is a code indicating the attribute or information of the page or block.

  Table number TBLNo. Is a code indicating table number information. The error detection / correction redundancy code CD is, for example, ECC, and the good block code BC, management information KJ, and table number TBLNo. Protect your data.

  The history information RJ of the management unit K includes an invalid flag MF and a valid sector (CA) flag YF, and the history information RJ of the management unit K2 includes a valid sector flag YF. The invalid flag MF is a code indicating that the data of the block is invalid, and is a flag that is set when all of the eight data portions D respectively provided in the primary block PB and the secondary block SB are additionally written. . The valid sector flag YF is a code indicating a location where the latest data is stored in the block.

  In FIG. 8, the invalid flag MF and the valid sector flag YF are not protected by an error detection / correction redundant code CD such as ECC. However, the invalid flag MF and the valid sector flag YF are protected from data. You may make it add.

  FIG. 9 shows the relationship between invalid / valid sectors and history information RJ in a block.

  The history information RJ of the management unit K1 is composed of 3 bytes, for example, and the history information RJ of the management unit K2 is composed of 2 bytes, for example. When the invalid flag MF is “x0”, it indicates that the corresponding sector is valid, and when the invalid flag MF is “xF”, it indicates that the block is invalid.

  Each valid sector flag YF indicates whether or not the latest data is contained in the corresponding sector.

  For example, when the sector CA00 is valid, the invalid flag MF is 'x0'. If the block is invalid, the invalid flag MF becomes 'xF'. When the latest data is stored in the sector CA00, the valid sector flag YF of the management unit K1 is 'F000', and the valid sector flag YF of the management unit K2 is '0000'.

  Here, 'x' is 'Don't Care'. Further, the history information RJ takes into account 1-bit corruption, and “E”, “D”, “B”, “7” are “F”, and “F”, “1”, “2”, “4”. ',' 8 'shall be regarded as' 0'.

  FIG. 10 is an explanatory diagram showing a configuration example of the history information table RT created from the history information RJ stored in the flash memory 3 and managed by the history storage unit 12.

  The history information table RT includes an offset block address BA, a primary / secondary selection unit PSS, an error flag EF, an initialization flag RF, and an intra-block valid sector position YCP.

  The offset block address BA is an offset address on the flash memory 3 storing the table data. The offset block address BA stores two, a primary address and a secondary address.

  The primary / secondary selection unit PSS indicates in which of the primary block PB and the secondary block SB the latest data is stored. The error flag EF is normally “0”, and the same table number TBLNo. When the valid block (invalid flag MF is “0”) is detected, it is set to “1”.

  The initialization flag RF is set to “1” when the initialization of the history information table RT is detected. The intra-block valid sector position YCP indicates the position of the latest data in the block.

  Next, reset processing of the memory card 1 according to the present embodiment will be described with reference to the flowchart of FIG.

  First, when the memory card 1 is powered on, a reset process is performed (step S101). This reset process includes the stabilization time of the oscillator, the negation of the reset IC, and reading of system data other than table data. Further, a part of the reset process may be divided and performed at the end of the reset process sequence.

  Subsequently, the defect registration table stored in the defect registration block FT is read, and the defect block address in the string is acquired (step S102).

  Thereafter, the management unit K in the primary block PB and the secondary block SB excluding the defective block address acquired in the process of step S102 is read to check that it is a good block (step S103).

  The invalid flag MF is checked (step S104), and the history information RJ is created for the valid block. Also, invalid blocks are skipped.

  Subsequently, table number TBLNo. (Step S105), a history information table RT is created in the history storage unit 12 from the valid sector flag YF and the offset block address BA of the flash memory 3 (step S106).

  In the process of step S105, the same table number TBLNo. Is detected, the error flag EF is set to "1" (step S107).

  After the process of step S107 or when the invalid flag MF is invalid in the process of step S104, it is confirmed whether reading of all the management units K is completed (step S108), and reading of all the management units K is performed. Is completed, the management unit K in the block whose error flag EF is “1” is re-read (steps S109 and S110), and the history information of the latest table data is left in the history information table RT (step S111).

  For example, two valid table numbers TBLNo. 0, a valid sector flag YF is a block of sector CA00 and a block of sector CA07, and table number TBLNo. When the sector CA07 is valid in 100 secondary blocks SB, the primary block PB of the sector CA07 is selected as valid data.

  That is, the block having the valid sector flag YF that can be consistent in the update order is selected as the latest block.

  Table data (sector data) is read after completion of the processing in step S111 or when there is no error flag EF ('1') in the processing in step S109 (step S112), and error detection / correction redundancy code such as ECC Data is checked using the CD (step S113).

  When all the table data are read (step S114), the reset process is completed. In the process of step S113, in the case of NG, it is confirmed whether or not the read count of the table data is 1 or less (step S115).

  In the process of step S115, if the number of times the table data is read is one or less, it is searched whether there is table data updated one time before (step S116). If there is table data updated immediately before in the processing of step S116, the table data is read, and the data is similarly checked with an error detection / correction redundant code CD such as ECC, and the history storage unit 12 history information tables RT are updated (step S117).

  In the process of step S115, if the number of times of reading the table data is 2 times or more (for example, if the primary block PB is NG, the secondary block SB is referred to and the process does not go back further). (Step S118). Thus, the reliability of data can be improved by not using the table data updated two times before.

  Furthermore, in the process of step S116, if there is no previous table data updated, the process ends with an error (step S118).

  Next, the writing process in the memory card 1 will be described using the flowchart of FIG.

  First, when the memory card 1 receives a write command from the host device 2, the flag information of the history information table RT in the history storage unit 12 is confirmed (step S201). It is checked whether the error flag EF is “1” in all table blocks (step S202).

  If there is a block with the error flag EF of “1”, the invalidation flag “FF” is written to the old block in order to invalidate the old block, and at the same time, the error flag EF = 0 is cleared (step S203).

  Subsequently, after the processing in step S202 or step S203, the sector CA07 is checked (step S204). If the sector CA07 is valid, history information for a new block (another free block different from the old data) is stored. RJ is generated (step S205), and new table data and management information K (including history information RJ) are written into a new block (step S206). Thereafter, the invalidation flag MF of the old block is written and invalidated (step S207).

  If the sector CA07 is not valid in the process of step S204, history information RJ is generated (step S208), and new table data and a valid sector flag YF are additionally written in the same block (step S209).

  When the processing in step 207 or step S209 ends, the history information table RT in the history storage unit 12 is updated (step S210), and the writing process ends.

  Next, a flowchart of the write error process in the memory card 1 will be described with reference to FIG.

  First, when an error occurs during the writing process, rewriting is performed on another new block (step S301). Thereafter, in order to make the block in which the error has occurred defective, the defect code (eg, 'FF') is written in the good block code BC in the block management unit K (step S302). An address is registered (step S303).

  As a result, according to the present embodiment, the number of erases of the flash memory 3 can be significantly reduced, so that a decrease in performance of the flash memory 3 can be suppressed.

  Further, when an error occurs in the data, the reliability of the memory card 1 can be improved by using the previously updated table data as the backup data.

  Further, in the present embodiment, in the reset process, the table data updated two times before is not used and the reliability of the data is improved (FIG. 11, step S116). You may make it perform the process which uses the set table data.

  FIG. 14 is an explanatory diagram showing an example of a history information table RT stored in the history storage unit 12 when using table data updated two times before.

  As shown in the figure, the history information table RT has a configuration shown in FIG. 10 consisting of an offset block address BA, a primary / secondary selector PSS, an error flag EF, an initialization flag RF, and a valid sector position YCP in a block. The (R_ERR) flag REF is newly added.

  The read error flag REF is a flag indicating that an uncorrectable error due to redundant data such as ECC has occurred in the table data, and that one or more previous updated table data is being referenced.

  The reset process in the memory card 1 in this case will be described using the flowchart of FIG.

  First, the processes of steps S101 to S111 shown in FIG. 11 are performed. After that, as shown in FIG. 15, the table data (sector data) is read (step S401), and the data is checked with the error detection / correction redundant code CD such as ECC (step S402). When all the table data are read (step S403), the reset process ends.

  In the process of step S402, in the case of NG, it is confirmed whether or not the read count of the table data is 1 or less (step S404). In the process of step S404, if the number of times table data is read is one or less, a search is made as to whether there is table data updated immediately before (step S405).

  In the process of step S405, if there is table data updated immediately before, the table data is read, and similarly, the data is checked by the error detection / correction redundant code CD such as ECC, and the history storage unit After the 12 history information tables RT are updated (step S406), the process of step 403 is performed.

  In the process of step S404, if the number of times of reading the table data is two or more, the read error flag REF is set to “1” so as to notify the MPU 6 that the table data is read twice or more. (Step S407) and Step S405 are performed.

  Furthermore, in the process of step S405, if there is no table data updated immediately before, the process ends with an error (step S408).

  Further, the writing process after the reset process of FIG. 15 will be described with reference to FIG.

  In FIG. 16, the processes of steps S201, S202, and S204 to S210 shown in FIG. 12 are the same, and only the part of the different process (the process of step S203) is shown.

  First, the memory card 1 receives a write command from the host device 2 and checks the flag information of the history information table RT in the history storage unit 12 (step S201), and the error flag EF is '1' in all the table blocks. A check is made (step S202).

  If there is a block with an error flag EF of “1”, as shown in FIG. 16, it is confirmed whether or not the read error flag EFR is “1” (step S501). When the read error flag EFR is “1”, history information RJ is generated (step S502), and new table data and management information K (including history information RJ) are written into a new block (step S503).

  If there is no block having the error flag EF of “1” in the process of step S501, or after the process of step S503, the old table data is invalidated by writing to the invalid flag MF of the old block (step S504). . Thereafter, steps S204 to S210 shown in FIG. 12 are performed.

  When the processes shown in FIGS. 14 and 15 are applied to user data, the number of erasures can be reduced by using the user data in an area where the number of rewrites of the user data is large, and the reliability of the memory card 1 can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, a configuration in which a management unit including history information and a data unit are stored in each block of one flash memory is used. However, as shown in FIG. 17, a plurality of flash memories 3 _{1 to} 3 are used. the _n provided to store the history information (optional) flash memory 3 _1, other flash memory 3 ₂ to 3 _n, a configuration for storing and a management unit data unit which is associated with the subsequent history information, Each block in the flash memories 3 _{2 to} 3 _n may be managed.

Thereby, data management of the plurality of flash memories 3 _{1 to} 3 _n can be facilitated.

  The data management technique shown in FIG. 17 is also effective when managing data in a plurality of memory systems.

  In this case, the memory systems MS1 to MS3 each including a memory card are configured to be connected to a line L such as a wired network or a wireless network, as shown in FIG.

  Then, only the history information is stored in the (arbitrary) memory system MS1, and the data section and the management section associated with the history information are stored in the other memory systems MS2 and MS3.

  These memory systems MS1 to MS3 are similarly controlled from the host device 2 connected to the line L. Thereby, the plurality of memory systems MS1 to MS3 can be managed collectively.

  The memory card of the present invention is suitable for suppressing performance deterioration in a nonvolatile semiconductor memory and improving the reliability of the memory card.

1 is a block diagram of a storage system according to an embodiment of the present invention. FIG. 2 is a block diagram of a controller provided in a memory card configuring the storage system of FIG. 1. FIG. 2 is an explanatory diagram showing a configuration example of a memory array in a flash memory provided in a memory card configuring the storage system of FIG. 1. FIG. 4 is an explanatory diagram showing a configuration example of a memory map in the memory cell array of FIG. 3. FIG. 5 is an explanatory diagram showing a procedure for updating table data stored in the memory array of FIG. 4. FIG. 4 is an explanatory diagram showing a configuration example of a block in the memory array of FIG. 3. It is explanatory drawing which shows the structural example of the data part provided in the block of FIG. It is explanatory drawing which shows the structural example of the management part provided in the block of FIG. FIG. 7 is an explanatory diagram showing a relationship between invalid / valid sectors and history information in the block of FIG. 6. It is explanatory drawing which shows the structural example of the log | history information table stored in the log | history storage part provided in the controller of FIG. 3 is a flowchart showing reset processing in the memory card of FIG. 1. 3 is a flowchart showing a writing process in the memory card of FIG. 1. 3 is a flowchart showing a write error process in the memory card of FIG. 1. It is explanatory drawing which shows the structural example of the log | history information table stored in the log | history storage part provided in the controller by other embodiment of this invention. It is a flowchart which shows the reset process of the memory card by other embodiment of this invention. It is a flowchart which shows the write-in process of the memory card by other embodiment of this invention. It is explanatory drawing which shows the structural example of the flash memory provided in the memory card by other embodiment of this invention. It is explanatory drawing which shows the structural example of the memory system by other embodiment of this invention.

Explanation of symbols

1 Memory card 2 Host device 3 Flash memory (nonvolatile semiconductor memory)
3 _{1 to} 3 _n flash memory (nonvolatile semiconductor memory)
4 Controller 5 Host side interface 6 MPU
7 Buffer interface 8 Data buffer 9 External storage interface 10 History detection unit 11 History generation unit 12 History storage unit MA Memory array GBL Global bit line SBL Sub bit line S Non-volatile memory cell WL Word line ST1, ST2 String PB Primary block SB Secondary block FT failure registration block D data part K, K1, K2 management part CA00 to CA07 sector BC good block code KJ management information TBLNo. Table number CD Redundancy code for error detection / correction RJ History information RT History information table MF Invalid flag YF Valid sector flag BA Offset block address PSS Primary / secondary selector EF Error flag RF Initialization flag YCP Valid sector position in block REF Read error flag MS1-MS3 Memory system L Line HC Host computer

Claims (2)

A nonvolatile semiconductor memory having a plurality of nonvolatile memory cells and capable of storing predetermined information;
A memory card comprising a controller for instructing operation of the nonvolatile semiconductor memory based on a command issued from the outside,
A history information table storage unit that stores a history information table that manages the position of the latest sector data stored in a block that is an erase unit of the nonvolatile memory cell;
The controller is
When updating sector data to a block that is an erase unit of the nonvolatile memory cell, sector data is sequentially written to an empty sector of the block, and the sector data of the block is erased when there is no empty sector in the block. after, it writes sequentially sector data from any of the free sectors,
Manage the position of the latest sector data based on the history information table stored in the history information table storage unit,
A memory card characterized in that, at the time of reset processing of the memory card, a position of the latest sector data is obtained based on management information stored in sector data and stored as a history information table in the history information table storage unit . The memory card according to claim 1 ,
The history information table storage unit is a volatile semiconductor memory.

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