JP4673007B2 - Loop control device and control method thereof - Google Patents

Description

  The present invention relates to sequence control of a program having a loop function, and more particularly to a loop control apparatus and a control method thereof in which a plurality of program counters use multiple loops.

Conventionally, there is a loop control apparatus that performs program sequence control for processing multiple loops (see, for example, Patent Document 1). In the loop control device, a method is generally used in which the above control is realized by storing a loop start address, a loop end address, the number of loops, and the like as a stack structure and referring to the top of the stack.
JP-A-8-63355

  However, the conventional loop control device does not assume the case where there are a plurality of program counters indicating the addresses on the instruction memory of the instruction being executed. Therefore, when a multiple loop is executed by each of a plurality of program counters, the top of the stack only holds information on the inner loop of any one of the plurality of program counters, No use at all. Although a method of preparing the stack structure by the number of program counters is conceivable, there is a problem that the stack structure has a scale of “the number of program counters × the number of loop counters” and the circuit scale increases more than necessary.

An object of the present invention is to enable a plurality of program counters to efficiently execute multiple loops in parallel with a simple and small-scale circuit configuration , and particularly to reduce stack even when executing multiple loop processing by a plurality of programs. It is an object of the present invention to provide a loop control device and a control method thereof capable of suppressing an increase in circuit scale by enabling execution with a structure .

In order to achieve the above object, the present invention provides a loop control device comprising a plurality of program counters and a plurality of loop counters , wherein an instruction memory stores a value of one program counter selected from the plurality of program counters. Selection means for outputting as the address of the instruction, instruction output means for outputting the instruction stored in the address output by the instruction memory to the instruction execution means to the instruction execution means, and the instruction output by the instruction output means is a loop instruction In this case, the end address of the loop process executed according to the loop instruction, the first identifier indicating the program counter for executing the loop process, and the first counter indicating the loop counter holding information on the loop count of the loop process. and second identifier, and a plurality retractable stack loop information held in association with the previous If the instruction output means stores the loop information regarding the loop instruction when outputting a loop instruction to the stack, the selection means selects a new program counter, loop information comprising a first identifier indicating the program counter The selection means selects the loop information closest to the top of the stack, based on the end address included in the loop information and the value of the loop counter indicated by the second identifier included in the loop information. Control means for determining whether or not the loop processing being executed by the program counter is completed.

According to the present invention, it is possible to suppress the increase in the circuit scale because it can perform a stack structure less even when running multiple loop processing by multiple programs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the loop control apparatus according to the first embodiment of the present invention.

  In FIG. 1, a loop control device includes program counters 1-1, 1-2, 1-3, a program counter selection unit 2, an instruction memory 3, an instruction decoding unit 4, an instruction execution unit 5, a loop difference register 6, and a loop counter. 7, a program counter selection signal generation unit (hereinafter abbreviated as a selection signal generation unit) 8, a loop information stack 9, a stack control unit 10, a program counter update unit 11, a multiplexer 12, an adder 13, a first comparator group 14, A second comparator group 15, a multiplexer group 16, a third comparator group 17, and a subtracter 18 are provided. Note that FIG. 1 does not show all the connections, but only representative connections necessary for the description.

  The program counters 1-1, 1-2, and 1-3 indicate addresses on the instruction memory 3 of instructions that are being executed, and are each configured of, for example, a 6-bit flip-flop. The program counter selection unit 2 selects a value stored in any one of the plurality of program counters 1-1, 1-2, and 1-3 as an address of the instruction memory 3 based on a program counter selection signal. Then output. The instruction memory 3 is a memory that stores data transfer instructions. The instruction decoding unit 4 decodes an instruction that is a data output of the instruction memory 3. The instruction execution unit 5 executes the instruction decoded by the instruction decoding unit 4.

  The loop difference register 6 (corresponding to an offset register OFST described later) holds the difference between the loop start address and the loop end address. The loop counter 7 (corresponding to a loop register LP described later) holds the number of instruction loops. Three loop difference registers 6 and three loop counters 7 are provided, and predetermined values are set by the instruction execution unit 5. The selection signal generation unit 8 generates a program counter selection signal to be sent to the program counter selection unit 2 for each instruction execution based on the selection permission signal generated by the instruction execution unit 5.

  The loop information stack 9 stores loop information. That is, the loop information stack 9 includes a flag (IN_USE (0), IN_USE (1), IN_USE (2)) indicating that the loop is being executed, and an identifier (that is, program counter selection) indicating the program counter that executed the loop instruction. Signal values) (PC_SEL (0), PC_SEL (1), PC_SEL (2)) and identifiers (LP_SEL (0), LP_SEL (1), LP_SEL (2)) and a value obtained by adding the program counter value when the loop instruction is executed and the value of the loop difference register 6 indicated by the identifier indicating the loop counter and the loop difference register (that is, the loop end address) (LP_END ( 0), LP_END (1), LP_END (2)).

  The stack control unit 10 controls the loop information stack 9 and performs the control described later. The program counter updating unit 11 updates the value of the program counter selected every time the data transfer instruction is executed based on the program counter selection signal, or the start address of the loop based on the loop back instruction signal output from the stack control unit 10 Update to The multiplexer 12 selects one of the three loop difference registers 6 based on the loop counter identifier (LP_SEL) output when the instruction decode unit 4 decodes the loop instruction. The adder 13 adds the output of the multiplexer 12 and the output (Address) of the program counter selection unit 2.

  The first comparator group 14 includes a program counter selection signal (PC_SEL) output from the selection signal generator 8 and an identifier (PC_SEL (0)) indicating a program counter that has executed a loop instruction stored in the loop information stack 9. , PC_SEL (1), PC_SEL (2)) are compared. The second comparator group 15 includes an output (Address) of the program counter selection unit 2 and a loop end address (LP_END (0), LP_END (1), LP_END (2)) stored in the loop information stack 9. Compare whether or not.

  The multiplexer group 16 stores the loop counter identifier (LP_SEL (0), LP_SEL (1), LP_SEL (2)) stored in the loop information stack 9 and indicating which loop counter and loop difference register the loop instruction uses. Based on the above, one of the three loop counters 7 is selected. The third comparator group 17 compares whether or not the output of each of the three multiplexer groups 16 is equal to 1. The subtractor group 18 subtracts 1 to 3 of the values of the three loop counters 7 based on the loop end detection signal output from the stack control unit 10.

  The characteristic control in the stack control unit 10 of the loop control device is summarized as follows.

  The stack control unit 10 indicates that the output of the first comparator group 14 indicates a match, the second corresponding to the entry corresponding to the entry in which the flag indicating that the loop information stack 9 is closest to the top of the loop information stack 9 is being executed. Output of the first comparator group 14 (in other words, output_match_pc (y) = “y” of the first comparator group 14 and output_in_use (y) = “1” of the loop information stack 9). Focusing on the y closest to the top of the loop information stack 9 among the y's, the output match_end (y) = “y” of the second comparator group 15) The following control is performed according to the output of the comparator group 17.

  That is, when the output of the third comparator group 17 corresponding to the entry does not indicate a match, the stack control unit 10 is indicated by an identifier indicating a loop counter and a loop difference register stored in the entry. The value held in the loop difference register 6 is subtracted from the value of the currently selected program counter, and the value held in the loop counter 7 indicated by the identifier indicating the loop counter and the loop difference register stored in the entry is obtained. Control to subtract one.

  Further, when the output of the third comparator group 17 corresponding to the entry indicates a match, the stack control unit 10 invalidates the entry in the loop information stack 9 (clears IN_USE (0)). At the same time, the value held by the loop counter 7 indicated by the loop counter and the identifier indicating the loop difference register stored in the entry is controlled to be decremented by 1 or cleared to 0.

  Furthermore, the stack control unit 10 indicates that the outputs of the first comparator group 14 indicate a match and the loop information stack 9 corresponds to two or more entries in which a flag indicating that a loop is being executed is set. When the outputs of the second comparator group 15 indicate coincidence, the following control is performed according to the output of the third comparator group 17.

  That is, when at least one of the outputs of the third comparator group 17 corresponding to the two or more entries does not indicate a match, the stack control unit 10 determines whether the loop information stack 9 among the ones that do not indicate a match. The value held in the loop difference register 6 indicated by the identifier indicating the loop counter and the loop difference register stored in the entry closest to the head is subtracted from the value of the currently selected program counter and stored in the entry. Control is performed so that the value held by the loop counter 7 indicated by the identifier indicating the loop counter and the loop difference register is decremented by one.

  Further, the stack control unit 10 selects all the two or more entries in the loop information stack 9 when all the outputs of the third comparator group 17 corresponding to the two or more entries indicate a match. Whether to invalidate and subtract 1 from all values held by two or more loop counters 7 indicated by two or more identifiers indicating loop counters and loop difference registers stored in the two or more entries Alternatively, control is performed to clear to zero.

  Next, among the above-mentioned units constituting the loop control device, the instruction memory 3, the program counters 1-1, 1-2, 1-3, the program counter selection unit 2, the program counter update unit 11, and the selection signal generation unit 8 A detailed configuration will be described.

  FIG. 2 is a diagram showing a detailed configuration of the instruction memory 3.

  In FIG. 2, the instruction memory 3 is composed of, for example, a 2-port (1 Read / 1 Write) SRAM, and has a data width of 32 bits and a word length of 64. The read address (READ ADDRESS) of the instruction memory 3 is 6 bits. When a read enable signal (READ ENABLE) is asserted, 32-bit read data is read from the READ DATA port. In the present embodiment, the read address is supplied from the program counter selection unit 2 and the read data is supplied to the instruction decoding unit 4.

  The write address (WRITE ADDRESS) of the instruction memory 3 is 6 bits, and when the write enable signal (WRITE ENABLE) is asserted, the instruction data driven on the 32-bit write data (WRITE DATA) signal is stored in the instruction memory 3. Written to the write address. In this embodiment, both the write address and the write data are supplied from an external device (not shown).

  When the writing of the instruction data to the instruction memory 3 is finished, the reset is released and the loop control device starts operation. Each of the program counters 1-1, 1-2, and 1-3 is composed of 6-bit flip-flops as described above, and initial values at reset are “000000”, “010000”, and “100000”, respectively. It has become. That is, the program counter 1-1 executes an instruction from address 0x0, the program counter 1-2 executes an instruction from address 0x10, and the program counter 1-3 executes an instruction from address 0x20.

  FIG. 3 is a block diagram showing detailed configurations of the program counters 1-1, 1-2, 1-3, the program counter selection unit 2, and the program counter update unit 11.

  In FIG. 3, the program counter updating unit 11 includes selectors 11-1, 11-2 and +1 adder 11-3 corresponding to the program counter 1-1, and selectors 11-4 and 11 corresponding to the program counter 1-2. -5, +1 adder 11-6, selectors 11-7, 11-8, and +1 adder 11-9 corresponding to the program counter 1-3.

  The output of the selector 11-1 is input to the program counter 1-1. The selector 11-1 includes the current value of the program counter 1-1, a value obtained by adding 1 to the current value, a value loaded by a LOAD instruction (store_d), and a program counter 1-1 when looping back by a LOOP instruction. One of the return value (lp_back_pc) and the jump destination address (jump_pc) by the JUMP instruction is selected and output. The selector 11-2 selects one of the output value of the program counter 1-1 and the value obtained by adding 1 to the output value of the program counter 1-1 (the output value of the +1 adder 11-3) as a program counter selection signal. Select based on pc_sel. That is, when the program counter 1-1 is selected in the clock cycle, a value obtained by adding 1 is selected, and when the program counter 1-1 is not selected, the current value is selected.

  The portions corresponding to the program counters 1-2 and 1-3 in the program counter updating unit 11 have the same configuration as described above. The program counter updating unit 11 sets the program counters 1-2 and 1-3. The value is updated.

  The program counter selection unit 2 responds to the 3-bit program counter selection signal pc_sel [2: 0] output from the selection signal generation unit 8 to program counters 1-1 (PC (0)), 1-2 (PC (1)) One of the outputs 1-3 (PC (2)) is selected and output as a read address of the instruction memory 3. The program counter selection signal pc_sel [2: 0] is a one-hot signal ((a signal in which 1 out of 3 bits is “1”)).

  The program counter selection unit 2 selects the program counter 1-1 when the program counter selection signal pc_sel is “001”, selects the program counter 1-2 when the program counter selection signal pc_sel is “010”, and selects the program counter. When the signal pc_sel is “100”, the program counter 1-3 is selected. That is, when the program counter selection signal pc_sel [n] = “1”, the program counter PC (n) is selected (where n = 0, 1, 2).

  FIG. 4 is a block diagram illustrating a detailed configuration of the selection signal generation unit 8.

  In FIG. 4, the selection signal generation unit 8 includes flip-flops 8-1, 8-2 and 8-3, selectors 8-4, 8-5 and 8-6, and a decoder 8-7.

  The flip-flops 8-1, 8-2, and 8-3 are connected to the clock signal line and the reset signal line, respectively, and the output is a program counter selection signal. The flip-flop 8-1 is set to “1” by the reset signal, the output of the selector 8-4 is connected to the D input, and the Q output becomes the program counter selection signal pc_sel [0]. In the flip-flop 8-2, "0" is set by the reset signal, the output of the selector 8-5 is connected to the D input, and the Q output becomes the program counter selection signal pc_sel [1]. In the flip-flop 8-3, "0" is set by the reset signal, the output of the selector 8-6 is connected to the D input, and the Q output becomes the program counter selection signal pc_sel [2].

  The decoder 8-7 decodes the program counter selection permission signal pc_en [2: 0] output from the instruction execution unit 5 and the stall signal indicating the instruction execution stall instruction, and selects the selectors 8-4, 8-5, 8- 6 select control signals sel-_cnt [0], sel-_cnt [1], and sel-_cnt [2], respectively. The decoding method of the decoder 8-7 is shown in FIG.

  FIG. 5 is a diagram showing the relationship between the decoding method of the program counter selection permission signal and the selection control signal.

  In FIG. 5, the illustrated table shows the relationship between the stall as an input and the selection control signal sel_cnt [2: 0] as an output with respect to the program counter selection permission signal pc_en [2: 0]. For example, when the stall is “1”, the selection control signals sel_cnt are all 2 and all the flip-flops of the selection signal generation unit 8 hold the current value. That is, the program counter selection signal pc_sel is not updated.

  When the stall is “0” and the program counter selection enable signal pc_en = “111”, the selection control signals sel_cnt are all 0, and the program counter selection signal pc_sel operates as a shift register. That is, the program counter selection signal pc_sel transits from “001” → “010” → “100” → “001”, and the program counter changes from PC (0) → PC (1) → PC (2) → PC (0). Selected in order.

  When the stall is “0” and the program counter selection enable signal pc_en = “011”, the selection control signal sel_cnt = “301” is set so that the program counter PC (2) is not allowed to be selected. That is, the program counter selection signal pc_sel transits from “001” → “010” → “001” → “010” → “001”, and the program counter changes from PC (0) → PC (1) → PC (0) → PC (1) → PC (0) is selected in this order.

  An instruction corresponding to the program counter selected by the program counter selection unit 2 is read from the instruction memory 3 and input to the instruction decoding unit 4. The instruction consists of 32 bits and is decoded as shown in FIG.

  FIG. 6 is a diagram illustrating a result of decoding the instruction.

  In FIG. 6, when a 32-bit instruction is expressed as Inst [31: 0], when Inst [31:30] = “00”, a special instruction (Instruction [31:30] = “01”) When it is Inst [31:30] = “10”, it is decoded as a store instruction (Store Instruction). When Inst [31:30] = “11”, it is decoded as an invalid instruction.

  The load instruction is a data transfer instruction from a memory (not shown) to an internal resource of the loop control device. The store instruction is a data transfer instruction from the internal resource of the loop control device to the memory. The special instruction includes an instruction provided in a general processor such as a NOP instruction (an instruction that does nothing), a loop instruction (LOOP), and a jump instruction (JUMP).

  Inst [29:27] is a field indicating the data size, and details are shown in FIG. For example, “000” indicates transfer of 1 byte, and “100” indicates transfer of 5 bytes. Inst [26:23] is a field indicating the index of the transfer source resource, Inst [22:19] is a field indicating the index of the transfer destination resource, and the identifier (load) of the resource indicated by Inst [18:16] In the case of an instruction, the data transfer destination is indicated, and in the case of a store instruction, the data transfer source is indicated).

  Details of the internal resource identifier are shown in FIG. “000” indicates a PC, that is, a program counter. “001” indicates AR, that is, an address register (corresponding to an internal resource of the instruction execution unit 5). “010” indicates GPR, that is, a general-purpose register (corresponding to an internal resource of the instruction execution unit 5). “011” indicates OUT / IN, that is, a DMA port (OUT / IN is identified as load or store). “100” indicates LP, that is, a loop register (corresponding to the loop counter 7 in FIG. 1). “101” indicates OFST, that is, an offset register (corresponding to the loop difference register 6 in FIG. 1).

  The internal resource identifier indicating the data transfer source in the case of the load instruction and the data transfer destination in the case of the store instruction is fixed in the address register AR, and only the index is designated by the respective index fields.

  Inst [15:13] is a field indicating the valid byte lane of the data transfer source or data transfer destination, and indicates how many bytes are transferred to which byte lane together with the data size field. .

  FIG. 9 and FIG. 10 are diagrams showing the relationship between the data size field (size), the byte lane field (pos_d / s), and the effective byte lane.

  In FIG. 9 and FIG. 10, the tables shown in detail show the effective byte lanes that are effective depending on the combination of the data size and the byte lanes. The data is 64 bits, and the byte lanes are [63:56], [55:48], [47:40], [39:32], [31:24], [21:16], [15: 8] and [7: 0], there are 8 lanes, and “v” is written in the effective byte lane. For example, when the data size field (size) is “000”, that is, 1 byte, and the byte lane field (pos_d / s) is “011”, that is, the fourth byte lane, data [31:24] (data bus signal) is used. 1 byte of data is transferred.

  In order to better understand the instructions in the present embodiment, some examples of the instructions are shown.

  When Inst = “01 — 000 — 0001 — 0010 — 100 — 001 — 000000000000”, this is a load instruction, and 1-byte data on the memory indicated by the address register AR (1) is loaded into [15: 8] of the loop register LP (2).

  When Inst = “10_111 — 0001 — 0010 — 011 — 000 — 000000000000”, this is a store instruction, and the 8-byte data read from the DMA input port IN (1) is stored in the memory indicated by the address register AR (2).

  FIG. 11 is a diagram illustrating encoding of special instructions.

  In FIG. 11, EnableThread is a command for enabling a specific program counter, and can be used when starting another program counter that is sleeping other than the program counter. DisableThread is a command that disables a specific program counter. When other program counters other than the program counter are put into a sleep state, or when program execution is finished, they are put into a sleep state. Can be used when JUMP is a jump instruction and copies the operand Inst [21:12] to the currently selected program counter. In the present embodiment, since the program counter has 6 bits, Inst [17:12] is actually copied.

  LoadImmidiateByte is an instruction for loading an immediate value into an internal resource, and copies 1 byte indicated by the operand Inst [7: 0] to the internal resource specified by the other operand. ClearResiger is an instruction to clear internal resources to zero. LoopIn is a loop entry command, and is specified by LoopIndicator (Inst [22:19]). Loop register LP (corresponding to loop counter 7 in FIG. 1) and offset register OFST (corresponding to loop difference register 6 in FIG. 1) A loop is realized by the combination of

  Returning to FIG. 1, the instruction execution unit 5 executes data transfer or the like according to the instruction decoding result of the instruction decoding unit 4. The instruction execution unit 5 includes four general-purpose registers GPR and four address registers AR as internal resources. Further, the instruction execution unit 5 is a DMA interface (IN (0) and OUT (0)) for performing data transfer with the direct memory access device and a bus interface for performing data transfer with the memory. (Not shown).

  The general-purpose register GPR is a register that temporarily holds data. For example, the general-purpose register GPR is used when data loaded from a memory is copied to another internal resource for each byte. The address register AR is a register that generates an address to be output to the bus interface. As in the case of a general processor, a configuration including a mode (automatic update addressing mode) for updating the value of the address register AR for each data transfer is also preferable.

  Further, the instruction execution unit 5 has a program counter execution suppression function, and generates a program counter selection permission signal to be input to the selection signal generation unit 8 in accordance with the execution of the above-described EnableThread instruction and DisableThread instruction.

  Next, various controls in the loop control apparatus of the present embodiment having the above-described configuration will be described in detail with reference to FIGS.

  First, loop control, which is the most important function of the loop control apparatus, will be described.

  First, for the sake of simplicity, the function of a loop instruction will be described with an example in which one program counter executes a single loop. The loop register LP (loop counter 7) indicates the number of instruction loops, and the offset register OFST (loop difference register 6) indicates the difference between the address of the instruction to be looped back and the address of the loop instruction.

  The instruction execution unit 5 loads predetermined values into the loop register LP and the offset register OFST, respectively, and enters the loop by executing the loop instruction. When the program counter advances and the value of the program counter advances by the value stored in the offset register OFST, the value of the program counter is updated to an address indicating the instruction next to the loop instruction. That is, the value of the offset register OFST minus 1 is subtracted from the value of the program counter and the value of the loop register LP is decremented by 1. When the value of the loop register LP is 1, the loop register LP is cleared and the loop is exited. That is, 1 is simply added to the value of the program counter.

A program example using a very simple loop is shown below.
Instruction address Instruction 0x00 Load immediate value 0x20 to instruction 0x00 AR (0) [7: 0] 0x01 Load value in memory indicated by AR (0) to LP (0) (0x20 ground data = 0x20)
0x02 Load immediate value 0x01 to OFST (0) 0x03 LoopIn instruction (Indicator 0)
0x04 Read data from DMAPort (0) to memory address indicated by AR (1)
Store and AR (1) ++
0x05 Sleep yourself with DisableThread.

  According to the above instruction sequence, the loop counter is executed by executing the LoopIn instruction at address 0x03, and in the data transfer from the DMAPort (0) at address 0x04 to the memory, the value of the program counter is the address of the LoopIn instruction (address 0x03) + offset register Loops back because it matches (0x01 address). Further, jump to the next address of the LoopIn instruction, that is, address 0x04, and subtract 1 from the value of the loop register LP (0) (LP (0) = 31). This process is repeated the number of loops indicated by the loop register LP (0), that is, 32 times, and the process exits the loop and ends.

  Next, the control procedure of the loop information stack 9 by the stack control unit 10 will be described with reference to the flowchart of FIG. The processing shown in this flowchart is executed by the stack control unit 10 based on the control program.

  First, when the instruction decode unit 4 detects a loop instruction (step S1), the stack control unit 10 sets “1” in the IN_USE (0) IN_USE (0) flag in the loop information stack 9 (a flag indicating that the loop is being executed). To be pushed. At the same time, the program counter selection signal PC_SEL is pushed from the selection signal generator 8 to PC_SEL (0) of the loop information stack 9, and the output of the adder 13, that is, the loop end address is pushed to LP_END (0) of the loop information stack 9. Then, the LoopIndicator, that is, the LP_SEL signal output from the instruction decoding unit 4 is pushed to LP_SEL (0) of the loop information stack 9. The stack pointer held internally by the stack control unit 10 is updated from 0 to 1 (step S2).

  When the value of the program counter advances and reaches (matches) the loop end address corresponding to the loop instruction, the output match_end (0) of the second comparator group 15 becomes “1”, and the identifier of the currently selected program counter And the identifier of the program counter indicated to be currently in the loop state from the information stored in the loop information stack 9, the output match_pc (0) of the first comparator group 14 and Since both outputs in_use (0) of the loop information stack 9 are “1”, a loop end is detected (step S3). At this time, the third comparator group 17 compares whether or not the output selected by the multiplexer group 16 based on LP_SEL (0) of the loop information stack 9 is equal to 1, and the output is 1. If there is, the lp_exp (0) signal becomes “1”.

  If the lp_exp (0) signal is “1” (determination in step S4 is “1”), it means that the loop instruction has expired (end), so the stack control unit 10 operates the subtractor 18 to operate the loop register LP. (0) is decremented (that is, cleared to 0), IN_USE (0) of the loop information stack 9 is cleared, and the internal stack pointer is updated from 1 to 0 (step S5).

  When the lp_exp (0) signal is “0” (determination in step S4 is “0”), it means that the loop instruction is continued. Therefore, the stack control unit 10 operates the subtractor 18 to operate the loop register LP (0). And the loop_back signal is asserted to the program counter update unit 11. As described above, the program counter update unit 11 loads lp_back_pc, that is, PC-OFST + 1, to the PC (step S6). As a result, the program counter indicates the instruction next to the loop instruction.

  Next, the operation of the multiple loop will be described with reference to the flowcharts of FIGS. The processing shown in this flowchart is executed by the stack control unit 10 based on the control program.

  First, when the instruction decoding unit 4 detects a loop instruction 0 (step S11), “1” is pushed to IN_USE (0) of the loop information stack 9. At the same time, the program counter selection signal PC_SEL is pushed to PC_SEL (0) of the loop information stack 9, the output of the adder 13, that is, the loop end address is pushed to LP_END (0) of the loop information stack 9, and the instruction decoding unit 4 Is output to the LP_SEL (0) of the loop information stack 9. The stack pointer held internally by the stack control unit 10 is updated from 0 to 1 (step S12).

  When the value of the program counter advances and the instruction decoding unit 4 further detects the loop instruction 1 (step S13), “1” is pushed to IN_USE (1) of the loop information stack 9. At the same time, the program counter selection signal PC_SEL is pushed to PC_SEL (1) of the loop information stack 9, the output of the adder 13, that is, the loop end address is pushed to LP_END (1) of the loop information stack 9, and the instruction decoding unit 4 Is output to LP_SEL (1) of the loop information stack 9. The stack pointer held internally by the stack control unit 10 is updated from 1 to 2 (step S14).

  Further, when the value of the program counter advances and reaches (matches) the loop end address corresponding to the loop instruction 1, the output match_end (1) of the second comparator group 15 becomes “1”, and the currently selected program Since the identifier of the counter and the identifier of the program counter indicated by the information stored in the loop information stack 9 that are currently in the loop state are the same, the output match_pc ( Since 1) and the output in_use (1) of the loop information stack 9 are both “1”, the loop end is detected (step S15). At this time, the third comparator group 17 compares whether or not the output selected by the multiplexer group 16 based on LP_SEL (1) of the loop information stack 9 is equal to 1, and the output is 1. If there is, the lp_exp (1) signal becomes “1”.

  When the lp_exp (1) signal is “0” (determination in step S16 is “0”), it means that the loop instruction 1 is continued. Therefore, the stack control unit 10 operates the subtracter 18 to operate the loop register LP (1 ) Is decremented, and the loop_back signal is asserted to the program counter update unit 11. As described above, the program counter update unit 11 loads lp_back_pc, that is, PC-OFST + 1, to the PC (step S18). As a result, the program counter indicates the instruction next to the loop instruction 1.

  If the lp_exp (1) signal is “1” (determination in step S16 is “1”), it means that the loop instruction 1 has expired, so the stack control unit 10 operates the subtractor 18 to operate the loop register LP (1 ) Is decremented (that is, cleared to 0), IN_USE (1) of the loop information stack 9 is cleared, and the internal stack pointer is updated from 2 to 1 (step S17).

  If the output match_pc (0) of the first comparator group 14, the output match_end (0) of the second comparator group 15, and the output in_use (0) of the loop information stack 9 are all “1”, the loop It can be seen that instruction 0 is also a loop end. In this case, it is further determined whether or not the loop instruction 0 has expired based on the value of lp_exp (0).

  If the loop instruction 0 has expired (the determination in step S19 has expired: lp_exp (0) = 1), the stack control unit 10 operates the subtractor 18 to decrement the loop register LP (0) (ie, clear it to 0). And IN_USE (0) of the loop information stack 9 is cleared and the internal stack pointer is updated from 1 to 0 (step S20).

  When the loop instruction 0 is continued (determination in step S19 continues: lp_exp (0) = 0), the stack control unit 10 operates the subtracter 18 to decrement the loop register LP (0) and at the same time, lp_back_pc, PC-OFST + 1 is loaded onto the PC (step S21). As a result, the program counter indicates the instruction next to the loop instruction 0.

  Next, the operation of a plurality of program counters and multiple loops will be described.

The instruction sequence corresponding to the program counter PC (0) is shown below.
Instruction address Instruction 0x00 Enable PC (1) 0x01 Load immediate value 0x02 to LP (0) 0x02 Load immediate value 0x05 to OFST (0) 0x03 LoopIn instruction (Indicator 0)
0x04 Load immediate value 0x04 to LP (1) 0x05 Load immediate value 0x01 to OFST (1) 0x06 LoopIn instruction (Indicator 1)
0x07 Data read from DMAPort (0) is stored in memory address indicated by AR (0)
Store AR (0) ++
0x08 AR (0) [7: 0] is added with 0x100 0x09 PC (0) is disabled The instruction sequence corresponding to the program counter PC (1) is shown below.
Instruction address Instruction 0x10 Load immediate value 0x10 to AR (1) [15: 8] 0x11 Load immediate value 0x02 to LP (2) 0x12 Load immediate value 0x05 to OFST (2) 0x13 LoopIn instruction (Indicator 2)
0x14 Data read from DMAPort (1) is stored in the memory address indicated by AR (1)
Store and AR (1) ++
The program counter PC (0) uses a double loop, and the program counter PC (1) uses a simple loop. Program counter PC (2) is not used.

  FIG. 12 is a timing chart showing the timing when a multi-loop program is executed.

  In FIG. 12, the illustrated example shows the behavior of the program counter PC (0), the program counter PC (1), the program counter selection permission signal pc_en, the program counter selection signal pc_sel, etc. when a multi-loop program is executed. Yes.

  The clock signal cycle (hereinafter abbreviated as cycle) 0 is in the reset state, and the program counter selection permission signal pc_en is in the initial state “001”, thereby causing the program counter selection signal pc_sel to be “001”.

  In cycle 1, since the reset state is released and the program counter (Selected PC) selected by the program counter selection signal pc_sel is PC (0), the program counter PC (1) is enabled as shown in the above instruction sequence. The program counter selection permission signal pc_en is “011”.

  As a result, in cycle 2, the program counter selection signal pc_sel becomes “010”, the program counter PC (1) is selected, and the instruction 0x10 (loading the immediate value 0x10 to the address register AR (1) [15: 8]) ) Is executed. Thereafter, the program counter PC (0) and the program counter PC (1) are alternately executed sequentially.

  In cycle 7, the first loop instruction indicated by program counter PC (0) = 0x03 is executed. The contents of the loop information stack at the end of cycle 7 are shown in FIG. The in-use flag IN_USE (0) is set to “1”, the program counter selection signal pc_sel = “001” which executed the loop instruction, LoopIndicator “001” (indicating LP (0)) and the loop end address (PC (0 ) + OFST (0) = 0x08) is pushed.

  In cycle 8, a loop instruction indicated by program counter PC (1) = 0x13 is executed. The contents of the loop information stack 9 at the end of cycle 8 are shown in FIG. The in-use flag IN_USE (0) is set to “1”, the program counter selection signal pc_sel = “010” which executed the loop instruction, LoopIndicator “100” (indicating LP (2)) and the loop end address (PC (1) ) + OFST (2) = 0x14) is pushed.

  In cycle 10, the program counter selection signal pc_sel (0) = “010” and the loop end address lp_end (0) = 0x14 stored in the loop information stack 9 match the current program counter selection signal pc_sel and the program counter PC. Therefore, a loop end determination is executed. Since the value of the loop register LP (2) is 4 and does not match 1, it is determined that the loop is back, the loop register LP (2) is decremented by 1, and the program counter PC (1) is PC-OFST + 1 = 1 = 0x14-0x01 + 1 = 0x14. Exactly the same operation as cycle 10 occurs in cycle 12 and cycle 14.

  In cycle 13, a loop instruction for entering the inner loop of the double loop of program counter PC (0) (= 0x06) is executed. The contents of the loop information stack 9 at the end of the cycle 13 are shown in FIG. The in-use flag IN_USE (0) is set to “1”, the program counter selection signal pc_sel = “001”, LoopIndicator “010” (indicating LP (1)) and the loop end address (PC (0)) that executed the loop instruction ) + OFST (1) = 0x07) is pushed.

  In cycle 14, the program counter selection signal pc_sel (0) = “010” and the loop end address lp_end (0) = 0x14 stored in the loop information stack 9 match the current program counter selection signal pc_sel and the program counter PC. Therefore, a loop end determination is executed. At this time, since the value of the loop register LP (2) is 1 and coincides with 1, it is determined that the loop is finished, the loop register LP (2) is decremented by 1 (cleared to 0), and the program counter PC ( 1) exits from the loop with PC + 1 = 0x15. The contents of the loop information stack 9 at the end of the cycle 14 are shown in FIG. The item (1) of the loop information stack 9 is popped, and the in-use flag IN_USE (2) is cleared to “0”.

  In cycle 18, an instruction of program counter PC (1) = 0x15 is executed, program counter PC (1) is disabled (program counter selection signal pc_en = “001”), and after cycle 19, program counter PC (0 Only the instruction of) is executed.

  On the other hand, in cycles 15, 17, 19, and 20, the one near the top of the loop information stack 9 (stack (0) in FIG. 16) is used, and the loop end determination of the inner loop of the program counter PC (0) Executed. In cycles 15, 17, and 19, a loopback occurs, and in cycle 20, the loop ends. The contents of the loop information stack at the end of cycle 20 are shown in FIG. The item (0) of the loop information stack 9 is popped, and the in-use flag IN_USE (1) is cleared to “0”.

  In cycle 21, the outer loop end of the program counter PC (0) is reached, and the loop end determination of the outer loop is executed. Since the value of the loop register LP (0) is 2, a loop back occurs, and the program counter PC (0) = PC (0) -OFST (0) + 1 = 0x08-0x05 + 1 = 0x04 is loaded, and cycle 22 The instruction stored at 0x04 is executed.

  Thereafter, in the cycle 24, the inner loop is again entered (the loop information stack 9 is in the state shown in FIG. 16), and in the cycles 25, 26, 27, and 28, the loop end determination is executed. In cycles 25, 26, and 27, loopback is performed, and in cycle 28, the loop ends.

  In cycle 29, the outer loop of the program counter PC (0) is ended (LP (0) = 1), and all in-use flags of the loop information stack 9 are cleared as shown in FIG. Although not shown in the timing chart of FIG. 12, the program counter PC (0) is incremented by 1 to 0x09, and the program counter PC (0) is disabled, that is, the program execution is terminated.

  As described above, according to the present embodiment, in the sequence control of a program that executes instructions that are sequentially referred to by the plurality of program counters 1-1, 1-2, and 1-3, An identifier (program counter selection signal) indicating a program counter corresponding to the instruction, a loop end address corresponding to the loop instruction, and an identifier indicating which loop counter and loop difference register the loop instruction uses are stored in the loop information stack 9. When the value of the program counter coincides with the loop end address, the presence or absence of the loop instruction is determined by referring to the identifier indicating the program counter from the top of the loop information stack 9.

  That is, by adding a program counter selection signal as a program counter identifier to the information stored in the loop information stack 9 and performing loop end determination from the top of the loop information stack 9 at the end of the loop, a plurality of program counters are enabled in parallel. Even when each executes a multiple loop, it is possible to easily determine whether it is a loopback or a loop end.

  As a result, it is not necessary to prepare as many stack structures as the number of program counters, and a plurality of program counters can efficiently execute multiple loops in parallel with a very simple and small circuit configuration.

[Second Embodiment]
The second embodiment of the present invention differs from the above-described first embodiment in how to process when a plurality of loops expire simultaneously. Since the other elements of the present embodiment are the same as the corresponding ones of the first embodiment (FIGS. 1 to 4) described above, description thereof is omitted.

In the present embodiment, the following program is executed by slightly changing the program of the program counter PC (0).
Instruction address Instruction 0x00 Enable PC (1) 0x01 Load immediate value 0x02 to LP (0) 0x02 Load immediate value 0x05 to OFST (0) 0x03 LoopIn instruction (Indicator 0)
0x04 Load immediate value 0x04 to LP (1) 0x05 Load immediate value 0x01 to OFST (1) 0x06 Add 0x100 to AR (0) [7: 0] 0x07 LoopIn instruction (Indicator 1)
0x08 Data read from DMAPort (0) is stored in the memory address indicated by AR (0)
Store AR (0) ++
Disable 0x09 PC (0) The inner loop of the program counter PC (0) starts from 0x07, and the loop end address is 0x08 for both the inner and outer loops of the program counter PC (0).

  FIG. 19 is a timing chart showing the timing when the changed program is executed.

  In FIG. 19, the illustrated example shows the behavior of the program counter PC (0), the program counter PC (1), the program counter selection permission signal pc_en, the program counter selection signal pc_sel, and the like when the changed program is executed. Yes.

  In cycle 15, all the loops are in use, and the contents of the loop information stack 9 are as shown in FIG. In cycle 16, the loop of program counter PC (1) is completed, and the contents of loop information stack 9 are as shown in FIG.

  In cycle 21, the inner and outer loops of program counter PC (0) are both loop ends. Evaluation is performed from the top of the loop information stack 9, and the stack (0) is determined to be the loop end because the loop register LP (1) = 1, and the stack (1) is determined to be the loop register LP (0) = 2. Therefore, it is determined as a loopback. In this case, the loop information stack 9 corresponding to the end of the loop is popped, and the value corresponding to the loopback, that is, PC (1) -OFST (0) + 1 = 0x08-0x05 + is stored in the program counter PC (0). 1 = 0x04 is loaded.

  In cycle 25, both the inner and outer loops of program counter PC (0) are again in use (loop information stack 9 is in the state shown in FIG. 21), and in cycle 29, both the inner and outer loops are loops. Become an end. In cycle 29, since both the loop register LP (0) and the loop register LP (1) are 1, it is determined that both the inner loop and the outer loop have ended, and all the in-use flags in the loop information stack 9 are cleared. The Although not shown in the timing chart of FIG. 19, the program counter PC (0) is incremented by 1 to 0x09, and the program counter PC (0) is disabled, that is, the program execution is terminated.

  As described above, according to the present embodiment, as in the first embodiment, it is not necessary to prepare stack structures as many as the number of program counters, and with a very simple and small circuit configuration, Multiple program counters can efficiently execute multiple loops in parallel.

[Other embodiments]
In the first and second embodiments, the loop control device has been described. However, the loop control device of the present invention can be applied to a direct memory access (DMA) control device. Further, the loop control device of the present invention can be applied to various image processing devices (printers, copiers, multifunction devices, facsimiles, etc.).

  According to the present invention, a software program (flowcharts in FIGS. 22 to 24) for realizing the functions of the above-described embodiments is supplied to a computer or CPU, and the computer or CPU reads and executes the supplied program. Can be achieved.

  In this case, the program is directly supplied from a storage medium storing the program, or downloaded from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like. Supplied.

  The form of the program may be in the form of object code, program code executed by an interpreter, script data supplied to an OS (operating system), and the like.

  The present invention also supplies a computer or CPU with a storage medium storing a software program that implements the functions of the above-described embodiments, and the computer or CPU reads and executes the program stored in the storage medium. Can also be achieved.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for storing the program code, for example, ROM, RAM, NV-RAM, floppy (registered trademark) disk, hard disk, optical disk (registered trademark), magneto-optical disk, CD-ROM, MO, CD-R, CD -RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW, magnetic tape, nonvolatile memory card, etc.

  The function of the above-described embodiment is not only by executing the program code read from the computer, but the OS or the like running on the computer performs part or all of the actual processing based on the instruction of the program code. Can also be realized.

It is a block diagram which shows the structure of the loop control apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the detailed structure of an instruction memory. It is a block diagram which shows the detailed structure of a program counter, a program counter selection part, and a program counter update part. It is a block diagram which shows the detailed structure of a selection signal production | generation part. It is a figure which shows the relationship between the decoding system of a program counter selection permission signal, and a selection control signal. It is a figure which shows the decoding result of an instruction | indication. It is a figure which shows the meaning of a data size field. It is a figure which shows the meaning of an internal resource identifier. It is a figure which shows the relationship between a data size field, a byte lane field, and an effective byte lane. It is a continuation of FIG. It is a figure which shows the encoding of a special instruction. It is a timing chart which shows the timing at the time of executing the program of a multiple loop. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 7 in FIG. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 8 in FIG. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 13 in FIG. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 14 in FIG. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 20 in FIG. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 29 in FIG. It is a timing chart which shows the timing at the time of running the program after a change concerning a 2nd embodiment of the present invention. It is a figure which shows the content of the loop information stack at the time of completion | finish of the cycle 15 in FIG. FIG. 20 is a diagram showing the contents of a loop information stack at the end of cycle 16 in FIG. 19. It is a flowchart which shows the control procedure of a loop information stack. It is a flowchart which shows the operation | movement of a multiplex loop. It is a continuation of FIG.

Explanation of symbols

1-1, 1-2, 1-3 Program counter 2 Program counter selection section (corresponding to selection means)
3 Instruction memory 4 Instruction decode unit 5 Instruction execution unit 6 Loop difference register (corresponding to difference holding means)
7 Loop counter (corresponding to loop count holding means)
8 Selection signal generator 9 Loop information stack (corresponding to the stack )
10 Stack controller (corresponding to control means)
11 Program counter update unit 14 First comparator group (corresponding to the first comparison means)
15 Second comparator group (corresponding to the second comparison means)
16 Multiplexer group (corresponding to output selection means)
17 Third comparator group (corresponding to third comparison means)

Claims (6)

A loop control device comprising a plurality of program counters and a plurality of loop counters ,
Selecting means for outputting a value of one program counter selected from the plurality of program counters as an address of an instruction memory;
An instruction output means for outputting an instruction stored in the address output by the selection means to the instruction execution means;
When the instruction output from the instruction output means is a loop instruction, an end address of the loop process executed according to the loop instruction, a first identifier indicating a program counter for executing the loop process, and a loop of the loop process A stack that can store a plurality of pieces of loop information that is held in association with a second identifier that indicates a loop counter that holds information about the number of times ;
When said instruction output unit stores the loop information regarding the loop instruction when outputting a loop instruction to the stack, the selection means selects a new program counter, loop including a first identifier indicating the program counter The selection means selects the loop information closest to the top of the stack from among the information based on the end address included in the loop information and the value of the loop counter indicated by the second identifier included in the loop information. And a control means for determining whether or not the loop processing being executed by the running program counter is terminated. First comparison means for detecting a match between a program counter selection signal supplied to the selection means and indicating a program counter selected by the selection means and a first identifier indicating the program counter;
Second comparison means for detecting a match between the value before disappeared command address of the program counter that said selecting means outputs,
Output selection means for selecting one value of the plurality of loop counters based on the second identifier held by the stack ;
A third comparing means for detecting whether the output of the output selecting means matches a predetermined value;
2. The loop control apparatus according to claim 1, wherein the control means controls a value held by the loop counter in accordance with outputs of the first, second and third comparison means. And further comprising difference holding means corresponding to the second identifier,
It said control means indicates the output match of the first comparison means, when the output of said second comparing means that corresponds to the end address with the nearest loop information at the top of the stack indicates the agreement In addition,
If the output of the third comparison means corresponding to the loop information does not indicate a match, the second identifier stored in the loop information is determined from the value of the program counter selected by the selection means. subtracting the value held in the holding means is subtracted, and controls such that the second identifier is 1 subtracts the value held in the loop counter indicating shown,
If the output of said third comparing means corresponding to the loop information indicates a match, as well as disable the loop, holding of the loop counter indicated by the second identifier that is stored in the loop information loop controller according to claim 2, wherein the controller controls the be so that the value that subtracts 1 or 0. And further comprising difference holding means corresponding to the second identifier,
The control means, the sample output matches the first comparison means, the output of two or more of said second comparison means corresponding to the loop information including the nearest loop information at the top of the stack match Where
If at least one of the outputs of the third comparison means corresponding to the two or more loop information does not indicate a match, the one not indicating a match is stored in the loop information closest to the top of the stack. The value held by the difference holding means indicated by the second identifier is subtracted from the currently selected program counter, and the value held by the loop counter indicated by the second identifier stored in the loop information is 1 Control to subtract,
When all the outputs of the third comparison means corresponding to the two or more loop information indicate coincidence, the two or more loop information are invalidated and the two or more loop information loop controller according to claim 2, wherein the controller controls the to so that all the values held by the two or more of the loop counter indicated by the second identifier stored in the decremented or 0.   5. The loop control device according to claim 1, wherein the number of stages of the stack matches the number of the loop counters. A plurality of program counters, a plurality of loop counters, an end address of a loop process executed according to a loop instruction, a first identifier indicating a program counter for executing the loop process, and information on the number of loops of the loop process are held. A control method of a loop control device comprising a stack capable of storing a plurality of pieces of loop information that is stored in association with a second identifier indicating a loop counter ,
A selection step of outputting a value of one program counter selected from the plurality of program counters as an address of an instruction memory;
An instruction output step for outputting the instruction stored in the address output by the selection step to the instruction execution means;
Loop information comprising a first identifier indicating the program counter when the loop information regarding the loop instruction when outputting the loop instruction is stored in the stack in the instruction output step, said selecting step selects a new program counter The loop information closest to the top of the stack is referred to and executed by the program counter selected in the selection step based on the end address included in the loop information and the second identifier included in the loop information. And a control step for determining the end of the loop processing being performed .

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