JP2926045B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microprocessor capable of executing a plurality of instructions in parallel.

[0002]

2. Description of the Related Art Conventionally, various processor architectures such as superscalar and multithread are known. If these architectures are employed, a plurality of instructions can be executed simultaneously in one cycle, so that a high-performance microprocessor can be realized.

[0003]

The conventional instruction parallel execution type microprocessor has a problem in easiness of programming in various aspects such as a need to avoid data dependence.

[0004] It is an object of the present invention to provide a high performance microprocessor which is easy to program.

[0005]

In order to achieve the above object, the present invention provides a micro processor comprising a plurality of arithmetic processing units connected to one instruction issuing unit so that a plurality of instructions can be executed in parallel. Adopt the processor configuration,
At least one specific processing unit among the plurality of processing units can autonomously execute a series of processing. This configuration facilitates programming of a group of instructions to be executed by the particular processing unit.

More specifically, the microprocessor of the present invention comprises a plurality of processing units, an instruction memory for storing a plurality of instructions to be executed by each of the plurality of processing units, An instruction issuing unit for fetching an instruction from a memory and supplying the fetched instruction to a corresponding arithmetic processing unit among the plurality of arithmetic processing units is employed. In addition, at least one specific arithmetic processing unit among the plurality of arithmetic processing units has an instruction buffer for storing a plurality of instructions supplied from the instruction issuing unit, and has been read from the instruction buffer. An instruction decoder for decoding the instruction, an operation execution unit for executing an operation according to the result of the decoding by the instruction decoder, and a write address of the instruction buffer in response to a control signal received from the instruction issue unit. And an address generation unit for generating a read address of the instruction buffer in accordance with a control signal generated and received from the instruction decoder.

In the instruction buffer in the specific arithmetic processing unit, instructions for controlling repetitive processing (for example, a repeat start instruction and a repeat end instruction) and instructions for controlling conditional execution processing (for example, conditional branch instructions) ) Can be stored. Also, an area for defining a macro, that is, an area for storing a macro body can be secured in the instruction buffer. Macro expansion based on a macro call instruction is performed by referring to a plurality of instructions (hereinafter, referred to as macro configuration instructions as appropriate) constituting a macro main body stored in a macro definition area, thereby allowing the specific arithmetic processing unit to execute. Can be done autonomously.

[0008]

FIG. 1 shows a configuration example of a microprocessor according to the present invention. The microprocessor of FIG. 1 includes an instruction memory 1, an instruction issuing unit 2, a first
Processing unit 3a and the second processing unit 3
b, an operation execution unit 8c, and a data memory 4c. The instruction memory 1 is a memory for storing a plurality of instructions to be executed by each of the first operation processing unit 3a, the second operation processing unit 3b, and the operation execution unit 8c. The instruction issuing unit 2 includes a control bus 1
The address and control signal are supplied to the instruction memory 1 via the instruction memory 8 and the instruction stored in the instruction memory 1 is transmitted to the instruction bus 19.
And a unit for supplying the fetched instruction to the instruction bus 9a. If the fetched instruction is an instruction to be executed by the operation execution unit 8c, the instruction issuing unit 2 further decodes the fetched instruction. Arithmetic execution unit 8c
Transmits / receives a control signal to / from the instruction issuing unit 2 via the control bus 9b, receives a decoded result of the instruction via the instruction bus 9a, and executes an operation according to the decoded result. It is a unit for. The data memory 4c is a memory that receives an address and a control signal from the operation execution unit 8c via the control bus 16c, and exchanges data with the operation execution unit 8c via the data bus 17c.

The first arithmetic processing unit 3a is a unit having an autonomous execution function of a repetition process and a condition execution process, and executes a plurality of instructions supplied from the instruction issuing unit 2 via the instruction bus 9a. An instruction buffer 6a for storing, an instruction decoder 7a for receiving and decoding the instruction read from the instruction buffer 6a via the instruction bus 12a, and an instruction from the instruction decoder 7a via the instruction bus 15a. Receive the decoding result of
And an operation execution unit 8a for executing an operation according to the decoding result, and an address and a control signal from the operation execution unit 8a via the control bus 16a.
And the operation execution unit 8a via the data bus 17a
A data memory 4a for transmitting and receiving data to and from the data memory 4a, a flag register 20a for receiving the operation result flag of the operation execution unit 8a via the control bus 14a and storing the operation result flag, and a control bus 9b. A control signal is exchanged with the instruction issuing unit 2 via the control bus 11a, a control signal is received from the instruction decoder 7a via the control bus 11a, an operation result flag is referenced via the control bus 13a, and An address generator 5a for outputting a write address and a read address of the instruction buffer 6a via the bus 10a.

The second arithmetic processing unit 3b is a unit having a macro function, and has an instruction buffer 6b for storing a plurality of instructions supplied from the instruction issuing unit 2 via the instruction bus 9a; Receiving the instruction read from the instruction buffer 6b via the instruction bus 12b;
An instruction decoder 7b for decoding, an operation execution unit 8b for receiving an instruction decoding result from the instruction decoder 7b via the instruction bus 15b, and executing an operation according to the decoding result, and a control bus 16b
, A data memory 4b for receiving an address and a control signal from the execution unit 8b via the data bus 17b, and transmitting and receiving data to and from the execution unit 8b via the data bus 17b, and an instruction via the control bus 9b. An address generation unit for receiving a control signal from the issuing unit 2, receiving a control signal from the instruction decoder 7b via the control bus 11b, and outputting a write address and a read address of the instruction buffer 6b via the address bus 10b 5b.

FIG. 2 shows the detailed configuration of the address generator 5a in FIG. In FIG. 2, 108 to 113 are selectors, 121 to 124 are registers, and 129 is an adder. The register (LNREG0) 121 is a register for storing the address of the instruction next to the repetition start instruction in the instruction buffer 6a. The input unit is connected to the output unit of the two-input selector 108, and the output unit is The first input unit of the 4-input selector 112 and the 2-input selector 108
Is connected to the first input unit. Register (LNR
EG1) 122 is a register for storing the address of the instruction next to the other repetition start instruction in the instruction buffer 6a. The input is connected to the output of the two-input selector 109, and the output is Second of 4-input selector 112
And the first input unit of the two-input selector 109. The register (LNREG2) 123 is a register for storing the address of the instruction next to the still other repetition start instruction in the instruction buffer 6a, the input part of which is connected to the output part of the two-input selector 110, and An output section is connected to a third input section of the four-input selector 112 and a first input section of the two-input selector 110. The register (RADR) 124 is a register for storing the read address of the instruction buffer 6a. The input unit is connected to the output unit of the three-input selector 111, and the output unit is connected to the fourth input of the four-input selector 112. Unit and a first input unit of the three-input selector 111. The output of the four-input selector 112 is connected to the first input of the adder 129. The output part of the 4-input selector 112 supplies the read address RADRS to the instruction buffer 6a.
To the address bus 10a. The adder 129 is configured such that the second input unit is a three-input selector 1
Thirteen outputs, and the output is connected to the second input of each of the two-input selectors 108-111. The third input unit of the three-input selector 111 receives a constant value “0” as an input.

Reference numeral 127 denotes a loop control unit, and 128 denotes a control block (CNT1). The input section of the loop control section 127 is connected to the instruction decoder 7a via the control bus 11a. The output (loop end signal: LED) of the loop control unit 127 is input to the input unit of the control block 128, and the output unit of the control block 128 is a four-input selector 11
2 control inputs.

Reference numeral 126 denotes a register, and 131 denotes a control block (CNT2). The first input of the three-input selector 113 receives a constant value “0”, and the second input thereof receives a constant value “1”. Register (JADR) 1
Reference numeral 26 denotes a register for storing a relative jump address in the instruction buffer 6a. The input unit is connected to the instruction decoder 7a via the control bus 11a, and the output unit is connected to the third input unit of the three-input selector 113. Have been. The control block 131 is such that the first input unit is the control bus 1
The second input unit is connected to the instruction decoder 7a via the control bus 11a, and the output unit is connected to the control input unit of the three-input selector 113, respectively.

Reference numeral 114 is a three-input selector, 125 is a register, and 130 is an incrementer. Register (WAD
R) 125 is a register for storing the write address of the instruction buffer 6a, the input part of which is connected to the output part of the three-input selector 114, and the output part of which is connected to the first input part of the three-input selector 114. It is connected to the input section of the incrementer 130. The output of the register 125 is also connected to the address bus 10a to supply the write address WADRS to the instruction buffer 6a. The second input of the three-input selector 114 receives the output of the incrementer 130, and the third input receives a constant value "0". The control input unit of the three-input selector 114 is connected to the instruction issuing unit 2 via the control bus 9b.
It is connected to the.

132 is a two-input selector, 133 is a control block (CNT3), and 134 is a flag register.
The two-input selector 132 has a first input unit connected to the output unit of the four-input selector 112, and a second input unit connected to the output unit of the register 125. 2 input selector 13
2 is connected to the input of the control block 133, and the output of the control block 133 is connected to the input of the flag register 134. The output of the flag register 134 is connected to the instruction issuing unit 2 via the control bus 9b. The control block 133 includes a two-input selector 1
It is provided with a 1-bit storage unit for each address value input via the interface 32.

FIG. 3 shows a detailed configuration of the loop control unit 127 in FIG. In FIG. 3, 200 to 207 are selectors, 215 to 220 are registers, 226 is an incrementer, and 227 is a comparator. Register (LCOR
EG0) 215 is a register for storing the number of times the repetition processing has been executed, and has an input unit connected to the output unit of the three-input selector 200, and an output unit connected to the first input unit of the three-input selector 203. First of three-input selector 200
Is connected to the input section. Register (LCOREG
1) Reference numeral 216 denotes a register for storing the number of times of execution of the inner repetition processing. The input unit is connected to the output unit of the three-input selector 201, and the output unit is connected to the second input of the three-input selector 203. Unit and the first input unit of the three-input selector 201. Register (LCORE)
G2) 217 is a register for storing the number of executions of the further inner repetition processing, the input unit being connected to the output unit of the three-input selector 202, and the output unit being the third input unit of the three-input selector 203; Input unit and three-input selector 20
2 first inputs. The output of the three-input selector 203 is connected to the input of the incrementer 226 and the first input of the comparator 227, and the output of the incrementer 226 is connected to the three-input selector 200, 201, 20.
2 is connected to the second input of each of the two. A constant value “1” is input to each of the third input units of the three-input selectors 200, 201, and 202.

The register (LCREG0) 218 is a register for storing the number of times the repetitive processing is to be executed. The input section is connected to the output section of the 2-input selector 204, and the output section is connected to the 3-input selector 207. And a first input unit of the two-input selector 204. The register 219 (LCREG1) is a register for storing the number of times the inner repetition processing is to be executed. The input section is connected to the output section of the 2-input selector 205, and the output section is connected to the 3-input selector 207. The second input unit and the first input unit of the two-input selector 205 are connected. Register 220 (LCREG2)
Is a register for storing the number of times the further inner repetition processing is to be performed. The input unit is connected to the output unit of the two-input selector 206, and the output unit is connected to the third input terminal of the three-input selector 207. Unit and the first input unit of the two-input selector 206. 3 input selector 207
Is connected to the second input of the comparator 227. The second input of each of the two-input selectors 204, 205, 206 is connected to the instruction decoder 7a via the control bus 11a. The output of the comparator 227 is the output LED of the loop control unit 127.

The selectors 108 to 111, 200 to
Each control input unit 207 is connected to the instruction decoder 7a via the control bus 11a, but illustration of these selector control inputs is omitted in FIGS.

FIG. 4 shows an example of the format of an instruction stored in the instruction memory 1 in FIG. In FIG. 4, reference numeral 21 denotes an execution unit designation bit (EUB);
22 is a code part. Execution unit specification bit 21
Is a 2-bit portion indicating which of the arithmetic execution unit 8c and the first and second arithmetic processing units 3a and 3b should execute the instruction. When EUB is expressed in binary, EUB = 00 specifies the operation execution unit 8c, EUB = 01 specifies the first operation processing unit 3a, and EUB = 10 specifies the second operation processing unit 3b. The code section 22 is a part indicating the execution content of the instruction, and includes an operation code and an operand. In the case of a conditional branch instruction, a condition code and a relative jump address are defined in the code section 22.

The operation of the microprocessor shown in FIG. 1 will be described. First, the instruction issuing unit 2 supplies an address and a read permission signal to the instruction memory 1 via the control bus 18, and fetches an instruction via the instruction bus 19. In the next step, the instruction issuing unit 2 executes decoding of the fetched instruction. In this instruction decoding process, the execution unit designation bit (EUB) 2 shown in FIG.
1 is decoded. When the EUB is "00 (binary notation)", the instruction issuing unit 2 further decodes the code part 22 of the instruction, and supplies the result of the decoding processing to the arithmetic execution unit 8c via the instruction bus 9a. Then, the process proceeds to the operation execution process in the operation execution unit 8c. If the EUB is "01", the instruction issuing unit 2 stores the code part 22 of the instruction in the instruction buffer 6a included in the first arithmetic processing unit 3a in the instruction bus 9a.
Write via. If EUB is "10", the instruction issuing unit 2 writes the code part 22 of the instruction to the instruction buffer 6b included in the second arithmetic processing unit 3b via the instruction bus 9a. EUB is "01",
In any case of "10", the instruction buffer 6a,
After the instruction writing process into the instruction execution units 8a and 8b, the process shifts to an instruction reading process from the instruction buffers 6a and 6b for each instruction, and through an instruction decoding process by the instruction decoders 7a and 7b. Move to execution.

FIG. 5 shows an example of an execution instruction sequence in the microprocessor of FIG. Here, it is assumed that the binary code of each of the twelve instructions shown in FIG. According to this example, the EUBs of the first and second instructions (OP1 and OP2) are both “0”.
0 ". These instructions are decoded by the instruction issuing unit 2 up to the code section 22, and the result of the decoding is supplied to the arithmetic execution unit 8c via the instruction bus 9a, and the arithmetic processing is executed. Third to sixth instructions (EX1
-OP1 to EX1-OP4) are all "01", so these instructions are written to the instruction buffer 6a in the first arithmetic processing unit 3a via the instruction bus 9a, and are executed. The arithmetic processing is performed in the unit 8a. Since the EUBs of the seventh to tenth instructions (from OP3 to OP6) are all "00", these instructions are decoded up to the code part 22 by the instruction issuing unit 2 similarly to the first and second instructions. The result of the decoding process is supplied to the operation execution unit 8c via the instruction bus 9a, and the operation process is executed. Finally, the E of the eleventh and twelfth instructions (EX2-OP1 and EX2-OP2)
Since all UBs are "10", these instructions are written to the instruction buffer 6b in the second arithmetic processing unit 3b via the instruction bus 9a, and arithmetic processing is performed in the arithmetic execution unit 8b.

Here, the process of writing an instruction to the instruction buffer 6a in the first arithmetic processing unit 3a will be described in detail. When the writing process to the instruction buffer 6a is started, first, the address generation unit is transmitted from the instruction issuing unit 2 via the control bus 9b so that the selector 114 selects the constant value "0" as the third input value. A control signal is supplied to 5a. The register 125 stores the value “0” received from the selector 114. The stored value “0” of the register 125 is the write address WA of the instruction buffer 6a.
It is output to the address bus 10a as the initial value of DRS. Based on the address WADRS, the writing of the instruction supplied from the instruction issuing unit 2 to the instruction buffer 6a via the instruction bus 9a is executed. When instructions are continuously written to the same instruction buffer 6a, the register 1 is incremented by the incrementer 130 every clock cycle.
25 is incremented by one, and this is
14 and stored as the next value in the register 125,
It is output via the address bus 10a as a write address of the next instruction in the instruction buffer 6a, and successive instructions are written to successive addresses in the instruction buffer 6a. In addition,
At the time of writing the instruction, although not shown in FIG. 2, a write enable signal is also supplied from the address generation unit 5a to the instruction buffer 6a to permit writing of the instruction to the address indicated by the output of the register 125. . When the instruction writing process from the instruction issuing unit 2 is not performed, the selector 114 selects the first input value.
That is, the register 125 is not updated. Further, the write enable signal is not supplied to the instruction buffer 6a, and the writing of the instruction to the instruction buffer 6a is in a waiting state.

On the other hand, the write address WADRS output from the register 125 is taken into the control block 133 via the selector 132. Control block 13
Inside 3, the value of the 1-bit storage unit corresponding to the write address fetched via the selector 132 is rewritten from "0" to "1". The output value of the control block 133 is the logical product of the values in the storage unit corresponding to all the addresses of the instruction buffer 6a, and the logical product is stored in the flag register 134. That is, the flag register 134
, Ie, the status flag is set to “1” so that the writing process to the instruction buffer 6a is stopped when the storage units of all the addresses of the instruction buffer 6a are filled with unread instructions. You. This flag register 1
The output value of 34 is transmitted to the instruction issuing unit 2 via the control bus 9b, and the instruction issuance to the first arithmetic processing unit 3a is controlled. Although not shown in FIG. 2, the output value of the flag register 134 is stored in the instruction buffer 6a.
This is also reflected in the write enable signal to

FIG. 6 shows an example of an execution instruction sequence including repetition processing in the first arithmetic processing unit 3a.
The second instruction (LOOP) in FIG. 6 is a repetition start instruction, and the sixth instruction (LOOP-end) is a repetition end instruction.

FIG. 7 shows the pipeline configuration of the first arithmetic processing unit 3a in accordance with the example of the instruction sequence shown in FIG. The operation of the first arithmetic processing unit 3a includes three stages: an instruction fetch process (IF) from the instruction buffer 6a, an instruction decode process (DEC) by the instruction decoder 7a, and an arithmetic execution process (EXE) by the arithmetic execution unit 8a. Pipeline. Each pipeline stage can be executed in one clock cycle. In FIG. 7, the right direction is the positive direction of time, the downward direction is the flow of execution instructions, and each cycle is denoted by T0 to T0.
Identified by T8.

First, in the cycle T0, the first instruction (EX
1-OP1) is read from the instruction buffer 6a. In the address generation unit 5a, the control block 128 supplies a default control signal so that the selector 112 selects the fourth input value based on the instruction execution start control signal obtained via the control bus 9b. . The selector 111 receives a default control signal so as to select a constant value “0” that is a third input value. As a result, the register 124
Stores the value “0”. The value “0” stored in the register 124 is output as the initial value of the read address RADRS of the instruction buffer 6a via the address bus 10a. At the same time, a read enable signal is supplied from the address generation unit 5a to the instruction buffer 6a, and the instruction is read from the instruction buffer 6a to the instruction decoder 7a via the instruction bus 12a. The read address RADRS is also supplied to the control block 133 via the selector 132. Control block 133
Performs a process of returning the value of the 1-bit storage unit set to “1” at the time of writing to “0” in accordance with the read address RADRS.

In the cycle T1, the decoding processing of the first instruction by the instruction decoder 7a and the reading processing of the repetition start instruction (LOOP) as the second instruction from the instruction buffer 6a are executed in parallel. Here, the update of the read address will be described in detail. In the address generator 5a, the control signal is fixed so that the selector 112 selects the fourth input value. In the cycle T1, the value of the register 124 output via the selector 112, which is the read address RADRS of the instruction buffer 6a in the cycle T0, is added with "1" by the adder 129 to make the selector 111 The value of the register 124 is updated via the terminal. In cycle T1, selector 1
08 to 110 select the first input value, and the control signal is applied so that the selector 111 selects the second input value, that is, the output value of the adder 129. On the other hand, the selector 113 sets the second input value, ie, the constant value “1”.
And the control block 131 supplies a default control signal to the selector 113 so that the constant value “1” is supplied to the second input of the adder 129. Thus, the read address R supplied to the instruction buffer 6a is
ADRS is incremented by one.

In cycle T2, the operation execution unit 8a
, A process of decoding the second instruction by the instruction decoder 7a, and a process of reading the third instruction (EX1-OP2) from the instruction buffer 6a are executed in parallel. When the first instruction is an instruction for storing a data processing result, the operation execution unit 8a is controlled by the control bus 16a.
Via the data bus 17a
The data is supplied to the data memory 4a via the data memory 4a. When the first instruction is an operation instruction, an operation result flag is stored in the flag register 20a via the control bus 14a according to the operation result in the operation execution unit 8a. The second instruction, which is a repetition start instruction, has a code part 2
2, the number of repetition processes (3 in the example of FIGS. 6 and 7).
Times). The number of repetitions decoded by the instruction decoder 7a is stored in the register 218 via the control bus 11a and the selector 204. At this time, control signals are supplied such that the selector 204 selects the value of the control bus 11a, which is the second input value, and the selectors 205 and 206 each select the first input value. on the other hand,
A control signal is supplied so that the selector 108 selects the second input value, that is, the output value of the adder 129, and the read address of the third instruction is stored in the register 121. A control signal to selector 108 is held so that the value of register 121 is held after the next cycle. Third
The read operation of the instruction is the same as the read operation of the first and second instructions.

In cycle T3, the operation execution processing of the second instruction, the decoding processing of the third instruction, and the fourth instruction (EX1-
The reading process of OP3) is executed in parallel. Since the second instruction is a repeat start instruction, there is no operation execution processing. The decoding processing of the third instruction and the reading processing of the fourth instruction are similar to those in the cycle T1.

In cycle T4, the operation execution processing of the third instruction, the decoding processing of the fourth instruction, and the fifth instruction (EX1-
The reading process of OP4) is executed in parallel.

In cycle T5, the operation execution processing of the fourth instruction, the decoding processing of the fifth instruction, and the reading processing of the repetition end instruction (LOOP-end) which is the sixth instruction are executed in parallel. The read sixth instruction is decoded in cycle T6. Instruction decoder 7a
Supplies a control signal so that the selector 200 of the address generation unit 5a selects the third input value "1" when decoding the repetition end instruction. Thereby, the register 2
The value “1” is stored in 15. Further, a control signal is supplied so that each of the selectors 203 and 207 selects the first input value. The comparator 227 compares the value of the register 215 with the value of the register 218. Upon receiving the output of the comparator 227, the control block 128
Is smaller than the value of the register 218, the selector 112 supplies a control signal to select the first input value. With this control, the instruction read address next to the sixth instruction becomes the value of the register 121 that is the first input value of the selector 112, that is, the storage address of the third instruction (EX1-OP2) in the instruction buffer 6a. . As a result, in the cycle T6, the read processing of the third instruction is executed again. Then, the value of the register 124 is added to the adder 129.
It is updated according to the output of.

According to the above process, the third to sixth instructions can be repeatedly supplied from the instruction buffer 6a to the instruction decoder 7a. Further, every time the repetition end instruction which is the sixth instruction is decoded, the value stored in the register 215 is incremented by the incrementer 226.
Is incremented by one. When the value of the register 215 matches the value of the register 218, that is, when the instruction reading from the instruction buffer 6a to the instruction decoder 7a is repeatedly executed by the number of times set in the register 218, the selector 112 sets the fourth A default control signal is provided from control block 128 to select an input value. As a result, the repetition processing ends, and the processing shifts to the processing of the subsequent instruction. With the above operation, the first arithmetic processing unit 3a including the instruction buffer 6a realizes the repetitive processing.

FIG. 8 shows an example of an execution instruction sequence including double repetition processing in the first arithmetic processing unit 3a. The outer repetition processing defined by the second instruction and the eleventh instruction is performed in the same manner as in the case of FIG.
15 and 218. When the sixth instruction that is the inner repetition start instruction is decoded by the instruction decoder 7a, the selector 204 outputs the first input value to the selector 2
As a result, a control signal is supplied so that the instruction signal 05 selects the second input value. As a result, the number of repetitions of the sixth instruction decoded by the instruction decoder 7a is stored in the register 219. Further, as a result of the control signal being supplied so that the selector 109 selects the second input value, the value of the storage address of the seventh instruction (the instruction next to the inner repetition start instruction) in the instruction buffer 6a is changed to the register 122. The ninth instruction which is the inner repetition end instruction is an instruction decoder 7a
, A control signal is provided so that the selector 201 selects the constant value “1” as the third input value, and the constant value “1” is stored in the register 216. Further, the selector 203 outputs the second input value, the register 21
A control signal is provided to select the output value of 6. On the other hand, a control signal is supplied so that selector 207 selects the second input value, and comparator 227 compares the value of register 216 with the value of register 219. If the value of the register 216 is smaller than the value of the register 219, the control block 1 causes the selector 112 to select the second input value.
As a result of the supply of the control signal from the
The read address RADRS of the seventh instruction is supplied to the instruction buffer 6a via a. As described above, the execution of the inner repetition processing is controlled. In the example of FIGS. 1 to 3, triple repetitive processing can be realized by the first arithmetic processing unit 3a including the instruction buffer 6a. It should be noted that it is easy to expand to a quadruple or more repetition process.

FIG. 9 shows an example of an execution instruction sequence including a conditional branch instruction in the first arithmetic processing unit 3a.
The third instruction (CEXEC) in FIG. 9 is a conditional branch instruction. When the zero flag (one of the operation result flags) specified by the condition code ZE is set, the operation proceeds to the sixth instruction (EX1-OP5). Instruction execution control is performed so as to jump. LABEL in the third instruction indicates a relative jump to the sixth instruction. When the third instruction, which is a conditional branch instruction, is decoded by the instruction decoder 7a,
The condition code decoded by the instruction decoder 7a is supplied to the control block 131 of the address generator 5a via the control bus 11a. Further, the relative jump address is stored in the register 126 via the control bus 11a, and the address is supplied to the third input section of the selector 113. The control block 131 refers to the condition code supplied from the instruction decoder 7a and the operation result flag stored in the flag register 20a to determine whether the conditions match or not. When the condition does not match, the selector 113 sets the relative jump address which is the input value of the second input value to the constant value "1"
Is given to each of them. Therefore, the output value of the adder 129, that is, the instruction buffer 6a
The next read address is changed according to the matching / mismatch of the condition. With the above operation, the processing of the conditional branch instruction is realized in the first arithmetic processing unit 3a including the instruction buffer 6a.

FIG. 10A shows a format example of a macro definition command, and FIG. 10B shows a format example of a macro call command. FIG. 10 (a) and FIG.
At 0 (b), the EUB 21 has a fixed value “10” so as to designate the second arithmetic processing unit 3b. The code part 22 of the macro definition instruction includes an operation code (OP) 31
And the number of instructions (DNUM) 32. DNUM32 is
It indicates the number of instructions constituting the macro body according to the macro definition instruction. Code part 22 of macro call instruction
Is an operation code (OP) 41 and a start address (TOPA)
DR) 42 and the number of instructions (ENUM) 43. TOP
The ADR 42 indicates at which position in the instruction buffer 6b the leading instruction of the plurality of instructions constituting the macro body relating to the macro call instruction is stored. ENUM 43 indicates the number of instructions constituting the macro body related to the macro call instruction.

FIG. 11 shows a detailed configuration of the address generator 5b in FIG. In FIG. 11, 300 to 30
3 is a selector, 310 to 312 are registers, and 320 is an incrementer. Register (MWADR) 310
Is a register for storing a write address of a macro configuration instruction in the instruction buffer 6b. The input unit is connected to the output unit of the three-input selector 300, and the output unit is connected to the first input unit of the two-input selector 303. And a first input unit of the three-input selector 300. The register (WADR) 311 is a register (WAD) for storing an instruction other than the macro configuration instruction in the instruction buffer 6b, that is, a write address of a non-macro configuration instruction.
R), wherein the input section is connected to the output section of the 4-input selector 301 and the output section is
And the first input unit of the four-input selector 301. The register (BDRYREG) 312 is
A boundary address (BDRY) in the instruction buffer 6b,
In other words, macro definition area (storage area for macro configuration instructions)
For storing an address next to the last address of the three-input selector 302, wherein the input part is connected to the output part of the three-input selector 302 and the output part is connected to the first input part of the three-input selector 302. . The control input section of the two-input selector 303 is connected to the instruction issuing unit 2 via the control bus 9b. The output of the two-input selector 303 is connected to the input of the incrementer 320, and is also connected to the address bus 10b so as to supply the write address WADRS to the instruction buffer 6b. The second input of each of the selectors 300 to 302 is connected to the output of the incrementer 320. The third input of the four-input selector 301 is connected to the output of the register 312. A constant value “0” is input to each of the third input unit of the three-input selector 300, the fourth input unit of the four-input selector 301, and the third input unit of the three-input selector 302.

304 to 306 are selectors, 313 and 31
4 is a register and 321 is an incrementer. A register (MRADR) 313 is a register for storing a read address of a macro configuration instruction in the instruction buffer 6b. The input unit is connected to the output unit of the three-input selector 304, and the output unit is connected to the two-input selector 306. The first input unit and the first input unit of the three-input selector 304 are connected. A register (RADR) 314 is a register for storing a read address of a non-macro configuration instruction in the instruction buffer 6b. The input unit is connected to the output unit of the three-input selector 305, and the output unit is set to two.
The second input unit of the input selector 306 and the three-input selector 3
05 is connected to the first input unit. The output of the two-input selector 306 is connected to the input of the incrementer 321 and is also connected to the address bus 10b so as to supply the read address RADRS to the instruction buffer 6b. The second input of each of the three-input selectors 304 and 305 is connected to the output of the incrementer 321. The third input of the three-input selector 304 receives a start address (TOPAD) from the instruction decoder 7b.
R) is connected to the control bus 11b. A third input of the three-input selector 305 is connected to an output of the register 312.

307 is a two-input selector, 315 is a register, 316 is a counter, 322 is a comparator, and 323 is a control block (CNT). Register (NUMREG)
Reference numeral 315 denotes a register for storing the number of instructions (ENUM) constituting the macro body relating to the macro call instruction. The input unit is connected to the output unit of the two-input selector 307, and the output unit is connected to the comparator 322. And a first input unit of the two-input selector 307.
A second input of the two-input selector 307 is connected to the control bus 11b so as to receive the number of instructions (ENUM) from the instruction decoder 7b. A second input of the comparator 322 is connected to an output of the counter 316. The control input of the counter 316 is connected to the instruction decoder 7b via the control bus 11b. Control block 323
The first input is connected to the output of the comparator 322, the second input is connected to the instruction decoder 7b via the control bus 11b, and the output is connected to the control input of the two-input selector 306. .

The control input units of the selectors 300, 301 and 302 are connected to the instruction issuing unit 2 via the control bus 9b, and the control input units of the selectors 304, 305 and 307 are connected to the instruction input unit via the control bus 11b. Although connected to the decoder 7b, these control inputs are not shown in FIG.

FIG. 12 shows an example of an execution instruction sequence including a macro definition instruction and a macro call instruction in the microprocessor of FIG. Here, 21 shown in FIG.
It is assumed that the binary code of each of the instructions is stored in the instruction memory 1. The third instruction (dmac in FIG. 12)
ro) is the macro definition instruction, the fourth, fifth and sixth instructions (d
m-OP1 to dm-OP3) are macro configuration instructions,
Tenth, eleventh, and twelfth instructions (from MACRO1 to MA
CRO3) is a macro call instruction associated with the third instruction.

FIG. 13 shows the detailed configuration of the instruction buffer 6b in accordance with the example of the instruction sequence shown in FIG. When the macro definition instruction (dmacro) is fetched from the instruction memory 1 as described in detail below, the instruction buffer 6b stores three macro configuration instructions (dm-OP1 to d-macro).
m-OP3), a macro definition area 51 storing
And an open area 52 for a non-macro configuration instruction. The boundary address BDRY is stored in the macro definition area 51.
Next to the last address of the
Is the start address of Here, the instruction buffer 6
It is assumed that b consists of 256 words.

FIGS. 14 and 15 show the pipeline configuration of the microprocessor shown in FIG. 1 based on the example of the instruction sequence shown in FIG. In FIGS. 14 and 15,
"WIF" indicates an instruction writing process to the instruction buffer 6b, "IF" indicates an instruction fetch process from the instruction memory 1 or the instruction buffer 6b, and "DEC" indicates an instruction decoding process in the instruction issuing unit 2 or the instruction decoder 7b. , "E
XE ”is the instruction execution unit 8c or the instruction execution unit 8
b shows the calculation execution process. In both figures,
The right direction is the positive direction of time, the downward direction is the flow of execution instructions, and each cycle is denoted by symbols S0 to S2.
5 is identified.

First, in cycle S0, the first instruction (OP
1) is fetched from the instruction memory 1. Cycle S1
Then, the first instruction is decoded by the instruction issuing unit 2, and an operation according to the result of the decoding is executed by the operation execution unit 8c in the cycle S2. Second instruction (OP
The same applies to 2).

In cycle S2, a macro definition instruction (dmacro), which is the third instruction, is fetched from the instruction memory 1, and the instruction definition unit 2 decodes the macro definition instruction. At this time, the instruction issuing unit 2 extracts the number DNUM of instructions constituting the macro body (“3” in the example of FIG. 12; see FIG. 10A) from the macro definition instruction, and further extracts the number DNNUM of instructions. The same number of instructions are sequentially fetched from the instruction memory 1. Thereby, the macro configuration instruction (dm-O), which is the fourth, fifth, and sixth instructions,
P1 to dm-OP3) respectively correspond to cycle S3,
Fetched in S4 and S5. These macro configuration instructions are sequentially written to the instruction buffer 6b via the instruction bus 9a.

Here, the process of writing a macro configuration instruction into the instruction buffer 6b will be described in detail. When the instruction issuing unit 2 fetches the macro definition instruction (dmacro) from the instruction memory 1 in the cycle S2, the instruction issuing unit 2 selects the third input value in the cycle S2 so that the three-input selector 300 selects the third input value.
Supplies a default control signal via the control bus 9b. As a result, the initial address value “0” is set in the register 310. Similarly, registers 311 and 312
, The same initial address value “0” is set. In the next cycle S3, the instruction issuing unit 2 fetches the first macro configuration instruction (dm-OP1) from the instruction memory 1, supplies the instruction to the instruction bus 9a, and the two-input selector 303 Control bus 9b to select the input value
Supply the control signal to This control allows the register 31
The value “0” of 0 is the write address W of the instruction buffer 6b.
Output as ADRS. At this time, the instruction buffer 6b
As a result, the first macro configuration instruction (dm-OP1) is stored at the address “0” of the instruction buffer 6b. In the cycle S3, the incrementer 320 receives the output value of the two-input selector 303 and outputs the write address value “1” in the next cycle.
Generate In the next cycle S4, the incrementer 3
The output value "1" of 20 is stored in the registers 310, 311 and 312.
It is taken in. Therefore, in cycle S4, the second
Of the register 310 as the write address of the macro configuration instruction (dm-OP2)
3 and the instruction buffer 6b via the address bus 10b.
And the second macro configuration instruction (dm-OP2)
Is stored in the address “1” of the instruction buffer 6b. Similarly, in the cycle S5, the third macro configuration instruction (dm-OP3) stores the address “2” of the instruction buffer 6b.
Is stored in When the writing of the three macro configuration instructions to the instruction buffer 6b is completed as described above, the values of the registers 310, 311 and 312 at this point are all "3". Thereafter, unless another macro definition instruction is fetched from the instruction memory 1, the registers 310, 312
Is not updated. That is, the macro definition area 51 is secured in the instruction buffer 6b as shown in FIG. When another macro definition instruction is fetched from the instruction memory 1, the macro definition area 51 in the instruction buffer 6b is expanded.

In cycle S6, a non-macro constituent instruction (EX2-OP1), which is the seventh instruction, is fetched from the instruction memory 1, and the fetched instruction is stored in the instruction buffer 6.
b. At this time, the value “3” of the register 311
Is selected as the write address WADRS of the instruction buffer 6b. Thereafter, each time a non-macro configuration instruction is written to the instruction buffer 6b, the value of the register 311 is updated with the output value of the incrementer 320. However, the register 311 stores the maximum address “25” of the instruction buffer 6b.
When "5" is output, the value "3" of the register 312 is set in the register 311 in the next cycle. This prevents a non-macro configuration instruction from being stored in the macro definition area 51.

In cycle S7, the process of reading the seventh instruction (EX2-OP1) from the instruction buffer 6b and the process of writing the eighth instruction (EX2-OP2) in the instruction buffer 6b are executed in parallel. Here, the instruction buffer 6
The reading of the non-macro configuration instruction from b will be described in detail. The value of the register 314 is set to an initial value “3” with reference to the register 312. The control block 323
An input selector 306 provides a default control signal to select a second input value. With this control, the value “3” of the register 314 is output as the read address RADRS of the instruction buffer 6b. At this time, a read enable signal is also supplied to the instruction buffer 6b.
The seventh instruction is read from the address “3” of the instruction buffer 6b. Then, the value of the register 314 is updated by the output value of the incrementer 321. Thereafter, each time a non-macro configuration instruction is read from the instruction buffer 6b, the value of the register 314 is updated with the output value of the incrementer 321. However, when the register 314 outputs the maximum address “255” of the instruction buffer 6b, the value “3” of the register 312 is set in the register 314 in the next cycle. This prevents a non-macro configuration instruction from being erroneously read from the macro definition area 51.

In cycle S8, the ninth instruction (EX2-O
P2) is fetched from the instruction memory 1, and the fetched instruction is written to the instruction buffer 6b. In the cycle S9, the first macro call instruction (MACRO1), which is the tenth instruction, and in the cycle S10, the second macro call instruction (MACRO2), the eleventh instruction,
In cycle S11, the third macro call instruction (MACRO3), which is the twelfth instruction, is stored in the instruction buffer 6b.
Is written to. Tenth and eleventh instruction buffer 6b
And the write processing of the twelfth instruction is performed in the same instruction buffer 6b.
This is the same as the process of writing the seventh, eighth, and ninth instructions to the. In cycle S12, the thirteenth instruction (EX2-OP4)
However, in cycle S13, the fourteenth instruction (EX2-OP5)
Are written in the instruction buffer 6b.

In cycle S10, the first macro call instruction (MACRO1) is read from the instruction buffer 6b, and the decoding processing of the first macro call instruction is performed by the instruction decoder 7b. At this time, the instruction decoder 7b extracts the head address TOPADR (“0” in the example of FIG. 12) and the number of instructions ENUM (“3” in the example of FIG. 12) from the first macro call instruction (FIG. 12). 1
0 (b)). The start address TOPADR is stored in the register 313, and the number of instructions ENUM is stored in the register 315 via the control bus 11b. Further, the value of the counter 316 is initialized to “0”, and updating of the value of the register 314 is prohibited. The control block 323 controls the two-input selector 306 to select the first input value. The above processing is the preparation processing for macro expansion. Since then
The value of the counter 316 is incremented by one each time the cycle proceeds.

The comparator 322 compares the value of the register 315 with the value of the counter 316. The control block 323 receiving the output of the comparator 322 supplies a control signal so that the two-input selector 306 selects the first input value when the value of the counter 316 is smaller than the value of the register 315. With this control, the instruction read address next to the tenth instruction is the value “0” of the register 313, that is, the first macro configuration instruction (dm−
OP1) is the storage address. As a result, the cycle S
11, the first macro configuration instruction (MACRO1 in FIG. 14)
A read process of an instruction (-OP1) is executed. Then, the value of the register 313 is incremented by 32.
The value is updated according to the output of 1 and the value of the counter 316 is incremented.

In cycle S12, the reading process of the second macro configuration instruction (instruction denoted as MACRO1-OP2 in FIG. 14) is performed, and in cycle S13, the third macro configuration instruction (indicated as MACRO1-OP3 in FIG. 14). Instruction) is executed. Then, when the value of the register 315 matches the value of the counter 316, that is, when the macro configuration instruction is read from the instruction buffer 6b the number of times set in the register 315, the two-input selector 306 again sets the second input selector 306 A control signal is supplied from the control block 323 to select an input value. As a result, the first macro call instruction (MA
The macro expansion based on CRO1) is completed, and the processing proceeds to the subsequent instruction. With the above operation, the macro expansion processing is realized by the second arithmetic processing unit 3b including the instruction buffer 6b.

According to FIG. 15, the cycles S14 to S1
The macro expansion based on the second macro call instruction (MACRO2) is executed up to 7, and the macro expansion based on the third macro call instruction (MACRO3) is executed from cycles S18 to S21. Then, the execution of the operation relating to the fourteenth instruction (EX2-OP5) by the operation execution unit 8b is completed in cycle S25. On the other hand, since the writing of the instruction to the instruction buffer 6b is completed in the cycle S13, after the cycle S14, the instruction issuing unit 2 uses the instruction bus 9a and the control bus 9b for purposes other than the writing of the instruction to the instruction buffer 6b. Can be. Therefore, the fifteenth to be executed by the operation execution unit 8c
The instruction fetch process (IF), the instruction decode process (DEC), and the operation execution process (EXE) related to the 21st to 21st instructions (OP3 to OP9) can be completed by cycle S22.

As described above, according to the microprocessor of FIG. 1, the first and second arithmetic processing units 3a and 3b
Facilitates programming for a group of instructions to be executed in each of the. Moreover, the first arithmetic processing unit 3
Since a can autonomously perform the repetition processing and the condition execution processing, the instruction issue rate of the instruction issue unit 2 is reduced, and as a result, the load on the instruction bus 9a is reduced. Also, by allocating the macro definition area 51 in the instruction buffer 6b, the second arithmetic processing unit 3b can autonomously perform macro expansion. Instruction bus 9a compared to
The load on the device is reduced. The more frequently the macro call instruction is used, the greater the effect of reducing the load.

The number of arithmetic processing units is arbitrary, and the number of EUB bits may be selected according to the number. An arithmetic processing unit having the same internal configuration as the first arithmetic processing unit 3a may be added to the configuration of FIG. In this case, since the arithmetic processing unit can be switched for each repetition processing, programming is further facilitated. An arithmetic processing unit having the same internal configuration as the second arithmetic processing unit 3b may be added to the configuration of FIG.
In this case, since the arithmetic processing unit can be switched for each function related to the macro definition, programming is further facilitated.

First and second arithmetic processing units 3a, 3
An arithmetic processing unit having an internal configuration having each of the characteristics b may be employed. Thus, a macro definition including a repetition process, a conditional branch process, and the like can be performed.
In the field of DSP (digital signal processing), DCT (discrete cosine transfor
m: discrete cosine transform), IDCT (inverse discrete)
Various functions such as cosine transform (inverse discrete cosine transform) are required. DC to implement each of these functions
If macro instructions such as the T instruction and the IDCT instruction are prepared, a high-performance microprocessor that can be easily programmed can be realized.

[0056]

As described above, according to the present invention, a microprocessor structure in which a plurality of arithmetic processing units are connected to one instruction issuing unit is employed, and At least one of the arithmetic processing units has an instruction buffer for storing a plurality of instructions supplied from the instruction issuing unit so that a series of arithmetic processing can be executed autonomously, and the instruction buffer An instruction decoder for decoding the instruction read from the CPU, an operation execution unit for executing an operation according to the result of the decoding by the instruction decoder,
An address generation unit for generating a write address of the instruction buffer according to a control signal received from the instruction issuing unit, and generating a read address of the instruction buffer according to a control signal received from the instruction decoder. Since a configuration having such a configuration is employed, a high-performance microprocessor that can be easily programmed can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a microprocessor according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of an address generation unit of a first arithmetic processing unit in FIG. 1;

FIG. 3 is a block diagram illustrating a detailed configuration of a loop control unit in FIG. 2;

FIG. 4 is a diagram illustrating an example of an instruction format in the microprocessor of FIG. 1;

FIG. 5 is a diagram illustrating an example of an execution instruction sequence in the microprocessor of FIG. 1;

FIG. 6 is a diagram showing another example (including repetition processing) of an execution instruction sequence in the microprocessor of FIG. 1;

7 is a diagram showing a pipeline configuration of the microprocessor of FIG. 1 corresponding to the execution instruction sequence of FIG. 6;

8 is a diagram showing still another example (including double repetition processing) of an execution instruction sequence in the microprocessor of FIG. 1;

9 is a diagram showing still another example (including a conditional branch instruction) of an execution instruction sequence in the microprocessor of FIG. 1;

10A is a diagram illustrating an example of a format of a macro definition instruction in the microprocessor of FIG. 1, and FIG. 10B is a diagram illustrating an example of a format of a macro call instruction in the microprocessor.

FIG. 11 is a block diagram illustrating a detailed configuration of an address generation unit of the second arithmetic processing unit in FIG. 1;

12 is a diagram showing still another example (including a macro definition instruction and a macro call instruction) of an execution instruction sequence in the microprocessor of FIG. 1;

FIG. 13 is a diagram showing a detailed configuration of an instruction buffer of the second arithmetic processing unit in FIG. 1;

14 is a diagram illustrating a pipeline configuration of the microprocessor in FIG. 1 corresponding to the execution instruction sequence in FIG. 12;

FIG. 15 is a view following FIG. 14;

[Explanation of symbols]

 1 instruction memory 2 instruction issuing unit 3a, 3b arithmetic processing unit 4a, 4b, 4c data memory 5a, 5b address generator 6a, 6b instruction buffer 7a, 7b instruction decoder 8a, 8b, 8c arithmetic execution unit 20a flag register 21 execution unit Designated bit (EUB) 22 Code part 31 Operation code (OP) 32 Number of instructions (DNUM) 41 Operation code (OP) 42 Start address (TOPADR) 43 Number of instructions (ENUM) 51 Macro definition area 52 Open area 108 to 114 Selector 121 to 126 Register 127 Loop control unit 128 Control block 129 Adder 130 Incrementer 131, 133 Control block 132 Selector 134 Flag register 200-207 Selector 215-220 Register 226 Kurimenta 227 comparators 300-307 selector 310-315 register 316 counters 320 and 321 incrementer 322 comparator 323 control block BDRY boundary address LED loop end signal RADRS read address WADRS write address

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38

Claims (14)

(57) [Claims] 1. A microprocessor capable of executing a plurality of instructions in parallel, comprising: a plurality of processing units; and an instruction for storing a plurality of instructions to be executed by each of the plurality of processing units. A memory; and an instruction issuing unit for fetching an instruction from the instruction memory and supplying the fetched instruction to a corresponding arithmetic processing unit of the plurality of arithmetic processing units. At least one specific processing unit includes: an instruction buffer for storing a plurality of instructions supplied from the instruction issuing unit; and an instruction decoder for decoding an instruction read from the instruction buffer. An operation execution unit for executing an operation according to a result of decoding by the instruction decoder; An address generation unit for generating a write address of the instruction buffer according to a control signal received from the instruction issuing unit, and generating a read address of the instruction buffer according to a control signal received from the instruction decoder. A microprocessor characterized in that: 2. The microprocessor according to claim 1, wherein the instruction issuing unit processes the fetched instruction according to an execution unit designation bit included in the instruction fetched from the instruction memory. A microprocessor having a function of determining which arithmetic processing unit among the units is to be supplied. 3. The microprocessor according to claim 1, wherein the address generation unit has a flag register for storing a status flag indicating whether the instruction buffer has been filled with an instruction that has not been read yet. The microprocessor according to claim 1, wherein the instruction issuing unit has a function of controlling supply of an instruction to the specific arithmetic processing unit in accordance with the status flag. 4. The microprocessor according to claim 1, wherein the address generation unit is configured to execute the repetition processing specified by a repetition control instruction read from the instruction buffer so that the specific arithmetic processing unit can execute the repetition processing. A microprocessor having control means for controlling a read sequence of an instruction buffer. 5. The microprocessor according to claim 4, wherein said control means includes: a first register for storing a read address of said instruction buffer; and said first register each time one instruction is read from said instruction buffer. Means for updating the value of the register, a second register for storing the number of repetitions specified by the repetition start instruction read from the instruction buffer, and the repetition start instruction in the instruction buffer A third register for storing the address of the next instruction, and a fourth register for storing the number of times the repetitive processing has been executed.
Means for incrementing the value of the fourth register when a repetition end instruction is read from the instruction buffer; and means for incrementing the value of the second register and the value of the fourth register. A comparator for detecting a match, and a value of the third register for continuing the repetition processing if the comparator does not detect a match even when the repeat end instruction is read from the instruction buffer. Is supplied to the instruction buffer, and when the repetition end instruction is read from the instruction buffer and a match is detected by the comparator, the value is indicated by the value of the first register so as to end the repetition processing. Means for supplying an address of an instruction next to the repeated end instruction to the instruction buffer. 6. The microprocessor according to claim 1, wherein the specific arithmetic processing unit executes the multiplex repetition processing specified by the plurality of repetition control instructions read from the instruction buffer. A microprocessor having control means for controlling a read sequence of the instruction buffer so as to be able to do so. 7. The microprocessor according to claim 1, wherein the specific operation processing unit stores an operation result flag corresponding to a result of the operation executed by the operation execution unit, and stores the operation result flag in the address. A flag register for transmitting to the generation unit, wherein the address generation unit is configured to execute the operation specified by the conditional execution instruction read from the instruction buffer so that the specific operation processing unit can execute the operation. A microprocessor having control means for controlling a read sequence of the instruction buffer with reference to a result flag. 8. The microprocessor according to claim 7, wherein the control unit updates a register for storing a read address of the instruction buffer, and updates a value of the register each time one instruction is read from the instruction buffer. Means for performing the relative jump specified by the conditional branch instruction when the operation result flag satisfies a condition code specified by the conditional branch instruction when the conditional branch instruction is read from the instruction buffer. A value obtained by adding an address to the value of the register is supplied to the instruction buffer, and when the operation result flag does not satisfy the condition code, an address of an instruction next to the conditional branch instruction indicated by the value of the register And a means for supplying the instruction buffer to the instruction buffer. 9. The microprocessor according to claim 1, wherein, when the instruction fetched from the instruction memory is a macro definition instruction, the instruction issuing unit further includes a plurality of macro configuration instructions following the macro definition instruction. Fetch and
And a function of supplying the fetched macro configuration instructions to the specific arithmetic processing unit such that the fetched macro configuration instructions are stored in a macro definition area in the instruction buffer. And a microprocessor. 10. The microprocessor according to claim 9, wherein the address generation unit controls a write sequence of the instruction buffer so that the specific arithmetic processing unit can execute a process corresponding to the macro definition instruction, And a control unit for controlling a read sequence of the instruction buffer so that the specific arithmetic processing unit can execute a process specified by a macro call instruction read from the instruction buffer. Processor. 11. The microprocessor according to claim 10, wherein the control means includes: a first register; a second register for storing a write address of the instruction buffer; and the first and second registers. Means for initializing the values of the first and second registers to the same value, and means for updating the values of the first and second registers each time one macro configuration instruction is written to the instruction buffer. The first register releases the value of the first register when writing of the last macro configuration instruction to the instruction buffer is completed, for the macro definition area and the non-macro configuration instruction in the instruction buffer. A microprocessor which stores the address as an address indicating a boundary with an area. 12. The microprocessor according to claim 11, wherein the address generation unit is configured to store the address of the first register so that the non-macro configuration instruction is not stored in the macro definition area. A means for updating the value of the second register with reference to FIG. 13. The microprocessor according to claim 11, wherein the control unit includes: a third register for storing the number of instructions specified by the macro call instruction; and a read address of a macro configuration instruction in the instruction buffer. And a means for updating the value of the fourth register each time one macro configuration instruction is read from the instruction buffer; and a macro configuration instruction read from the instruction buffer. A counter for counting the number of the counters; a comparator for detecting a match between the value of the third register and the count value of the counter; and a macro call instruction if no match is detected by the comparator. Supplies the value of the fourth register to the instruction buffer so as to continue macro expansion based on Microprocessor, characterized by further comprising a means for controlling to terminate the macro expansion when it. 14. The microprocessor according to claim 13, wherein the address generation unit includes: a fifth register for storing a read address of a non-macro configuration instruction in the instruction buffer; and a non-macro configuration from the instruction buffer. Means for updating the value of the fifth register with reference to the holding address of the first register each time an instruction is read.