JP4664024B2 - Chip resistor manufacturing method, collective substrate, and chip resistor - Google Patents

Description

  The present invention relates to a method of manufacturing a chip resistor, a collective substrate, and a chip resistor, and more specifically, a method of manufacturing a chip resistor having a relatively small size, a low resistance value, and a resistance film formed by plating, and its The present invention relates to a collective substrate obtained in the manufacturing process and a chip resistor manufactured from the collective substrate.

  As a conventional method for manufacturing a chip resistor, for example, a method described in JP-A-10-70001 (Patent Document 1) can be cited. In the manufacturing method described in Patent Document 1, a sheet-like collective insulating substrate having a plurality of sections to be divided vertically and horizontally is used, and (1) a pair of front electrodes is provided for each section in the collective substrate. Formed on the surface of the substrate, (2) a base layer made of Ag-Pd resistance film or the like is formed between the surface electrodes, (3) a resistance film is formed on the base layer by plating, and (4) the insulating substrate A pair of backside electrodes are formed on the backside, (5) a protective layer covering the plating resistance film is formed, (6) the aggregate substrate is divided into strips, and (7) end face electrodes are formed on the divided surfaces, 8) A strip-shaped insulating substrate is divided into individual chip resistor sizes, and (9) a plating layer is formed on the exposed portion of the electrode and plating resistance film.

  Here, FIG. 5 is a cross-sectional view of the chip resistor formed as described above. The chip resistor 50 includes a pair of front electrode 52 and back electrode 53 formed on the front and back sides of the insulating substrate 51, respectively. A surface base layer 54 (base resistance film), a surface plating resistance film 55 by plating on the surface base layer 54, a surface protective layer 56, an end face electrode 57, and an electrode plating layer 58 covering the exposed surface of the electrode. It is what has. FIG. 6 is a cross-sectional view showing a state after the step (4) in the manufacturing method. As shown in FIG. 6, in the conventional chip resistor manufacturing method, since the surface underlayer 54 and the surface plating resistance film 55 are formed only on the surface, the substrate warp A due to the plating stress may occur depending on the case. It sometimes occurred.

In addition, as a result of investigating known techniques in the present applicant, in addition to the above-mentioned Patent Document 1, the following patent documents were also found. Patent Documents 1 to 6 describe a chip resistor in which a resistive film is formed by plating, and Patent Documents 7 and 8 describe a chip resistor in which a resistive film is formed on the front and back surfaces of a substrate. ing.
Japanese Patent Laid-Open No. 10-70001 JP 60-115201 A Japanese Patent Laid-Open No. 06-120013 Japanese Patent Laid-Open No. 08-138902 JP 09-320806 A JP 2001-155901 A JP-A-55-120101 Japanese Patent Laid-Open No. 11-191502

  The size of the conventional chip resistor is, for example, 5.0 mm × 2.5 mm, 3.2 mm × 1.6 mm, 3.2 mm × 2.5 mm, and the chip resistor of such a size is often used. In addition, a substrate having a thickness of about 0.5 mm is used. Such an aggregate substrate having a thickness of about 0.5 mm does not cause substrate warpage due to plating stress even if a surface plating resistance film is formed.

  However, with the progress of miniaturization and high-density packaging of electronic devices, further miniaturization of chip resistors is required. For example, chip resistors of about 1.0 mm × 0.5 mm The thickness of the substrate is 0.25 mm to 0.3 mm. When the plating resistance film is formed on such a thin substrate in the state of the collective substrate, the substrate warp due to the plating stress occurs.

  Further, when the insulating substrate is provided with the dividing grooves, the warpage of the substrate is increased, and there is a possibility that the insulating substrate is cracked by processing in another process.

  Furthermore, when the plating resistance film is formed by an electroless plating method, it is difficult to adjust the plating stress in the electroless plating solution, and thus the substrate is likely to warp. On the other hand, when the plating resistance film is formed by electroplating, since the plating stress in the plating solution is adjusted, a certain amount of substrate warpage can be eliminated, but the plating stress in all plating solutions is reduced. Since the adjustment has not been made, if the plating stress is not matched with the insulating substrate to be used, or if the chip resistor substrate is thin, the insulating substrate is warped.

  Further, when the plating resistance film is formed thick for the purpose of further reducing the resistance, or when a plurality of plating resistance films are laminated, it causes a warpage of the insulating substrate.

  The present invention solves the above-mentioned conventional problems, and the problem is that in a chip resistor in which the chip size is relatively small, the resistance value is relatively low, and a resistance film is formed by plating, the substrate warps. Another object of the present invention is to provide a chip resistor manufacturing method, a collective substrate, and a chip resistor that can prevent cracking.

  The above-described problems of the present invention are solved by the following means.

(1) Chip resistors are formed by forming electrodes and a resistive film on a thin aggregated insulating substrate having a plurality of vertical and horizontal sections each serving as a chip resistor and having a thickness of 0.25 mm to 0.3 mm, and then dividing each section into individual sections. In the method of manufacturing a chip resistor to obtain a device, a step of forming a base layer serving as a conductor for passing a current between electrodes formed on the front and back surfaces of the collective insulating substrate; and the resistance film on the front and back surfaces of the base layer a step of sides simultaneously formed by plating, the step of dividing the pre-SL current if the insulating substrate into strips, forming an end surface electrode to conduct resistance film on the front and back surfaces of the strip-shaped substrate in parallel, the strip And a step of dividing the substrate into individual chips.

(2) A method of manufacturing a chip resistor according to claim 1, characterized in that to form a more the resistance film in an electroless plating method.

(3) A sheet-like collective insulating substrate of 0.25 mm to 0.3 mm having a plurality of sections to be individual chip resistors vertically and horizontally, on a base layer serving as a conductor for passing a current between electrodes on both the front and back sides of the substrate In addition , a collective substrate in which resistance films are simultaneously formed on both the front and back surfaces of the substrate by plating.

(4) the resistive film is assembled board according to 請 Motomeko 3 formed by resistive films by come electroless plating.

(5) Using the collective substrate according to (3) or (4) above, an end face electrode that conducts the resistance film on the front and back surfaces is formed on a divided surface formed by dividing the collective substrate into strips. And a chip resistor formed by dividing the strip-shaped substrate individually.

  In the method of manufacturing a chip resistor described in (1) above, the plating stress is offset on the front and back sides of the collective substrate by simultaneously forming a resistance film by plating on both the front and back sides of the collective substrate, thereby reducing the size of the chip resistor. Even if the substrate becomes thin, the warpage of the collective substrate can be prevented and the yield can be improved. Also, the process of connecting the resistance films by plating on the front and back surfaces in parallel with the end face electrodes makes it possible to manufacture a chip resistor having a lower resistance than the conventional technique, and when obtaining the same resistance value, In comparison, the resistance film by plating can be made thinner, so that the plating time can be shortened.

When the resistance film is formed by the electroless plating method, it is difficult to adjust the plating stress by the conventional method and the collective substrate has to be subjected to the plating stress. However, in the manufacturing method of the chip resistor described in (2) above, The plating stress can be offset between the front and back of the collective substrate to prevent the collective substrate from warping. On the other hand, when the resistance film is formed by the electroplating method, even if the adjustment of the plating stress is not complete or the insulating substrate is thin, according to the manufacturing method of (2) above, Therefore, the warpage of the collective substrate can be prevented.
Further, even when a resistive film formed by electroless plating and a resistive film formed by electroplating are stacked to form a thick resistive film, the chip resistor manufacturing method described in (2) above Warpage of the substrate can be prevented. By forming the plating resistance film thick in this way, it is possible to manufacture a chip resistor having a relatively low resistance value. When connected in parallel by the end face electrodes, the chip resistor according to the conventional method is used. Compared with, the plating resistance film on each of the front and back surfaces for obtaining a desired resistance value can be made thin, so that the plating time can be shortened.

In the collective substrate described in (3) above, the same effects as in the manufacturing method in (1) can be obtained.
That is, since the resistance film by plating is formed simultaneously on both the front and back surfaces, it becomes possible to cancel the plating stress, and even if the substrate is made thinner due to the downsizing of the chip resistor, the warpage of the substrate can be prevented. Thus, the yield at the time of manufacturing the chip resistor can be improved.

  In the aggregate substrate described in (4) above, the same effect as in (2) above can be obtained. In the chip resistor described in (5) above, the same effect as in (1) or (2) can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.

  1A to 1H are cross-sectional views showing respective steps in the method for manufacturing a chip resistor of the present invention. FIG. 1A shows a collective insulating substrate 11A made of alumina ceramic or the like, and has a groove 12 for dividing the substrate. Due to the miniaturization of the chip resistor, the collective insulating substrate becomes thinner and easily warps due to plating stress. That is, when a chip resistor is manufactured by a conventional method, plating is performed from a collective insulating substrate having a chip resistor size of 1005 (1.0 mm × 0.5 mm, substrate thickness 0.25 mm to 0.3 mm). The occurrence of defects tends to increase due to warping due to stress, and the collective insulating substrate 11A having the substrate dividing grooves 12 as shown in FIG. 1A is more susceptible to plating stress. . The present invention has been made to eliminate these problems.

First, as shown in FIG. 1B, electrodes 13 are formed on both the front and back surfaces of the collective insulating substrate 11A. In this step, the presence / absence and material of the electrodes 13 on both the front and back surfaces are not particularly limited to the above forms. For example, when the base layer is formed of a Pd—Ag thick film, the resistance value of the electrode portion is reduced. Therefore, it is effective to form with an Ag-based thick film.
In the case the base layer in the later step, a material other than Pd-Ag-based thick film, both sides of the electrode 13, a thin film of Ag thick film and other materials can be used, Oh Rui Patent As described in Japanese Patent Application Laid-Open No. 2001-155901, it is also possible to form it so as to overlap the upper surface of the plating resistor.

  Next, as shown in FIG. 1C, a base layer 14 is formed between the electrodes 13 formed on the front and back surfaces of the collective insulating substrate 11A. In this step, the material of the underlayer 14 is not particularly limited. For example, there are various thick films including a Pd—Ag thick film, various thin films including a NiCr sputtered film, a Pd activation layer, and the like. . The action of the underlayer is necessary to improve the adhesion when the resistance film is formed by electroless plating. When the resistance film is formed by electroplating, the underlayer serves as a conductor through which a current flows.

  Next, a resist film (not shown) is formed on the front and back surfaces of the collective insulating substrate 11A at locations where the plating resistance film is not formed.

Next, as shown in FIG. 1 (d), the plating resistance film 15 is formed simultaneously on the front and back surfaces of the base layer 14 on both the front and back surfaces of the collective insulating substrate 11A. FIG. 2 is a cross-sectional view showing the state of the collective insulating substrate 11A after the completion of this step. In this step, the material of the plating resistance film 15 is not particularly limited. For example, if Ni-WP electroless plating is used, the chip resistance is low and the TCR (resistance temperature coefficient) is small. Can be obtained. As described above, the plating stress acting on the front and back surfaces is offset by forming the plating resistance film 15 simultaneously on the front and back surfaces. Further, this process makes it possible to prevent the trouble that has occurred in the conventional manufacturing method, that is, the warpage of the collective insulating substrate 11A.
In addition to the Ni-WP electroless plating described above, the plating resistance film 15 formed on both the front and back surfaces is electroless plating, electroplating, or electroless with various metals and alloys including Ni and Cu. A combination of plating and electroplating can be used. For example, Cu, Cu-Ni, Ni-P, Ni-Cu-P, Ni-Cr-P, Ni-Re-P, Ni-B, etc. can be used.

  Next, the resist films (not shown) on both the front and back surfaces of the collective insulating substrate 11A are peeled and removed.

  Next, as shown in FIG. 1E, a protective layer 16 is formed on the plating resistance films 15 on both the front and back surfaces. As is conventionally known, the protective layer 16 is for protecting the plating resistance film 15 and can be formed of glass or resin.

  Next, as shown in FIG. 1F, the collective insulating substrate is divided into strips.

  Next, as shown in FIG. 1 (g), the end face electrode 18 is formed on the end face of the insulating substrate 11B divided into strips to conduct the plating resistance films on both the front and back sides. As is known in the art, such an end face electrode 18 is for ensuring connection with the outside. In addition to its purpose, the end face electrode 18 has a function of connecting resistors on both the front and back sides in parallel. is there.

  Next, the strip-shaped insulating substrate 11 </ b> B is divided into individual chip resistors 20.

Next, as shown in FIG. 1H, the chip resistor 20 is completed by forming the electrode plating layer 19 that covers the exposed portions of the end face electrode 18 and the plating resistance film 15. As conventionally known, for example, a plating layer made of Ni plating and Sn plating, or a plating layer made of Cu plating, Ni plating, and Sn plating can be used as the electrode plating layer 19. A plating layer composed of Cu plating, Ni plating, and Sn plating has a small resistance value of the resistor, and Cu plating is added to minimize the influence of the resistance value of the electrode 18.
In order to facilitate understanding of the chip resistor 20 formed as described above, a cross-sectional view of the chip resistor 20 is shown in FIG. In FIGS. 1A to 1H and FIG. 2, since each configuration is relatively fine, the hatched cross section is omitted to facilitate the understanding of the drawings, and each configuration is illustrated in FIGS. 3 and 4. Since it is relatively large, the cross section is hatched.

Next, FIG. 4 is a cross-sectional view of a chip resistor 30 which is a different embodiment, and the chip resistor 30 is not provided with the front and back electrodes 13 as shown in FIG.
That is, the chip resistor 30 has a base layer 32 formed on both front and back surfaces of the insulating substrate 31, a plating resistance film 33 is provided on each base layer 32, end face electrodes 34 are formed on both end surfaces, and a plating resistance A protective layer 35 is provided on the film 33, and an electrode plating layer 36 is provided to cover the end face electrodes 34 on both sides and the exposed plating resistance film 33. In this chip resistor 30 as well, in the manufacturing process, the plating resistance film 33 is simultaneously formed on both the front and back surfaces as in the embodiment of FIGS.

[Example]
In order to verify the effect of the present invention, an experiment was conducted using a collective insulating substrate for forming a chip resistor having a size of 1.0 mm × 0.5 mm. The collective insulating substrate has a thickness of 0.28 mm, and has grooves for division on both the front and back surfaces. A thick film was formed as an underlying resistance film using an Ag—Pd metal glaze paste, and Ni—WP was formed as an plating resistance film by electroless plating. The warpage of the collective insulating substrate was measured by measuring the difference between the substrate edge and the substrate center.
In the conventional manufacturing method implemented as a comparative example, warpage of about 3 mm to 4 mm occurred, but in the manufacturing method of the present invention, the warpage of the collective insulating substrate can be suppressed to 0.5 mm or less, and its effect can be confirmed. did it. Moreover, in the conventional manufacturing method, the resistance value of the chip resistor was about 40 mΩ, but in the manufacturing method of the present invention, a chip resistor having a resistance value of about 20 mΩ to 30 mΩ was obtained.
Further, when the plating resistance film was formed by electroplating, the manufacturing method of the present invention similarly reduced the warpage of the collective insulating substrate, and confirmed its effect.

(A)-(h) is sectional drawing which shows each process in the manufacturing method of the chip resistor of this invention. It is sectional drawing which shows the assembly board | substrate of the chip resistor by this invention. It is sectional drawing which shows the chip resistor by this invention. It is sectional drawing which shows the chip resistor of embodiment different from FIG. It is sectional drawing which shows the aggregate substrate of the chip resistor by a prior art. It is sectional drawing which shows the chip resistor by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11A Collective insulating board 11B Strip-shaped insulating board 13 Front and back both-side electrodes 14 Underlayer on both front and back sides 15 Plating resistance film 16 Protective layer 18 End surface electrode 19 Electrode plating layer 20 Chip resistor 30 Chip resistor 31 Insulating substrate 32 Underlayer 33 Plating resistance film 34 End face electrode 35 Protective layer 36 Electrode plating layer

Claims (5)

An electrode and a resistance film are formed on a thin insulating substrate having a thickness of 0.25 mm to 0.3 mm having a plurality of sections to be individual chip resistors vertically and horizontally, and then divided into each section to obtain a chip resistor. In the manufacturing method of the chip resistor,
Forming a base layer serving as a conductor for passing a current between electrodes formed on both front and back surfaces of the collective insulating substrate;
Forming the resistance film on the front and back surfaces of the underlayer simultaneously by plating on the front and back surfaces; and
A step of dividing the pre-SL current if the insulating substrate into strips,
Forming an end face electrode that conducts the resistive films on the front and back surfaces of the strip-shaped substrate in parallel;
And a step of dividing the strip substrate into individual chips. Method for producing a chip resistor according to claim 1, characterized in that to form a more the resistance film in an electroless plating method. A sheet-like collective insulating substrate of 0.25 mm to 0.3 mm having a plurality of sections to be individual chip resistors vertically and horizontally , plated on a base layer serving as a conductor for passing a current between electrodes on both sides of the substrate A collective substrate in which a resistance film is simultaneously formed on both the front and back surfaces of the substrate. Collective substrate according to the resistive film, 請 Motomeko 3 formed of a resistance film by come electroless plating.   Use of the collective substrate according to claim 3 or claim 4, and having an end face electrode for conducting the resistance film on the front and back surfaces on a divided surface formed by dividing the collective substrate into strips, A chip resistor formed by dividing a strip-shaped substrate individually.

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