JP4661220B2 - Electro-optical device and electronic apparatus - Google Patents

Description

The present invention relates to an electro-optical device using an electro-optical material such as liquid crystal, and an electronic apparatus including the electro-optical device.

An electro-optical device such as a liquid crystal device has a configuration in which wiring for transmitting a drive signal such as a scanning signal or a video signal to an electro-optical material is formed on the surface of a substrate. For example, in Patent Document 1, in a liquid crystal device in which a scanning line driving circuit is mounted on the surface of a second substrate that holds liquid crystal in a gap with the first substrate, the scanning line formed on the first substrate and the second A configuration is disclosed in which one end of a wiring formed on a substrate is made conductive by a conductive material, and the other end of the wiring is connected to a scanning line driving circuit. For example, in a configuration in which the data line driving circuit is mounted on the second substrate, the second
A number of data lines are formed on the substrate, and each end is connected to a data line driving circuit.
JP 2001-75118 A (paragraph 0031 and FIG. 1)

However, in this configuration, since the total length of each wiring is different, there is a problem that the resistance value varies for each wiring. If the resistance value of each wiring is different in this way, the waveform distortion (waveform dullness or delay, etc.) and the voltage drop of the drive signal supplied to each pixel differ from wiring to wiring. If the same gradation is displayed on all the pixels, the gradation actually displayed by each pixel differs depending on the position of the pixel and the display quality deteriorates. There is. The present invention has been made in view of such circumstances, and an object thereof is to suppress the resistance value of each wiring and its variation.

To achieve this object, an electro-optical device according to the present invention includes a first substrate and a second substrate facing each other, an electro-optical material disposed in a gap between the first substrate and the second substrate, A plurality of wirings formed on a surface on the first substrate side of the two substrates, each of the plurality of wirings being a second wiring
The first wiring part formed of the first conductive material in a region of the substrate that overlaps the first substrate, and the overhanging region of the second substrate that protrudes from the periphery of the first substrate than the first conductive material. The second wiring portion formed of a material having high resistivity, and the wiring width of the first portion located at the boundary with the first wiring portion of the second wiring portion is the first portion of the second wiring portion. On the other hand, it is characterized by being wider than the wiring width of the second portion located on the opposite side to the first wiring portion.
According to this structure, the wiring width of the 1st part located in the 1st wiring part side among the 2nd wiring parts is a dimension wider than the wiring width of the 2nd part located in the other side. Therefore, the resistance value of the second wiring portion is reduced as compared with the configuration in which the wiring width of the second wiring portion is the wiring width of the second portion over the entire length. Further, since the wide wiring width can be secured also for the first wiring portion connected to the second portion, the resistance value of each wiring can be reduced, thereby suppressing the variation of the resistance value of each wiring. Is done.

In a preferred aspect of the present invention, each of the plurality of wirings has a third wiring part connected to the opposite side of the second wiring part to the first wiring part, and the second part is formed of the second wiring part. Of these, the portion is located at the boundary with the third wiring portion. The third wiring portion in this aspect is, for example, the connection terminal portion 55 shown in FIG. However, the third wiring portion is not necessarily a portion connected to the IC chip. For example, a configuration in which a connection terminal portion connected to the IC chip is coupled to an end portion of the third wiring portion opposite to the second wiring portion is also employed.

In a desirable aspect of the present invention, the wiring width of the second wiring portion continuously increases from the second portion toward the first portion. In still another aspect, at least one of the wiring width of the second portion in the second wiring portion and the wiring width of the first portion in the second wiring portion is substantially the same for the plurality of wirings. According to these aspects, the configuration of the second wiring portion can be simplified. But it is good also as a structure from which the wiring width of the 2nd part in a 2nd wiring part and a 1st part differs for every wiring. In this aspect, the area of the second wiring portion is substantially the same for the plurality of wirings.

In another aspect, a frame-shaped sealing material is provided to join the two substrates with a gap between the first substrate and the second substrate, and the boundary between the first wiring portion and the second wiring portion of each wiring is It is located inside the outer peripheral edge of the sealing material. According to this aspect, since the contact between the first wiring portion and the outside air is inhibited by the sealing material, there is an advantage that the corrosion of the first wiring portion can be reliably suppressed.

Further, in a desirable aspect of the present invention, there is provided one IC chip that is mounted on an overhanging region that extends in the first direction from the periphery of the first substrate among the second substrate and is connected to each wiring.
The first wiring portion of each wiring has a connecting portion that is directed to the IC chip at a first angle (for example, the angle θ1 in FIG. 7) with respect to the first direction, and the second wiring portion of each wiring is The first portion extends from the first portion toward the IC chip at a second angle smaller than the first angle (for example, the angle θ2 in FIG. 7) with respect to the first direction. According to this aspect, it is possible to equalize each resistance value regardless of the position of each wiring. Note that the wiring width of the connecting portion is substantially the same for a plurality of wirings.

In yet another aspect, a plurality of first drive wirings (for example, one of scanning lines and data lines) formed on a surface of the first substrate facing the electro-optic material are provided, and the first of each wiring is provided.
The wiring portion has a vertical conduction portion extending in a second direction intersecting the first direction and having an end portion connected to the connection portion, and the end portion on the opposite side of the connection portion of the vertical conduction portion is: Conduction to the first drive wiring is made through conduction particles arranged in the gap between the first substrate and the second substrate. According to this aspect, since the IC chip for driving the first drive wiring can be mounted on the second substrate, so-called frame region can be symmetrized or narrowed. In this aspect, a plurality of second drive wirings (for example, the other of the scanning lines and the data lines) formed on the surface of the second substrate facing the electro-optical material and extending in the second direction are provided. The IC chip is connected to a plurality of wires and a plurality of second drive wires. According to this aspect, both the circuit that outputs a signal to the first drive wiring and the circuit that outputs a signal to the second drive wiring can be mounted on the second substrate.

In a desirable aspect of the present invention, the first wiring portion includes a first layer (for example, the first layer 61 shown in FIG. 9) formed of a material having a higher resistivity than the first conductive material and the first conductive portion. It has a structure in which a second layer (for example, the second layer 62 shown in FIG. 9) formed of a conductive material is laminated. According to this aspect, even when the second layer is disconnected due to some defect, the function as the wiring can be maintained by the first layer. Further, if the first layer and the second wiring portion are collectively formed from a single film body in a common process, the manufacturing cost can be reduced.
The positional relationship between the first layer and the second layer is arbitrary. In other words, the first layer may be formed on the surface of the second layer, or the second layer may be formed on the surface of the first layer. Further, another film body (for example, the insulating layer 65 shown in FIG. 9) may be interposed between the first layer and the second layer.

The “wiring width” is typically a dimension of the wiring in a direction perpendicular to the direction in which the wiring extends. From this point of view, the electro-optical device according to the present invention is the first that faces each other.
A substrate and a second substrate; an electro-optic material disposed in a gap between the first substrate and the second substrate;
A plurality of wirings formed on a surface of the substrate on the first substrate side, and each of the plurality of wirings is formed of a first conductive material in a region of the second substrate overlapping the first substrate. First
A wiring portion; and a second wiring portion formed of a material having a higher resistivity than the first conductive material in a protruding region of the second substrate that extends from the periphery of the first substrate. The wiring width, which is the dimension of the second wiring portion in the direction perpendicular to the extending direction, is such that the first portion located at the boundary with the first wiring portion of the second wiring portion is more than the first portion. It is specified as a configuration larger than the second portion located on the opposite side to the first wiring portion.

The electro-optical device according to the present invention is typically used as display means of various electronic devices. Examples of this type of electronic device include a personal computer, a mobile phone, and a projection display device (so-called projector). However, the electro-optical device according to the present invention can be used for purposes other than displaying images. For example, an electro-optical device according to the present invention is:
It is also used as a mask for selectively exposing a workpiece under a photolithography technique.

First, an embodiment in which the present invention is applied to an electro-optical device (liquid crystal device) using liquid crystal as an electro-optical material will be described. In the drawings shown below, the dimensions and ratios are appropriately different from the actual ones in order to make each element large enough to be recognized on the drawings.

<A: Configuration of electro-optical device>
FIG. 1 is an exploded perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. 2 is a plan view of the electro-optical device when viewed from the positive side in the Z direction in FIG. It is. As shown in these drawings, the electro-optical device D includes a first substrate 10 and a second substrate 20 that face each other. The first substrate 10 and the second substrate 20 are plate-like members made of a light-transmitting material such as glass or plastic. The first substrate 10 and the second substrate 20 are made of a sealing material 30 formed in a substantially rectangular frame shape (hatched for convenience in FIG. 2).
It is pasted through.

As shown in FIGS. 1 and 2, the second substrate 20 has a larger outer dimension than the first substrate 10. One IC chip 40 is mounted by COG (Chip On Glass) technology in a region of the second substrate 20 that extends in the Y direction from the periphery of the first substrate 10 (hereinafter referred to as “projected region 20a”). More specifically, the IC chip 40 is disposed in the central portion in the X direction in the overhanging region 20a. The IC chip 40 is an integrated circuit in which the scanning line driving circuits 411 and 412 and the data line driving circuit 43 are mounted on one chip.

FIG. 3 is a cross-sectional view showing a configuration of a region surrounded by the sealing material 30 in the cross section taken along line III-III in FIG. As shown in FIG. 3, the liquid crystal 35 is sealed in the space surrounded by the first substrate 10, the second substrate 20, and the sealing material 30. Actually, the first substrate 1
A polarizing plate and a retardation plate are attached to the surface of each of the 0 and the second substrate 20 opposite to the liquid crystal 35, but the illustration thereof is omitted.

As shown in FIGS. 1 to 3, a plurality of scanning lines 15 are formed on the surface of the first substrate 10 facing the liquid crystal 35. Each scanning line 15 is a strip-like electrode extending in the X direction,
For example, it is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As shown in FIG. 2, the odd-numbered scanning lines 15 counted from above in FIG. 2 extend so that the positive end 155 in the X direction reaches the vicinity of the periphery of the first substrate 10. The end portion 155 overlaps the sealing material 30. Similarly, even-numbered scanning lines 15 counted from above in FIG.
The end portion 155 on the negative side in the X direction extends so as to reach the vicinity of the periphery of the first substrate 10, and the end portion 155 overlaps with the sealing material 30. Although details will be described later, the odd-numbered scanning lines 1
5 is electrically connected to the scanning line driving circuit 412 of the IC chip 40, while the even-numbered scanning lines 15 are electrically connected to the scanning line driving circuit 411.

On the other hand, on the surface of the second substrate 20 facing the liquid crystal 35, a plurality of pixel electrodes 22 are arranged in a matrix in the display area Ad. Each pixel electrode 22 is a substantially rectangular electrode made of a light-transmitting conductive material such as ITO. As shown in FIG. 2, one row of pixel electrodes 22 arranged in the X direction faces one scanning line 15 with a liquid crystal 35 interposed therebetween. One pixel is composed of one pixel electrode 22, a portion of one scanning line 15 facing the pixel electrode 22, and the liquid crystal 35 sandwiched between the gaps. Therefore, these pixels are arranged in a matrix over the X direction and the Y direction in the display area Ad.

FIG. 4 is a plan view showing the configuration of elements formed on the surface of the second substrate 20 facing the liquid crystal 35. In the figure, only the elements related to one pixel are shown, but the other pixels have the same configuration. As shown in FIGS.
A plurality of data lines 21 are formed on the surface of the second substrate 20. Each data line 21 is a wiring extending in the Y direction with a gap between the pixel electrodes 22 in each column aligned in the Y direction. A two-terminal nonlinear element 24 is disposed in the gap between each pixel electrode 22 and the data line 21 adjacent thereto. As shown in FIGS. 1 and 2, each data line 21 extends in the Y direction so as to reach the overhanging area 20 a from the display area Ad, and its end serves as an output terminal of the data line driving circuit 43. Connected.

5 is a cross-sectional view taken along line VV in FIG. 4 (that is, a cross-sectional view of the data line 21). As shown in FIGS. 4 and 5, each data line 21 has a first layer 211 and a second layer 212. A surface of the first layer 211 that is substantially parallel to the surface of the first substrate 10 is covered with an insulating layer 215. On the other hand, the edge part (edge part) in the width direction of the data line 21 in the first layer 211 is exposed from the insulating layer 215. The second layer 212 is formed slightly wider than the first layer 211 and covers the first layer 211 and the insulating layer 215. Therefore, the second
The layer 212 is in contact with the edge portion of the first layer 211 exposed from the insulating layer 215 so as to be in contact with the first layer 21.
1 is conducted.

Next, FIG. 6 is a sectional view taken along line VI-VI in FIG. As shown in FIGS. 4 and 6, the two-terminal nonlinear element 24 includes a long first conductive layer 24 whose longitudinal direction is the Y direction.
1, an insulating layer (hereinafter referred to as “interlayer insulating layer”) 245 formed by anodizing the surface of the first conductive layer 241, and first insulating layers disposed on the surface of the interlayer insulating layer 245. 2 conductive layers 242a and 242b. The first layer 211 of each data line 21 is formed of the same material in the same process as the first conductive layer 241.

The second conductive layer 242 a is a portion of the second layer 212 of the data line 21 that branches in the X direction toward the first conductive layer 241, and overlaps the first conductive layer 241 with the interlayer insulating layer 245 interposed therebetween. On the other hand, the second conductive layer 242b overlaps the first conductive layer 241 with the interlayer insulating layer 245 interposed therebetween. Each pixel electrode 22 is electrically connected to the second conductive layer 242b. The second layer 212 (including the second conductive layer 242a) of each data line 21 and the second conductive layer 24 of the two-terminal nonlinear element 24.
2b is formed of the same material in a common process.

The two-terminal nonlinear element 24 shown in FIG. 4 includes a first element S1 and a second element S2. Among these, as shown in FIG. 6, the first element S1 has a configuration in which the second conductive layer 242a, the interlayer insulating layer 245, and the first conductive layer 241 are stacked in this order as viewed from the data line 21 side. Yes.
Thus, since the first element S1 has a metal / insulator / metal sandwich structure, it exhibits diode switching characteristics in both positive and negative directions. On the other hand, the second element S2 has a configuration in which the first conductive layer 241, the interlayer insulating layer 245, and the second conductive layer 242b are stacked in this order when viewed from the second substrate 20 side. Therefore, the second element S2 exhibits a diode switching characteristic opposite to that of the first element S1. Thus, since the two-terminal nonlinear element 24 has a configuration in which two diodes are connected in series so as to be opposite to each other, the data line 2
Compared with a configuration in which 1 and the pixel electrode 22 are connected via a single diode, the current-voltage nonlinear characteristic is symmetric in both positive and negative directions.

Next, the configuration of wiring for connecting each scanning line 15 to the scanning line driving circuit 411 or 412 of the IC chip 40 will be described. In the following description, a configuration for electrically connecting the odd-numbered scanning lines 15 to the scanning line driving circuit 411 will be described. However, a configuration for electrically connecting the even-numbered scanning lines 15 to the scanning line driving circuit 412 is also left and right. This is the same except that the positional relationship is reversed.

As shown in FIG. 2, in the region extending in the Y direction along the sealing material 30 in the second substrate 20, a plurality of (ie, scanning lines) each corresponding to one of the odd-numbered scanning lines 15. (Half of the total number of 15) wirings 50 are formed. These wirings 50 are wirings for electrically connecting each scanning line 15 in the odd-numbered row and the scanning line driving circuit 411.

FIG. 7 is an enlarged plan view showing the wiring 50 together with the sealing material 30. As shown in the figure, each wiring 50 has a configuration in which a first wiring part 51, a second wiring part 52, and a connection terminal part 55 are connected in this order toward the positive side in the X direction. . The first wiring part 51 and the second wiring part 52 are divided between the inner periphery and the outer periphery of the sealing material 30 with a straight line B extending in the X direction along the sealing material 30 as a boundary. That is, the second wiring portion 52 is a portion located on the overhanging region 20 a side with respect to the boundary B, and the first wiring portion 51 is overhanging the region 20 with respect to the boundary B.
It is a part located on the opposite side to a. Accordingly, the first wiring portion 51 is located in a region of the second substrate 20 surrounded by the outer peripheral edge of the sealing material 30 (in other words, in a region of the second substrate 20 facing the first substrate 10). The second wiring portion 52 is formed so as to extend from one end portion (first end portion 521 described later) located on the boundary B to the overhanging region 20a and the other end portion (second end portion 522 described later). ) Is coupled to the connection terminal portion 55. The connection terminal portion 55 is connected to the output terminal of the scanning line driving circuit 411 in the IC chip 40.

8 is a cross-sectional view taken along line VIII-VIII in FIG. As shown in the figure, the second wiring portion 52 of each wiring 50 has a first layer 61. A surface of the first layer 61 that is substantially parallel to the surface of the second substrate 20 is covered with an insulating layer 65. This insulating layer 65 is formed by anodizing the first layer 61. On the other hand, the edge of the first layer 61 in the width direction of the second wiring portion 52 is exposed from the insulating layer 65.

Next, FIG. 9 is a sectional view taken along line IX-IX in FIG. As shown in the figure,
The first wiring part 51 of each wiring 50 has a second layer 62 in addition to the first layer 61 and the insulating layer 65 similar to the second wiring part 52. The second layer 62 is a film body that covers the first layer 61 and the insulating layer 65, and comes into contact with the edge of the first layer 61 exposed from the insulating layer 65 and is electrically connected to the first layer 61.
Further, FIG. 10 is a sectional view taken along line XX in FIG. In FIG. 10, I
A bump 45 formed on an output terminal of the C chip 40 (an output terminal of the scanning line driving circuit 412) is shown together with a connection terminal portion 55. As shown in the figure, the connection terminal portion 55 is formed on the surface of the second layer 62 in addition to the first layer 61, the insulating layer 65, and the second layer 62 similar to the second wiring portion 52. The third layer 63 is provided. The third layer 63 is a film body formed of the same material (for example, ITO) in the same process as the pixel electrode 22. The IC chip 40 is
It is mounted on the second substrate 20 through an anisotropic conductive film 47 in which conductive particles 471 are dispersed.
In this state, the connection terminal portion 55 is a bump 4 formed on the output terminal of the IC chip 40.
5 is electrically connected to the scanning line driving circuit 412 of the IC chip 40 through the particles 471 interposed in the gap between the third layer 63 and the third layer 63.

The first layer 61 of each wiring 50 and the first layer 211 of the data line 21 are connected to the two-terminal nonlinear element 24.
The first conductive layer 241 is formed of the same material (for example, tantalum) in the same process. That is, by selectively removing (etching) the conductive thin film formed so as to cover the entire surface of the second substrate 20, the first layer 61 of each wiring 50 and the first layer 2 of the data line 21.
11 and the first conductive layer 241 of the two-terminal nonlinear element 24 are collectively formed. Each wiring 50
In the step of forming the interlayer insulating layer 245 of the two-terminal nonlinear element 24, the insulating layer 65 of the data line 21 and the insulating layer 215 of the data line 21 are collectively formed by anodizing the first layers 61 and 211 serving as the respective bases. Formed. Furthermore, the second layer 62 constituting the first wiring part 51 and the connection terminal part 55 is formed of the same material (for example, chromium) in the same process as the second conductive layer 242 of the two-terminal nonlinear element 24. . Thus, the 1st wiring part 51 in this embodiment consists of an electroconductive material (chromium, aluminum, or its alloy) whose resistivity is lower than the electroconductive material (tantalum or its alloy) which forms the 1st layer 61. A second layer 62 is included. According to this configuration, the resistance of the wiring 50 can be suppressed as compared with the case where the wiring 50 is formed only by the first layer 61 over its entire length. On the other hand, a conductive material having a low resistivity such as chromium or aluminum has a high ionization tendency as a conductive material such as tantalum that constitutes the first layer 61 (that is, has low corrosion resistance), and thus is easily corroded by adhesion of moisture or ions. . Therefore, if the second layer 62 is also formed in the second wiring part 52 that contacts the outside air in the overhanging region 20a, there is a problem that the wiring 50 is corroded and the display quality is deteriorated. In the present embodiment, the second layer 62 is formed only on the first wiring part 51 covered with the sealing material 30 and the first substrate 10, and the second wiring part 52 exposed to the overhanging region 20 a has the second layer. Since 62 is not formed, it is possible to prevent moisture and ions from adhering to the second layer 62. Therefore, corrosion of the second layer 62 can be suppressed and the durability and reliability of the device can be improved.

As shown in FIG. 7, the first wiring part 51 has a vertical conduction part 511 and a connection part 512. Among these, the vertical conduction portion 511 is from an end portion (hereinafter referred to as “conduction end portion”) 51E facing the end portion 155 of the scanning line 15 corresponding to the wiring 50 with the seal material 30 interposed therebetween.
This is a portion extending in the Y direction within a region surrounded by the inner peripheral edge. Here, FIG.
FIG. 12 is an enlarged plan view showing the conduction end portion 51E of the vertical conduction portion 511 together with the scanning line 15 on the first substrate 10, and FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. As shown in FIG. 12, the contact hole CH is formed so as to penetrate the first layer 61 and the insulating layer 65 in the conduction end 51 </ b> E. The second layer 62 of the conductive end portion 51E is the first layer 6
In addition to the edge portion of 1, the first layer 61 is electrically connected to the inner surface of the contact hole CH. Further, a third layer 63 is formed of the same material (for example, ITO) in the same process as the pixel electrode 22 on the surface of the second layer 62 of the conduction end portion 51E. As shown in FIGS. 11 and 12, a large number of conductive particles 31 are interposed in the gap between the end portion 155 of the scanning line 15 and the third layer 63 of the end portion 51E for conduction. The conductive particles 31 are conductive particles dispersed in the sealing material 30 and function as a spacer that keeps the distance between the first substrate 10 and the second substrate 20 (so-called cell gap) substantially constant, as well as scanning. The third layer 63 of the end portion 155 of the line 15 and the end portion 51E for conduction
It also plays a role of making the scanning line 15 and the wiring 50 conductive by contacting with each other. With the above configuration, the output terminal of the scanning line driving circuit 412 mounted on the IC chip 40 is connected via the wiring 50 and the conductive particles 31 from the connection terminal portion 55 to the second wiring portion 52 and the first wiring portion 51. Are electrically connected to each scanning line 15.

Next, FIG. 13 is an enlarged plan view showing a portion from the connecting portion 512 to the connection terminal portion 55 of the first wiring portion 51 in FIG. As shown in FIGS. 7 and 13, the first wiring portion 5
One connecting portion 512 extends in an oblique direction from the end portion connected to the vertical conduction portion 511 toward the center portion of the overhang region 20a, and the other end portion reaches the boundary B. More specifically, the connecting portion 512 of each wiring 50 is counterclockwise with respect to the Y direction (the wiring 50 connected to the scanning lines 15 in the even-numbered rows).
(In the clockwise direction), each extends in parallel toward the IC chip 40 in a direction forming an angle θ1. The wiring width Wa of each connecting portion 512 and the interval Wb are substantially the same for all wirings.

On the other hand, as shown in FIG. 7 and FIG. 13, the second wiring portion 52 extends from a portion (hereinafter referred to as “first end portion”) 521 connected to the connecting portion 512 toward the IC chip 40. A portion (hereinafter referred to as a “second end”) 522 opposite to the connecting portion 512 as viewed from the end portion 521 is connected to the connection terminal portion 55. The second wiring portion 52 of each wiring 50 converges toward the positive side in the Y direction so that the closer to the IC chip 40, the narrower the range in which these second wiring portions 52 are distributed. Here, the second wiring portion 52 of the wiring 50 (the wiring 50 connected to the lowermost scanning line 15 among the scanning lines 15 in the odd-numbered rows) that is farthest in the X direction from the center of the overhanging region 20a is: It extends toward the IC chip 40 in a direction that forms an angle θ2 counterclockwise with respect to the Y direction (clockwise in the case of the wiring 50 connected to the scanning lines 15 in even-numbered rows). This angle θ2 is smaller than the angle θ1 formed by the extending direction of the connecting portion 512 of the first wiring portion 51 and the Y direction. Therefore,
Each wiring 50 bends toward the overhanging region 20 a at the boundary between the first wiring part 51 and the second wiring part 52.

As shown in FIG. 13, the first end portion 5 connected to the connecting portion 512 of the second wiring portion 52.
The wiring width W1 of 21 is substantially the same for all the wirings 50, and the wiring width W2 of the second end 522 connected to the connection terminal portion 55 is substantially the same for all the wirings 50. Second of each wiring 50
Since the wiring portion 52 has a trapezoidal shape when viewed in a plan view, the wiring width W1 corresponding to the length of the upper base and the wiring width W2 corresponding to the length of the lower base are all about the wiring 50. The fact that they are substantially the same means that the area of the second wiring portion is the same for all the wirings 50.

As shown in FIG. 13, the wiring width W 1 at the first end 521 of the second wiring portions 52 of each wiring 50 is larger than the wiring width W 2 at the second end 522. For example, the wiring width W2 is 50
The wiring width W1 is about 80 μm while it is about μm (micrometer). In the present embodiment, the wiring width of the second wiring portion 52 continuously increases from the wiring width W2 to the wiring width W1 from the second end portion 522 toward the first end portion 521. By selecting the planar shape of the second wiring part 52 as described above, each scanning line 1 is connected to each output terminal of the scanning line driving circuit 412.
The effect is that the wiring resistance up to 5 can be reduced and the wiring resistance of each wiring 50 can be made uniform. This effect will be described in detail as follows.

As a comparison with the present embodiment, the wiring width of the second wiring portion 52 is the wiring width corresponding to the wiring width of the connection terminal portion 55 over the entire length (that is, from the second end portion 522 to the first end portion 521). Assume a configuration with W2. In this comparative configuration, it is necessary to limit the first wiring part 51 connected to the second wiring part 52 to a wiring width corresponding to the wiring width W2. On the other hand, in the present embodiment, the wiring width of the first wiring portion 51 can be expanded to a dimension corresponding to the wiring width W1 wider than the wiring width W2. Therefore, according to the present embodiment, the wiring resistance over the entire length of each wiring 50 (particularly, the connecting portion 512 of the first wiring portion 51 as compared with the proportionality).
Wiring resistance) can be reduced.

Next, FIG. 14 is a graph showing the relationship between the position of each wiring 50 and the wiring resistance in each part. In the horizontal axis of the figure, as shown in FIG. 7, the position of the wiring 50 connected to the scanning line 15 closest to the IC chip 40 among the odd-numbered scanning lines 15 is set to “0.0”. The position of the wiring 50 connected to the scanning line 15 farthest from the IC chip 40 among the odd-numbered scanning lines 15 is “1.0”, and each position of the plurality of wirings 50 is changed from “0.0” to “ It is expressed as a numerical value in the range up to 1.0 ”(hereinafter referred to as“ position coefficient ”). A characteristic R1a in FIG. 14 indicates a resistance value of the connecting portion 512 of the first wiring portion 51 among the wirings 50, and a characteristic R1b in FIG.
Of 0, the resistance value of the vertical conduction part 511 of the first wiring part 51 is shown. As is apparent from FIG. 7, the total length of the connecting portion 512 and the vertical conducting portion 511 in the first wiring portion 51 is longer as the wiring having a larger position coefficient. Therefore, as shown in FIG. 14 as the characteristic R1a and the characteristic R1b, 51
The resistance values of 2 and the upper and lower conductive portions 511 are larger as the wiring 50 has a larger position coefficient. Therefore, for example, in a configuration in which the connecting portion 512 is directly connected to the IC chip 40 (hereinafter referred to as “proportional”), the resistance value variation over the entire length of the wiring 50 becomes excessive, which causes display unevenness and the like. . In contrast, in the present embodiment, the position coefficient of each wiring 50 and the resistance value of the second wiring portion 52 of the wiring 50 are different from each other in the position coefficient of each wiring 50 and the wiring 50.
The entire length of the second wiring portion 52 is selected so as to be reversed from the magnitude of the resistance value of the connecting portion 512 or the vertical conduction portion 511. That is, as shown in FIG. 7, the second wiring portion 52 in each wiring 50 is designed so that the total length becomes longer as the wiring has a smaller position coefficient. Therefore, as shown as the characteristic R2 in FIG. 14, the resistance value of the second wiring portion 52 is the characteristic R1a.
Contrary to the characteristic R1b, the wiring having a larger position coefficient is reduced. According to the present embodiment in which the wiring 50 is configured by connecting these parts, the variation in the resistance value of each wiring 50 is suppressed as compared with the proportionality, and thus display unevenness due to the variation is suppressed. There is an advantage that.
In particular, in the present embodiment, the second wiring portion 52 for adjusting the resistance value of each wiring 50 is made of a material such as tantalum having a high resistivity. When the wiring width of the high resistance portion is changed in this way, the resistance of the entire wiring 50 is reduced as compared with the case where the wiring width of the first wiring portion 51 made of a material having low resistivity such as chromium is changed. There is an advantage that it can be largely varied.

<B: Modification>
Various modifications are added to each embodiment. An example of a specific modification is as follows. In addition, you may combine each aspect shown below suitably.

(1) In the embodiment, the first end 521 and the second end 5 of the second wiring portion 52 of each wiring 50.
22 illustrates the configuration in which the first end portion 52 and the first end portion 52 are linearly connected.
A configuration in which the first end portion 522 and the second end portion 522 are connected in a curved manner is also employed. In this configuration, the first
The point that the wiring width W1 of the end 521 is larger than the wiring width W2 of the second end 522 is the same as in the embodiment.

(2) In the embodiment, the scanning line driving circuits 411 and 412 for driving each scanning line 15 and the data line driving circuit 43 for driving each data line 21 are mounted on one IC chip 40. Although the configuration is illustrated, a configuration in which each of these circuits is mounted on the second substrate 20 as a separate IC chip is also employed. However, in the configuration in which both the data line 21 and the wiring 50 are connected to one IC chip 40 as in the above-described embodiment, a portion from the vertical conduction portion 511 to the connection terminal portion 55 (that is, the coupling portion 512). And the second wiring part 5
Since 2) needs to be secured for a relatively long time, it can be said that the resistance value in this portion is likely to increase. Therefore, the effect of the present invention to reduce the resistance value of the wiring 50 and suppress the variation in the resistance value of each wiring 50 is that both the data line 21 and the wiring 50 are connected to one IC chip 40 as in the embodiment. This is particularly significant in the configuration that is made.

(3) In the embodiment, the scanning line 15 is formed on the first substrate 10 and the second substrate 2 is formed.
Although the configuration in which the data line 21 and the pixel electrode 22 are formed on 0 is illustrated, on the contrary, the data line 21 and the pixel electrode 22 are formed on the first substrate 10 and the scanning line 15 is formed on the second substrate 20. A configuration in which is formed is also adopted. It does not matter whether the first substrate 10 or the second substrate 20 is located on the observation side or the back side.

(4) In the embodiment, the vertical conduction part 51 on the display area Ad side with respect to the conduction end part 51E.
1 and the connection part 512 are exemplified, but instead of this structure, the conduction end 51E
On the other hand, the vertical conduction portion 511 and the connection portion 512 may extend in the Y direction in a region opposite to the display region Ad (for example, a region covered with the sealing material 30). Even in this configuration, the same operations and effects as in the embodiment are exhibited.

(5) The layer structure of the wiring 50 and the data line 21 is not limited to that shown in the embodiment. For example,
The first layer 61 may not be formed on the display area Ad side with respect to the straight line B, and the first wiring part 51 may be configured by only the second layer 62, or the third layer 63 may be formed on the surface of the second layer 62. The first wiring part 51 may be configured by further stacking layers.

(6) In the embodiment, the configuration in which the present invention is applied to the wiring 50 connected to the scanning line 15 is illustrated, but the present invention is also applied to other wiring. For example, each data line 21 is divided into a first wiring portion on the display region Ad side and a second wiring portion on the overhanging region 20a side with the straight line B as a boundary, and the first wiring portion is electrically conductive such as chromium. The second wiring portion is formed of a material (for example, tantalum) having a lower resistivity than that of the second wiring portion.
A configuration in which the wiring width at the end on the wiring portion side is wider than the wiring width at the second end on the opposite side is also employed. Thus, in the present invention, the planar shape of the “wiring” and the type of signal transmitted thereby are not questioned.

(7) In the embodiment, the electro-optical device D including the TFD element that is a two-terminal switching element is illustrated, but a TFT (Thin Film Transistor) that is a three-terminal switching element.
The present invention is applied to an electro-optical device having an element and a passive matrix electro-optical device having no switching element as in the embodiments. Further, in each embodiment, the configuration in which the TFD element is connected to the data line 21 is illustrated, but a configuration in which the TFD element is connected to the scanning line 15 is also employed instead of this configuration.

(8) In the embodiment, the configuration using the liquid crystal as the electro-optical material is exemplified.
Various electro-optical devices such as electro-optical devices using OLED (Organic Light Emitting Diode) elements such as L (ElectroLuminescent) as electro-optical materials, or plasma display panels using inert gases such as neon and xenon as electro-optical materials The present invention also applies to an apparatus.

<C: Electronic equipment>
Next, an electronic apparatus including the electro-optical device according to the invention as a display unit will be described.
FIG. 16 is a perspective view showing a configuration of a mobile phone having the electro-optical device D according to each embodiment. As shown in this figure, the mobile phone 1200 includes a plurality of operation buttons 1202 operated by a user, a mouthpiece 1204 for outputting a sound received from another terminal device, and a sound transmitted to the other terminal device. In addition to the mouthpiece 1206 for inputting, an electro-optical device D for displaying various images is provided.

In addition to the mobile phone shown in FIG. 16, electronic devices that can use the electro-optical device according to the present invention include notebook personal computers, liquid crystal televisions, projectors, viewfinder types (or monitor direct view types). ) Video recorders, digital cameras, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like.

1 is an exploded perspective view illustrating a configuration of an electro-optical device according to a first embodiment of the invention. 1 is a plan view illustrating a configuration of an electro-optical device according to a first embodiment. It is sectional drawing which shows the structure of the element in a display area among the cross sections seen from the III-III line | wire of FIG. It is a top view which expands and shows the vicinity of one pixel electrode. It is sectional drawing seen from the VV line in FIG. It is sectional drawing seen from the VI-VI line in FIG. It is a top view which shows the structure of the wiring formed on the 2nd board | substrate. It is sectional drawing seen from the VIII-VIII line in FIG. It is sectional drawing seen from the IX-IX line in FIG. It is sectional drawing seen from the XX line in FIG. It is a top view which expands and shows the vicinity of the edge part for conduction | electrical_connection in a vertical conduction part. It is sectional drawing seen from the XII-XII line | wire in FIG. It is a top view which expands and shows the wiring formed on the 2nd board | substrate. It is a graph which shows the relationship between the position of each wiring, and the wiring resistance in each part. It is a top view which shows the shape of each wiring which concerns on a modification. It is a perspective view which illustrates the specific form of the electronic device which concerns on this invention.

Explanation of symbols

D: Electro-optical device, Ad: Display area, 10: First substrate, 15: Scan line, 20:
2nd substrate, 20a ... overhang area, 21 ... data line, 22 ... pixel electrode, 30 ... sealing material, 31 ... conductive particles, 35 ... liquid crystal, 40 ... IC chip, 411, 412 ... Scanning line drive circuit, 43 ... Data line drive circuit, 24 ... Two-terminal nonlinear element, 241 ... First
Conductive layer, 245 ... interlayer insulating layer, 242a, 242b ... second conductive layer, 50 ... wiring, 5
DESCRIPTION OF SYMBOLS 1 ... 1st wiring part, 511 ... Vertical conduction part, 512 ... Connection part, 52 ... 2nd wiring part, 5
21... First end portion, 522... Second end portion, 55... Connection terminal portion.

Claims (12)

A first substrate and a second substrate facing each other;
An electro-optic material disposed between the first substrate and the second substrate;
A plurality of drive wires arranged in the display area and intersecting each other;
A plurality of wirings formed on the second substrate and connected to the driving wirings ;
The second substrate has an overhanging region extending in a first direction from a first peripheral edge of the first substrate, and a region overlapping the first substrate;
The plurality of wirings are wired in overlapping areas and connected to the drive wiring, and second wiring is connected to the projecting area and connects between the first wiring part and the terminal part. And
The wiring width of the first portion along the second direction intersecting the first direction located at the boundary with the first wiring portion in the second wiring portion is the terminal of the second wiring portion. Wider than the wiring width of the second part along the second direction located in the part, the wiring of the second wiring part has substantially the same area,
Of the wirings of the second wiring part, the short wiring is connected to the long wiring of the first wiring part, and the long wiring of the second wiring part is the first wiring. Connected to the short wiring in one wiring section
An electro-optical device. An inter-substrate conduction portion extending in the second direction and electrically connecting the first substrate and the second substrate;
The drive wiring includes a plurality of first drive wirings formed on a side of the first substrate facing the electro-optic material,
The first drive wiring and the wiring of the first wiring part are connected via the inter-substrate conduction part.
The electro-optical device according to claim 1. The first wiring portion and the second wiring portion are formed of a first conductive material,
The first wiring portion is further laminated with a second conductive material having a resistivity lower than that of the first conductive material.
The electro-optical device according to claim 1 or 2. The first conductive material is tantalum;
The second conductive material is chromium or aluminum.
The electro-optical device according to claim 3. The first wiring part is wired along a second peripheral edge along the first direction of the first substrate and is connected to the scanning line; the conduction part; and the second wiring part. A connecting portion that connects between the first direction with respect to the first direction,
The second wiring portion is connected between the terminal portion and the connecting portion at a second angle smaller than the first angle with respect to the first direction.
The electro-optical device according to any one of claims 1 to 4. The wiring width of the second wiring portion continuously increases from the second portion toward the first portion.
The electro-optical device according to any one of claims 1 to 5, characterized in that. A frame-shaped sealing material that joins both the substrates interposed in the gap between the first substrate and the second substrate;
The boundary between the first wiring portion and the second wiring portion of each wiring is located inside the outer peripheral edge of the sealing material.
The electro-optical device according to any one of claims 1 to 6, characterized in that. One IC chip mounted on an overhanging region extending in the first direction from the peripheral edge of the first substrate of the second substrate and connected to each wiring,
The first wiring portion has a connecting portion that faces the IC chip at a first angle with respect to the first direction,
The second wiring portion of each wiring extends from the first portion toward the IC chip at a second angle smaller than the first angle with respect to the first direction. The electro-optical device according to any one of 1 to 7 . The wiring width of the connecting portion is the same for the plurality of wirings.
The electro-optical device according to claim 7. The inter-substrate conduction part includes conductive particles disposed in a gap between the first substrate and the second substrate.
The electro-optical device according to claim 5, wherein the electro-optical device is provided. A plurality of second drive wirings formed on a surface of the second substrate facing the electro-optic material and extending in the second direction;
The IC chip is connected to the plurality of wirings and the plurality of second drive wirings.
The electro-optical device according to claim 1 . An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 11 .

Images