JPH11327464A - Plane display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a pixel display luminance from being dispersed due to the level of the wiring resistance of lead wires, especially, to prevent the difference of luminance from being visualized even when lead wires remarkably different in wiring resistance are arranged adjacently in a panel display device having so-to-call oblique wiring as input wiring from a driving circuit section arranged at a peripheral part. SOLUTION: A lead wire 1 is provided with a thin wire part 11, by adjusting the length of the thin wire part 11 based on the wiring length of the length of the lead wiring 1, each [length of the thin wire part 11 (L1)]/[width of the thin wire part 11 (W1)]+[length of a part 12 other than the thin wire part (L2)]/width of a part 12 other than the thin wire part (W2)] is made equal. Thus, the wiring resistance of each lead wiring 1 is made equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device having a so-called diagonal wiring as a lead wiring for inputting a driving input from a driving circuit section at a peripheral portion to a signal line or a scanning line in an image display area.

[0002]

2. Description of the Related Art In recent years, flat display devices replacing CRT displays have been actively developed. Among them, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption.

A light transmitting type active matrix type liquid crystal display device in which a switch element is disposed in each display pixel will be described as an example. The active matrix type liquid crystal display device has a configuration in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. In an array substrate, for example, a plurality of signal lines as an upper metal wiring pattern and a plurality of scanning lines as a lower metal wiring pattern are formed on a transparent insulating substrate such as glass or quartz through an insulating film. Are arranged in an area, and I
A pixel electrode made of a transparent conductive material such as TO (Indium-Tin-Oxide) is provided. At each intersection of the grid, a switching element for controlling each pixel electrode is arranged. When the switching element is a thin film transistor (hereinafter abbreviated as TFT), the gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode. It is connected to the.

[0004] The opposing substrate is configured such that an opposing electrode made of ITO is disposed on a transparent insulating substrate such as glass, and a color filter layer is disposed for realizing color display.

Usually, a plurality of drive ICs are mounted and connected by a COG method or the like on a shelf-like peripheral portion where the array substrate protrudes from the counter substrate to the outside of the panel. The driving signal is supplied to the signal line or the scanning line. At this time, a lead wire extends from one end of the signal line or the scanning line to the shelf-like peripheral portion, and an input pad formed at the leading end thereof is connected to an output terminal of a tape carrier package (TCP) or an output terminal of a driving IC. The terminal is connected via an ACF (anisotropic conductive film) or the like. The lead wiring is usually formed by a pattern wiring of a metal thin film made of aluminum (Al) or the like at the same time as the signal line, the scanning line, the input pad, and the like.

The structure of the lead-out wiring in the prior art will be described with reference to FIG. 3 taking a scanning line drive input side in a liquid crystal display device as an example.

The input pad groups 113A and 113B connected to the output terminal groups of each TCP respectively include a shelf-shaped peripheral portion 121.
, That is, the pitch thereof is determined by a portion 103A, 103A, of the pixel display area to which the drive signal is supplied from the TCP.
103B is smaller than the dimension in the same direction, that is, the pitch.
Therefore, the lead wiring 101 (101-A1, 101-A1,
-A2,..., 101-B1, 101-B2,.
3B and extend to each other, and most of them are arranged obliquely with respect to the scanning line 115.

[0008]

Therefore, the same width W
In the lead wiring 101, the wiring length L varies depending on the degree of oblique inclination, so that the wiring resistance varies accordingly.

In particular, as shown in FIG. 3, a wiring group 101A composed of lead wirings 101-A1, 101-A2,... Having a relatively short wiring length, and a lead wiring 101-B1 having a wiring length L significantly larger than these. , 101-B2,..., 101-B2,.
Between 1, the wiring resistance changes abruptly. Therefore, the boundary 103C between the image display areas 103A and 103B corresponding to the lead wiring groups 101A and 101B.
In this case, a difference in display luminance was visually recognized, resulting in poor image quality.

This is because, for example, in each TFT 118,
The “gate pulse distortion” increases as the wiring resistance of the extraction wiring 101 to the scanning line 115 increases, and the signal line 11 changes in accordance with the “gate pulse distortion”.
This is because the “penetration voltage of the pixel” transmitted from 6 to the pixel electrode 117 also changes. This also occurs on the signal line side.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a drawback wiring extending from a scanning line or a signal line to a peripheral portion for driving input of a display panel. The present invention provides a flat panel display device having a remarkable difference between them and capable of preventing poor image quality due to the level of wiring resistance and steps.

[0012]

According to a first aspect of the present invention, there is provided a flat display device, wherein scanning lines and signal lines arranged in a matrix in an image display area of a display panel are driven by the scanning lines or the signal lines. A drive circuit portion disposed on a peripheral portion of the display panel to supply an input signal; and an input portion formed in an island shape on the peripheral portion to receive the drive input signal from the drive circuit portion. And a plurality of lead-out lines formed as pattern wiring on the display panel and transmitting the drive input signal from each input part of the input part group to one end of the corresponding scanning line or signal line. In the flat panel display device, when the wiring length of the one lead-out wiring is larger than that of the adjacent lead-out wiring, the wiring width of the one lead-out wiring is set to a part or the whole of the wiring length. Characterized in that the small Te.

With the above configuration, it is possible to suppress variations in pixel display luminance due to the level of the wiring resistance of the lead wiring.

According to a second aspect of the present invention, in the flat panel display device according to the first aspect, the wiring length is divided by the wiring width in each of the minute regions of the one drawing wiring and the drawing wiring adjacent thereto. The values obtained by integrating the values over the entire length of the wiring are substantially equal to each other.

With the above configuration, it is possible to prevent variations in pixel display luminance due to the level of the wiring resistance of the lead-out wiring. In particular, even when lead-out wirings with remarkably different wiring lengths are arranged adjacent to each other, the luminance difference is reduced. It can be prevented from being visually recognized.

According to a fourth aspect of the present invention, in the flat display device, the one lead-out line has a thin line portion, and the one lead-out line and the adjacent lead-out line have a width other than the width of the thin line portion and a portion other than the thin line portion. The widths of the portions are substantially equal to each other, and the wiring resistance value is adjusted by the wiring length of the fine line portion.

With such a configuration, wiring design is easy, and stability in the manufacturing process is high.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 1 is a plan view schematically showing the structure of a lead wiring according to an embodiment, and FIG. 2 is a schematic perspective view of a liquid crystal display device of the embodiment.

First, the overall structure of the liquid crystal display device will be described with reference to FIG.

The liquid crystal display device 10 has a liquid crystal layer held between an array substrate 20 and a counter substrate 25 via an alignment film (not shown). As shown in an enlarged portion in FIG. 2, in the array substrate 10, a plurality of signal lines 16 belonging to an upper metal wiring pattern made of an aluminum (Al) alloy are formed on a glass substrate as a transparent insulating substrate, for example.
And a plurality of scanning lines 15 belonging to a lower metal wiring pattern made of an Al alloy are arranged in a grid via an insulating film, and a region corresponding to each grid of the grid is made of, for example, ITO as a transparent conductive film. A pixel electrode 17 is provided. At each intersection of the grid, a TFT 18 having the scanning line 15 as a gate is arranged, and the TFT 18 changes a pixel line from the signal line 16 to the pixel electrode 17 in accordance with a gate pulse inputted to the scanning line 15. Is transmitted.

As shown in FIG. 2, a scanning line drive I is provided on a scanning line input shelf 21 formed by projecting an array substrate 20 from a counter substrate 25 to one short side (hereinafter referred to as a Y side).
Two scanning line TCPs each equipped with C4A and 4B
41A and 41B are mounted via an anisotropic conductive film (ACF). Then, the scanning line driving ICs 4A and 4B are based on the scanning line driving signals input from one scanning line driving printed wiring board 5 to the scanning line driving ICs 4A and 4B.
Output terminal groups of the scanning line TCPs 41A and 41B, and input pad groups 13A and 13B on the substrate connected to the output terminals.
Then, a gate pulse is input to the scanning line 15 via the lead-out wiring groups 1A and 1B extending from the scanning line 15 to the shelf-shaped peripheral portion 21.

A signal line driving IC 42 is mounted on the signal line input shelf 22 formed by projecting the array substrate 20 from the counter substrate 25 to one long side (hereinafter referred to as X side). Three signal line TCPs 43 are mounted via the ACF, and the printed wiring board 51 is mounted in the same manner as the scanning line side.
A drive signal is input to each signal line 16 based on the drive input from the CPU.

Here, the TCP for the scanning line closer to the X side
41B is arranged so as to be biased toward the side close to the X side, and slightly protrudes into the corner 23 where the shelf-shaped peripheral portions 21 and 22 for scanning line input and signal line input meet. Then, the scanning line T
In the input pad group 13B on the board connected to the output terminal of the CP 4B, the end on the X side is further larger than the end on the X side of the image display area portion 3B driven by an input signal from the input pad group 13B. It is formed at a position protruding from the X side. Therefore, the lead wiring group 1B connecting each signal line 15 of the portion 3B of the image display area and the input pad group 13B is formed in a trapezoidal region which is largely shifted from left-right symmetry such that the parallelogram is distorted. The degree of inclination of the wiring 1 is large as a whole.

On the other hand, the other scanning line TCP
The lead wiring group 1A according to 41A is formed in a substantially symmetric trapezoidal region, and the degree of inclination of the lead wiring 1 is small as a whole.

Therefore, each of these scanning lines TCP 4
At the places where the lead-out wirings 1A and 4B are arranged adjacent to each other, that is, at the boundary between the lead-out wiring groups 1A and 1B, a noticeable difference in inclination occurs between the lead-out wirings 1. Will occur.

Next, a plan configuration of the lead wiring, which is a main part of this embodiment, will be described with reference to FIG. The plan view of FIG. 1 shows a boundary portion between the lead wiring groups 1A and 1B.

As shown in FIG. 1, each lead wiring 1
Thick line portion 12 arranged in a direction inclined with respect to scanning line 15
And a thin line portion 11 which is arranged in the same direction as the scanning line 15 and has substantially the same wiring width as the scanning line 15.

The thin wire portion 11 of the lead wiring 1 is formed longer in the lead wiring having a small inclination angle with respect to the signal line and a short wiring length, and becomes shorter as the inclination angle with respect to the signal line becomes larger, that is, as the wiring length becomes longer. Formed. For example, in FIG.
In A3, the thin line portion 11 is formed to be the longest, and is formed shorter in the order of the lead wiring 1-A2 and the lead wiring 1-A1. The lead wirings 1-B1, 1-B2, 1-B3 belonging to the lead wiring group 1B are the lead wirings 1-A1, 1-A2, 1 belonging to the lead wiring group 1A.
Since the entire wiring length is longer than that of -A3, the thin line portion 11 is formed shorter overall.

Here, in particular, the thin line portion 1 of the lead wiring 1
The length L1 and the width W1 are set such that the wiring resistances of the lead-out wirings 1 are equal to each other. Specifically, for example, the lead wiring 1-A1 and the lead wiring 1-B1 located at the boundary between the lead wiring groups 1A and 1B.
Are formed to the dimensions shown in the table below.

[0030]

[Table 1] As in the specific example shown in the above table, by shortening the thin line portion 11 by the length of the wiring, the “length (L) ÷ sum of width (W)” of each wiring is made equal. It is formed. Since the lead wirings 1 formed from the pattern wirings have the same thickness, the wiring resistances are equal to each other. Similarly, the wiring resistance can be made equal for all the scanning line lead lines or all the signal line lead lines.

According to the present embodiment, it is possible to prevent variations in the pixel display luminance due to the level of the wiring resistance of the lead wiring. Particularly, even when lead wirings having significantly different wiring resistances are arranged adjacent to each other. It is possible to prevent the luminance difference from being visually recognized.

In addition, the wiring resistance is adjusted without changing the widths of the thin line portion 1 and the thick line portion 12 only by adjusting the length of the thin line portion 11 having substantially the same direction and the same width as the signal line 15. In addition, wiring design is easy, and stability in the manufacturing process is high.

In the present embodiment, the wiring resistance is made equal by adjusting the length of the thin wire portion 11. However, it is also possible to adjust the entire wiring width without providing the thin wire portion 11.

In the present embodiment, the description has been given of the lead-out wiring on the scanning line side. However, the lead-out wiring on the signal line side can be similarly made equal in wiring resistance.
In this case, even on the signal line side, the level difference and the variation of the wiring resistance need only be equal to a level that does not cause a visible luminance difference.

Further, the wiring resistance is set equal for all the lead-out wirings on the scanning line side. However, if the step of the luminance is not visually recognized as the step of the wiring resistance between the adjacent lead-out wirings, the wiring resistance is determined. Is hardly observed.

[0036]

According to the present invention, it is possible to prevent variations in pixel display luminance due to the level of the wiring resistance of the lead-out wiring.
Even when the lead-out wirings having significantly different wiring resistances are arranged adjacent to each other, it is possible to prevent the luminance difference from being visually recognized.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a structure of a lead wiring according to an example.

FIG. 2 is a schematic perspective view of a liquid crystal display device according to an embodiment.

FIG. 3 is a schematic plan perspective view schematically showing the structure of a lead wiring according to a conventional flat panel display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead-out wiring 11 Thin-line part 12 Thick-line part 13 Input pad 15 Scan line 1A Lead-out wiring group connected to one drive circuit part 1B Lead-out wiring group connected to another drive circuit part 3A Image driven by one drive circuit part Display area part 3B Image display area part driven by another drive circuit part 13A Input pad group connected to one drive circuit part 13B Input pad group connected to another drive circuit part

Claims (8)

[Claims] 1. A scanning line and a signal line arranged in a matrix in an image display area of a display panel, and arranged on a peripheral portion of the display panel to supply a drive input signal to the scanning line or the signal line. A drive circuit section, an input section group formed in an island shape on the peripheral portion to receive the drive input signal from the drive circuit section, and an input section formed as a pattern wiring on the display panel; In a flat panel display device including a plurality of lead-out lines that transmit the drive input signal from each input unit of the unit group to one end of the corresponding scanning line or signal line, a wiring length of the one lead-out line is In a case where the wiring width is larger than that of the adjacent wiring, the wiring width of the one wiring is reduced in part or all of the wiring length in accordance with the difference in the wiring length. Flat display device. 2. In the one lead wiring and the lead wiring adjacent thereto, the value obtained by integrating the value obtained by dividing the wiring length by the wiring width in each of the minute regions of these wirings over the entire wiring length is substantially equal to each other. 2. The flat display device according to claim 1, wherein wiring resistance values determined from the planar shape are substantially equal to each other. 3. The flat display device according to claim 2, wherein the one lead wiring has a smaller wiring width than the adjacent lead wiring over the entire wiring length. 4. The one lead-out line includes a thin line portion, and the one lead-out line and the adjacent lead-out line are substantially mutually different in a width of the thin line portion and a width of a portion other than the thin line portion. 3. The flat display device according to claim 2, wherein a wiring resistance value is adjusted according to a wiring length of the thin line portion. 5. The thin line portion forms a continuous wiring pattern with the scanning line or signal line electrically connected to the thin line portion, and has a wiring width and a wiring direction substantially equal to each other. A flat display device as described in the above. 6. The one outgoing line belongs to one outgoing line group formed continuously with the one input pad group, and the next outgoing line is connected to the next input pad group. 3. The plane according to claim 2, wherein there is a step in the wiring length between the one lead wiring group and the adjacent lead wiring group. Display device. 7. The wiring resistance value determined from the planar shape is substantially equal for each of the lead wirings on the scanning line drive side, or substantially equal for each of the lead wirings on the signal line drive side. The flat display device according to claim 2. 8. The flat display device according to claim 2, further comprising a thin film transistor connected to a pixel electrode near each intersection of the scanning line and the signal line.