JP4656373B2 - Storage device - Google Patents

Description

  The present invention relates to a storage device, and is suitable for application to a semiconductor storage device configured to store data in a semiconductor memory such as a flash memory, for example.

  In recent years, semiconductor memory devices designed to store data in a semiconductor memory such as a flash memory have become widespread. Such a semiconductor storage device is configured to be connectable to an external device such as a personal computer, and thereby functions as a storage device of the external device. (For example, Patent Document 1)

  Here, as an example, a card-type semiconductor memory device is shown in FIG. The semiconductor memory device includes a controller unit 101 and a flash memory unit 102 in which data is stored under the control of the controller unit 101.

  In practice, when the controller unit 101 receives data to be written to the flash memory unit 102 from the outside (hereinafter referred to as “write data”), an error correction encoder circuit (inside it) ( (Not shown), an error correction encoding process such as adding an error correction code to the input write data is executed, and the processed data is supplied to the flash memory unit 102. The flash memory unit 102 writes the supplied write data to an internal memory chip (not shown) in accordance with a memory control signal supplied from the controller unit 101.

  The flash memory unit 102 reads out data stored in the memory chip in accordance with a memory control signal supplied from the controller unit 101, and sends the read data (hereinafter referred to as “read data”) to the controller unit 101. Supply. The controller unit 101 executes an error correction decoding process such as detecting an error correction code for the read data from the flash memory unit 102 by an error correction decoder circuit (not shown) provided therein. The read data after the processing is output to an external device.

Incidentally, the memory control signal supplied from the controller unit 101 to the flash memory unit 102 is once input to a predetermined flip-flop circuit and then supplied to the flash memory unit 102 in order to avoid a hazard being superimposed. Is done. As a result, the memory control signal supplied to the flash memory unit 102 is obtained by frequency-dividing (dividing by two or more) an internal clock that is an operation reference of the controller unit 101 or the like. As a result, the read data read by the flash memory unit 102 that operates based on the memory control signal and supplied to the controller unit 101 always takes at least one wait with respect to the internal clock.
JP-A-9-282111

  By the way, in the semiconductor memory device having such a configuration, for example, when the data writing processing speed of the flash memory unit 102 is slow compared with the processing speed of the controller unit 101, for example, when writing data from an external device to the semiconductor memory device, There is a problem that it takes a long time to finish writing the data.

  As a technique for solving this problem, for example, conventionally, as shown in FIG. 19, an 8-bit data-compatible flash memory unit 102 having 8-bit data input / output terminals (MD0 to MD7) has been applied. Can be replaced with a flash memory unit corresponding to 16-bit data. For example, as shown in FIG. 20, when the flash memory unit 2 corresponding to 16-bit data is replaced, the controller unit 1 corresponding to 16-bit data is provided. In this way, the controller unit 1 and the flash memory unit 2 are connected via the 16-bit data input / output terminals (MD0 to MD15) provided in the controller unit 1 and the flash memory unit, respectively. 2 can be widened, and thus the data transfer rate can be improved. Further, the flash memory unit 2 corresponding to 16-bit data can write / read 16-bit data at a time, so that the data writing / reading speed can be improved as a whole semiconductor memory device.

  However, at this time, if the encoder circuit and the decoder circuit for error correction provided in the controller unit 1 are replaced with those corresponding to 16-bit data having input / output terminals for 16 bits, they are proportional to this. As a result, the circuit scale of the encoder circuit and the decoder circuit increases.

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose a storage device that can avoid an increase in circuit scale when increasing the data writing / reading speed. .

In the present invention for solving the above problems, a write data input from the external, obtained from the first time generator unit produced by dividing the timing clock of the write data in accordance with the number of divisions A first data dividing means for dividing the divided write data into a plurality of divided write data using a division timing clock; and a first data dividing means for selecting the divided write data from the plurality of divided write data and supplying the divided write data to the encoding unit a select means, after the error correction processing by the encoding unit, and a first data combining means for supplying to the memory unit by combining a plurality of divided write data, to read out data read out from the memory unit, using the division timing clock select a second data dividing means for dividing the plurality of read divided data, the read divided data from a plurality of read data segment A second selector means against the decoding unit test sheet, after being error correction processing by the decoding unit, so as to provide a second data synthesis means for generating a plurality of divided read data as synthesized by combining read data did.

As a result, the divided write data and divided read data obtained by dividing the data having a large number of bits can be processed as an error correction encoder unit and decoder unit, so that writing to the memory corresponding to the data having a large number of bits is performed. Even when reading is performed, processing of the encoder unit and the decoder unit can be performed at high speed.

As described above , according to the present invention, the frequency division obtained from the first time generator unit generated by dividing the write data input from the outside by dividing the timing clock of the write data according to the number of divisions A first data dividing means for dividing the divided write data into a plurality of divided write data using a timing clock; and a first selecting means for selecting divided write data from the plurality of divided write data and supplying the divided write data to the encoding unit. A first data synthesizing unit that synthesizes a plurality of divided write data and supplies the resultant divided write data to the memory unit after the error correction process is performed by the encoding unit; A second data dividing means for dividing the read divided data into a plurality of read divided data by using a clock; A second selector means for supplying, and after the error correction processing by the decoding unit, by providing the second data synthesis means for generating a plurality of divided read data as synthesized by combining read data, for error correction As encoder unit and decoder unit, it is possible to process divided write data and divided read data obtained by dividing data with a large number of bits, so even when writing to and reading from a memory corresponding to data with a large number of bits parts and the processing of the decoder section can be performed at high speed, thus can Ru can achieve a storage device may be possible to avoid the circuit scale of the encoder and the decoder unit is increased.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment In FIG. 1, in which parts corresponding to those in FIGS. 18 and 20 are assigned the same reference numerals, 50 denotes a card type semiconductor memory device according to the first embodiment as a whole, It has a controller unit 1 and a flash memory unit 2 in which data is stored under the control of the controller unit 1.

  The controller unit 1 supplies the flash memory unit 2 with a memory control signal obtained by dividing the internal clock, which is an operation reference of the controller unit 1, by two. The flash memory unit 2 executes data write processing and data read processing in accordance with the supplied memory control signal. Incidentally, the flash memory unit 2 has a data input / output terminal for 16 bits, and is compatible with 16-bit data capable of processing 16-bit data at a time.

  For example, when write data to be written to the flash memory unit 2 is input to the host interface unit 3 in the controller unit 1 from an external device (not shown) connected to the semiconductor memory device 50, this host interface The unit 3 supplies the input write data to the page buffer unit 5 under the control of an MCU (Micro Controller Unit) 4.

  The page buffer unit 5 temporarily stores the supplied write data under the control of the MCU 4 and appropriately supplies the temporarily stored write data to an ECC (Error Correcting Circuit) unit 6. To do.

  Under the control of the MCU 4, the ECC unit 6 performs error correction encoding processing on the write data from the page buffer unit 5 by using an error correction encoder circuit provided in the ECC unit 6. Embedded data is supplied to the flash memory unit 2 via the time generator unit 7.

  The flash memory unit 2 writes the supplied write data to an internal memory chip (not shown) in accordance with a memory control signal supplied from the time generator unit 7.

  The flash memory unit 2 reads the data stored in the memory chip in accordance with the memory control signal given from the time generator unit 7 and supplies the read data thus read to the ECC unit 6 via the time generator unit 7. .

  Under the control of the MCU 4, the ECC unit 6 performs error correction decoding processing on the read data from the flash memory unit 2 by an error correction decoder circuit provided therein, and the read data after the processing is performed. Is supplied to the page buffer unit 5.

  The page buffer unit 5 outputs read data from the ECC unit 6 to an external device via the host interface unit 3 under the control of the MCU 4.

  Here, the configuration of the semiconductor memory device 50 will be described in detail with reference to FIGS. Incidentally, the output buffer circuit 7C, the input buffer circuit 7D, the first and second flip-flop circuits 7A and 7B shown in FIG. 2, the first and second time generator circuits 7E and 7F shown in FIG. It corresponds to the time generator unit 7 shown. Here, the first and second time generator circuits 7E and 7F cooperate with the MCU 4 to generate various control signals for controlling each circuit shown in FIG. 2, the flash memory unit 2, and the like.

  The encoder circuit 6A, the decoder circuit 6B, and the like shown in FIG. 2 correspond to the ECC unit 6 shown in FIG. Here, the encoder circuit 6A has a data input / output terminal for 8 bits, and is compatible with 8-bit data capable of processing 8-bit data at a time. The decoder circuit 6B also has an 8-bit data input / output terminal, and is compatible with 8-bit data that can process 8-bit data at a time. Further, the page buffer circuit 5A and the like shown in FIG. 2 correspond to the page buffer unit 5 shown in FIG.

  For example, when 16-bit write data to be written to the flash memory unit 2 is supplied from the external device to the first selector circuit 5B via the page buffer circuit 5A, the first selector circuit 5B at this time According to the control signal from the generator circuit 7E, the supplied write data is divided every 8 bits, and the obtained lower 8 bits write data and upper 8 bits write data are sent to the encoder circuit 6A. (In the first and second embodiments, for convenience of explanation, lower 8 bits of write data and upper 8 bits of write data are respectively supplied as first divided write data and second This is called divided write data).

  Specifically, as shown in FIG. 4, the first selector circuit 5B has the write signal supplied from the page buffer circuit 5A during the period when the control signal (Sel) from the first time generator circuit 7E rises. Among the data (BDOn), the first divided write data (EeDIn_L) is selected and supplied to the encoder circuit 6A, while the control signal (Sel) falls during this period Of the write data (BDOn) supplied from the buffer circuit 5A, the second divided write data (EeDIn_U) is selected and supplied to the encoder circuit 6A.

  In FIG. 4 and FIGS. 6 and 10 described later, 16-bit data is represented by XXX [15: 0], lower 8-bit data is represented by XXX_L [7: 0], and upper 8-bit data is represented by It is expressed as XXX_U [7: 0].

  The encoder circuit 6A sequentially executes an error correction encoding process on each of the first divided write data and the second divided write data sequentially supplied from the first selector circuit 5B, and the first divided data after the process is processed. The divided write data and the second divided write data are sequentially output.

  Specifically, as shown in FIG. 4, the first divided write data (EeDOn_L) output from the encoder circuit 6A is output with a delay of two clocks (internal clock). Similarly, the second divided write data (EeDOn_U) output from the encoder circuit 6A is also output with a delay of 2 clocks (internal clock).

  The first flip-flop circuit 7A latches the first divided write data output from the encoder circuit 6A according to the control signal from the first time generator circuit 7E. Next, the second flip-flop circuit 7B latches the second divided write data output next from the encoder circuit 6A in accordance with the control signal from the first time generator circuit 7E.

  Specifically, as shown in FIG. 4, the first flip-flop circuit 7A has a first divided document output from the encoder circuit 6A at the timing when the control signal (en0) from the first time generator circuit 7E rises. Data (EeDOn_L) is latched. The second flip-flop circuit 7B latches the second divided write data (EeDOn_U) output next from the encoder circuit 6A at the timing when the control signal (en1) from the first time generator circuit 7E rises. To do.

  The output buffer circuit 7C has the first divided write data and the second divided write data from the first flip-flop circuit 7A and the second flip-flop circuit 7B in accordance with the control signal from the first time generator circuit 7E. The first divided write data and the second divided write data are taken in at the output timing and synthesized, and the obtained 16-bit data is written to the flash memory unit 2 as a 16-bit It is output to the flash memory unit 2 as write data.

  Specifically, as shown in FIG. 4, the output buffer circuit 7C includes a first flip-flop circuit 7A and a second flip-flop circuit during a period when the control signal (OB_en) from the first time generator circuit 7E rises. The first divided write data (QAn) and the second divided write data (QBn) output together from the circuit 7B are taken and synthesized, and the obtained 16-bit data is written data ( MDOn) is output to the flash memory unit 2.

  The flash memory unit 2 takes in the write data output from the output buffer circuit 7C in accordance with the memory control signal supplied from the second time generator circuit 7F and writes it to the internal memory chip. ing.

  Specifically, as shown in FIG. 4, the flash memory unit 2 is output from the output buffer circuit 7C at the timing when the memory control signal (ExtMemXWE) supplied from the second time generator circuit 7F falls. Capture of write data (MDOn) is started, and capture of the write data (MDOn) is completed at the timing when the control signal (ExtMemXWE) rises.

  In this way, in this semiconductor memory device 50, 16-bit write data supplied from the outside is divided to generate two 8-bit divided write data, which are sequentially supplied to the encoder circuit 6A. The first selector circuit 5B, the first and second flip-flop circuits 7A and 7B for latching the divided write data sequentially output from the encoder circuit 6A, and the first and second flip-flop circuits 7A and 7B, respectively. An output buffer circuit 7C for synthesizing the divided write data output together and outputting the 16-bit data obtained as a result as write data is provided.

  As a result, the encoder circuit 6A of the semiconductor memory device 50 may be capable of processing at least 8-bit divided write data at a time, so that it is not necessary to apply an encoder circuit corresponding to 16-bit data. An increase in scale can be avoided.

  In the case of the present embodiment, the encoder circuit 6A does not encode 16-bit write data at a time, but separates each of 8-bit divided write data obtained by dividing the 16-bit write data into two. Are sequentially encoded, and accordingly, it takes a long time until one write data is encoded. However, in the case of the present embodiment, the flash memory unit 2 is operated based on the memory control signal obtained by dividing the internal clock that is the operation reference of the encoder circuit 6A by 2, so that the encoder circuit 6A performs the encoder process. The flash memory unit 2 executes data write processing at a corresponding speed.

  In recent years, it has become difficult to improve the processing speed of the flash memory unit 2, while the processing speed of the controller unit 1 (MCU 4, encoder circuit 6 </ b> A, etc.) has improved remarkably. For this reason, for example, when the flash memory unit 2 operating at 20 [MHz] is applied, it is possible to apply the controller unit 1 operating at 40 [MHz] which is twice that of the flash memory unit 2.

  Therefore, the semiconductor memory device 50 is provided with the controller unit 1 that operates at a clock twice that of the flash memory unit 2 as described above, and the flash memory is generated by a clock (memory control signal) obtained by dividing the clock of the controller unit 1 by two. If the unit 2 is operated, the processing speed of the entire semiconductor memory device 50 can be improved by the configuration of the present embodiment.

  By the way, when the flash memory unit 2 reads data from the memory chip in accordance with a memory control signal given from the controller unit 1 and supplies the read data to the input buffer circuit 7D shown in FIG. In accordance with the control signal from the first time generator circuit 7E, the third flip-flop circuit 7D1 and the fourth flip-flop circuit 7D2 (FIG. 5) provided therein provide the lower 8 bits of the supplied read data and Latch the upper 8 bits.

  Specifically, as shown in FIG. 6, the third flip-flop circuit 7D1 and the fourth flip-flop circuit 7D2 include the lower 8 bits of the read data (MDIn) read by the flash memory unit 2 according to the memory control signal (ExtMemXRE) and The upper 8 bits are latched at the timing when the control signal (IB_en) from the first time generator circuit 7E rises.

  The second selector circuit 7D3 in the input buffer unit receives the lower 8 bits or the upper 8 bits of the read data output from the third flip-flop circuit 7D1 and the fourth flip-flop circuit 7D2 according to the control signal from the first time generator circuit 7E. Bits are selectively supplied to a subsequent decoder circuit 6B.

  Specifically, as shown in FIG. 6, the second selector circuit 7D3 includes the third flip-flop circuit 7D1 and the fourth flip-flop circuit during the period when the control signal (Sel) from the first time generator circuit 7E rises. The lower 8-bit read data (EdDIn_L) of the read data (mdi_Idn) output from 7D2 is supplied to the decoder unit, and the control signal (Sel) from the first time generator circuit 7E falls. During this period, the read data (EdDIn_U) for the upper 8 bits of the read data (mdi_Idn) output from the third flip-flop circuit 7D1 and the fourth flip-flop circuit 7D2 is supplied to the decoder circuit 6B.

  In this manner, the input buffer circuit 7D divides the 16-bit read data supplied from the flash memory unit 2 into lower 8 bits and upper 8 bits, and the lower 8 bits read data and upper 8 bits obtained as a result. Bit read data is sequentially supplied to the decoder circuit 6B (in the first and second embodiments, for the sake of convenience of explanation, the lower 8-bit read data and the upper 8-bit read data are used. Are referred to as first divided read data and second divided read data, respectively).

  The decoder circuit 6B performs an error correction decoding process on each of the first divided read data and the second divided read data sequentially supplied from the input buffer circuit 7D, and the first divided read data after the process is performed. The second divided read data is sequentially output.

  Specifically, as shown in FIG. 6, the first divided read data (EeDOn_L) output from the decoder circuit 6B is output with a delay of two clocks (internal clock). Similarly, the second divided read data (EeDOn_U) output from the decoder circuit 6B is output with a delay of 2 clocks (internal clock).

  The fifth flip-flop circuit 5C latches the first divided read data output from the decoder circuit 6B according to the control signal from the first time generator circuit 7E. Next, the sixth flip-flop circuit 5D latches the second divided read data output next from the decoder circuit 6B in accordance with the control signal from the first time generator circuit 7E.

  Specifically, as shown in FIG. 6, the fifth flip-flop circuit 5C has the first divided read output from the decoder circuit 6B at the timing when the control signal (en10) from the first time generator circuit 7E rises. Latch data (EeDOn_L). Next, the sixth flip-flop circuit 5D latches the second divided read data (EeDOn_U) output next from the decoder circuit 6B at the timing when the control signal (en11) from the first time generator circuit 7E rises. .

  The page buffer circuit 5A is configured to output first divided read data and second divided read data output from the fifth flip-flop circuit 5C and the sixth flip-flop circuit 5D in accordance with a control signal from the first time generator circuit 7E. Are combined, and the obtained 16-bit data is output to the outside as read data.

  Specifically, as shown in FIG. 6, the page buffer circuit 5A includes the fifth flip-flop circuit 5C and the sixth flip-flop at the timing when the control signal (PB_XWE) supplied from the first time generator circuit 7E falls. The first divided read data (QCn) and the second divided read data (QDn) output together from the circuit 5D are started to be fetched, and at the timing when the control signal (ExtMemXWE) rises, the first divided read data is output. The data (QCn) and the second divided read data (QDn) are taken in.

  As described above, the semiconductor memory device 50 generates two pieces of 8-bit divided read data by dividing the 16-bit read data read from the flash memory unit 2 and sequentially supplies them to the decoder circuit 6B. From the input buffer circuit 7D to be supplied, the fifth and sixth flip-flop circuits 5C and 5D for latching the divided read data sequentially output from the decoder circuit 6B, and the fifth and sixth flip-flop circuits 5C and 5D, respectively. A page buffer circuit 5A for synthesizing the divided read data output together and outputting the 16-bit data obtained as a result as read data is provided.

  As a result, the decoder circuit 6B of the semiconductor memory device 50 may be capable of processing at least 8-bit divided read data at a time, so that it is not necessary to apply a decoder circuit corresponding to 16-bit data. Can be avoided.

  In the above configuration, the semiconductor memory device 50 divides 16-bit write data supplied from the outside to generate two 8-bit divided write data, which are sequentially supplied to the encoder circuit 6A. A first selector circuit 5B for latching, first and second flip-flop circuits 7A and 7B for latching divided write data sequentially output from the encoder circuit 6A, and the first and second flip-flop circuits 7A, The encoder circuit 6A is provided with an output buffer circuit 7C that synthesizes the divided write data output from 7B and outputs the 16-bit data obtained as a result as write data. Encoder circuit for 16-bit data is applied because it can process at least 8-bit data at a time Need without.

  In the semiconductor memory device 50, 16-bit read data read from the flash memory unit 2 is divided to generate two 8-bit divided read data, which are sequentially supplied to the decoder circuit 6B. The input buffer circuit 7D, the fifth and sixth flip-flop circuits 5C and 5D for latching the divided read data sequentially output from the decoder circuit 6B, and the fifth and sixth flip-flop circuits 5C and 5D, respectively. By providing the page buffer circuit 5A for synthesizing the divided read data to be output and outputting the 16-bit data obtained as a result as the read data, the decoder circuit 6B receives at least 8-bit data as 1 It can be processed at any time, so a decoder circuit that supports 16-bit data is suitable. You do not have to.

  According to the above configuration, in order to improve the data write processing / data read processing speed of the semiconductor memory device 50, the flash memory unit 2 corresponding to 16-bit data that can process 16-bit data at a time is applied. Even so, as the encoder circuit 6A and the decoder circuit 6B, those corresponding to 8-bit data capable of processing 8-bit data at a time can be applied, and thus an increase in the circuit scale can be avoided. it can.

(2) Second Embodiment In FIG. 7 in which parts corresponding to those in FIG. 1 are given the same reference numerals, 50X indicates a semiconductor memory device according to the second embodiment as a whole, and this semiconductor memory device 50X is Compared with the semiconductor memory device 50 according to the first embodiment, the configuration around the page buffer unit 5X is mainly different. Therefore, the corresponding parts in FIG. 2 and FIG. 9 will be described in detail with a focus on that point.

  That is, the page buffer circuit 5AX shown in FIG. 8 has a function of taking data output from the decoder circuit 6B in units of bytes (8 bits).

  Accordingly, the page buffer circuit 5AX separately takes in the first divided read data and the second divided read data that are sequentially output from the decoder circuit 6B in accordance with the control signal from the first time generator circuit 7EX. , And the obtained 16-bit data is output to the outside as read data.

  Specifically, as shown in FIG. 10, the page buffer circuit 5AX outputs the first output from the decoder circuit 6B at the timing when the control signal (PB_XWE [0]) supplied from the first time generator circuit 7EX falls. The acquisition of one divided read data (EdDon_L) is started, and at the timing when the control signal (PB_XWE [0]) rises, the acquisition of the first divided read data (EdDon_L) is completed. Next, the page buffer circuit 5AX outputs the second divided read data (EdDon_U) output next from the decoder circuit 6B at the timing when the control signal (PB_XWE [1]) supplied from the first time generator circuit 7EX falls. ) Is started, and at the timing when the control signal (PB_XWE [1]) rises, the acquisition of the second divided read data (EdDon_U) is completed. Thereafter, the page buffer circuit 5AX combines the fetched first divided read data and second divided read data, and outputs the obtained 16-bit data to the outside as read data. .

  As a result, in the semiconductor memory device 50 according to the first embodiment, the fifth and sixth flip-flop circuits 5C and 5D are provided between the decoder circuit 6B and the page buffer circuit 5A as shown in FIG. However, in the semiconductor memory device 50X of the second embodiment, since the fifth and sixth flip-flop circuits 5C and 5D need not be provided, the configuration can be simplified correspondingly.

11 where the same reference numerals are assigned to corresponding parts of (3) Embodiment Figure 1 of a third embodiment, 50Y represents a semiconductor memory device according to the third embodiment as a whole, the semiconductor memory device 50Y is , as compared with the semiconductor memory device 50 of the first embodiment, since the main structure of the ECC unit 6Y and a time generator section 7Y are different, it shows the same reference numerals are applied to corresponding parts in FIGS. 2 and 3 12, FIG. 13 and FIG. 14 will be described in detail with a focus on this point.

  Incidentally, in the case of the third embodiment, the controller unit 1Y supplies the flash memory unit 2 with a memory control signal obtained by dividing the internal clock, which is an operation reference of the controller unit 1Y, by four. The flash memory unit 2 executes data write processing and data read processing in accordance with the supplied memory control signal.

  The output buffer circuit 7FY, the input buffer circuit 7GY, the first to fifth flip-flop circuits 7AY, 7BY, 7CY, 7DY, and 7EY shown in FIGS. 12 and 13 and the first and second time generator circuits 7HY shown in FIG. , 7IY and the like correspond to the time generator unit 7Y shown in FIG. Here, the first and second time generator circuits 7HY and 7IY shown in FIG. 14 generate various control signals for controlling the circuits shown in FIGS. 12 and 13 and the flash memory unit 2 and the like in cooperation with the MCU 4. To do.

  The encoder circuit 6AY and the decoder circuit 6BY shown in FIGS. 12 and 13 correspond to the ECC unit 6Y shown in FIG. The encoder circuit 6AY has a 4-bit data input / output terminal and is compatible with 4-bit data capable of processing 4-bit data at a time. The decoder circuit 6BY also has a 4-bit data input / output terminal, and is compatible with 4-bit data capable of processing 4-bit data at a time. Further, the page buffer circuit 5AY and the like shown in FIGS. 12 and 13 correspond to the page buffer unit 5Y shown in FIG.

  For example, when 16-bit write data to be written to the flash memory unit 2 is supplied from the external device to the first selector circuit 5BY via the page buffer circuit 5AY, at this time, the first selector circuit 5BY receives the first time. According to the control signal from the generator circuit 7HY, the supplied write data is divided in 4-bit units, and each of the obtained four data (hereinafter referred to as “divided write data”) is converted into an encoder circuit. Sequentially supplied to 6AY.

  In the following, for convenience of explanation, of the four divided write data, the data corresponding to the least significant 4 bits of the write data is referred to as first divided write data. Further, the next upper 4 bit part following the lowest 4 bit part and the next higher 4 bit part are further divided into the second divided write data and the third divided write data, respectively. Call. Further, the data corresponding to the most significant 4 bits of the write data is referred to as fourth divided write data.

  Specifically, as shown in FIG. 15, the first selector circuit 5BY performs the write operation supplied from the page buffer circuit 5AY during the period when the control signal (Sel0) from the first time generator circuit 7HY rises. Among the data (BDOn), the first divided write data (EeDIn_0) is supplied to the encoder circuit 6AY, and then the page buffer during the period when the control signal (Sel1) from the first time generator circuit 7HY rises. Of the write data (BDOn) supplied from the circuit 5AY, the second divided write data (EeDIn_1) is supplied to the encoder circuit 6AY. Subsequently, during the period when the control signal (Sel2) from the first time generator circuit 7HY rises, the first selector circuit 5BY outputs the third of the write data (BDOn) supplied from the page buffer circuit 5AY. The divided write data (EeDIn_2) is supplied to the encoder circuit 6AY, and the write supplied from the page buffer circuit 5AY during the period when the control signal (Sel3) from the first time generator circuit 7HY rises. Of the data (BDOn), the fourth divided write data (EeDIn_3) is supplied to the encoder circuit 6AY.

  Incidentally, in FIG. 15 and FIG. 16 described later, 16-bit data is represented by XXX [15: 0], and 4-bit data is represented by XXX_N [3: 0].

  The encoder circuit 6AY sequentially executes error correction encoding processing for each of the first to fourth divided write data sequentially supplied from the first selector circuit 5BY, and the first to fourth division after the processing. Write data is sequentially output.

  Specifically, as shown in FIG. 15, the first to fourth divided write data (EeDOn_0, EeDOn_1, EeDOn_2, EeDOn_3) output from the encoder circuit 6AY are delayed by 2 clocks (internal clock), respectively. It is made to output.

  The first flip-flop circuit 7AY latches the first divided write data output from the encoder circuit 6AY according to the control signal from the first time generator circuit 7HY. Next, the second flip-flop circuit 7BY latches the first divided write data output from the first flip-flop circuit 7AY according to the control signal from the first time generator circuit 7HY, and at this time, the third flip-flop circuit simultaneously. Similarly, 7CY latches the second divided write data output from the encoder circuit 6AY according to the control signal from the first time generator circuit 7HY. Subsequently, the fourth flip-flop circuit 7DY latches the third divided write data output from the encoder circuit 6AY according to the control signal from the first time generator circuit 7HY. Then, the fifth flip-flop circuit 7EY latches the fourth divided write data output from the encoder circuit 6AY according to the control signal from the first time generator circuit 7HY.

  Specifically, as shown in FIG. 15, the first flip-flop circuit 7AY has a first divided document output from the encoder circuit 6AY at the timing when the control signal (en0) from the first time generator circuit 7HY rises. Data (EeDOn_0) is latched. Next, the second flip-flop circuit 7BY and the third flip-flop circuit 7CY are output from the first flip-flop circuit 7AY and the encoder circuit 6AY at the timing when the control signal (en1) from the first time generator circuit 7HY rises. The first divided write data (QAn) and the second divided write data (EeDOn_1) are latched. Subsequently, the fourth flip-flop circuit 7DY latches the third divided write data (EeDOn_2) output from the encoder circuit 6AY at the timing when the control signal (en2) from the first time generator circuit 7HY rises. The fifth flip-flop circuit 7EY latches the fourth divided write data (EeDOn_3) output from the encoder circuit 6AY at the timing when the control signal (en3) from the first time generator circuit 7HY rises.

  The output buffer circuit 7FY outputs the first to fourth divided write data from the second to fifth flip-flop circuits 7BY, 7CY, 7DY, 7EY in accordance with the control signal from the first time generator circuit 7HY. At this timing, the first to fourth divided write data are fetched and synthesized, and the obtained 16-bit data is written to the flash memory unit 2 as write data to be written to the flash memory unit 2. Output.

  Specifically, as shown in FIG. 15, the output buffer circuit 7FY includes the second to fifth flip-flop circuits 7BY and 7CY during the period when the control signal (OB_en) from the first time generator circuit 7HY rises. 1st to 4th divided write data (QA &#0; n, QBn, QCn, QDn) output together from 7DY, 7EY, combine them, and write the obtained 16-bit data Is output to the flash memory unit 2 as embedded data (MDOn).

  The flash memory unit 2 takes in the write data output from the output buffer circuit 7FY according to the memory control signal given from the second time generator circuit 7IY, and writes it into the internal memory chip. ing.

  Specifically, as shown in FIG. 15, the flash memory unit 2 is configured to write data output from the output buffer circuit 7FY at the timing when the memory control signal (ExtMemXWE) supplied from the second time generator circuit 7IY falls. The capture of the write data (MDOn) is started, and the capture of the write data (MDOn) is completed at the timing when the control signal (ExtMemXWE) rises.

  As described above, in this semiconductor memory device 50Y, 16-bit write data supplied from the outside is divided to generate four 4-bit divided write data, which are sequentially supplied to the encoder circuit 6AY. First selector circuit 5BY, first to fifth flip-flop circuits 7AY, 7BY, 7CY, 7DY, 7EY, and second to fifth flip-flops for latching divided write data sequentially output from encoder circuit 6AY, respectively. An output buffer circuit 7FY is provided which synthesizes the divided write data output from the group circuits 7BY, 7CY, 7DY, 7EY and outputs the 16-bit data obtained as a result as write data.

  As a result, the encoder circuit 6AY of the semiconductor memory device 50Y may be capable of processing at least 4-bit divided write data at a time, so that it is not necessary to apply an encoder circuit corresponding to 16-bit data. Can be avoided.

  In the case of this embodiment, the encoder circuit 6AY does not encode 16-bit write data at a time, but separates each of 4-bit divided write data obtained by dividing the 16-bit write data into four. Are sequentially encoded, and accordingly, it takes a long time until one write data is encoded. However, in the case of the present embodiment, the flash memory unit 2 is operated based on the memory control signal obtained by dividing the internal clock, which is the operation reference of the encoder circuit 6AY, by 4, so that the encoder circuit 6AY performs encoder processing. The flash memory unit 2 executes data write processing at a corresponding speed.

  In recent years, it has become difficult to improve the processing speed of the flash memory unit 2, while the processing speed of the controller unit 1Y (MCU 4, encoder circuit 6AY, etc.) has been remarkably improved. For this reason, for example, when the flash memory unit 2 operating at 20 [MHz] is applied, it is possible to apply the controller unit 1Y operating at 80 [MHz], which is four times as much.

  Therefore, the controller unit 1Y that operates with the clock four times that of the flash memory unit 2 is provided for the semiconductor memory device 50Y, and the clock (memory control signal) obtained by dividing the clock of the controller unit 1Y by four is used for the flash memory. If the unit 2 is operated, the processing speed of the entire semiconductor memory device 50Y can be improved by the configuration of the present embodiment.

  By the way, when the flash memory unit 2 reads data from the memory chip according to the memory control signal given from the controller unit 1Y and supplies the read data to the input buffer circuit 7GY shown in FIG. 13, the input buffer circuit 7GY at this time In accordance with the control signal from the first time generator circuit 7HY, the supplied read data is transferred to 4 by the sixth to ninth flip-flop circuits 7GY1, 7GY2, 7GY3, 7GY4 (FIG. 17) provided therein. Latch every bit.

  Specifically, as shown in FIG. 16, the flip-flop circuits 7GY1, 7GY2, 7GY3, and 7GY4 in the input buffer circuit 7GY are read data that the flash memory unit 2 reads and outputs according to the memory control signal (ExtMemXRE). (MDIn) is latched every 4 bits at the timing when the control signal (IB_en) from the first time generator circuit 7HY rises.

  The second selector circuit 7GY5 in the input buffer circuit 7GY outputs read data output every 4 bits from each flip-flop circuit 7GY1, 7GY2, 7GY3, 7GY4 according to a control signal from the first time generator circuit 7HY. These are sequentially selected and supplied to the subsequent decoder circuit 6BY.

  Specifically, as shown in FIG. 16, when the outputs of the sixth to ninth flip-flop circuits 7GY1, 7GY2, 7GY3, and 7GY4 are combined, 16-bit read data (mdi_Idn) is output. The second selector circuit 7GY5 selects the 4-bit read data (EdDIn_0) output from the sixth flip-flop circuit 7GY1 during the period when the control signal (Sel0) from the first time generator circuit 7HY rises. This is supplied to the decoder circuit 6BY. The second selector circuit 7GY5 selects the 4-bit read data (EdDIn_1) output from the seventh flip-flop circuit 7GY2 during the period when the control signal (Sel1) from the first time generator circuit 7HY rises. This is supplied to the decoder circuit 6BY. Further, the second selector circuit 7GY5 selects the 4-bit read data (EdDIn_2) output from the eighth flip-flop circuit 7GY3 during the period when the control signal (Sel2) from the first time generator circuit 7HY rises. This is supplied to the decoder circuit 6BY. Further, the second selector circuit 7GY5 selects the 4-bit read data (EdDIn_3) output from the ninth flip-flop circuit 7GY4 during the period when the control signal (Sel3) from the first time generator circuit 7HY rises. Then, this is supplied to the decoder circuit 6BY.

  In this way, the input buffer circuit 7GY divides the 16-bit read data supplied from the flash memory unit 2 into four, and the resulting four data (hereinafter referred to as “divided read data”). Are sequentially supplied to the decoder circuit 6BY.

  Hereinafter, for convenience of explanation, of the four divided read data, the data corresponding to the least significant 4 bits of the read data is referred to as first divided read data. Also, the next higher 4 bits following the lowest 4 bits and the next higher 4 bits are called second divided read data and third divided read data, respectively. Further, the data corresponding to the most significant 4 bits of the read data is referred to as fourth divided read data.

  The decoder circuit 6BY sequentially executes error correction decoding processing on each of the first to fourth divided read data sequentially supplied from the input buffer circuit 7GY, and the first to fourth divided read data after the processing. Are output sequentially.

  Specifically, as shown in FIG. 16, the first to fourth divided read data (EeDOn_0, EeDOn_1, EeDOn_2, EeDOn_3) sequentially output from the decoder circuit 6BY are delayed by 2 clocks (internal clock), respectively. Is output.

  The tenth flip-flop circuit 5CY latches the first divided read data output from the decoder circuit 6BY in accordance with the control signal from the first time generator circuit 7HY. Next, the eleventh flip-flop circuit 5DY latches the first divided read data output from the tenth flip-flop circuit 5CY in accordance with the control signal from the first time generator circuit 7HY, and at the same time, the twelfth flip-flop circuit 5EY. Similarly latches the second divided read data output from the decoder circuit 6BY in accordance with the control signal from the first time generator circuit 7HY. Subsequently, the thirteenth flip-flop circuit 5FY latches the third divided read data output from the decoder circuit 6BY in accordance with the control signal from the first time generator circuit 7HY. Then, the fourteenth flip-flop circuit 5GY latches the fourth divided read data output from the decoder circuit 6BY in accordance with the control signal from the first time generator circuit 7HY.

  Specifically, as shown in FIG. 16, the tenth flip-flop circuit 5CY receives the first divided read output from the decoder circuit 6BY at the timing when the control signal (en10) from the first time generator circuit 7HY rises. Latch data (EdDOn_0). Next, the eleventh flip-flop circuit 5DY latches the first divided read data (QEn) output from the tenth flip-flop circuit 5CY at the timing when the control signal (en11) from the first time generator circuit 7HY rises. At the same time, the twelfth flip-flop circuit 5EY latches the second divided read data (EdDOn_1) output from the decoder circuit 6BY. Subsequently, the thirteenth flip-flop circuit 5FY latches the third divided read data (EdDOn_2) output from the decoder circuit 6BY at the timing when the control signal (en12) from the first time generator circuit 7HY rises. Then, the fourteenth flip-flop circuit 5GY latches the fourth divided read data (EdDOn_3) output from the decoder circuit 6BY at the timing when the control signal (en13) from the first time generator circuit 7HY rises.

  The page buffer circuit 5AY takes in the first to fourth divided read data output from the first to fourteenth flip-flop circuits 5DY, 5EY, 5FY, and 5GY in accordance with the control signal from the first time generator circuit 7HY. Are combined, and the obtained 16-bit data is output to the outside as read data.

  Specifically, as shown in FIG. 16, the page buffer circuit 5AY includes the first to fourteenth flip-flop circuits 5DY, 5EY at the timing when the control signal (PB_XWE) supplied from the first time generator circuit 7HY falls. The first to fourth divided read data (QE′n, QFn, QGn, QHn) output from 5FY and 5GY are started to be fetched, and at the timing when the control signal (PB_XWE) rises, The capture of the first to fourth divided read data (QE'n, QFn, QGn, QHn) is completed.

  As described above, in this semiconductor memory device 50Y, four divided read data are generated by dividing the 16-bit read data read from the flash memory unit 2, and these are sequentially supplied to the decoder circuit 6BY. The supplied input buffer circuit 7GY and the tenth to fourteenth flip-flop circuits 5CY, 5DY, 5EY, 5FY, which latch the divided read data sequentially output from the decoder circuit 6BY after the error correction decoding process of the decoder circuit 6BY. 5GY and page buffer circuit 5AY for synthesizing divided read data output from 11th to 14th flip-flop circuits 5DY, 5EY, 5FY and 5GY and outputting the 16-bit data obtained as a result as read data It was made to provide.

  As a result, the decoder circuit 6BY of the semiconductor memory device 50Y may be capable of processing at least 4-bit data at a time, so that it is not necessary to apply a decoder circuit corresponding to 16-bit data, thus increasing the circuit scale. Can be avoided.

  In the above configuration, the semiconductor memory device 50Y divides 16-bit write data supplied from the outside to generate four 4-bit divided write data, and sequentially supplies them to the encoder circuit 6AY. First selector circuit 5BY, first to fifth flip-flop circuits 7AY, 7BY, 7CY, 7DY, 7EY, and second to fifth flip-flops for latching divided write data sequentially output from encoder circuit 6AY, respectively. Output buffer circuit 7FY that combines 16-bit data obtained as a result of synthesizing the divided write data that are output together from the output circuits 7BY, 7CY, 7DY, and 7EY. The encoder circuit 6AY of the semiconductor memory device 50Y can process at least 4-bit data at a time. Since in good need not apply the 16-bit data corresponding encoder circuit.

  Further, the semiconductor memory device 50Y generates four pieces of 4-bit divided read data by dividing the 16-bit read data read from the flash memory unit 2, and sequentially supplies them to the decoder circuit 6BY. A buffer circuit 7GY and tenth to fourteenth flip-flop circuits 5CY, 5DY, 5EY, 5FY, 5GY for latching divided read data sequentially output from the decoder circuit 6BY after the error correction decoding process of the decoder circuit 6BY; A page buffer circuit 5AY that synthesizes the divided read data output from the 11th to 14th flip-flop circuits 5DY, 5EY, 5FY, and 5GY and outputs the resulting 16-bit data as read data; The decoder of the semiconductor memory device 50Y Since road 6BY may be capable to process at least four bits of data at a time, it is not necessary to apply the 16-bit data corresponding decoder circuit.

  According to the above configuration, in order to improve the data write processing / data read processing speed of the semiconductor memory device 50Y, the 16-bit data compatible flash memory unit 2 capable of processing 16-bit data at a time is applied. Even so, as the encoder circuit 6AY and the decoder circuit 6BY, those corresponding to 4 bits capable of processing 4 bits of data at a time can be applied, and thus an increase in circuit scale can be avoided. .

(4) Other Embodiments In the above-described embodiment, the first selector circuits 5B, 5BX, 5BY (or the second selector circuits 7D3, 7GY5) are supplied with write data (or from the previous stage circuit). In the above description, the read data) is sequentially selected from the lower 8 bits (or 4 bits) and sequentially output to the subsequent circuit. However, the present invention is not limited to this, and the first selector circuit 5B. 5BX, 5BY (or the second selector circuits 7D3, 7GY5) may sequentially select the write data (or read data) supplied from the preceding circuit from the upper side.

  In the above-described embodiment, the case where the flash memory unit 2 corresponding to a flash EEPROM (Electrically Erasable and Programmable ROM) or the like is applied as the memory unit is described. However, the present invention is not limited to this, and the SRAM (Static Various other memories such as RAM) and DRAM (Dynamic RAM) may be applied.

  Furthermore, in the above-described embodiment, the case where the card-type semiconductor storage devices 50, 50X, and 50Y corresponding to, for example, the memory stick (R) are applied as the storage device has been described. However, the present invention is not limited to this. Various other types of storage devices may be applied.

  Furthermore, in the above-described embodiment, a plurality of divided write data is generated by dividing external write data, and the generated plurality of divided write data is sent to the encoder unit (encoder circuits 6A, 6AY). In the above description, the first selector circuits 5B, 5BX, and 5BY are applied as the first data dividing unit that is sequentially supplied. However, the present invention is not limited to this, and various other configurations can be applied.

  Furthermore, in the above-described embodiment, after the encoding process (error correction encoding process) of the encoder unit, a plurality of divided write data sequentially output from the encoder unit are combined, and the obtained data is stored in the memory as write data. Although the flip-flop circuits 7A, 7B, 7AY, 7BY, 7CY, 7DY, and 7EY and the output buffer circuits 7C and 7FY are applied as the first data synthesizing unit supplied to the unit, the present invention has been described. Not limited to this, various other configurations can be applied.

  Further, in the above-described embodiment, a plurality of divided read data are generated by dividing the read data read from the memory unit, and the generated plurality of divided read data are decoded (decoder circuits 6B, 6BY). In the above description, the input buffer circuits 7D and 7GY are applied as the second data dividing unit to be sequentially supplied. However, the present invention is not limited to this, and various other configurations can be applied.

  Further, in the above-described embodiment, after the decoding process (error correction decoding process) of the decoder unit, a plurality of divided read data sequentially output from the decoder unit are combined, and the obtained data is output as read data. Although the flip-flop circuits 5C, 5D, 5CY, 5DY, 5EY, 5FY, and 5GY and the page buffer circuits 5A, 5AX, and 5AY are described as the data synthesizer 2 in the second embodiment, the present invention is not limited to this. Various configurations can be applied.

  The present invention can be used, for example, in a semiconductor memory device configured to store data in a semiconductor memory such as a flash memory.

1 is a schematic diagram illustrating a configuration of a semiconductor memory device according to a first embodiment. It is a basic diagram which shows the internal structure (1) of a semiconductor memory device. It is a basic diagram which shows the internal structure (2) of a semiconductor memory device. It is a basic diagram which shows the time chart (1) at the time of data writing. It is a basic diagram which shows the structure (1) of an input buffer circuit. It is a basic diagram which shows the time chart (1) at the time of data reading. It is a basic diagram which shows the structure of the semiconductor memory device by 2nd Embodiment. It is a basic diagram which shows the internal structure (3) of a semiconductor memory device. It is a basic diagram which shows the internal structure (4) of a semiconductor memory device. It is a basic diagram which shows the time chart (2) at the time of data reading. It is a basic diagram which shows the structure of the semiconductor memory device by 3rd Embodiment. It is a basic diagram which shows the internal structure (5) of a semiconductor memory device. It is a basic diagram which shows the internal structure (6) of a semiconductor memory device. It is a basic diagram which shows the internal structure (7) of a semiconductor memory device. It is a basic diagram which shows the time chart (2) at the time of data writing. It is a basic diagram which shows the time chart (3) at the time of data reading. It is a basic diagram which shows the structure (2) of an input buffer circuit. It is a basic diagram which shows the structure of a semiconductor memory device. It is a basic diagram which shows the connection form (1) of a controller part and a flash memory part. It is a basic diagram which shows the connection form (2) of a controller part and a flash memory part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Controller part, 2 ... Flash memory part, 4 ... MCU, 5 ... Page buffer part, 6 ... ECC part, 7 ... Time generator part, 5A ... Page buffer circuit, 5B ... Selector circuit 5C, 5D, 7A, 7B: Flip-flop circuit, 6A: Encoder circuit, 6B: Decoder circuit, 7C: Output buffer circuit, 7D: Input buffer circuit, 50: Semiconductor memory device.

Claims (1)

The write data input from the external, a plurality of divided document using the division timing clock obtained from a first time generator unit produced by dividing the timing clock of the write data in accordance with the number of divisions First data dividing means for dividing into embedded data ;
First select means for selecting divided write data from a plurality of divided write data and supplying the selected write data to the encoding unit;
A first data synthesizing unit configured to synthesize a plurality of divided write data and supply the resultant to the memory unit after error correction processing by the encoding unit;
To read out data read out from said memory unit, a second data dividing means for dividing the plurality of read divided data by using the division timing clock,
A second selector means for test sheet against the decoding unit selects the read divided data from the plurality of read divided data,
After being error correction processing by the decoding unit, a second data combining means and the comprising Ru storage peripherals for generating a plurality of divided read data as synthesized by combining read data.

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