JP4654133B2 - Wiring board - Google Patents

Description

  The present invention relates to a wiring board.

JP 2001-035966 A

  In recent years, semiconductor integrated circuit elements that operate at high speed, such as CPUs and other LSIs, are becoming increasingly smaller, and the number of signal terminals, power supply terminals, or ground terminals is increasing, and the distance between terminals is also decreasing. For the integrated circuit side terminal array, where many terminals are densely packed, the technology of connecting to the motherboard side in a flip-chip form has become common, but there is a large difference in terminal spacing between the integrated circuit side terminal array and the motherboard side terminal array. There is a need for a wiring board as an intermediate board for converting this.

  Among the above-mentioned intermediate substrates, what is called an organic package substrate has a wiring laminated portion in which dielectric layers and conductor layers made of a polymer material are alternately laminated, and the dielectric of the wiring laminated portion. A terminal array for flip chip connection is arranged on the first main surface formed of the body layer. The wiring laminated portion is formed on a substrate core mainly composed of a polymer material such as an epoxy resin reinforced with glass fiber. When there is a considerable gap between the terminal spacing on the IC side and the terminal spacing on the main board (motherboard) side that is the connection destination, the number of terminals increases in the wiring and via arrangement pattern for the conversion. However, the organic package substrate can form such a fine and complicated wiring pattern with high accuracy and ease by combining the photolithography technology and the plating technology. There are advantages.

  However, in the organic package substrate, in addition to the main substrate (for example, the mother board) as the connection destination being mainly composed of a polymer material, the component material itself is mainly composed of a polymer material. When a thermal history such as solder reflow is applied, the linear expansion of a semiconductor integrated circuit element mainly composed of silicon (linear expansion coefficient is, for example, 2-3 ppm / ° C.) and the main substrate (linear expansion coefficient is, for example, 17-18 ppm / ° C.). The coefficient difference cannot be fully absorbed, which may lead to problems such as solder peeling.

  On the other hand, Patent Document 1 discloses a ceramic package substrate in which the main material of the substrate is made of ceramic. By using such a ceramic package substrate, it is possible to fill a large difference in linear expansion coefficient between the flip-chip connected semiconductor integrated circuit element and the main substrate, and in particular, solder bonding between terminals of the semiconductor integrated circuit element. It is possible to effectively prevent a problem that the portion is disconnected due to thermal stress.

  However, in a ceramic package substrate, the wiring part is formed by printing and baking metal paste, so that it is difficult to make the wiring part finer and highly integrated than an organic package substrate that can use photolithography technology. Therefore, there is a limit to the reduction of the terminal interval on the semiconductor integrated circuit element side. Therefore, a first intermediate substrate made of an organic package substrate is connected to the main substrate side, a second relay substrate made of ceramic is connected to the first intermediate substrate, and a semiconductor integrated circuit element is connected to the second relay substrate. It is also possible to consider a multi-stage board connection structure that connects the two, but as the number of intermediate boards increases, the height of the board connection structure increases, making it difficult to meet the demand for miniaturization. Since the number of connection processes increases, there is also a disadvantage that becomes inefficient.

  An object of the present invention is to provide a wiring board that is less likely to cause disconnection due to thermal stress, and that can easily reduce the overall height of the board connection structure and reduce the number of connection steps.

Means for Solving the Invention and Effects of the Invention

In order to solve the above problems, the first of the wiring boards of the present invention is:
It is made of a polymer material (conceptually including materials combined with fillers such as ceramic fibers and particles), and the sub-core housing part is formed in the first main surface so as to reduce its thickness. And a sub-core portion that is configured in a plate shape with a material having a smaller linear expansion coefficient than the core main-body portion, and is accommodated in the sub-core accommodating portion so that the thickness direction coincides with the core main-body portion. A substrate core, and a filling and bonding layer made of a polymer material that fills a gap between the inner peripheral surface of the sub-core housing portion and the outer peripheral surface of the sub-core portion,
A first side first type terminal and a first side second type terminal formed on the first main surface side of the substrate core, one functioning as a power supply terminal, the other functioning as a ground terminal, and a first side signal terminal. A one-terminal array;
Second side first type terminal and second side second type terminal formed on the second main surface side of the substrate core and conducting to the first side first type terminal and second type terminal, respectively, and the first side signal terminal A second terminal array comprising a second side signal terminal conducting to
The first terminal array is formed in a positional relationship that overlaps with the projection region of the sub-core portion in the orthogonal projection onto the reference plane parallel to the plate surface of the substrate core,
The sub-core portion includes a first electrode conductor layer conducting to the first side first type terminal and the second side first type terminal, a dielectric layer, a first side second type terminal, and a second side second type. A multilayer capacitor in which a second electrode conductor layer conducting to a terminal is laminated in this order is incorporated, and
The sub-core housing part has a quadrilateral inner peripheral edge in a cross section by a plane parallel to the plate surface of the sub-core part, and a rounded part or a chamfered part having a dimension of 0.1 mm or more and 2 mm or less is formed at the corner part. It is characterized by becoming.

Similarly, the second is formed in a plate shape by a polymer material (including a material combined with a filler such as ceramic fibers and particles), and the thickness of the first main surface is reduced by reducing the thickness of the first main surface. The core body part having an opening formed in the core housing part, and a plate-like material made of a material having a smaller linear expansion coefficient than the core body part, are accommodated in the sub core housing part so that the thickness direction coincides with the core body part. A substrate core composed of the sub-core portion, and a filling and bonding layer made of a polymer material that fills a gap between the inner peripheral surface of the sub-core housing portion and the outer peripheral surface of the sub-core portion,
A first side first type terminal and a first side second type terminal formed on the first main surface side of the substrate core, one functioning as a power supply terminal, the other functioning as a ground terminal, and a first side signal terminal. A one-terminal array;
Second side first type terminal and second side second type terminal formed on the second main surface side of the substrate core and conducting to the first side first type terminal and second type terminal, respectively, and the first side signal terminal A second terminal array comprising a second side signal terminal conducting to
The first terminal array is formed in a positional relationship that overlaps with the projection region of the sub-core portion in the orthogonal projection onto the reference plane parallel to the plate surface of the substrate core,
The sub-core portion includes a first electrode conductor layer conducting to the first side first type terminal and the second side first type terminal, a dielectric layer, a first side second type terminal, and a second side second type. A multilayer capacitor in which a second electrode conductor layer conducting to a terminal is laminated in this order is incorporated, and
The sub-core housing portion is characterized in that an inner peripheral edge of a cross section formed by a plane parallel to the plate surface of the sub-core portion is composed only of a curved portion having an outwardly convex curvature radius of 0.1 mm or more.

  According to the above configuration, the sub-core portion made of a material having a smaller linear expansion coefficient than the core body made of a polymer material is disposed on the substrate so as to overlap the region of the first terminal array flip-chip connected to the semiconductor integrated circuit element side. Since it has a structure embedded in the core, the difference in coefficient of linear expansion between the terminals in the first terminal array and the semiconductor integrated circuit element side can be sufficiently reduced, resulting in significant disconnection due to thermal stress. Can be difficult. Further, since the sub-core portion corresponding to the second wiring board is embedded in the core body portion corresponding to the first wiring board, the overall connection structure between the semiconductor integrated circuit element using the wiring board and the main board is reduced. The height can be reduced and the connection man-hours can be reduced. Furthermore, a capacitor functioning as a decoupling capacitor (or a bypass capacitor) can be directly connected to the semiconductor element in the form of a wiring board, and the decoupling capacitor can be brought close to the semiconductor element. As a result, the wiring length between the power supply terminal and the decoupling capacitor can be shortened, and the inductance of the capacitor terminal portion can be reduced, which contributes to lowering the impedance of the decoupling capacitor. Further, since the decoupling capacitor is incorporated in the wiring board, it is not necessary to dispose the decoupling capacitor as a separate element on the back side of the main board, and the number of parts can be reduced or the apparatus can be downsized.

  By the way, in any configuration of the present invention, the sub-core portion and the core main body portion are filled and bonded made of a polymer material that fills the gap between the inner peripheral surface of the sub-core housing portion and the outer peripheral surface of the sub-core portion. Combined by layers. If the inner edge corners of the secondary core housing part are all formed at a right angle of 90 ° (so-called pin angle), the filled bonding layer filled here also has four corners at right angles along the secondary core housing part. Have. When the filling and bonding layer is filled in the sub-core housing portion with a liquid polymer material and solidified, fine bubbles may be formed in the vicinity of the protruding corner. In addition, cracks may occur in the vicinity of the protruding corners of the filled bonded layer during a heat cycle test or the like. If the above cracks or bubbles are generated, the adhesion between the sub-core part and the filling and bonding layer is lowered, and the wiring board is damaged, or the build-up resin insulation layer provided on the core body part and the sub-core part is hindered. There was a problem of coming.

  However, according to the first aspect of the present invention, a curved surface following the rounded surface of the sub-core housing portion or an inclined surface following chamfering is also formed at the protruding corner portion of the filling bonded layer. For this reason, bubbles are less likely to be formed in the polymer material in the vicinity of the protruding corner, and stress concentration can be avoided even when subjected to a temperature history, so that cracks and the like are less likely to occur. Therefore, the adhesion between the sub-core portion and the filling bonding layer is ensured, and problems such as inadvertent breakage of the wiring board or hindering the formation of the build-up resin insulating layer can be effectively prevented. In addition, when the dimension of the rounded portion or the chamfered portion (the radius of curvature in the former case, the chamfered dimension in the longitudinal direction of the side surface of the wiring substrate in the latter case) is less than 0.1 mm, the protruding corner portion of the filling bonded layer is too narrow, Air bubbles and cracks are likely to occur. On the other hand, when the dimension of the rounded portion or the chamfered portion exceeds 2 mm, the above-described problem prevention effect may be saturated.

  On the other hand, according to the second aspect of the present invention, the inner edge of the sub-core housing portion is composed only of a curved portion having an outwardly convex curvature radius of 0.1 mm or more, so that bubbles and the like are likely to remain in the filled bonded layer. Since corners are less likely to be formed, and stress concentration can be avoided even when subjected to a temperature history, cracks and the like are less likely to occur. Therefore, the adhesion between the sub-core portion and the filling bonding layer is ensured, and problems such as inadvertent breakage of the wiring board or hindering the formation of the build-up resin insulating layer can be effectively prevented. In the second aspect of the present invention, “the inner edge of the sub-core housing portion is composed only of a curved portion having an outwardly convex curvature radius of 0.1 mm or more” means that the configuration of the inner edge of the sub-core housing portion is It is equivalent to the fact that “curved part having a radius of curvature of less than 0.1 mm” is excluded from the element. The concept of “curved part with a radius of curvature of less than 0.1 mm” includes “pin corners with a radius of curvature of less than 0.1 mm”. In the second aspect of the present invention, it is particularly effective if the inner peripheral edge of the cross section of the sub-core housing portion is formed in a circular shape.

Hereinafter, requirements that can be commonly added to both the first and second aspects of the present invention will be described.
First, the sub-core portion can have a quadrilateral outer peripheral edge in a cross section formed by a plane parallel to the plate surface of the sub-core portion, and a corner portion or a chamfer having a dimension of 0.1 mm or more and 2 mm or less. The part can be formed. When the corner portion of the sub-core portion is a pin angle, when temperature history is applied, back stress from the sub-core portion tends to concentrate on the corner portion of the filling and bonding layer, and cracks are likely to occur. In addition, cracks are likely to occur in the filling bonded layer starting from the corner tip of the sub-core portion. However, by forming the rounded portion or the chamfered portion at the corner portion of the sub-core portion, the stress concentration on the corner portion of the filling and bonding layer can be further eased. In addition, it is possible to effectively suppress the occurrence of cracks starting from the corner tip of the sub-core portion.

  Next, the first terminal array can be formed in a positional relationship in which the whole is included in the projection region of the sub-core portion in the orthogonal projection onto the reference plane parallel to the plate surface of the substrate core. According to this configuration, since the sub-core portion whose size is adjusted to include the entire region of the first terminal array flip-chip connected to the semiconductor integrated circuit element side has a structure embedded in the substrate core, The difference in linear expansion coefficient from the semiconductor integrated circuit element side can be sufficiently reduced with respect to all the terminals in the one-terminal array, so that disconnection due to thermal stress can be further prevented. In addition, since the sub-core portion corresponding to the second wiring board is embedded in the core body portion corresponding to the first wiring board, the overall connection structure between the semiconductor integrated circuit element using the intermediate board and the main board is reduced. The height can be reduced and the connection man-hours can be reduced. Furthermore, a capacitor that functions as a decoupling capacitor (or a bypass capacitor) can be directly connected to the semiconductor element in the form of an intermediate substrate, and the decoupling capacitor can be brought close to the semiconductor element. As a result, the wiring length between the power supply terminal and the decoupling capacitor can be shortened, and the inductance of the capacitor terminal portion can be reduced, which contributes to lowering the impedance of the decoupling capacitor. Further, since the decoupling capacitor is incorporated in the intermediate board, it is not necessary to arrange the decoupling capacitor as a separate element on the back side of the main board, and the number of parts can be reduced or the apparatus can be downsized. The above effect is particularly remarkable when the sub-core portion is formed in the same area as the first terminal array or in a large area.

  The material of the sub-core part is not particularly limited as long as the linear expansion coefficient is smaller than that of the core body part. However, considering that the linear expansion coefficient of the polymer material is relatively high, it is possible to reduce the difference in linear expansion coefficient with the semiconductor integrated circuit element by making the sub core part a ceramic sub core part made of ceramic. This is advantageous in terms of achieving the effect more remarkably.

  In this case, 40-60 parts by weight of an inorganic ceramic filler such as alumina is added to alumina (7-8 ppm / ° C.) or glass ceramic (borosilicate glass or lead borosilicate glass) as the ceramic forming the ceramic sub-core part. It is a kind of composite material). The former has a particularly small linear expansion coefficient among various ceramics, and is excellent in the effect of reducing the difference in linear expansion coefficient with the semiconductor integrated circuit element to be connected. On the other hand, the latter is easy to be fired at a low temperature, and when forming a metal wiring part, a via, or the like, if necessary, a relatively low melting point high conductivity metal material mainly composed of Cu or Ag. There are advantages such as simultaneous firing.

In addition, the ceramic constituting the ceramic sub-core part has a Si component content of 68% by mass or more and 99% by mass or less in terms of SiO ₂ , and a cation component other than Si is SiO in a temperature range from room temperature to 200 ° C. The average linear expansion coefficient from 1 ppm / ° C. room temperature to 200 ° C. is adjusted to 1 ppm / ° C. or more and 7 ppm / ° C. or less by being composed of oxide-forming cations that form oxides having a linear expansion coefficient larger than _2. It can also be comprised with the oxide type glass material formed.

The linear expansion coefficient of the SiO ₂ in the temperature range up to 200 ° C. from room temperature 1 ppm / ° C. before and after the very small, the glass such as containing an oxide forming cation forming a large oxide coefficient of linear expansion than By constituting the sub-core portion with the material, the linear expansion coefficient of the glass material can be freely adjusted to an arbitrary value of 1 ppm / ° C. or more according to the type and content of the oxide-forming cation. As a result, the sub-core portion using the glass material can reduce the difference in linear expansion coefficient with the semiconductor integrated circuit element to be mounted as much as possible. The reliability of the terminal connection state can be greatly improved.

  When the semiconductor integrated circuit element to be connected is a Si semiconductor component, since the linear expansion coefficient of Si is around 3 ppm / ° C., the linear expansion coefficient of the oxide-based glass material is 1 ppm or more and 6 ppm or less, particularly 2 ppm. It is desirable to adjust to / ppm or more and 5 ppm / ° C or less. On the other hand, when the semiconductor integrated circuit element to be connected is a compound semiconductor component made of a III-V group compound lattice-matched with GaAs, the linear expansion coefficient of the semiconductor is about 5-6 ppm / ° C. It is desirable that the linear expansion coefficient is adjusted to 4 ppm / ° C. or more and 7 ppm / ° C. or less. In either case, thermal shear stress based on the difference in coefficient of linear expansion between the component and the substrate is less likely to act on the terminal connection structure with the semiconductor integrated circuit element mounted on the sub-core part, and connection breakage, etc. The probability of failure occurrence can be greatly reduced.

In this case, if the SiO ₂ content of the oxide glass material constituting the sub-core portion is less than 68% by mass, it is difficult to keep the linear expansion coefficient of the glass material at 7 ppm / ° C. The difference in linear expansion coefficient cannot be sufficiently reduced. When it exceeds 99% by mass, the glass melting point increases, and the production cost of glass of high quality glass with small residual bubbles and the like increases. Moreover, it may be difficult to ensure the linear expansion coefficient of the glass material to 1 ppm / ° C. or higher.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example in which an intermediate substrate (wiring substrate) 200 constituting an embodiment of the wiring substrate of the present invention is configured as an intermediate substrate disposed between a semiconductor integrated circuit element 2 and a main substrate 3. In the present embodiment, the first main surface of the plate-like member is a surface appearing on the upper side in the drawing, and the second main surface is a surface appearing on the lower side.

  The semiconductor integrated circuit element 2 has an element-side terminal array 4 including a plurality of signal terminals, a power supply terminal, and a ground terminal on the second main surface, and a first terminal array 5 formed on the first main surface of the intermediate substrate 200. On the other hand, it is flip-chip connected via the solder connection portion 6. On the other hand, the main substrate 3 is a mother board or an organic laminated package substrate forming a second-stage intermediate substrate, each of which is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers. The main board-side terminal array 8 made of metal pins is connected to the second terminal array 7 formed on the second main surface of the intermediate board 200 via the solder connection portion 6.

  As shown in FIG. 4, the intermediate substrate (wiring substrate) 200 is mainly formed of a polymer material in a plate shape, and the sub-core housing portion 100 h is formed in the first main surface so as to reduce its thickness. The substrate core 100 is composed of a core body portion 100m and a sub-core portion 1 that is configured in a plate shape with ceramic and is housed in the sub-core housing portion 100h so that the core body portion 100m and the thickness direction are aligned with each other. . On the first main surface side of the substrate core 100, a first side first type terminal 5a and a first side second type terminal 5b, one of which functions as a power supply terminal and the other functions as a ground terminal, and a first side signal terminal 5s. A first terminal array 5 is formed.

  The first terminal array 5 is formed and formed in a positional relationship that is entirely included in the projection region of the ceramic sub-core portion 1 in the orthogonal projection onto the reference plane parallel to the plate surface of the substrate core 100. Has been. That is, all of the first-side first-type terminal 5a, the first-side second-type terminal 5b, and the first-side signal terminal 5s are connected to the semiconductor integrated circuit element 2 (the element-side terminal array 4) on the ceramic sub-core portion 1. ) And flip chip bonding. As a result, for all the terminals in the first terminal array 5, the difference in linear expansion coefficient from the semiconductor integrated circuit element 2 side can be sufficiently reduced, so that disconnection due to thermal stress is hardly caused. Can do. In the intermediate substrate 200 of FIG. 4, the ceramic sub-core portion 1 has a larger area than the region where the first terminal array 5 is formed, and the thermal stress reduction effect is further enhanced.

  The core main body 100m is configured in a plate shape with, for example, a heat-resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like.

The constituent material of the ceramic layer 52 constituting the main part of the ceramic sub-core part 1 includes alumina (thermal expansion coefficient 7 to 8 ppm / ° C.), borosilicate glass or lead borosilicate glass and inorganic ceramics such as alumina. A glass ceramic added with 40 to 60 parts by weight of a filler or a low-temperature fired ceramic such as Bi ₂ O ₃ —CaO—ZnO—Nb ₂ O ₅ ceramic can be used. As other ceramic materials, aluminum nitride, silicon nitride, mullite, silicon dioxide, magnesium oxide, and the like can also be used. Further, if the ceramic sub-core portion 1 can satisfy the condition that the linear expansion coefficient is smaller than that of the core main body portion 100m, for example, a composite material of a polymer material and ceramic (for example, a ceramic material more than the core main body portion). It can also be composed of a composite material of a polymer material and a ceramic having a high weight content ratio. On the other hand, as a reference technique, the ceramic sub-core portion 1 can be replaced with a silicon sub-core portion from the viewpoint of a similar linear expansion coefficient with the semiconductor element.

On the other hand, the ceramic forming the ceramic sub-core portion can also be made of a glass material, for example, silica-based glass whose skeleton component is silica dioxide (silica). In this case, various glass additive components other than SiO ₂ can be blended in order to adjust physical properties suitable for use as a ceramic dielectric. From the viewpoint of enhancing the fluidity of the molten glass and suppressing bubble residuals, the glass material may contain alkali metal oxides such as Na ₂ O, K ₂ O or Li ₂ O, B ₂ O ₃ (boric acid) is effective. On the other hand, when an alkaline earth metal oxide such as BaO or SrO is added, the dielectric constant characteristics of the glass material can be improved. However, excessive addition tends to cause an increase in the linear expansion coefficient of the glass, and consequently an increase in the difference in linear expansion coefficient from the component side, which may lead to a connection failure due to thermal stress. Further, the increase in the glass softening point causes a significant decrease in fluidity, which may lead to problems such as residual bubbles.

In order to suppress the increase in the linear expansion coefficient of glass, it is effective to increase the content of the SiO ₂ component or to blend ZnO as a glass additive component. On the other hand, oxides of Ti, Zr, and Hf are effective in improving the water resistance of glass as well as improving the dielectric constant characteristics of glass. However, excessive addition causes a significant decrease in fluidity due to an increase in the glass softening point, which may cause problems such as residual bubbles.

The silica-based glass material (oxide-based glass material) has a Si component content of 68% by mass or more and 99% by mass or less in terms of SiO ₂ , and a cationic component other than Si has a temperature range from room temperature to 200 ° C. The average linear expansion coefficient from room temperature to 200 ° C. is formed by an oxide-forming cation that forms an oxide having a larger linear expansion coefficient than SiO ₂ (hereinafter referred to as “linear expansion coefficient adjusting oxide”). Is adjusted to 1 ppm / ° C. or more and 7 ppm / ° C. or less, so that the linear expansion coefficient of the glass material is changed according to the type and content of the oxide component (the linear expansion coefficient is larger than SiO ₂ ). It can be freely adjusted to an arbitrary value of 1 ppm / ° C. or higher. As a result, the ceramic sub-core part 1 can reduce the difference in linear expansion coefficient with the semiconductor component 2 to be mounted as much as possible. When the semiconductor integrated circuit element 2 is a Si semiconductor component (average linear expansion coefficient from room temperature to 200 ° C .: 3 ppm / ° C.), the linear expansion coefficient of the silica-based glass material is 1 ppm to 6 ppm, particularly 2 ppm / ° C. to 5 ppm. It is desirable to adjust to below / ° C. On the other hand, the semiconductor integrated circuit element 2 is a compound semiconductor component made of a III-V group compound lattice-matched with GaAs (for example, a GaAs-based next-generation high-speed CPU or MMIC (Monolithic).
In this case, the linear expansion coefficient of the semiconductor is about 5 to 6 ppm / ° C., so that the linear expansion coefficient of the silica-based glass material is adjusted to 4 ppm / ° C. or more and 7 ppm / ° C. or less. It is desirable that

Oxides having a larger linear expansion coefficient than SiO ₂ include alkali metal oxides (Na ₂ O, K ₂ O, Li ₂ O: 20 to 50 ppm / ° C.), alkaline earth metal oxides (BeO, MgO, CaO, Various examples such as SrO, BaO: 8 to 15 ppm / ° C., ZnO (6 ppm / ° C.), Al ₂ O ₃ (7 ppm / ° C.) can be exemplified. do it. The content of SiO ₂ is adjusted to 68% by mass or more and 99% by mass or less (preferably 80% by mass or more and 85% by mass or less) so that the linear expansion coefficient is within the above range, and the balance is the above. The linear expansion coefficient adjusting oxide can be used.

The following are specific examples of glass compositions that can be employed in the present invention:
SiO _2: 80.9 _{wt%, B} 2 O 3: 12.7 _{wt%, Al} 2 O 3: 2.3 _wt%, Na 2 O: 4.0 _wt%, K 2 O: 0.04 wt% , Fe ₂ O ₃ : 0.03 mass%
Softening point: 821 ° C., linear expansion coefficient (average value from 20 ° C. to 200 ° C.): 3.25 ppm / ° C.

  Next, the ceramic sub-core portion 1 is entirely configured as a multilayer ceramic capacitor in the present embodiment. The multilayer ceramic capacitor includes a first electrode conductor layer 54 electrically connected to the first side first type terminal 5a and the second side first type terminal 7a, a ceramic layer 52 serving as a dielectric layer, and a first side second type. A second electrode conductor layer 57 conducting to the terminal 5b and the second-side second-type terminal 7b is laminated in this order. In the present embodiment, the ceramic layer 52 is made of a high dielectric constant ceramic mainly composed of barium titanate (BaTiO3). In addition, perovskite complex oxides such as strontium titanate, calcium titanate, lead titanate and the like can be suitably used as the ceramic layer.

  In FIG. 4, specifically, the ceramic sub-core portion 1 includes a first electrode conductor layer 54 that is conductive to the first-type sub-core conductor 51a, and a second electrode conductor layer 57 that is conductive to the second-type sub-core conductor 51b. The fired multilayer ceramic capacitor is formed by alternately laminating the fired ceramic dielectric layers 52 that are fired simultaneously with the first electrode conductor layer 54 and the second electrode conductor layer 57. The ceramic sub-core portion 1 made of such a multilayer ceramic capacitor can be manufactured using a ceramic green sheet, and the first electrode conductor layer 54 and the second electrode conductor layer 57 can be formed by printing and applying a metal paste. . The electrode conductor layers 54 or 57 having the same polarity are connected in the stacking direction by sub-core conductors 51a and 51b forming vias, and the first electrode conductor layer 54 and the second electrode conductor layer 57 having different polarities are the first type. The sub-core conductor 51a and the second-type sub-core conductor 51b are galvanically separated by the through holes 56 and 58 formed in the electrode conductor layers 54 and 57 during the printing patterning of the metal paste. The capacitor functions as a decoupling capacitor connected in parallel to the power supply line of the semiconductor integrated circuit element 2 as shown in FIG.

  Next, on the second main surface side of the substrate core 100, a second-side first-type terminal 7a and a second-side second that are respectively connected to the first-side first-type terminal 5a and the first-side second-type terminal 5b. A second terminal array 7 including a seed terminal 7b and a second side signal terminal 7s that is electrically connected to the first side signal terminal 5s is formed. The first terminal array 5 is projected from the ceramic sub-core portion 1 in orthographic projection onto a reference plane parallel to the plate surface of the substrate core 100 (for example, can be set on the first main surface of the substrate core 100 itself). It is formed in a positional relationship in which the entire region is included. Note that a filling and bonding layer 55 made of a polymer material is formed in a space forming a gap between the ceramic sub-core portion 1 and the core main body portion 100m in the sub-core housing portion 100h. The filling bonding layer 55 fixes the ceramic sub-core portion 1 to the core main body portion 100m, and the difference in linear expansion coefficient between the ceramic sub-core portion 1 and the core main body portion 100m in the in-plane direction and the thickness direction itself. It plays a role of absorbing by elastic deformation of the.

  As shown in FIG. 3, in the first terminal array 5, the first-side first-type terminals 5 a and the first-side second-type terminals 5 b are arranged in an alternating grid pattern (or may be a staggered pattern). Similarly, also in the second terminal array 7, the second-side first-type terminals 7 a and the second-side second-type terminals 7 b are arranged in an alternating lattice shape (or staggered shape corresponding to the terminal arrangement of the first terminal array 5. Good). Each of the arrays 5 and 7 has a plurality of first-side signal terminals 5s and second-side signal terminals 7s in a form surrounding a grid-like arrangement of power supply terminals and ground terminals.

  In FIG. 4, the substrate core 100 includes a dielectric main layer 102 made of a polymer material and a surface for wiring, grounding or power supply, as well as the first main surface of the core body 100m and the first main surface of the ceramic sub-core unit 1. The first terminal array 5 is covered with a first wiring laminated portion 61 (so-called build-up wiring layer) in which conductor layers including conductors are alternately laminated, and the first main surface of the first wiring laminated portion 61 is covered. It is exposed and formed. According to this configuration, since the ceramic sub-core part 1 is collectively covered with the first wiring laminated part 61 together with the core main body part 100m, the first wiring laminated part 61 and the first terminal array 5 are generally built-up type organic. It can be formed in almost the same process as the package substrate, contributing to simplification of the manufacturing process.

  The second main surface of the substrate core 100 has a second wiring laminated portion 62 in which dielectric layers 102 made of a polymer material and conductor layers including wiring or ground or power supply surface conductors are alternately laminated. The second terminal array 7 is exposed and formed on the first main surface of the second wiring laminated portion 62.

In any of the wiring laminated portions 61 and 62, the dielectric layer 102 is formed as a build-up resin insulating layer made of a resin composition such as an epoxy resin with a thickness of, for example, 20 μm or more and 50 μm or less. In the present embodiment, the dielectric layer 102 is composed of an epoxy resin, and a dielectric filler made of SiO ₂ is blended at a ratio of 10% by mass to 30% by mass, and the relative dielectric constant ε is 2 to 4. (For example, about 3). In addition, the conductor layer is formed to have a thickness of, for example, 10 μm or more and 20 μm or less as a pattern plating layer (for example, an electrolytic Cu plating layer) on the dielectric layer 102 for both the wiring and the surface conductor. The conductor layer has a region where a part of the conductor is not arranged by patterning. In addition, the upper and lower dielectric layers may be in direct contact with each other in the conductor non-formation region.

  In FIG. 4, the second side first type terminal 7 a and the second side first type terminal 5 a of the second terminal array 7 correspond to the first side first type terminal 5 a and the first side second type terminal 5 b of the first terminal array 5. A first-type sub-core conductor 51a and a second-type sub-core conductor 51b that are respectively connected to the side second-type terminals 7b are formed in the thickness direction of the ceramic sub-core portion 1. The first-type sub-core conductor 51a and the second-type sub-core conductor 51b are connected to the first side first via via conductors 107 formed so as to penetrate the dielectric layers 102 of the first wiring laminated portion 61. Each is connected to the seed terminal 5a and the first-side second-type terminal 5b. By forming the ground and power supply conductors 51a and 51b in parallel in the ceramic sub-core portion 1, it is possible to reduce the inductance of the path for the ground and the power supply, and thus to reduce the impedance. The first-type sub-core conductor 51a and the second-type sub-core conductor 51b are both connected via the via conductor 107 to the second-side first-type surface conductor 211a and the second-side first conductor in the second wiring laminated portion 62. It is coupled to the second type conductor 211b. Furthermore, the second-side first-type terminal 7a and the second-side second-type terminal 7b of the second-terminal array 7 are connected to the second-side first-type surface conductor 211a and the second-side second-type surface conductor 211b. Each is connected.

  The ceramic sub-core portion 1 is fired by laminating a well-known ceramic green sheet containing a raw material powder of a constituent ceramic and a via hole formed by punching or laser drilling and filling a metal powder paste. Thus, the sub-core conductors 51a and 51b (and 51s described later) are formed as laminated vias.

  The via conductors 107 of the wiring laminated portions 61 and 62 are formed in the dielectric layer 102 by a photo via process (the dielectric layer 102 is made of a photosensitive resin composition, for example, an ultraviolet curable epoxy resin), or laser drilling. A via hole is formed by a known method such as a via process (dielectric layer 102 is made of a non-photosensitive resin composition), and the inside thereof is filled or covered with a via conductor such as plating. Each of the wiring laminated portions 61 and 62 is covered with a solder resist layer 101 made of a photosensitive resin composition so that the terminal arrays 5 and 7 are exposed.

  As shown in FIG. 3, in the first terminal array 5 (and the second terminal array 7), the first-side first-type terminal 5 a and the first-side second-type terminal 5 b are in the array inner region, and the first-side signal Terminals 5s are arranged in the array outer region. As shown in FIG. 4, in the first wiring laminated portion 61, the first-side signal for leading out the signal transmission path to the outside of the arrangement region of the ceramic sub-core portion 1 in a form that is electrically connected to the first-side signal terminal 5 s. A wiring 108 is provided. The end of the first signal wiring 108 is electrically connected to a signal through-hole conductor 109s formed in the thickness direction of the core body 100m so as to bypass the ceramic sub-core 1.

  The element-side terminal array 4 of the semiconductor integrated circuit element 2 has signal terminals 4s arranged at narrow intervals like the power supply and ground terminals 4a and 4b, and the signal terminals 4s located on the outer periphery of the array are: The distance in the in-plane direction to the corresponding second-side signal terminal 7s in the second terminal array formed on the back surface side of the intermediate substrate 200 also increases, and in many cases, it does not protrude outside the ceramic sub-core portion 1. I do not get. However, according to the above-described configuration, the element-side signal terminal 4s and the first-side signal terminal 5s that are solder-connected can be positioned directly above the ceramic sub-core portion 1 that has a remarkable linear expansion coefficient difference reduction effect. In addition, it is possible to form a conductive state without problems even for the second-side signal terminal 7s that is sufficiently far away.

  The through-hole conductor 109s formed in the core main body 100m has a larger axial cross-sectional diameter than the via conductor 107 formed in the wiring laminated portions 61 and 62. Such a through-hole conductor can be formed, for example, by drilling a through-hole with a drill or the like so as to penetrate the core body 100m in the thickness direction and covering the inner surface with a metal layer such as Cu plating. The inside of the through-hole conductor 109s is filled with a resin hole filling material 109f such as an epoxy resin. Furthermore, both end surfaces of the through-hole conductor 109s are sealed with a conductor pad 110. Further, when it is desired to achieve direct current separation between the via conductor 107 and the conductor pad 110 and the surface conductor such as the power supply layer and the ground layer, a hole 107i formed in the surface conductor is formed, and an annular shape is formed inside the hole 107i. The via conductors 107 or the conductor pads 110 may be arranged with a gap therebetween.

  In the intermediate substrate 200 of FIG. 4, the secondary core housing part 100h is configured to penetrate the core body 100m, and the ceramic secondary core part 62 is housed in the secondary core housing part 100h. 1 in contact with the second main surface. In this configuration, since the core body 100m mainly composed of a polymer material having a large linear expansion coefficient is excluded from the position of the ceramic sub-core portion 1, the linear expansion between the semiconductor integrated circuit element 2 and the intermediate substrate 200 is eliminated. The effect of reducing the coefficient difference can be achieved more remarkably.

  FIG. 13 schematically shows a cross section of the sub core housing part 100h and the sub core part 1 in a plane (SS) parallel to the plate surface of the sub core part 1 in the intermediate substrate 200 of FIG. . The gap between the inner peripheral surface of the sub core housing portion 100 h and the outer peripheral surface of the sub core portion 1 is filled with the above-described filling bonding layer 55. And the sub-core accommodating part 100h has the inner periphery by the said cross section having a quadrilateral shape, and the corner | angular part R of the dimension of 0.1 mm or more and 2 mm or less is formed in the corner | angular part. A curved surface that follows the rounded surface of the sub-core housing portion 100h is also formed at the protruding corner portion formed in the filling bonding layer 55 at a position corresponding to the corner portion. For this reason, bubbles are not easily formed in the polymer material in the vicinity of the protruding corner, and stress concentration can be avoided even when subjected to a temperature history, so that cracks and the like are less likely to occur. Instead of the rounded portion R, a chamfered portion T having a similar size range may be formed as shown in FIG. 13 and 14, the inner edge of the sub-core housing portion 100 h is formed such that each side portion other than the corner rounded portion R or chamfered portion T is linear. In addition, the formation of the rounded portion R or chamfered portion T of 0.1 mm or more and 2 mm or less exhibits the most remarkable effect of preventing air bubbles and cracks. When the thickness (the distance between the inner peripheral surface of the sub-core housing portion 100h and the outer peripheral surface of the sub-core portion 1 facing this in the rounded portion or the portion where the chamfered portion is not formed) is θ, This is a case where / L is adjusted to 0.040 or more and 0.090 or less (for example, θ = 0.8 mm, L = 12 mm, θ / L = 0.067). From the same viewpoint, the absolute value of the thickness θ is set to 0.50 mm or more and 2.00 mm or less, desirably 0.75 mm or more and 1.50 mm or less, more desirably 0.75 mm or more and 1.25 mm or less. It is good.

  The inner edge shape of the sub-core housing part 100h can also be formed as shown in FIG. That is, each corner is formed with a rounded portion R having a dimension of 0.1 mm or more and 2 mm or less, and each remaining side portion is an outwardly convex curved portion B having a larger radius of curvature than the rounded portion. It has become. That is, the sub-core housing part 100h is composed only of a curved part having an outwardly convex curvature radius of 0.1 mm or more, with an inner peripheral edge of a cross section formed by a plane parallel to the plate surface of the sub-core part 1. This configuration also brings about the effect of suppressing bubble remaining and crack generation. Further, as shown in FIG. 16, the effect is further enhanced if the inner peripheral edge C of the cross-section of the sub-core housing portion 100h is circular.

  The results of experiments conducted to confirm the above effects will be described. A test product of the intermediate substrate (wiring substrate) 200 having the structure shown in FIG. 4 was produced in the following configuration. First, the core main body portion 100m was set to (a substrate on which copper foil was pasted on both sides of a glass fiber reinforced epoxy resin), and the thickness was set to (0.87) mm. The dimension u of one side of the sub core housing part 100h was variously set in the range of 13.5 mm to 15 mm. Moreover, the magnitude | size of the radius formed in each corner | angular part was made into 2 levels, 0.5 mm and 1.5 mm. On the other hand, the ceramic sub-core portion 1 was a sintered product (alternate laminate of barium titanate and nickel electrodes) having dimensions of 12 mm × 12 mm (0.87) mm. Each corner was formed by chamfering various values of chamfered portions t of 0.311 mm to 1.174 mm with a cutting machine.

  The ceramic sub-core portion 1 as described above was placed in the sub-core housing portion 100h, and the (epoxy) resin was filled in the gap between the two as a filling bonding layer 55 and cured to obtain a test product. By adjusting the gap, the formation wall thickness θ of the filling and bonding layer 55 was set to various values of 0.75 mm or more and 1.50 mm or less. A thermal shock test defined in US MIL standard 883D is performed on these test products for 90 cycles under the condition C of the standard, and cracks are formed in the corners of the sub-core housing portion 100h and the ceramic sub-core portion 1. It was confirmed whether or not this occurred. And the dimension of the chamfered part on the ceramic sub-core part 1 side is classified into three levels of less than 0.1 mm, 0.1 mm or more and less than 0.6 mm, and 0.6 mm or more, and the number of test products in which cracks occurred. The ratio (the total number of test samples was 7 to 10 for each level) was determined. As a result, a test product in which cracks occurred at the corners of the secondary core housing part 100h was not recognized. On the other hand, for the corners of the ceramic sub-core part 1, excellent (ク ラ ッ ク) when no cracks were observed for all the test products, good (◯) if there was even one test product with no cracks, Although cracks did not occur at the corners of the sub-core housing part 100h, when cracks were found at all corners of the ceramic sub-core part 1, it was determined as acceptable (Δ). The above results are shown in Tables 1 to 3.

  As a result of the above, by setting the chamfering amount formed at the corner of the ceramic sub-core part 1 to 0.1 mm or more, particularly 0.6 mm or more, cracks starting from the corner of the ceramic sub-core part 1 are effective. It can be seen that it can be suppressed.

  Moreover, in any structure of FIGS. 13-16, although the outer periphery of the cross section by the plane parallel to the plate | board surface of the subcore part 1 is a quadrilateral shape, and a corner | angular part is a pin angle | corner shape, As shown by a one-dot chain line, a rounded portion r having a dimension of 0.1 mm or more and 2 mm or less can be formed at a corner portion of the sub-core portion 1. As a result, the stress concentration at the corners (protruding corners) of the filling and bonding layer 55 can be further alleviated. In addition, the occurrence of cracks in the filling and bonding layer 55 starting from the corners of the sub-core part 1 can also be suppressed. As shown by broken lines in each drawing, a chamfered portion t having the same size range may be formed instead of the rounded portion r, and the same effect can be achieved. The effect of suppressing the occurrence of cracks starting from the corners of the sub-core part 1 is most noticeable when θ / L is adjusted to 0.040 or more and 0.090 or less. From the same viewpoint, the absolute value of the thickness θ is preferably set to 0.75 mm to 1.50 mm, and more preferably 0.75 mm to 1.25 mm.

Furthermore, the outer edge shape of the sub-core part 1 can also be formed as shown in FIG. In other words, round portions r having dimensions of 0.1 mm or more and 2 mm or less are formed at the respective corners, but the remaining side portions are curved portions B ′ having outwardly convex curvatures larger than the round portions. It has become. That is, the sub-core portion 1 is composed only of a curved portion having a radius of curvature of 0.1 mm or more whose outer peripheral edge in a cross section formed by a plane parallel to the plate surface of the sub-core portion 1 is convex outward. This configuration also brings about the effect of suppressing bubble remaining and crack generation. Furthermore, as shown in FIG. 18, if the cross-sectional inner peripheral edge C of the sub-core part 1 is circular, the effect is further enhanced.
If the peripheral edge C is circular, the effect is further enhanced.

  Hereinafter, various modifications of the wiring board of the present invention will be described. In the following configuration, parts that are configured in the same manner as the intermediate substrate 200 of FIG. 4 are given common reference numerals, and detailed description thereof is omitted. First, the intermediate substrate (wiring substrate) 300 in FIG. 5 is configured such that the sub-core housing portion 100h is a bottomed concave portion that opens on the first main surface of the core main body portion 100m. The second wiring laminated portion 62 is formed in contact with the second main surface of the core body portion 100m on the back side of the concave portion. This structure has an advantage that the flat second wiring laminated portion 62 can be more easily formed because the ceramic sub-core portion 1 is not exposed on the second main surface side of the core main body portion 100m. Specifically, a bottom through-hole conductor portion 209 that is electrically connected to each terminal of the second terminal array 7 is formed so as to penetrate the portion of the core main body portion 100m that forms the bottom portion of the sub-core housing portion 100h. The sub-core conductors 51 a and 51 b formed in the core part 1 are electrically connected to the bottom through-hole conductor part 209. More specifically, the pad 80 on the bottom through-hole conductor portion 209 side and the pad 70 on the sub core conductor side are flip-chip connected via the solder connection portion 6 ′. About the cross-sectional shape of the subcore part 1 and the subcore accommodating part 100h, the thing similar to what was demonstrated using FIGS. 13-16 is employable.

  Next, in the intermediate substrate (wiring substrate) 400 of FIG. 6, the first side first type terminal 5 a and the first side second type terminal 5 b constituting the first terminal array 5 are the first main of the ceramic sub-core portion 1. It is exposed on the surface. Further, the second side first type terminal 7a and the second side second corresponding to the first side first type terminal 5a and the first side second type terminal 5b of the first terminal array 5 and the second terminal array 7. A first-type sub-core conductor 51a and a second-type sub-core conductor 51b that respectively conduct to the seed terminal 7b are formed in the thickness direction of the ceramic sub-core portion 1. According to this configuration, the first wiring laminated portion 61 mainly composed of a polymer material is excluded from the first main surface of the ceramic sub-core portion 1, and the semiconductor integrated circuit element 2 and the ceramic sub-core portion 1 are connected to the solder connection portion. 6 is directly connected. Thereby, the reduction effect of the linear expansion coefficient difference between the semiconductor integrated circuit element 2 and the intermediate substrate 200 is further improved. Further, since the wiring that conducts to the terminal is not routed immediately above the ceramic sub-core portion 1, it is possible to reduce the inductance of the transmission path that conducts to the terminal, and thus to reduce the impedance. In the intermediate substrate (wiring substrate) 600 of this embodiment, the first side wiring laminated portion is not formed. About the cross-sectional shape of the subcore part 1 and the subcore accommodating part 100h, the thing similar to what was demonstrated using FIGS. 13-16 is employable.

  On the other hand, in the intermediate substrate (wiring substrate) 500 of FIG. 7, the outer peripheral edge portion of the first main surface of the ceramic sub-core portion 1 together with the first main surface of the core body portion 100m is a dielectric layer made of a polymer material. 102 and a first wiring laminated portion 61 in which wirings or conductor layers including ground or power supply surface conductors are alternately laminated. The first side signal terminal 5 s is formed so as to be exposed on the surface of the first wiring laminated portion 61. A first signal wiring 108 is provided in the first wiring laminated portion 61 so as to be electrically connected to the first side signal terminal 5s. The first signal wiring 108 leads the signal transmission path outside the arrangement region of the ceramic sub-core portion 1. Yes. The end of the first signal wiring 108 is electrically connected to a signal through-hole conductor 109s formed in the thickness direction of the core body 100m so as to bypass the ceramic sub-core 1. This configuration can be said to be advantageous when the distance between the terminals of the first terminal array 5 is small because the wiring that conducts to the signal terminals on the outer periphery of the array can be drawn largely in and out of the plane. About the cross-sectional shape of the subcore part 1 and the subcore accommodating part 100h, the thing similar to what was demonstrated using FIGS. 13-16 is employable.

  In each of the above embodiments, the sub-core portion 1 is formed to have a larger area than the semiconductor integrated circuit element 2. However, the sub-core portion 1 has substantially the same area as the projection region of the semiconductor integrated circuit element 2. It can also be formed. Further, as in the intermediate substrate 600 of FIG. 8, it is possible to configure the sub-core portion 1 to have a smaller area than the semiconductor integrated circuit element 2 while accommodating the entire first terminal array 5 in the region of the sub-core portion 1. It is. In addition, when the influence on the connection state of the solder connection portion 6 at the terminal located on the outer periphery of the semiconductor integrated circuit element 2 is not so much concerned, the first terminal array as shown in the intermediate substrate (wiring substrate) 700 in FIG. It is not impossible to make the sub-core part 1 smaller in area than the area of 5. About the cross-sectional shape of the subcore part 1 and the subcore accommodating part 100h, the thing similar to what was demonstrated using FIGS. 13-16 is employable.

  Further, the intermediate substrate (wiring substrate) 800 of FIG. 10 forms a capacitor using only a part of the ceramic layer 52 included in the sub-core portion 1, and the remaining ceramic layer 52 is replaced with a sub-core main body not including the capacitor. This is an example of 1M. In any case, the cross-sectional shapes of the sub-core portion 1 and the sub-core housing portion 100h can be the same as those described with reference to FIGS.

  An intermediate substrate (wiring substrate) 900 in FIG. 11 is a further development of the intermediate substrate 800 in FIG. 10, and the multilayer capacitor is a thin film capacitor unit 10 formed on the main surface of the ceramic sub-core unit 1M. It is. The thin film capacitor unit 10 includes a plurality of dielectric thin films 13 (dielectric layers) and a plurality of electrode conductor thin films 14 and 17 (first electrode conductor layer 14 and second electrode conductor layer 17) that are alternately stacked. It has been done. The electrode conductor thin films 14 and 17 are composed of a first type electrode conductor thin film 14 that conducts to the first side first kind terminal 5a and a second type electrode conductor thin film 17 that conducts to the first side second kind terminal 5b. They are alternately arranged in the stacking direction in a form separated by the body thin film 13. The total area is expanded by multilayering the electrode conductor thin films 14 and 17 and, in combination with the thinning effect of each dielectric layer, the achievable capacitance is greatly increased even if the element size is small. Can do. About the cross-sectional shape of the subcore part 1 and the subcore accommodating part 100h, the thing similar to what was demonstrated using FIGS. 13-16 is employable. In FIG. 11, the electrode conductor thin films 14 and 17 appear to be divided in the in-plane direction with the illustration of the through holes 16 and 18, but in actuality, in the portions other than the through holes 16 and 18 as shown in FIG. A continuous thin film is formed in the inward direction. The same applies to the dielectric thin film 13 (this structure is the same for the fired capacitor 1 of FIGS. 4 to 11).

  The thickness of the dielectric thin film 13 is, for example, not less than 10 nm and not more than 1000 nm, and more preferably not less than 30 nm and not more than 500 nm. On the other hand, the thickness of the electrode conductor thin films 14 and 17 is, for example, not less than 10 nm and not more than 500 nm, and more preferably not less than 50 nm and not more than 500 nm. The electrode conductor thin films 14 and 17 and the coupling conductor portions 15 and 19 (each conducting to the first-type sub-core conductor 51a and the second-type sub-core conductor 51b of the sub-core portion 1) are, for example, Cu, Ag, Au, or It can be composed of a metal such as Pt, and is formed by a vapor deposition method such as sputtering or vacuum vapor deposition. In this embodiment, it is formed by vacuum vapor deposition. On the other hand, the dielectric thin film 13 is made of an inorganic dielectric such as oxide or nitride, and is formed by a vapor deposition method such as high frequency sputtering, reactive sputtering, or chemical vapor deposition (CVD). Is done. In this embodiment, the dielectric thin film 13 is a composite oxide having a perovskite crystal structure, for example, an oxide thin film composed of one or more of barium titanate, strontium titanate and lead titanate. The sol-gel method is used.

The side surface schematic diagram which shows an example of the usage condition of the intermediate board (wiring board) of this invention. The equivalent circuit diagram which shows an example of the usage condition of the decoupling capacitor for integrated circuits. The top view which shows an example of the arrangement | positioning form of the 1st terminal array of the intermediate | middle board | substrate of FIG. The cross-sectional schematic diagram which shows 1st embodiment of the intermediate substrate of this invention. The cross-sectional schematic diagram which similarly shows 2nd embodiment. The cross-sectional schematic diagram which similarly shows 3rd embodiment. The cross-sectional schematic diagram which similarly shows 4th embodiment. The cross-sectional schematic diagram which similarly shows 5th embodiment. The cross-sectional schematic diagram which similarly shows 6th embodiment. The cross-sectional schematic diagram which similarly shows 7th embodiment. The cross-sectional schematic diagram which similarly shows 8th embodiment. The schematic diagram which illustrates and illustrates the plane form of the electrode conductor layer of the capacitor | condenser integrated in the intermediate board | substrate. The schematic diagram which shows the 1st example of the cross-sectional shape of a subcore accommodating part and a subcore part. The schematic diagram which similarly shows a 2nd example. The schematic diagram which similarly shows a 3rd example. The schematic diagram which similarly shows a 4th example. The schematic diagram which similarly shows a 5th example. The schematic diagram which similarly shows a 6th example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ceramic sub core part 5 1st terminal array 5a 1st side 1st class terminal 5b 1st side 2nd class terminal 5s 1st side signal terminal 7 2nd terminal array 7a 2nd side 1st class terminal 7b 2nd side 2nd Type 2 terminal 10 Thin film capacitor 14 Type 1 electrode conductor thin film (first electrode conductor layer)
17 Second kind electrode conductor thin film (second electrode conductor layer)
51a First-type sub-core conductor 51b Second-type sub-core conductor 52 Ceramic layer 53 Filling and bonding layer R, r round portion T, t Chamfered portion 54 First electrode conductor layer 57 Second electrode conductor layer 61 First wiring laminated portion 100 Substrate core 100h Sub core housing portion 100m Core body portion 102 Dielectric layer 107 Via conductor 108 First-side signal wiring 109a First-type through-hole conductor 109b Second-type through-hole conductor 109s Signal through-hole conductor 200, 300, 400 , 500, 600, 700, 800, 900 Intermediate substrate

Claims (17)

It is composed of a polymer material in a plate shape, and a core main body portion in which a sub core housing portion is formed in the form of reducing its thickness on the first main surface, and a material having a smaller linear expansion coefficient than the core main body portion. A substrate core that is configured in a plate shape and is accommodated in the sub core housing portion so that the core main body portion and the thickness direction coincide with each other, an inner peripheral surface of the sub core housing portion, and the sub core portion A filling and bonding layer made of a polymer material that fills a gap with the outer peripheral surface of the core portion;
Formed on the first main surface side of the substrate core, one is a power supply terminal, the other functions as a ground terminal, a first side first type terminal and a first side second type terminal, and a first side signal terminal A first terminal array;
A second side first type terminal and a second side second type terminal formed on the second main surface side of the substrate core and respectively conducting to the first side first type terminal and the second type terminal; A second terminal array comprising a second side signal terminal conducting to the side signal terminal;
In the orthographic projection onto the reference plane parallel to the plate surface of the substrate core, the first terminal array is formed in a positional relationship overlapping with the projection region of the sub-core portion,
The sub-core portion includes a first electrode conductor layer conducting to the first-side first-type terminal and the second-side first-type terminal, a dielectric layer, the first-side second-type terminal, and the first A multilayer capacitor in which a second electrode conductor layer conducting to the second-side second-type terminal is laminated in this order is incorporated, and
The sub-core housing portion has a quadrilateral inner periphery in a cross section by a plane parallel to the plate surface of the sub-core portion, and a rounded portion or a chamfered portion having a dimension of 0.1 mm or more and 2 mm or less is formed at a corner portion thereof. A wiring board characterized by being made. It is composed of a polymer material in a plate shape, and a core main body portion in which a sub core housing portion is formed in the form of reducing its thickness on the first main surface, and a material having a smaller linear expansion coefficient than the core main body portion. A substrate core that is configured in a plate shape and is accommodated in the sub core housing portion so that the core main body portion and the thickness direction coincide with each other, an inner peripheral surface of the sub core housing portion, and the sub core portion A filling and bonding layer made of a polymer material that fills a gap with the outer peripheral surface of the core portion;
Formed on the first main surface side of the substrate core, one is a power supply terminal, the other functions as a ground terminal, a first side first type terminal and a first side second type terminal, and a first side signal terminal A first terminal array;
A second side first type terminal and a second side second type terminal formed on the second main surface side of the substrate core and respectively conducting to the first side first type terminal and the second type terminal; A second terminal array comprising a second side signal terminal conducting to the side signal terminal;
In the orthographic projection onto the reference plane parallel to the plate surface of the substrate core, the first terminal array is formed in a positional relationship overlapping with the projection region of the sub-core portion,
The sub-core portion includes a first electrode conductor layer conducting to the first-side first-type terminal and the second-side first-type terminal, a dielectric layer, the first-side second-type terminal, and the first A multilayer capacitor in which a second electrode conductor layer conducting to the second-side second-type terminal is laminated in this order is incorporated, and
The wiring board according to claim 1, wherein the sub-core housing portion includes only a curved portion having an outwardly convex curvature radius of 0.1 mm or more, with an inner peripheral edge of a cross section formed by a plane parallel to the plate surface of the sub-core portion. The wiring board according to claim 2, wherein the sub-core housing portion has an inner peripheral edge of the cross section formed in a circular shape. The sub-core part has a quadrilateral outer peripheral edge in a plane parallel to the plate surface of the sub-core part, and a rounded part or a chamfered part having a dimension of 0.1 mm to 2 mm is formed at the corner. The wiring board according to any one of claims 1 to 3. The sub-core portion is composed only of a curved portion having an outwardly convex curvature radius of 0.1 mm or more, with an outer peripheral edge of a cross section formed by a plane parallel to the plate surface of the sub-core portion. The wiring board according to claim 1. The wiring board according to claim 5, wherein the sub-core portion has an outer peripheral edge of the cross section formed in a circular shape. The first terminal array is formed in a positional relationship in which the first terminal array is entirely included in a projection region of the sub-core portion in an orthogonal projection onto a reference plane parallel to a plate surface of the substrate core. The wiring board according to claim 6. The substrate core includes a first main surface of the core main body portion and a first main surface of the sub-core portion including a dielectric layer made of a polymer material, and a conductor layer including a wiring or ground or power supply surface conductor. 8. The method according to claim 1, wherein the first terminal array is exposed on the first main surface of the first wiring laminated portion. The wiring board according to item 1. Corresponding to the first side first type terminal and the first side second type terminal of the first terminal array, and to the second side first type terminal and the second side second type terminal of the second terminal array The first-type sub-core conductor and the second-type sub-core conductor that are respectively conductive are formed in the thickness direction of the sub-core portion, and the first-type sub-core conductor and the second-type sub-core conductor are connected to the first wiring. The wiring board according to claim 8, wherein the wiring board is electrically connected to the first-side first-type terminal and the first-side second-type terminal via via conductors formed so as to penetrate the dielectric layers of the laminated portion. In the first terminal array, the first-side first-type terminals and the first-side second-type terminals are arranged in the array inner area, and the first-side signal terminals are arranged in the array outer area, respectively.
A first signal wiring is provided in the first wiring laminated portion so as to be electrically connected to the first signal terminal, and a first signal wiring is provided outside the arrangement region of the sub core portion to draw a signal transmission path. 10. The wiring board according to claim 8, wherein an end of the wiring is electrically connected to a signal through-hole conductor formed in a thickness direction of the core main body so as to bypass the sub-core. The first side first type terminal and the first side second type terminal constituting the first terminal array are exposed and formed on the first main surface of the sub-core portion, and the first terminal array includes the first terminal array. A first-type sub-core conductor corresponding to the first-type first terminal and the first-type second-type terminal and conducting to the second-type first-type terminal and the second-side second-type terminal of the second terminal array, respectively. The wiring board according to claim 1, wherein the second-type sub-core conductor is formed in a thickness direction of the sub-core portion. The outer peripheral edge portion of the first main surface of the sub-core portion together with the first main surface of the core main body portion, a dielectric layer made of a polymer material, and a conductor layer including a wiring or ground or power surface conductor And is covered with the laminated first wiring laminated portion, and the first signal terminal is formed in a form exposed on the surface of the first wiring laminated portion,
A first signal wiring is provided in the first wiring laminated portion so as to be electrically connected to the first signal terminal, and a first signal wiring is provided outside the arrangement region of the sub core portion to draw a signal transmission path. 12. The wiring board according to claim 11, wherein an end of the wiring is electrically connected to a signal through-hole conductor formed in a thickness direction of the core main body so as to bypass the sub-core. The wiring board according to any one of claims 1 to 12, wherein the sub-core portion is formed in a size equal to or larger than a formation region of the first terminal array. The wiring board according to claim 1, wherein the sub-core portion is a ceramic sub-core portion made of ceramic. The wiring board according to claim 14, wherein the ceramic forming the ceramic sub-core portion is made of alumina or glass ceramic. The wiring board according to claim 1, wherein the multilayer capacitor is a fired multilayer ceramic capacitor. The wiring board according to claim 1, wherein the multilayer capacitor is a thin film capacitor formed on a main surface of the ceramic sub-core portion.

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