JP2005191307A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high reliability wiring board, in which stripping is unlikely to take place between a core substrate and a build-up resin insulating layer. <P>SOLUTION: In the wiring board 1, where resin insulation layers 7 and 9 and conductor layers 8 and 10 are laid in layers on a core substrate 2 principally comprising ceramic, following relations are satisfied: the linear expansion coefficient α of the core substrate 2 in the temperature range of -55°C to 125°C is between 3-20 ppm/°C, the linear expansion coefficient β of the build-up resin insulation layer 7 contiguous with the core substrate 2 is between 5-30 ppm/°C, and 0.5≤β/α≤1.5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wiring board. In particular, the present invention relates to a wiring board in which a resin insulating layer and a conductor layer are built up on a ceramic core board.

  Conventionally, for example, as a package substrate for mounting an integrated circuit chip, there are roughly classified an organic wiring substrate and a ceramic wiring substrate. In recent years, in the field of organic wiring substrates, a build-up method in which a resin insulating layer and a conductor layer are formed one by one on a core substrate is becoming mainstream. The build-up method is advantageous for finer wiring and has excellent productivity. On the other hand, ceramic wiring boards have advantages over organic wiring boards, such as excellent high frequency characteristics and heat dissipation.

In recent years, development of a wiring board having a structure that can make use of the characteristics of both, that is, a wiring board in which a resin insulating layer and a conductor layer are formed on a ceramic core board by a build-up method has been promoted (for example, Patent Document 1) below.
JP 2001-284805 A

  By the way, a wiring board having a multilayer structure is required not to cause peeling or cracking between layers when heating and cooling are repeated. Of course, such a reliability problem extends to a wiring board in which a resin insulating layer (hereinafter also referred to as a build-up resin insulating layer) and a conductor layer are formed on a ceramic core substrate. In a ceramic wiring board, since all the layers are laminated and fired simultaneously, the problem of delamination between layers hardly occurs. Further, in the organic wiring substrate, since the core substrate is also made of a resin, the adhesion between the core substrate and the build-up resin insulating layer can be relatively easily ensured.

  However, in a wiring board in which a build-up resin insulation layer is formed on a ceramic core board, peeling is likely to occur between the core board and the build-up resin insulation layer. Therefore, preventing peeling between the core substrate and the build-up resin insulation layer is an urgent need for improving the reliability of the product.

  An object of the present invention is to provide a highly reliable wiring board in which peeling between a ceramic core substrate and a build-up resin insulating layer hardly occurs.

Means for Solving the Problems and Effects of the Invention

  In order to solve the above-described problems, the present invention provides a wiring board in which a resin insulating layer and a conductor layer are laminated on a core board, the core board is mainly composed of ceramic, and is in a temperature range of −55 ° C. or more and 125 ° C. or less. The linear expansion coefficient α of the core substrate is 3 ppm / ° C. or more and 20 ppm / ° C. or less, the linear expansion coefficient β of the resin insulating layer adjacent to the core substrate is 5 ppm / ° C. or more and 30 ppm / ° C. or less, and 0.5 ≦ β / The main feature is that α ≦ 1.5 is satisfied.

  According to the present invention, the linear expansion coefficient α of the core substrate and the linear expansion coefficient β of a resin insulating layer (hereinafter also referred to as “build-up resin insulating layer”) on the core substrate are close to each other. The main cause of peeling of the buildup resin insulation layer is that when the wiring board is heated and cooled, it is pulled near the interface between the core board and the buildup resin insulation layer based on the difference in linear expansion coefficient, compression, etc. It is thought that this is due to the generation of stress. The present inventors investigated in detail the presence or absence of delamination in a thermal cycle test for test products made of various materials having different linear expansion coefficients. When the linear expansion coefficient satisfies the above relationship, delamination occurred extremely. I learned that it was difficult. As a result, the present invention has been completed. That is, the composition and the like of the ceramic and the buildup resin insulation layer are adjusted so that the linear expansion coefficient α of the core substrate and the linear expansion coefficient β of the buildup resin insulation layer satisfy the above relationship. By doing so, it is possible to easily manufacture a highly reliable wiring board in which peeling between the core substrate and the build-up resin insulating layer hardly occurs.

  In one preferable aspect, the core substrate is electrically connected to the surface conductor covering a part on the first main surface, the back conductor covering a part of the second main surface, and both the surface conductor and the back conductor. A via conductor, and the front conductor, the back conductor and the via conductor are made of one kind of metal selected from the group of highly conductive metals made of Cu, Cu alloy, Au, Ni, Ag and Ag alloy, and ceramic. Is composed of a low-temperature fired ceramic. The low-temperature fired ceramic is suitable because the conductor layer can be composed of the above-described highly conductive metal.

  The above-mentioned resin insulation layer is mainly composed of an epoxy resin or a polyimide resin mixed with an inorganic filler, and is composed of a material whose linear expansion coefficient β is adjusted within a range of 5 ppm / ° C. to 30 ppm / ° C. It is preferable to consider the linear expansion coefficient matching with the ceramic. Epoxy resins and polyimide resins have a sufficient track record and are excellent in reliability. In addition, the material cost is low.

  For the same reason, the resin insulating layer can be made of a material mainly composed of a liquid crystal polymer and having a linear expansion coefficient β adjusted within a range of 5 ppm / ° C. to 10 ppm / ° C. Further, for the same reason, the resin insulation layer can be composed of a material whose resin insulation layer is mainly composed of a fluororesin and whose linear expansion coefficient β is adjusted within a range of 10 ppm / ° C. or more and 20 ppm / ° C. or less. .

  In the present specification, unless otherwise specified, the linear expansion coefficient indicates a linear expansion coefficient in the temperature range of −55 ° C. or more and 125 ° C. or less and in the in-plane direction of the substrate. In addition, “mainly” or “including as a main body” means containing the largest amount by mass%. In addition, the core substrate includes conductors such as via conductors and surface conductors, and the coefficient of thermal expansion slightly changes depending on the thickness of the conductor. The coefficient of linear expansion of the substrate.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 schematically shows a cross-sectional structure of a wiring board 1 according to an embodiment of the present invention. The wiring substrate 1 includes a core substrate 2 having a multilayer structure in which ceramic dielectric layers 50, 51, 52 and conductor layers 60, 61, 62, 63 are alternately stacked, and a first main surface CP of the core substrate 2. On the side, a build-up wiring laminated portion 3 disposed on the core substrate 2 is provided. The buildup wiring laminated portion 3 includes buildup resin insulation layers 7 and 9 and conductor layers 8 and 10.

  The core substrate 2 is provided with a plurality of via conductors 4 conducting the conductor layers 60 to 63 so as to penetrate each of the ceramic dielectric layers 50 to 52 in the thickness direction. These via conductors 4 provide electrical connection between layers. The conductor layer 60 on the second main surface DP side of the core substrate 2 has the mounting pins 14 brazed with a brazing material 16 (including solder), and serves as a mounting pad for electrical connection with another mounting substrate or the like. It's being used. Further, as shown in the figure, a passive element such as a chip capacitor 18 may be mounted on the core substrate 2 with brazing materials 20 and 20. In the present embodiment, a single-sided wiring board in which a resin insulating layer and a conductor layer are laminated only on one side of the core substrate 2 is shown, but a resin insulating layer and a conductor layer can be laminated on both sides of the core substrate 2. .

  The first buildup resin insulation layer 7 is disposed so as to cover the first main surface CP of the core substrate 2 and has a portion in contact with the ceramic dielectric layer 52 and a portion in contact with the conductor layer 63. Further, a conductor layer 8 is formed on the main surface of the first buildup resin insulation layer 7 by Cu plating. The conductor layer 8 and the conductor layer 63 of the core substrate 2 are connected to each other by a via 34. The via 34 in FIG. 1 shows a filled via in which the hole is filled with Cu plating. However, conformal vias in which Cu plating is applied only to the inner walls of the holes can also be employed.

  A second buildup resin insulation layer 9 is further provided on the conductor layer 8. The second buildup resin insulation layer 9 can be composed of a resin composition having the same composition as the first buildup resin insulation layer 7. On the main surface of the second buildup resin insulation layer 9, a conductor layer 10 is further formed by Cu plating. Part or all of the conductor layer 10 is used as a metal terminal pad. The conductor layer 8 and the conductor layer 10 disposed above and below the second buildup resin insulation layer 9 are connected to each other by filled vias 34 penetrating the second buildup resin insulation layer 9 vertically.

  The second buildup resin insulation layer 9 is covered with a solder resist layer SR1 having an opening so that the conductor layer 10 is exposed. The conductor layer 10 exposed from the opening of the solder resist layer SR1 is subjected to Ni / Au plating, Sn-Pb eutectic solder, Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Sb, etc. Solder bumps 11 made of solder substantially containing no Pb are provided. A similar solder resist layer SR2 is formed on the second main surface DP side of the core substrate 2.

  Build-up resin insulation layers 7 and 9 and solder resist layers SR1 and SR2 are manufactured, for example, as follows. That is, a photosensitive adhesive film obtained by forming a photosensitive resin composition varnish into a film is laminated, and a transparent mask (for example, a glass mask) having a pattern corresponding to the via 34 is overlaid and exposed. The film portion other than the via 34 is cured by this exposure, while the via 34 portion remains uncured, so if it is removed by dissolving it in a solvent, the via 34 can be easily formed in the desired pattern. (So-called photovia process). Note that a laser via process of drilling with a laser may be employed instead of the photo via process.

  The build-up resin insulation layers 7 and 9 are made of a resin composition mainly composed of one kind of resin selected from the group consisting of a liquid crystal polymer, a polyimide resin, an epoxy resin, and a fluorine resin. Such a resin composition is obtained by blending a resin as a substrate with additives such as a curing agent and a stabilizer, a filler, and the like as necessary. Examples of the filler include inorganic fillers such as silica powder and glass fiber. The linear expansion coefficient changes according to the amount of filler mixed. When the linear expansion coefficient of the buildup resin insulation layer 7 is close to the core substrate 2, the buildup resin insulation layer 7 has excellent peeling resistance. That is, the build-up resin insulation layer 7 and the core substrate 2 are unlikely to peel off when heat reception and heat dissipation from an integrated circuit chip or the like mounted via the solder bumps 11 are repeated. In addition, both photosensitive and thermosetting can be employ | adopted for the above-mentioned resin composition. In addition, any of a technique of laminating a resin composition formed into a film on the core substrate 2 or the like and a technique of applying a liquid resin composition to the core substrate 2 or the like can be employed.

  The dielectric layers 50 to 52 constituting the core substrate 2 include dielectric loss even in a high frequency region such as alumina ceramic, mullite ceramic, aluminum nitride ceramic, silicon nitride ceramic, silicon carbide ceramic, glass ceramic, low temperature fired ceramic, etc. Is preferably used in the present invention. In particular, it is desirable to use a composite material of glass and a ceramic filler other than glass (hereinafter referred to as glass ceramic) or a high-purity alumina ceramic in terms of excellent surface smoothness upon baking of the dielectric substrate surface. .

  The ceramic dielectric layers 50 to 52 are configured such that the linear expansion coefficient in the temperature range of −55 ° C. or more and 125 ° C. or less is 3 ppm / ° C. or more and 20 ppm / ° C. or less. The conductor layers 60 to 63 of the core substrate 2 are made of a metal that can be fired simultaneously with the ceramic dielectric layers 50 to 52. Specifically, when firing at a high temperature is required, a refractory metal such as W or Mo is employed. When the ceramic dielectric layers 50 to 52 are composed of a low-temperature fired ceramic, a highly conductive metal such as Ag, Ag alloy (eg, Ag—Pt, Ag—Pd), Au, Ni, Cu, and Cu alloy is employed. it can. The conductor layer 63 is formed of a surface conductor provided so as to cover a part of the first main surface CP. Similarly, the conductor layer 60 is composed of a back conductor provided so as to cover a part of the second main surface DP.

  The conductor layers 60 to 63 of the core substrate 2 shown in FIG. 1 are assumed to include a surface conductor pattern having a certain area. However, the surface conductor pattern should not be formed on the core substrate 2. Is also possible. That is, the conductor layers 61 and 62 inside the core substrate 2 can be provided only as via pads that overlap the via conductor 4 in the thickness direction, or can be omitted at all. In that case, the upper and lower via conductors 4 and 4 can be arranged in direct contact with each other.

Hereinafter, the manufacturing process of the wiring board 1 will be described.
First, the core substrate 2 is produced. The core substrate 2 is manufactured using a ceramic green sheet. The ceramic green sheet can be produced by a known doctor blade method. First, raw material ceramic powder made of dielectric ceramic (for example, in the case of glass ceramic powder, mixed powder of borosilicate glass powder and ceramic filler powder such as alumina, BaTiO _3, etc .: average particle size is about 0.3 μm to 1 μm ) Solvent (acetone, methyl ethyl ketone, diacetone, methyl isobutyl ketone, benzene, bromochloromethane, ethanol, butanol, propanol, toluene, xylene, etc.), binder (acrylic resin (eg polyacrylic acid ester, polymethyl methacrylate)) , Cellulose acetate butyrate, polyethylene, polyvinyl alcohol, polyvinyl butyral, etc.), plasticizer (butyl benzyl phthalate, dibutyl phthalate, dimethyl phthalate, phthalate ester, polyethylene Glycol derivatives, tricresol phosphate, etc.), peptizers (fatty acids (glycerin triolates, etc.), surfactants (benzenesulfonic acid, etc.), wetting agents (alkyl allyl polyether alcohol, polyethylene glycol ethyl ether, nithyl phenyl glycol, A mixture of additives such as polyoxyethylene ester) is kneaded to form a slurry, which is applied onto a back sheet such as PET using a doctor blade and dried appropriately, thereby producing a ceramic green sheet. Get.

  Next, a metallized paste for forming via conductors (hereinafter referred to as via conductor paste) is prepared. The metal powder to be used can be the above-described highly conductive metal, and those having an average particle diameter adjusted in the range of 2 μm to 20 μm are preferable. A via conductor paste can be obtained by blending and preparing an organic solvent such as butyl carbitol in the metal powder so as to obtain an appropriate viscosity.

Next, a metallized paste (hereinafter referred to as a conductor layer paste) used for forming the conductor layers 60 to 63 is prepared. The metal powder to be used is preferably the same type as that used in the via conductor paste and having an average particle size adjusted to be as small as 0.1 μm to 3 μm. To this metal powder, an inorganic compound powder having an average particle size of 500 nm or less (preferably 100 nm or less, more preferably 50 nm or less) is blended in the range of 0.5% by mass or more and 30% by mass or less. A conductor layer paste can be obtained by blending and preparing a binder and an organic solvent such as butyl carbitol so as to obtain an appropriate viscosity. The inorganic compound powder may be a ceramic green sheet raw material ceramic powder, or at least one of aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), and titanium oxide (TiO ₂ ). You may mix | blend and use the inorganic compound powder (average particle diameter of 100 nm or less, desirably 50 nm or less) which consists of seeds.

  Here, a supplementary description will be given of a method for producing a ceramic having a high linear expansion coefficient of 10 ppm / ° C. or more. First, some of the resins used for the buildup resin insulating layer 7 are listed above. These resins are limited in the range in which the linear expansion coefficient can be adjusted by addition of fillers. For example, liquid crystal polymers and fluororesins can achieve a low linear expansion coefficient (for example, around 10 ppm / ° C. or less), but it is difficult to mix a considerable amount of filler with polyimide resins and epoxy resins. It is.

  The ceramic dielectric constituting the conventional ceramic wiring board usually has a linear expansion coefficient of less than 10 ppm / ° C. When the core substrate 2 is composed of such a ceramic dielectric, in order to match the linear expansion coefficient between the core substrate 2 and the buildup resin insulation layer 7, a linear expansion coefficient of about 10 ppm / ° C. or less can be realized. What is necessary is just to employ | adopt a liquid crystal polymer and fluorine resin as a buildup material. However, these resins are more expensive than epoxy resins and polyimide resins. Epoxy resins and polyimide resins have a good track record, but it is difficult to achieve low linear expansion coefficients. To use them as build-up materials, the core substrate 2 is made of ceramic with a high linear expansion coefficient. It will be necessary to configure.

Specifically, the linear expansion coefficient of the low-temperature fired ceramic can be increased by taking the following measures.
(I) A high thermal expansion filler (for example, quartz, forsterite) is mixed with a high thermal expansion glass (for example, BaO—SiO ₂ ) or a high thermal expansion crystallized glass.
(Ii) Based on high thermal expansion SiO ₂ (quartz), alkaline earth metal oxides (BaO, SrO, CaO, etc.) and low melting point sintering aids (B ₂ O ₃ , alkali metal oxides, Bi ₂ O ₂ , V ₂ O _5, etc.) are mixed, and pre-baking (for example, 800 ° C.) and main baking (950 to 1000 ° C.) are performed.

For example, to obtain a glass ceramic having a linear expansion coefficient of 5 ppm / ° C. to 8 ppm / ° C., 25 parts by mass of SiO ₂ , ₃ parts by mass of B ₂ O ₃ , 3 parts by mass of Al ₂ O ₃ , and Na ₂ O A ceramic raw material powder obtained by mixing glass powder having a composition of 1 part by mass, 16 parts by mass of PbO, 1 part by mass of K ₂ O, and 2 parts by mass of CaO and 50 parts by mass of alumina filler can be used. Similarly, to obtain a glass ceramic having a linear expansion coefficient of 8 ppm / ° C. to 12 ppm / ° C., 45 parts by mass of SiO ₂ , 9 parts by mass of Al ₂ O ₃ , 8 parts by mass of SrO, and 12 parts by mass of BaO A glass ceramic raw material powder having a composition can be used. V ₂ O ₅ and CoO can also be added. Of course, these compositions are examples, and a desired linear expansion coefficient can be obtained by appropriately adjusting the composition.

  Various low-temperature fired ceramics having a linear expansion coefficient adjusted to 3 ppm / ° C. or more and 20 ppm / ° C. or less can be produced by adjusting the composition and the like by the method (i) and (ii) above. It can be suitably employed. The first main surface CP of the core substrate 2 is subjected to a surface treatment using a silane coupling agent or a titanate coupling agent in order to improve the adhesion between the build-up resin insulating layer 7 and the core substrate 2. Desirable from.

  After producing the core substrate 2 as described above, the build-up wiring laminated portion 3 is formed on the first main surface CP side of the plate-like core 2 by a known build-up method. In the embodiment of FIG. 1, the build-up wiring laminated portion 3 has a two-layer laminated structure of the resin insulating layers 7 and 9 and the conductor layers 8 and 10, but it is also possible to adopt a laminated structure of one layer or three or more layers. It is. 1 is obtained by sequentially forming the solder resist layers SR1 and SR2 and forming the solder bumps 11 after the formation of the build-up wiring laminated portion 3 is completed.

  The magnitude relationship between the linear expansion coefficient α of the ceramic dielectric layers 50, 51, 52 and the linear expansion coefficient β of the build-up resin insulation layers 7, 9 is as follows: (1) α> β, (2) α Any of <β is conceivable. However, it can be said that the case (2) is preferable because it is relatively difficult to produce a ceramic having a high linear expansion coefficient. Of course, the case of α = β is also conceivable.

  In order to examine the peel resistance of the buildup resin insulation layer 7 formed on the core substrate 2, the following test was performed. First, a binder (acrylic resin) and a plasticizer (dibutyl phthalate) are added to a plurality of types of ceramic raw material powders, in which the mixing ratio of the raw material powders is adjusted so that the linear expansion coefficient of the fired product is in the range of 3 ppm / ° C. to 20 ppm / ° C. (DBP)) and a solvent (toluene) were added and kneaded to prepare a slurry. Ceramic green sheets were prepared by a doctor blade method so that the thickness after firing of each slurry was 100 μm. Sheet pieces obtained by punching the green sheets into a predetermined shape were laminated by thermocompression bonding of 8 pieces of the same kind, and fired at 950 ° C. The fired product thus produced was cut to obtain several types of ceramic plate-like bodies molded to 35 mm × 35 mm × 800 μm.

  Next, by sticking several types of build-up materials formed into a film having a thickness of 45 μm to these ceramic plates, the linear expansion coefficient of the ceramic plates and / or build-up materials is increased. Different types of test products (No. 1 to No. 25) were obtained. Each test article was prepared with 10 pieces as one unit. The build-up material is a liquid crystal polymer (made by Kuraray Co., Ltd.) for those having a linear expansion coefficient of less than 10 ppm / ° C., and a bisphenol A type epoxy resin (oiled shell) for those having a linear expansion coefficient of 10 ppm / ° C. to 30 ppm / ° C. Used). A silica filler (manufactured by Tatsumori Co., Ltd.) was used as a filler for adjusting the linear expansion coefficient.

  In addition, the linear expansion coefficient of the ceramic plate-like body and the build-up material was measured under a temperature rising condition from −55 ° C. to 125 ° C. using a differential expansion thermomechanical analyzer (manufactured by Rigaku Corporation, model “TMA8140C”). It was measured. The linear expansion coefficient of the build-up material is a value in the in-sheet direction after being cured.

  A thermal shock test was performed on each test product prepared as described above. Specifically, 500 cycles of cooling / heating cycles were applied to all the test products, with -55 ° C. × 1 minute → temperature increase → 125 ° C. × 1 minute → temperature decrease as one cycle. Then, the presence or absence of peeling was confirmed visually and the quality of each test product was determined. The criteria for pass / fail judgment were that the test product with peeling occurred in half or more of 10 pieces (×), the test product with peeling was 2 or more in 5 pieces and less than 5 (△), and peeling occurred. A test product having 1 or less of 10 pieces was defined as (◯). The results are shown in Table 1.

  Here, the horizontal axis represents the linear expansion coefficient (CTE) of the build-up material, the vertical axis represents the linear expansion coefficient of the ceramic, and Table 1 is plotted in the scatter diagram of FIG. As a result of intensive studies by the present inventors on this scatter diagram, it has been found that non-defective products are concentrated in a certain range. That is, the test product in the region surrounded by the solid line and the broken line shown in the scatter diagram of FIG. 2 showed a very high yield rate compared to the test product outside the region. Then, the slopes of the two solid lines shown in FIG. 2 were determined with the coefficient of linear expansion of the ceramic plate-like body as α and the coefficient of linear expansion of the build-up material as β, which were 0.5 and 1.5, respectively. It was.

  From the above results, as shown in FIG. 1, the linear expansion coefficient α of the core substrate 2 and the linear expansion coefficient β of the build-up resin insulating layer 7 in contact with the ceramic dielectric layer 52 are at least 0.5 ≦ β / If the wiring board 1 is manufactured so as to satisfy α ≦ 1.5, it can be said that the build-up resin insulation layer 7 exhibits excellent peeling resistance.

The cross-sectional schematic diagram of the wiring board concerning this invention. A scatter diagram in which Table 1 is plotted.

Explanation of symbols

1 Wiring board 2 Core board 7, 9 Build-up resin insulation layer 8, 10 Conductor layer

Claims (5)

  In a wiring board in which a resin insulating layer and a conductor layer are laminated on a core substrate, the core substrate is mainly composed of ceramic, and a linear expansion coefficient α of the core substrate is in a temperature range of −55 ° C. or more and 125 ° C. or less. 3 ppm / ° C. to 20 ppm / ° C., the coefficient of linear expansion β of the resin insulating layer adjacent to the core substrate is 5 ppm / ° C. to 30 ppm / ° C., and satisfies 0.5 ≦ β / α ≦ 1.5 A wiring board characterized by:   The core substrate has a surface conductor that covers a part on the first main surface, a back conductor that covers a part of the second main surface, and a via conductor that conducts both the surface conductor and the back conductor, These surface conductors, back conductors and via conductors are composed of one kind of metal selected from the group of highly conductive metals consisting of Cu, Cu alloy, Au, Ni, Ag and Ag alloy, and the ceramic is composed of a low-temperature fired ceramic. The wiring board according to claim 1.   2. The resin insulation layer is mainly composed of an epoxy resin or a polyimide resin mixed with an inorganic filler, and its linear expansion coefficient β is adjusted within a range of 5 ppm / ° C. to 30 ppm / ° C. Or the wiring board of 2.   3. The wiring board according to claim 1, wherein the resin insulating layer is mainly composed of a liquid crystal polymer, and has a linear expansion coefficient β adjusted within a range of 5 ppm / ° C. to 10 ppm / ° C. 3. The wiring board according to claim 1, wherein the resin insulating layer is mainly composed of a fluorine-based resin, and the linear expansion coefficient β thereof is adjusted within a range of 10 ppm / ° C. or more and 20 ppm / ° C. or less.

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