JP4645294B2 - Imaging device and power supply method for imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus which is an example of a semiconductor device for physical quantity distribution detection, and a power supply method for the imaging apparatus.

  Physical quantity distribution formed by arranging multiple unit components (for example, pixels) that are sensitive to changes in physical quantity such as electromagnetic waves or pressure (contact, etc.) input from outside such as light and radiation, in a line or matrix form. Sensing semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell). For example, many CMOS solid-state imaging devices have such a configuration.

  In such an amplification type solid-state imaging device, in order to read out a pixel signal to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are assigned to a predetermined address. The data is read out in order or arbitrarily. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons and holes) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  On the other hand, generally, a solid-state imaging device receives incident light incident from a light receiving surface by each light receiving element constituted by a photodiode or the like, performs photoelectric conversion, detects the generated charge by a detection circuit, and then amplifies it, Output sequentially.

  For example, as one configuration example of the solid-state imaging device, a p-type impurity region (P well) as a second conductivity type semiconductor region is formed on an n-type silicon substrate (first conductivity type semiconductor substrate), A sensor unit (light receiving unit; for example, a photo diode such as a photodiode) having a charge storage layer (hereinafter also referred to as a first sensor region) formed by ion implantation of a first conductivity type impurity into a second conductivity type semiconductor region. Conversion element) is formed. Signal charges obtained by receiving light and performing photoelectric conversion are accumulated in the charge accumulation layer.

  In general, in a CMOS type sensor, the unit pixel configuration including the sensor portion tends to be complicated because the noise is reduced as compared with a CCD (Charge Coupled Device). For example, as a general-purpose CMOS sensor, a four-transistor type having four transistors (TRansistor) in a unit pixel portion while adopting a floating diffusion (FDA) configuration which is a diffusion layer having a parasitic capacitance. A pixel configuration, a so-called 4TR configuration (hereinafter also referred to as a unit pixel in the first example) is well known (see FIG. 2A).

  On the other hand, as a technique for reducing the pixel size by reducing the area occupied by the transistor in the unit pixel in order to reduce the number of elements within a range where performance is not degraded, the unit pixel is configured by the sensor unit and the three transistors. There is a three-transistor pixel configuration, a so-called 3TR configuration (hereinafter also referred to as a unit pixel of the second example) (see, for example, Japanese Patent No. 2708455 and FIG. 2B of this specification).

  Further, unlike a CCD solid-state imaging device, a MOS type solid-state imaging device may have a CMOS logic circuit mounted on the same chip, and a pixel is configured to operate with one power source having the same low voltage as the logic circuit. . Therefore, for example, when the transfer transistor, the vertical selection transistor, and the like are NchMOS transistors, the gate voltage of the transistors in the pixel is driven by binary values of 0 V (so-called ground voltage) and the power supply voltage.

  On the other hand, when driving a unit pixel, a voltage different from the voltage between the power supply voltage and the ground voltage, in other words, a voltage different from the normal operating voltage (hereinafter also referred to as a local voltage) is applied to the driving transistor. Thus, the applicant of the present invention has proposed various techniques for improving various performances such as suppressing dark current, suppressing blooming, expanding a dynamic range, and reducing power consumption.

  For example, in the charge accumulation period, the signal charge corresponding to the amount of incident light and the dark current component (dark electrons) that flows into the sensor when no light is incident are accumulated in the sensor unit. Dark electrons cannot be separated from signal charges at the time of reading, and the variation becomes noise. In particular, the variation in dark current from pixel to pixel becomes fixed pattern noise, and an image is taken through a rubbed glass. Moreover, the temporal variation of dark current becomes random noise. For this reason, in the solid-state imaging device, how to reduce the dark current is a major issue.

  In order to suppress this dark current, the applicant of the present application has proposed a mechanism in Patent Document 1 that enables reduction of the dark current, ensures the function of the overflow path, and more reliably suppresses blooming.

JP 2002-217397 A

  The mechanism of Patent Document 1 is to obtain a dark current suppressing effect and the like by applying a predetermined voltage to a transfer gate for a unit pixel having a four-transistor configuration including a selection transistor. Specifically, the gate voltage of the transfer transistor when the signal charge (electrons or holes) is accumulated in the photodiode is set to a negative voltage (when the signal charges are electrons) or a positive voltage (when the signal charges are holes). The dark current is reduced. In this case, since the function of the transfer transistor as an overflow path is weakened, the charge overflowing from the photodiode is preferably allowed to flow through the bulk other than the channel portion of the transfer transistor. The region where the charges overflowing from the photodiode are formed in a region having a concentration lower than that of the semiconductor well region.

  By doing so, charges having the opposite polarity to the signal charges are accumulated in the channel portion of the transfer transistor, and the generation of dark current components from the interface with the gate insulating film can be dramatically reduced. Further, by flowing the charge overflowing from the photodiode through the bulk other than the channel portion of the transfer transistor, the so-called overflow path area is increased, and the function as the overflow path is improved.

  Here, there are various circuit configurations for generating a local voltage and supplying it to a predetermined terminal of the element in order to improve a predetermined characteristic, but most of them have a sudden change in output current (load current). This will affect the stability of the output voltage.

  For example, FIG. 22 shows a configuration example of a conventional local voltage supply unit using a charge pump circuit (see, for example, JP-A-2002-171748). In this configuration, the voltage divided by the resistance elements 322 and 324 of the resistance divider 320 is used as the feedback voltage VFB, the feedback voltage VFB and the reference voltage Vref0 are compared by the error amplifier 350, and the error voltage is supplied to the power supply of the charge pump circuit. The charge is supplied to the pump capacitor 302 (charge) and the charge is transferred from the pump capacitor 302 to the output capacitor 304 by controlling the switches 311 to 314 in the charge pump switch group 310 on / off. Thus, the step-up operation by the negative feedback control is performed so that the output voltage Vout generated in the output capacitor 304 becomes constant.

  Here, in the case of the local voltage supply unit 162 having such a configuration, for a sudden load current fluctuation, the recovery time is limited only by a response with a time constant determined by the feedback loop, and the recovery time is limited by the band in the loop. The Therefore, there is a problem that it takes time to recover the voltage change of the output voltage Vout due to the electric charge supplied from the pump capacitor 302 to the output capacitor 304 to a stable level when the load current changes suddenly. As a result, the improvement effect by generating a local voltage and supplying it to a predetermined terminal of the element for a predetermined characteristic improvement is reduced.

  Further, as a method for solving this problem, a method of widening the band of the error amplifying unit 350 of the local voltage supply unit 162 can be considered. However, inconveniences such as the deterioration of stability and the effect of switching noise increase by widening the band. Further, as another means for reducing the fluctuation of the output voltage Vout, it is conceivable to take measures by increasing the output capacity 304. This method causes a new problem in terms of space and cost.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a mechanism capable of supplying an appropriate local voltage even when there is a sudden change in load current.

  In the imaging device according to the present invention, as in the conventional configuration, in order to improve the predetermined characteristics, a local voltage supply unit for applying a local voltage different from the normal operating voltage to a predetermined terminal is provided. The magnitude of the local voltage generated by the local voltage supply unit is hardly affected by a sudden change in the load current.

  Various methods are conceivable as a mechanism for making the generated local voltage difficult to be affected by a sudden change in load current. For example, a feedback control configuration is adopted so that the local voltage is maintained at a constant value while using a switching power supply. At this time, the generated local voltage is compared with a predetermined reference voltage, and the magnitude of the generated local voltage is maintained at a predetermined value based on the comparison result. In the meantime, this can be realized by providing an operating point switching unit that switches the operating point of the switching operation for generating the local voltage based on the boost signal. That is, when the load current changes rapidly, the operating point of the control loop is switched so that a large amount of output current can be temporarily obtained.

  In the imaging device, the rapid fluctuation of the load current is related to the operation mode, and it can be specified what kind of operation causes the load current of the local voltage supply unit to increase suddenly. There is also a trigger signal that triggers this. Therefore, this trigger signal is used to temporarily disconnect from the normal control loop at the timing when the load current of the local voltage supply unit suddenly increases, so that the output current capability of the local voltage supply unit is increased. Is forcibly set. Since a sudden increase in load current can be instantaneously compensated for, it is possible to suppress a change in output voltage caused by the rapid increase in load current.

  At first glance, it can be thought of as feedforward control, but the operating point is only forcibly switched in the direction of increasing the output current supply capability, and the operating point at which the output current capability of the local voltage supply unit is increased. Even if it is forcibly set, the operation of the entire control loop is the same as that of the normal control loop, and if the normal control loop is a feedback control loop, the feedback control loop is similarly configured. The local voltage is controlled to be constant according to the operating point after switching.

  In the present invention, the imaging device includes a plurality of detection units that detect a change in physical quantity and a unit signal generation unit that outputs a unit signal based on the change in physical quantity detected by each detection unit. Using a physical quantity distribution detection device in which the unit components are arranged in a predetermined order, and based on a unit signal acquired under a predetermined detection condition for the physical quantity, A general term for physical information acquisition devices that acquire information.

  According to the present invention, a boost corresponding to a trigger signal indicating a trigger for a sudden increase in the load current so that the magnitude of the local voltage generated by the local voltage supply unit is less affected by a sudden change in the load current. Based on the signal, the operating point is forcibly set to increase the output current capability of the local voltage supply unit by temporarily disconnecting from the normal control loop at the timing when the load current of the local voltage supply unit suddenly increases. As a result, a sudden increase in load current can be instantaneously compensated for, and a change in output voltage caused by the rapid increase in load current can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example.

  However, this is merely an example, and the target device is not limited to a MOS imaging device. Embodiments described later are applied to all semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix. The same applies.

<Schematic configuration of imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device which is an embodiment of an imaging device (one aspect of a physical information acquisition device) according to the present invention. The solid-state imaging device 1 is applied as, for example, an electronic still camera or an FA (Factory Automation) camera that can capture a color image.

  The solid-state imaging device 1 includes unit pixels including light receiving elements as detection units (not shown) that output signals corresponding to the amount of incident light, arranged in a square lattice of rows and columns, that is, a two-dimensional matrix imaging unit (pixels). And a signal output from each unit pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit and other function units are provided for each vertical column. Is.

  That is, as shown in FIG. 1, the solid-state imaging device 1 includes an amplifying photoelectric conversion including at least one charge generation unit formed of a photodiode or a photogate (both examples of photoelectric conversion elements) and an active element. An imaging unit (pixel unit) 10 in which a large number of pixels (hereinafter referred to as unit pixels 3) are arranged in a row direction and a column direction (in a two-dimensional matrix), a so-called area sensor unit, and drive control provided outside the imaging unit 10 A column processing unit 20 having a column signal processing unit 22 (denoted as a column circuit in the drawing) arranged in each vertical row, and a horizontal selection switch unit 60.

  As the drive control unit 7, for example, a horizontal scanning unit 12 and a vertical scanning unit 14 are provided. Further, as another component of the drive control unit 7, a drive signal operation for supplying a control pulse at a predetermined timing to each functional unit of the solid-state imaging device 1 such as the horizontal scanning unit 12, the vertical scanning unit 14, or the column processing unit 20. A unit (an example of a read address control device) 16 is provided.

  Each element of the drive control unit 7 is integrally formed in a semiconductor region such as single crystal silicon together with the imaging unit 10 using a technique similar to the semiconductor integrated circuit manufacturing technique, and is a solid-state imaging that is an example of a semiconductor system. It is configured as an element (imaging device).

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column of the imaging unit 10. . Although illustration is omitted, the imaging unit 10 is formed with a color separation filter having a predetermined color coding for each pixel. Of course, the color separation filter is not essential depending on the configuration such as for monochrome imaging. Although not shown, each unit pixel 3 of the imaging unit 10 is configured by a photoelectric conversion element such as a photodiode or a photogate, and a transistor circuit.

  The unit pixel 3 is detected by the vertical scanning unit 14 via the vertical control line 15 for selecting a vertical column, and after being amplified by a unit signal generation unit (not shown) having an amplification element detected by a plurality of detection units. The column processing unit 20 is connected to each other via a vertical signal line 18 as a transmission line for transmitting pixel signals S0 (_1 to h; pixel numbers in one row) output from the unit pixel 3 respectively.

  That is, the vertical signal line 18 from which the pixel signal is output from the unit pixel 3 of the imaging unit 10 is connected in common to the unit pixel 3 in the column direction in the imaging unit 10, and each of the vertical signal lines 18 in the column processing unit 20 as a readout circuit. Each is connected to a column circuit 22 corresponding to the column.

  The horizontal scanning unit 12 and the vertical scanning unit 14 start a shift operation (scanning) in response to a driving pulse given from the driving signal operation unit 16. The vertical control line 15 includes various pulse signals for driving the unit pixel 3.

  The horizontal scanning unit 12 defines a horizontal readout column (horizontal address) (selects each column signal processing unit 22 in the column processing unit 20), and a horizontal address setting unit 12a. The horizontal drive unit 12b guides each signal of the column processing unit 20 to a horizontal signal line (horizontal read line) 86 in accordance with the read address defined in FIG.

  Although not shown, the horizontal address setting unit 12a includes a shift register or a decoder, selects pixel information from the column signal processing unit 22 in a predetermined order, and selects the selected pixel information as a horizontal signal. It functions as a selection means for outputting to the line 86.

  The vertical scanning unit 14 defines a vertical readout row (vertical address) and a horizontal readout column (horizontal address) (selects a row of the imaging unit 10), and a vertical address setting unit 14a. A vertical drive unit 14b that drives by supplying a pulse to the control line for the unit pixel 3 on the read address (in the horizontal direction) defined by the address setting unit 14a.

  Although not shown in the figure, the vertical address setting unit 14a has a shutter shift register that controls a row for an electronic shutter in addition to a vertical shift register or a decoder that performs basic control of a row from which a signal is read.

  The vertical shift register is for selecting each pixel in units of rows when reading out pixel information from the imaging unit 10, and constitutes a signal output row selection means together with the vertical drive unit 14b of each row. The shutter shift register is for selecting each pixel in units of rows when performing the electronic shutter operation, and constitutes an electronic shutter row selection means together with the vertical drive unit 14b of each row.

  Although not shown, the drive signal operation unit 16 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock necessary for the operation of each unit and a pulse signal of a predetermined timing, and an input clock via a terminal 1a. A communication interface functional block that receives data instructing CLK0, an operation mode, and the like, and that outputs data DATA including information of the solid-state imaging device 1 via the terminal 1b. In addition, the horizontal address signal is output to the horizontal address setting unit 12a and the vertical address signal is output to the vertical address setting unit 14a, and each address setting unit 12a, 14a receives it and selects a corresponding row or column.

  The drive signal operation unit 16 may be provided as a separate semiconductor integrated circuit independently of other functional elements such as the imaging unit 10 and the horizontal scanning unit 12. In this case, an imaging device which is an example of a semiconductor system is constructed by the imaging device including the imaging unit 10 and the horizontal scanning unit 12 and the drive signal operation unit 16. This imaging device may be provided as an imaging module in which peripheral signal processing circuits, power supply circuits, and the like are also incorporated.

  The column processing unit 20 is configured to include a column signal processing unit 22 for each vertical column (column), and each column signal processing unit 22 receives a pixel signal for one row, and each column signal processing unit 22 outputs a pixel signal of the corresponding column. S0 (_1 to h; pixel number in one row) is processed to output a processed pixel signal S1 (_1 to h; pixel number in one row). Although not shown, the vertical signal line 18 is connected to a load transistor having a role of a constant current source at one end and to a column signal processing unit 22 at the other end.

  For example, the column signal processing unit 22 has a coupling capacitor, a signal transfer switch, and a storage capacitor, and can have a function (signal holding circuit) for storing signal charges based on a signal from the vertical signal line 18. . Further, a function of a noise removing means using a CDS (Correlated Double Sampling) process may be provided.

  For example, in the case of the former configuration, as illustrated, each column circuit 22 is provided with a coupling capacitor 123, a signal transfer switch 124, and a storage capacitor 126 as an example. The coupling capacitors 123 in each column are collectively referred to as a coupling capacitor group 123C, the signal transfer switches 124 in each column are collectively referred to as a signal transfer switch unit 124QT, and the storage capacitors 126 in each column are collectively referred to as a storage capacitor group 126C. The clock φT is commonly input to the control gate ends of the signal transfer switch unit 124QT.

  In the column processing unit 20, the column output line 128 is connected to a storage capacitor 126 whose other end is grounded, and each storage capacitor 126 constitutes a storage capacitor group 126C in the row direction. The electric signal output from the pixel passes through the vertical signal line 18 and is held in the storage capacitor 126 connected to each vertical signal line 18.

  An output signal from the column processing unit 20 is input to a horizontal selection switch unit 60 including a horizontal reading switch (for example, a MOS transistor) 62. The output of each column circuit 22 of the column processing unit 20 is connected via a column output line 128 to a horizontal read switch 62 corresponding to each column for sequentially reading out the charges held in the storage capacitor 126. ing.

  A horizontal signal line 86 for sequentially transferring and outputting signal charges in the row direction is commonly connected to the output end side of the horizontal selection switch unit 60. On the other hand, each control gate end of the horizontal selection switch unit 60 is composed of a horizontal shift register, a decoder, and the like, and is driven horizontally by a horizontal address setting unit 12a for controlling a horizontal read address and a switch 62 of the horizontal selection switch unit 60. It is connected to the horizontal scanning part 12 provided with the part 12b.

  On the other hand, when performing the CDS process, the pixel information of the voltage mode input via the vertical signal line 18 based on two sample pulses such as the sample pulse SHP and the sample pulse SHD given from the drive signal operation unit 16 is obtained. By performing the process of taking the difference between the signal level immediately after pixel reset (noise level; 0 level) and the true signal level, fixed pattern noise (FPN) due to fixed variation for each pixel and reset noise The noise signal component is removed.

  The column signal processing unit 22 may be provided with an AGC (Auto Gain Control) circuit having a signal amplification function, other processing function circuits, or the like as required after the CDS processing function unit.

  In the subsequent stage of the column processing unit 20, a horizontal selection switch unit 60 including a horizontal reading switch (selection switch) (not shown) is provided, and the output terminal of the column signal processing unit 22 of each vertical column is connected to the column signal. Each is connected to an input terminal i of a selection switch corresponding to each vertical column for sequentially reading signals from the processing unit 22.

  The control gate terminal c of each vertical column of the horizontal selection switch unit 60 is connected to the horizontal driving unit 12b of the horizontal scanning unit 12 that controls and drives the readout address in the horizontal direction. On the other hand, a horizontal signal line 86 for sequentially transferring and outputting pixel signals in the row direction is commonly connected to the output terminals o of the selection switches in the vertical columns of the horizontal selection switch unit 60. An output circuit 88 is provided at the rear end of the horizontal signal line 86.

  The horizontal signal line 86 functions as a readout line for outputting individual pixel signals S0 transmitted from the unit pixels 3 via the vertical signal lines 18 in a predetermined order in the horizontal direction that is the arrangement direction of the vertical signal lines 18. From the column signal processing unit 22, a signal selected by a selection switch (not shown) that exists for each vertical column is extracted and passed to the output circuit 88.

  That is, the voltage signal of each vertical column corresponding to the signal charge representing the pixel information processed by the column signal processing unit 22 is driven by the driving pulses φg1 to φgh corresponding to the horizontal selection signals φH1 to φHh from the horizontal scanning unit 12. The selected switch provided for each vertical column is selected at a predetermined timing and read out to the horizontal signal line 86. Then, it is input to an output circuit 88 provided at the rear end of the horizontal signal line 86.

  The external circuit 97 outside the imaging chip, which is a subsequent stage of the output circuit 88, has a functional unit that converts the analog imaging signal S3out (collection of individual pixel signals S1_1 to n) output from the output circuit 88 into digital imaging data. The AD conversion unit 972, the digital signal processing unit 974 which is a functional unit that performs digital signal processing based on digitized imaging data, and the image data D2 digitally processed by the digital signal processing unit 974 are converted into analog data. A DA (Digital to Analog) converter 976 is provided for converting into an image signal.

  Although the details of the configuration example will be described later, the output circuit 88 can operate by switching between two states of a signal transfer state and a reset state. Correspondingly, various drive pulses CN10 such as a pulse for switching between the signal transfer state and the reset state and a pulse for sampling the signal in the signal transfer state are supplied from the drive signal operation unit 16. The

  The output circuit 88 amplifies the pixel signals S1_1 to h (h = n) of each unit pixel 3 output from the imaging unit 10 through the horizontal signal line 86 with an appropriate gain, and then controls the drive pulse CN10. The imaging signal S3out is supplied to the external circuit 97 via the output terminal 88a. For example, the output circuit 88 may only perform buffering, or may perform black level adjustment, column variation correction, color-related processing, and the like before that.

  The AD conversion unit 972 converts the analog imaging signal S3out output from the column processing unit 20 to the outside of the solid-state imaging device 1 via the output circuit 88 into digital imaging data D0, and performs a subsequent digital signal processing unit 974. To pass.

  The digital signal processing unit 974 has a function of a digital amplifier unit that appropriately amplifies and outputs a digital signal output from the AD conversion unit 972, for example. Further, for example, color separation processing is performed to generate image data RGB representing each image of R (red), G (green), and B (blue), and other signal processing is performed on the image data RGB for monitoring. Output image data D2 is generated. Further, the digital signal processing unit is provided with a functional unit that performs signal compression processing for storing imaging data in a recording medium.

  The image signal S1 output from the DA conversion unit 976 is sent to a display device such as a liquid crystal monitor. The operator can perform various operations such as switching the imaging mode while viewing the menu and images displayed on the display device.

  That is, in the column-type solid-state imaging device 1 of the present embodiment, the output signal (voltage signal) from the unit pixel 3 is the vertical signal line 18 → the column processing unit 20 (column signal processing unit 22) → the horizontal signal line 86. → Transmitted in the order of the output circuit 88. The drive is such that the pixel output signals for one row are sent in parallel to the column processing unit 20 via the vertical signal line 18, and the processed signals are serially output via the horizontal signal line 86.

  As long as driving for each vertical column or horizontal column is possible, each pulse signal is supplied to the unit pixel 3 from either the horizontal direction or the vertical column direction, that is, driving for applying a pulse signal. The physical wiring method of the clock line is free.

  In the solid-state imaging device 1 having such a configuration, the horizontal scanning unit 12 and the vertical scanning unit 14 and the drive signal operation unit 16 that controls them are sequentially selected for each pixel of the imaging unit 10 in a horizontal unit, and the selection is performed. A CMOS image sensor of a type that simultaneously reads out information of one horizontal parallel pixel is configured.

  The external circuit 97 provided at the subsequent stage of the output circuit 88 is on a substrate (printed substrate or semiconductor substrate) different from the solid-state imaging device in which the imaging unit 10 and the drive control unit 7 are integrally formed in the same semiconductor region. The circuit configuration corresponding to each photographing mode is adopted.

  A solid-state imaging device 1 is configured by a solid-state imaging device (an example of a semiconductor device or a physical information acquisition device according to the present invention) including an imaging unit 10 and a drive control unit 7 and an external circuit. The drive control unit 7 is separated from the imaging unit 10 and the column processing unit 20, and the imaging unit 10 and the column processing unit 20 constitute a solid-state imaging device (an example of a semiconductor device). You may comprise with the control part 7 as an imaging device (an example of the physical information acquisition apparatus which concerns on this invention).

  Although an example in which the external circuit in charge of signal processing in the subsequent stage of the solid-state image sensor is performed outside the solid-state image sensor (imaging chip) is shown here, all or part of the external circuit (for example, an A / D converter or digital The functional element of the amplifier unit or the like may be built in the chip of the solid-state imaging device. In other words, an external circuit is configured on the same semiconductor substrate as the solid-state image pickup element in which the image pickup unit 10 and the drive control unit 7 are integrally formed in the same semiconductor region, and is substantially the same as the solid-state image pickup device 1 physically. The information acquisition apparatus may be the same.

  In the figure, the solid-state imaging device 1 is configured by including the horizontal selection switch unit 60 and the drive control unit 7 together with the imaging unit 10, and the solid-state imaging device 1 substantially functions as a physical information acquisition device. However, the physical information acquisition apparatus is not necessarily limited to such a configuration. It is not a requirement that the entire horizontal selection switch unit 60 and the drive control unit 7 or the one functional part be integrally formed in the same semiconductor region as the imaging unit 10. The horizontal selection switch unit 60 and the drive control unit 7 are formed on a circuit board different from the imaging unit 10 (which means not only another semiconductor substrate but also a general circuit board), for example, a circuit board on which an external circuit is provided. May be.

<Configuration example of unit pixel>
FIG. 2 is a diagram illustrating a configuration example of the unit pixel 3. In an XY address type solid-state imaging device, for example, an imaging unit 10 is configured by arranging a large number of pixel transistors in a two-dimensional matrix, and signal charges corresponding to incident light are accumulated for each line (row) or each pixel. The current or voltage signal based on the accumulated signal charge is sequentially read from each pixel by addressing. The basic configuration is typically the first example with a four-transistor (4TR) configuration and the second example with a three-transistor (3TR) configuration with fewer transistors than the four-transistor configuration. .

  FIG. 2A shows the configuration of the unit pixel 3 of the first example. The unit pixel 3 of the first example includes a charge generation unit 32 having both a photoelectric conversion function for converting light into a charge and a charge storage function for storing the charge. A sensing element that detects potential changes in a read selection transistor 34 that is an example of a read unit (transfer gate unit / read gate unit), a reset transistor 36 that is an example of a reset gate unit, a vertical selection transistor 40, and a floating diffusion 38. An amplifying transistor 42 having a source follower configuration as an example. For the charge generation unit 32, for example, an embedded photodiode is used.

  The read selection transistor 34 is driven by a transfer pulse φTG by a transfer drive buffer 150 via a transfer wiring (read selection line) 55. The reset transistor 36 is driven by a reset pulse φRST by a reset driving buffer 152 via a reset wiring 56. The vertical selection transistor 40 is driven by the selection pulse φSEL by the selection drive buffer 154 via the vertical selection line 52. Each drive buffer 150, 152, 154 is arranged in the vertical drive unit 14b.

  The unit pixel 3 includes a pixel signal generation unit 5 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 38 which is an example of a charge injection unit having a function of a charge storage unit. The floating diffusion 38 is a diffusion layer having parasitic capacitance.

  The reset transistor 36 in the pixel signal generator 5 has a source connected to the floating diffusion 38 and a drain connected to the power supply VDD, and a reset pulse φRST is input from the reset drive buffer 152 to the gate (reset gate RG).

  The vertical selection transistor 40 has a drain connected to the power supply VDD, a source connected to the drain of the amplification transistor 42, and a gate (in particular, a vertical selection gate SELV) connected to a vertical selection line 52. A vertical selection signal is applied to the vertical selection line 52. The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the source of the vertical selection transistor 40, and a source connected to the vertical signal line 53 via the pixel line 51.

  In such a configuration, since the floating diffusion 38 is connected to the gate of the amplifying transistor 42, the amplifying transistor 42 sends a signal corresponding to the potential of the floating diffusion 38 (hereinafter referred to as FD potential) via the pixel line 51. To the vertical signal line 53. The reset transistor 36 resets the floating diffusion 38. The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A large number of pixels are connected to the vertical signal line 53. To select a pixel, the vertical selection transistor 40 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 53, and the signal of the selected pixel is output to the vertical signal line 53.

  As described above, the unit pixel 3 is generally provided with a vertical selection transistor 40 for the purpose of selecting a pixel, and the unit pixel 3 in most current CMOS sensors has a selection transistor.

  In the illustrated configuration, the example in which the vertical selection transistor 40 is disposed on the power supply VDD side and the amplification transistor 42 is disposed on the pixel line 51 side is shown, but on the contrary, the vertical selection transistor 40 is disposed. May be arranged on the pixel line 51 side, and the amplifying transistor 42 may be arranged on the power supply VDD side.

  On the other hand, the unit pixel 3 of the second example shown in FIG. 2B has a pixel size reduced by reducing the area occupied by the transistors in the unit pixel 3.

  The unit pixel 3 of the second example corresponds to the charge generation unit 32 (for example, a photodiode) that generates a signal charge corresponding to the received light by performing photoelectric conversion, and the signal charge generated by the charge generation unit 32. The amplifying transistor 42 connected to the drain line (DRN) for amplifying the signal voltage to be reset and the reset transistor 36 for resetting the charge generation unit 32 are provided. In addition, a read selection transistor (transfer gate portion) 34 that is scanned from a vertical shift register (not shown) via a transfer wiring (TRF) 55 is provided between the charge generation portion 32 and the gate of the amplification transistor 42. Yes.

  The gate of the amplifying transistor 42 and the source of the reset transistor 36 are connected to the charge generation unit 32 via the read selection transistor 34, and the drain of the reset transistor 36 and the drain of the amplifying transistor 42 are connected to the drain line. The source of the amplifying transistor 42 is connected to the vertical signal line 53. The read selection transistor 34 is driven by the transfer pulse φTG by the transfer drive buffer 150 via the transfer wiring 55. The reset transistor 36 is driven by a reset pulse φRST by a reset driving buffer 152 via a reset wiring 56. Both the transfer drive buffer 150 and the reset drive buffer 152 operate with a reference voltage of 0 V and a binary power supply voltage. In particular, a typical low level voltage supplied to the gate of the read selection transistor 34 in this pixel is 0V.

  In the unit pixel 3 of the second example, as in the first example, the floating diffusion 38 is connected to the gate of the amplifying transistor 42, so that the amplifying transistor 42 outputs a signal corresponding to the potential of the floating diffusion 38. Output to the vertical signal line 53.

  In the reset transistor 36, a reset wiring (RST) 56 extends in the row direction, and a drain line (DRN) 57 is common to most pixels. The drain line 57 is driven by a selection pulse φSEL by a drain drive buffer (hereinafter referred to as a DRN drive buffer) 140. The reset transistor 36 is driven by the reset drive buffer 152 and controls the potential of the floating diffusion 38. Here, in the 3TR configuration, the drain line 57 is separated in the row direction. However, since the drain line 57 must flow the signal current of the pixels for one row, the current can actually flow in the column direction. In addition, the wiring is common to all rows.

  The signal charge generated by the charge generation unit 32 (photoelectric conversion element) is transferred to the floating diffusion 38 by the read selection transistor 34.

  Here, unlike the first example, the unit pixel 3 of the second example is not provided with the vertical selection transistor 40 connected in series with the amplifying transistor 42. A large number of pixels are connected to the vertical signal line 53, but the pixels are selected by controlling the FD potential instead of the selection transistor. Usually, the FD potential is set to low. When selecting a pixel, the signal of the selected pixel is output to the vertical signal line 53 by setting the FD potential of the selected pixel to high. Thereafter, the FD potential of the selected pixel is returned to low. This operation is performed simultaneously for one row of pixels.

  In order to control the FD potential in this way, 1) when the selected row FD potential is made high, the drain line 57 is made high, and the FD potential is made high through the reset transistor 36 of the selected row. 2) When the selected row FD potential is returned to low, the drain line 57 is set low and the FD potential is set low through the reset transistor 36 of the selected row.

<Configuration of local voltage application; basic>
FIG. 3 is a diagram illustrating a basic configuration example for applying a local voltage such as a negative voltage to a predetermined transistor of the unit pixel 3. Here, a configuration example in which the local voltage is applied via the various drive buffers 150, 152, and 154 already shown in FIG. However, this is merely an example, and a configuration example in which a local voltage is applied to predetermined terminals of other elements constituting the unit pixel 3 without using the drive buffers 150, 152, and 154 may be employed.

  As shown in FIG. 3A, each of the drive buffers 150, 152, and 154 includes a level shifter 160 and an output buffer 161. The level shifter 160 and the output buffer 161 are connected to a local voltage supply unit 162 as a voltage supply unit. A local voltage such as a negative voltage is supplied.

  As shown in FIG. 3B, the output buffer 161 has a cascade connection configuration of a Pch MOS transistor (P-MOS) and an Nch MOS transistor (N-MOS). The MOS is arranged on the local voltage supply unit 162 side.

  That is, the output buffer 161 is constituted by an inverter circuit formed of a P-MOS and an N-MOS, which is a so-called CMOS transistor. The power supply voltage VDD is connected to the drain side of the P-MOS, and the local voltage supply unit 162 is connected to the source side of the N-MOS. The input terminal of the inverter circuit is connected to the vertical drive unit 14b of the vertical scanning unit 14 through the level shifter 160, and the output terminal is connected to the vertical selection line 52, the transfer wiring 55, the reset wiring 56, and the like. In this example, in order to facilitate understanding, the output buffer 161 is configured by a single-stage inverter circuit, but may be configured by a plurality of stages of inverter circuits.

  Each of the drive buffers 150, 152, and 154 receives an input pulse having a low level GND from the vertical address setting unit 14a, and the low level is a pulse of a local voltage such as a negative voltage. Output toward the gate terminal of the read selection transistor 34.

  The local voltage supply unit 162 may use a known DC voltage conversion circuit (so-called step-up circuit or step-down circuit) such as a general charge pump configuration or a chopper type DC-DC converter using a coil. it can. For example, when a negative voltage is generated as the local voltage, a circuit that boosts the ground (ground) voltage to the negative side when viewed from the power supply voltage VDD can be used.

  The main part of the local voltage supply unit 162 may be built in each of the drive buffers 150, 152, and 154, or may not be built in, and the local voltage supply unit 162 may be provided outside the drive buffers 150, 152, and 154 as illustrated. A configuration in which a supply unit 162 is provided to supply a local voltage to a predetermined one of the drive buffers 150, 152, and 154 can also be adopted. When not built in, semiconductor components such as transistors and amplifiers and resistor elements constituting the local voltage supply unit 162 are accommodated in an independent semiconductor IC separate from the imaging unit 10, and a capacitor (capacitance) or coil having a large capacitance value Are arranged in the vicinity of the semiconductor IC as external components.

  For example, when the negative voltage is a local voltage, a configuration is adopted in which a negative voltage is supplied to the transfer drive buffer 150 in order to suppress dark current in the read selection transistor 34 as a transfer gate. In this case, the output buffer 161 is formed by being separated by the semiconductor well region. More specifically, the P-MOS is formed in the n-type semiconductor well region, and the N-MOS is formed in the p-type semiconductor well region. Therefore, the output of the local voltage supply unit 162 enters the p-type semiconductor well region of the output buffer 161 and the source region of the N-MOS in the p-type semiconductor well region. The threshold value of the N-MOS is set high.

  In this buffer circuit, and therefore in the output buffer 161, when a low pulse level is input from the vertical scanning unit 14, the P-MOS is turned on and the power supply voltage VDD is output to the transfer wiring 55 on the output side. When a high level is input, the N-MOS is turned on and a negative voltage is output to the output transfer line 55.

<Example of negative voltage drive>
FIG. 4 is a diagram illustrating a method of driving a transistor so that the low level becomes a negative voltage. Here, FIG. 4 shows a circuit in which attention is paid to the charge generation unit 32 and the read selection transistor 34 which are formed of embedded photodiodes. Here, as described in Japanese Patent Laid-Open No. 2002-217397, a pulse signal whose low level is a negative voltage is supplied to the read selection transistor 34 as a transfer gate (transfer transistor) in the unit pixel 3 having a 4TR configuration. This shows the case of a configuration that reduces dark current. The pulse signal whose low level is a negative voltage applies a negative voltage to the gate electrode of the read selection transistor 34 during the charge accumulation period.

  Although a detailed timing chart at the time of pixel driving is omitted in the drawing, it is important that the transfer gate potential of the read selection transistor (transfer transistor) 34 is a negative potential during the charge accumulation period. When the transfer gate potential becomes a negative potential, the amplitude of the transfer gate voltage increases, so the saturation signal amount increases and the dynamic range is expanded.

  In addition, another important point is that the value of the negative potential of the transfer gate is a level (about -1.1 V in this case) at which a channel (hole channel in this example) is formed under the gate. is there. Dark current can be suppressed by forming a hole channel under the transfer gate.

  In other words, during the charge accumulation period, dark current flows into the photodiode simultaneously with the photoelectrically converted charge, but the conductivity type opposite to the charge accumulation region of the photodiode (eg, n-type semiconductor region) at the interface with the oxide film as a photodiode. The main source of dark current when using a so-called embedded photodiode in which a region (for example, a p-type semiconductor region) is formed is the oxide film interface under the transfer gate. Here, by forming a hole channel with the transfer gate as a negative potential, dark current can be prevented without deteriorating transfer characteristics.

  Note that setting the value of the negative potential of the transfer gate to about −1.1 V is merely an example. Although the illustration is omitted for details, it has been found that a dark current reduction effect occurs from a negative potential of about −0.5 V, and the dark current becomes substantially zero at about −0.8 V or less. The negative potential to be applied is −0.5 V or less, preferably −0.8 or less (see Japanese Patent Application Laid-Open No. 2002-217397, particularly FIG. 9 and its description). However, if an excessive negative potential is applied to the transfer gate, a sufficient dark current reduction effect can be obtained, but the reliability of the transistor decreases, so an appropriate value (typically the absolute maximum rating) To a value not exceeding.

<Configuration example of local voltage supply unit; Part 1>
FIG. 5 is a diagram illustrating a first configuration example of the local voltage supply unit 162. The first configuration example of the local voltage supply unit 162 (also referred to as the local voltage supply unit 162 of the first example) is characterized in that a switched capacitor type DC-DC converter so-called charge pump circuit is used. Yes.

  That is, as illustrated, the local voltage supply unit 162 of the first example includes a charge pump switch group 310 having a plurality of switching elements, and a first resistance element 322 that divides the output voltage Vout of the charge pump switch group 310 ( A resistance dividing unit 320 including a resistance value R1) and a second resistance element 324 (resistance value R2), and a reference voltage generating unit 330 that sets a reference voltage Vrefout for the resistance dividing unit 320. The resistance dividing unit 320 and the reference voltage generation unit 330 constitute a detection unit that detects the magnitude of the output voltage Vout (local voltage) generated by the local voltage supply unit 162.

  Each of the resistance elements 322 and 324 constituting the resistance dividing unit 320 can be a so-called external discrete component or can be positively adapted to be an external component. By using external parts, the output voltage value can be adjusted externally.

  A pump capacitor 302 for transferring or storing charges is connected to the two capacitor connection terminals a and b of the charge pump switch group 310, and an output is provided between the output terminal c from which the output voltage Vout is output and the ground. A capacitor 304 is connected.

  It is assumed that the reference voltage generation unit 330 can obtain a certain reference voltage Vrefout even if the power supply voltage changes. For example, as the reference voltage generation unit 330, a band gap type reference voltage circuit or the like can be used. The power source of the reference voltage generator 330 may be the power source VDD from the external power source, or may be the output voltage Vout at the output terminal c of the charge pump switch group 310 depending on the circuit configuration. In any case, a power supply voltage higher than the generated reference voltage Vref0 is required. In this example, the reference voltage Vrefout is a stable voltage value of 0 or more.

  Further, the local voltage supply unit 162 of the first example receives the reference voltage generation unit 340 that generates the reference voltage Vref0 and the feedback voltage VFB obtained by dividing the output voltage Vout by the resistance division unit 320 at the inverting input terminal (−). And an error amplification unit (error amplifier unit) 350 that receives the reference voltage Vref0 from the reference voltage generation unit 340 at the non-inverting input terminal (+) and amplifies or attenuates the difference between the feedback voltage VFB and the reference voltage Vref0. . As the error amplifier 350, an operational amplifier (op amp OP) can be used.

  It is assumed that the reference voltage generation unit 340 can obtain a certain reference voltage Vref0 even if the power supply voltage changes. For example, as the reference voltage generation unit 340, a band gap type reference voltage circuit or the like can be used. The power supply of the reference voltage generation unit 340 may be the power supply VDD from the external power supply, or may be the output voltage Vout at the output terminal c of the charge pump switch group 310 depending on the circuit configuration. In any case, a power supply voltage higher than the generated reference voltage Vref0 is required.

  Although not shown, a gain phase correction unit for stabilizing the feedback network can be provided between the inverting input terminal (−) and the output terminal of the error amplifying unit 350. Although not shown, the resistance divider 320 is also provided between the input side (output voltage Vout side) and the output side (error amplifier 350 side) of the resistor divider 320 to stabilize the feedback network. Can be provided.

  In addition, the local voltage supply unit 162 of the first example receives the output voltage or output current of the error amplification unit 350 at one input terminal IN1, and directly or indirectly sends an on / off control signal to the charge pump switch group 310. The switching control part 360 supplied as is provided.

  Here, the switching control unit 360 of the first example switches the boost signal generation unit 362 that generates the boost signal Bst, which is a characteristic part of this configuration example, and the output voltage control signal Sout that indicates the operating point in the control loop. It has a selection unit 364 and a periodic signal generation unit 370 that generates a predetermined periodic signal OSC such as a rectangular wave. The periodic signal OSC is supplied from the control output terminal O2 of the switching control unit 360 to the charge pump switch group 310.

  From the charge pump switch group 310, the pump capacitor 302, and the output capacitor 304 for generating the output voltage Vout as the local voltage based on the boost signal Bst corresponding to the trigger signal TRG by the boost signal generator 362 and the selector 364. An operating point switching unit that switches the operating point of the switching operation of the switching unit is configured.

  Here, the boost signal generating unit 362 synchronizes with the trigger signal (load fluctuation control signal; internal signal for transmitting an abrupt load) TRG indicating a trigger for performing an operation in which the load current of the local voltage supply unit 162 increases. The signal Bst is activated for a predetermined period.

  In the selection unit 364 of the first example, one input terminal IN1 is connected to the output of the error amplification unit 350, and the other input terminal IN2 is connected to the ground (GND). The selection unit 364 is configured such that the boost signal Bst generated by the boost signal generation unit 362 is supplied to its control input terminal, and is controlled by the output voltage Va of the error amplification unit 350 under the control of the boost signal Bst. Switching between control and control with a fixed potential of another system is performed.

  Specifically, when the boost signal Bst is inactive, the selection unit 364 of the first example selects and outputs the output voltage Va of the error amplification unit 350 to the control output terminal O1, while the boost signal Bst is active. In some cases, a fixed potential (ground voltage in this example) of a system different from that of the error amplifier 350 is selected and output to the control output terminal O1.

  When the operating point of the negative feedback control is forcibly switched, the boost signal Bst corresponding to the period in which a sudden load current is generated is effectively disconnected from the normal negative feedback control loop during the active period. Negative feedback control is performed so that the pump capacity 302 is switched at the maximum amplitude.

  Details of the functions of the boost signal generation unit 362 and the selection unit 364 will be described later.

  The periodic signal generator 370 outputs a signal waveform having a fixed frequency even when the power supply voltage changes. As the periodic signal generation unit 370, for example, a ring oscillation circuit, an unstable multivibrator circuit, a blocking oscillation circuit, or the like can be used. The power source of the periodic signal generation unit 370 may be the power source VDD from the external power source, similarly to the reference voltage generation unit 340, or may be the output voltage Vout at the output terminal c of the charge pump switch group 310 depending on the circuit configuration. Depending on the conditions of the output current and the pump capacity 302, the periodic signal generator 370 may be able to adjust the oscillation frequency according to a voltage given from the outside or a capacitance value connected to the outside.

  The charge pump switch group 310 includes four switches 311 to 314 and an inverter 316. The switches 311 to 314 can be configured by switch elements such as MOSFETs and bipolar transistors, for example.

  One input / output terminal of the switch 311 is grounded, one input / output terminal of the switch 312 is connected to the output terminal c, one input / output terminal of the switch 313 is connected to the power source VDD, and one input / output of the switch 314 is connected. The terminal is connected to one control output terminal O1 of the switching control unit 360, specifically, the output terminal of the selection unit 364, and is supplied with the output voltage control signal Sout in the control loop. The other input / output terminals of the switches 311 and 312 are connected to the capacity connection terminal a, and the other input / output terminals of the switches 313 and 314 are connected to the capacity connection terminal b.

  Further, the control terminals of the switches 311 and 313 are connected to the other control output terminal O2 of the switching control unit 360, specifically, the output terminal of the periodic signal generation unit 370, and are controlled in conjunction with each other. Yes. In addition, each control terminal of the switches 312 and 314 is connected to the other control output terminal O2 of the switching control unit 360 via the inverter 316, and is controlled in conjunction with the switches 311 and 313 in reverse polarity. ing.

  Although a detailed operation timing chart is omitted in the drawing, according to the connection mode of the charge pump switch group 310, when the switches 311 and 313 are on and the switches 312 and 314 are off, the pump capacitor 302 is charged from an external power source (not shown). The pump capacitor 302 is charged with a positive potential (power supply VDD) on the capacitor connection terminal b side and with a negative potential (ground) on the capacitor connection terminal a side. Thereafter, the switches 311 and 313 are turned off and the switches 312 and 314 are turned on, so that the charge charged in the pump capacitor 302 is transferred to the output capacitor 304. By repeating such an operation, a predetermined voltage appears at the output terminal c of the charge pump switch group 310, that is, the output capacitor 304, and a current can be supplied from the output capacitor 304 to the load. That is, the charge is not directly transferred from the external power source to the output capacitor 304.

  In the connection mode of the switches 311 to 314 of the charge pump switch group 310 of this example, when the charge charged in the pump capacitor 302 is transferred to the output capacitor 304, the output voltage Va of the error amplifier 350 is connected to the capacitor connection terminal b. The corresponding output voltage control signal Sout is supplied via the switch 314. At the capacitor connection terminal b, it appears as a switching signal CB between the output voltage control signal Sout and the power supply voltage VDD, the voltage appearing at the output capacitor 304 is negative, and the theoretical maximum output possible voltage value is −1 × VDD. It becomes.

  The configuration of the charge pump switch group 310 is not limited to the illustrated connection mode, and the output voltage value can be changed by appropriately changing the connection mode. For example, the maximum output voltage of the external power supply can be changed. It is also possible to obtain twice the voltage VDD.

  Further, the number of switches is not limited to four as in the illustrated charge pump switch group 310, and the maximum number of absolute values of the output voltage can be increased by increasing the number of switches and adopting a connection mode corresponding thereto. The value can be further increased.

  The overall control amplifier configuration centering on the error amplifier 350 is a negative feedback circuit, and the divided voltage (feedback voltage VFB) of the reference voltage Vref0 and the output voltage Vout divided by the resistance divider 320 is controlled. Will be.

  Therefore, by adjusting the division ratio of the reference voltage Vref0 by the reference voltage generation unit 340, the reference voltage Vrefout by the reference voltage generation unit 330, or the output voltage Vout by the resistance division unit 320, the output current supply capability and the output voltage value can be adjusted. Can be changed.

  The configuration of the local voltage supply unit 162 using the charge pump circuit shown here is merely an example, and various modifications are possible (for example, JP-A-6-351229 and JP-A-10-248240). Gazette and JP-A-2002-171748).

  Also, the local voltage supply unit 162 using the charge pump circuit transfers the charged charge to the pump capacitor 302 and performs n-fold voltage boosting corresponding to so-called n-fold voltage rectification, which is suitable for a relatively low power device. Compared to a chopper type, which will be described later, it is convenient in reducing the size and power consumption.

  When the local voltage supply unit 162 is configured using a charge pump circuit, the transistors to which a negative voltage is applied include the switches 311 and 312 in the local voltage supply unit 162 shown in FIG. 2 and the output buffer shown in FIG. There is an N-MOS that constitutes 161.

<Exposure time control function>
6 and 7 are diagrams for explaining an exposure control (electronic shutter) function in an XY address type imaging apparatus. As shown in FIG. 6, the vertical address setting unit 14 a of the vertical scanning unit 14 has a function of designating a normal readout target row address φTG, in addition to the row address of the shutter target unit pixel 3 (shutter pixel), that is, the shutter. It also has a function of generating address information (specifically, transfer gate pulses TGs as drive pulses) that specify pixel positions.

  The shutter timing control functional element of the vertical address setting unit 14a adopts a wiring configuration in which drive pulses (transfer pulses) φTGs that specify a row address to be shuttered are supplied to all unit pixels 3 in the same row. Thereby, the unit pixel 3 in the row designated by the drive pulse φTGs is designated as the shutter pixel.

  When a CMOS image sensor is used as a solid-state image sensor, generally, from the basic operation method, a pixel that outputs a signal starts accumulation of signal charges obtained by photoelectric conversion again from that point. For this reason, the accumulation period is shifted in accordance with the scanning timing of the imaging surface, that is, the accumulation period is shifted by the scanning time for each scanning line, which is so-called line exposure. Unlike CCD (Charge Coupled) type, global exposure that accumulates the light incident on the photoelectric conversion element during the same period as signal charge and reads it from all pixels to the vertical CCD at the same time to satisfy the simultaneous accumulation (Global Exposure) It is not.

  Here, for example, consider a case where the readout row n and the shutter row ns are separated by Δs rows in the imaging region. Since the accumulation of signal charges starts again after the pixel in the target column of row ns that has received the instruction of the electronic shutter is reset, for example, when the scanning direction of the imaging surface is from top to bottom, row n and row n + Δs The time difference has a predetermined relationship between the frame rate and the number of scanning lines, and by adjusting the interval between the readout row n and the shutter row ns, the accumulation time of the signal read from the CMOS image sensor is set to the line period (1 The horizontal scanning period) can be changed as an adjustment unit.

  Here, in a general CMOS sensor, at the time of imaging one screen, the electronic shutter control is performed in units of rows by setting one readout row n and one shutter row ns. For the readout row n at a certain point set by the vertical address setting unit 14a, the readout row for the pixels in all the columns (H1, H2,..., Hh) by the shutter timing control functional element of the vertical address setting unit 14a. The pixel is reset by setting the shutter row ns at any row position except n, that is, at a position (time point) separated by Δs rows. This reset operation can be realized by sweeping away the charge accumulated in the photoelectric conversion element before the shutter timing. In the case of a CMOS image sensor, for example, it can be realized by turning on the transfer gate.

  The time until the pixels in the shutter row ns are set to the next readout row n by the vertical address setting unit 14a is the accumulation time, that is, the time interval between the readout row n and the shutter row ns is the accumulation time. As a result, the accumulation time can be controlled in units of rows. When setting the normal exposure time, the shutter row ns is not accessed, and charges are accumulated for the time corresponding to the frame rate.

  As described above, by utilizing the characteristics of line exposure of the CMOS image sensor, the driving pulse φTGs for the electronic shutter is supplied to each unit pixel 3 in the row in units of rows, so that the readout row n and the shutter row n + Δs. Can be set for each unit pixel 3 in units of rows, and the accumulation time can be easily controlled for each row.

  However, as described above, the XY address type image pickup apparatus employs an accumulation sequential readout method in which each surface element is read out every accumulation frame time. In this case, the drive pulse φTGs is supplied in units of rows, so the accumulation simultaneous readout is performed. This method is greatly different from the CCD type, which is a global exposure (see FIG. 7D), and becomes a line exposure (also called rolling shutter or focal plane accumulation) (see the lower part of FIG. 7A). ).

  When the shutter speed is slow and the pixel accumulation time is set sufficiently long, the shift in the accumulation period can be ignored, but if the shutter speed is set so fast that it does not differ from the horizontal scanning period, the horizontal direction of the object Due to the difference between the movement and the scanning time point (accumulation period) (see FIG. 7B), as shown in FIG. 7C, the difference in the accumulation period is the time in the line direction (row direction; horizontal scanning direction). Shading distortion (also referred to as focal poon phenomenon) appears as a motion distortion in the image and becomes a problem.

  In order to solve this problem, an electronic shutter using a mechanical shutter is used to realize a function of a global shutter that makes the exposure accumulation period of each pixel constant (exposure at the same time), or unit pixel 3 For example, for each pixel, a charge storage unit is provided between the charge generation unit and the pixel signal generation unit, and after exposing all the pixels simultaneously, the signal charges generated in the charge generation unit are simultaneously A pure electronic global shutter that makes the exposure accumulation period of each pixel constant by performing an electronic shutter (see US Pat. No. 5,986,297) with a structure for transferring to a charge storage unit. Realize the function. In this embodiment, a global shutter function using a mechanical shutter is employed.

<Global shutter function>
8 and 9 are diagrams for explaining a global shutter function using a mechanical shutter together. For reference, a normal line exposure operation (normal electronic shutter operation) is also shown.

  The electronic shutter operation is divided into a charge accumulation period and a readout period, and all pixels in the same row perform processing at the same timing. Further, as shown in FIG. 8 (A), normal shutter mode in which accumulation and reading are performed by continuous operation for each row, and output is repeated for the number of rows, and as shown in FIG. 8 (B), There is a global shutter mode in which readout is performed row by row after charge accumulation is performed simultaneously for all pixels while using a mechanical shutter.

  In the normal shutter mode, first, charge accumulation is started after the charge diffusion section 32 formed of a photodiode or the like and the floating diffusion 38 constituting the pixel signal generation section 5 are reset. In the readout period after the completion of the charge accumulation, the signal charge detected and accumulated in the charge generation unit 32 is transferred to the floating diffusion 38 when the readout selection transistor 34 is turned on, and is transferred to the amplification transistor 42 and the vertical signal line 18. A signal voltage corresponding to the floating diffusion 38 is passed to the column signal processing unit 22 of the column processing unit 20 through the vertical signal line 18 by a source follower configured by a connected load transistor.

  On the other hand, in the global shutter mode, when the global shutter signal Shut is turned on, the reset is performed, and when the global shutter signal Shut is turned off, the charge accumulation in the charge generation unit 32 is performed at the same time. The subsequent readout period is the same as the control sequence for one row at the time of normal shutter. By repeating this for the number of rows, signals of all pixels are output to the column processing unit 20 side.

  Next, paying attention to the read selection transistor 34 (also referred to as a transfer gate or transfer transistor) of the unit pixel 3, a reset operation at the start of charge accumulation which is a problem will be described below.

  8A and 8B, timing charts of the transfer pulse φTG for driving the read selection transistor 34 and the reset pulse φRST for driving the reset transistor 36 are shown.

  First, at the start of reset, the read selection transistor 34 is turned on by the transfer pulse φTG, and the reset transistor 36 is turned on by the reset pulse φRST (t1). The charge generator 32 and the floating diffusion 38 are reset because dark charges are swept out to the power supply VDD side by this operation. Next, at time t2, when both the transfer pulse φTG and the reset pulse φRST are set to the L level, the read selection transistor 34 is turned off and charge accumulation in the charge generation unit 32 starts.

  FIGS. 9A and 9B are diagrams for explaining voltage fluctuations caused by load current fluctuations during the reset operation in the global shutter mode, which may occur in the local voltage supply unit 162. FIG. Here, in order to pay attention to the reset operation of the read selection transistor 34 and the reset transistor 36, the local voltage supply unit 162 outputs a negative voltage. In addition, the specific value of the negative voltage is set to −1.1V as disclosed in JP-A-2002-217397.

  At the time before starting the reset operation (before t1), the full load capacitance CQT of the read selection transistor 34 is connected to the local voltage supply unit 162. At the time point t1, the load capacitance CQT of the read selection transistor 34 is disconnected from the local voltage supply unit 162 at the moment when the transfer pulse φTG is set to the H level. At this time, the load of the output of the local voltage supply unit 162 is reduced, and the output voltage Vout slightly fluctuates. However, since it is disconnected from the read selection transistor 34, it does not appear as an image.

  Next, at time t2, the transfer pulse φTG is set to the L level, the reset is completed, and charge accumulation in the charge generation unit 32 is started. At this time, the load capacitance CQT of the read selection transistor 34 is connected to the local voltage supply unit 162 all at once. The load capacity CQT at this time is for all the pixels constituting the imaging unit 10 in the global shutter mode.

  Therefore, the reset operation before the accumulation period in the global shutter causes the local voltage supply unit 162 to give a large capacitance load fluctuation (capacity load corresponding to the total number of pixels) to the output, and the output current (load current) is increased. If the load current increases instantaneously and the load current changes greatly, the output voltage Vout also fluctuates due to a response delay of the control loop. In this example, there is a possibility that the negative voltage fluctuates in the direction of decreasing absolute value due to an increase in the capacitive load. In addition, this period corresponds to the charge accumulation time, and there is a possibility that an image with shading is generated due to dark current due to the voltage fluctuation period.

<Operation sequence of local voltage supply unit during global shutter>
FIG. 10 is a diagram illustrating an example of an operation sequence for explaining the influence on the local voltage supply unit 162 during the global shutter.

  In the local voltage supply unit 162 of this example, a negative feedback control loop by the error amplification unit 350 is configured to constantly stabilize the output voltage Vout so as to follow the load current fluctuation to some extent, It is unnecessary to separately provide a stabilization circuit after the local voltage supply unit 162. By eliminating the need for the stabilization circuit, the reactive power consumption can be made virtually zero.

  However, since the response to the change of the output voltage Vout is limited by the bandwidth of the control loop, particularly the bandwidth of the error amplifier 350, if the boost signal generator 362 and the selector 364 are not provided, a sudden load current fluctuation occurs. If so, it takes time for the output voltage Vout to return to the set voltage, and it is difficult to avoid fluctuations in the output voltage Vout due to momentary fluctuations in the load current.

  This will be described with reference to FIG. Simultaneously with the fall of the global shutter signal Shut, a negative voltage (for example, −1.1 V) is applied to the transfer gates (readout selection transistors 34) of all the pixels, so the load as the local voltage supply unit 162 increases instantaneously. Will do.

  For this reason, in the local voltage supply unit 162, the output voltage Vout fluctuates due to the movement of the charge from the output capacitor 304 to the load capacitor CQT, whereby the error amplifying unit 350 supplies the charge to the pump capacitor 302. An operation for decreasing the value Va is performed. Since the amplifier output value Va is connected to the switch 314, the L level of the switching signal CB for switching the pump capacitor 302 operates in the same manner as the output change of the error amplifying unit 350. By such a feedback operation, the output voltage Vout converges to the set value. Here, since the response of the output voltage Vout follows the response of the feedback loop, it is difficult to quickly restore the output voltage Vout.

  The problem of convergence of the output voltage Vout means that the negative voltage applied to the gate of the read selection transistor 34 as a transfer transistor becomes slow to become the set voltage, and is sufficiently negative to suppress the dark current. Since a voltage cannot be applied, a dark current may be generated, which may cause a problem of causing shading.

  As a mechanism for solving such a problem, the local voltage supply unit 162 of the first example is characterized in that a boost signal generation unit 362 and a selection unit 364 are provided in the switching control unit 360. . Hereinafter, these functions will be described.

<Details of boost signal generator>
FIG. 11 is a diagram for explaining the boost signal generation unit 362. Here, FIG. 11A is a diagram showing an example of the configuration, and FIG. 11B is a timing chart for explaining the operation. Here, an example in which the boost signal Bst is activated during the global shutter is shown.

  FIG. 12 is a timing chart for explaining the operation of the edge detection unit 710. For reference, FIG. 12A shows a form of this example for detecting the falling edge of the global shutter signal Shut, and FIG. 12B shows a form of detecting the rising edge of the global shutter signal Shut. .

  As shown in FIG. 11A, the boost signal generator 362 detects the falling edge of the global shutter signal Shut as the trigger signal TRG and outputs a one-shot pulse Edge synchronized with the falling edge. 710, a stop timing determination unit 720 that determines the timing for stopping the active state of the boost signal Bst, a boost signal based on the information detected by the edge detection unit 710 and the stop timing determined by the stop timing determination unit 720 And a pulse generation unit 730 for shaping Bst.

  The edge detection unit 710 includes four inverters 711, 712, 713, 714 connected in multiple stages, a NAND gate 715 arranged at the subsequent stage of the inverter 714, and an inverter 716 arranged at the subsequent stage of the NAND gate 715. ing. The edge detection unit 710 is arranged between a constant current source 717 that supplies a predetermined operating current to the third-stage inverter 713 and a connection point between the third-stage and fourth-stage inverters 713 and 714 and the ground. And a capacitor 718 for setting time.

  As the stop timing determination unit 720, the output voltage Va of the error amplification unit 350 is input to the inverting input terminal (−), the reference voltage Vref2 having a predetermined potential slightly higher than the ground voltage is input to the non-inverting input terminal (+), The comparator 722 outputs the comparison result between the output voltage Va and the reference voltage Vref2 as the reset signal RST.

  The pulse generation unit 730 includes a D-type flip-flop (D-FF) 732, and the one-shot pulse Edge output from the edge detection unit 710 is input from the power supply voltage VDD to the D input terminal. A reset pulse RST input to the clock terminal CK and generated by the stop timing determination unit 720 is input to the reset terminal R, and an active H boost signal Bst is output from the non-inverted output terminal Q.

  The boost signal generation unit 362 having such a configuration receives the global shutter signal Shut as the trigger signal TRG, and responds to the falling edge of the global shutter signal Shut in response to a boost signal for a certain period of time (this period is referred to as a boost period). Bst is set to active H (high level), and this boost signal Bst is supplied to the selection unit 364. That is, the boost signal Bst is set to active H in synchronization with the falling edge of the global shutter signal Shut, and the voltage output Va of the error amplifier 350 is compared with the reference voltage Vref2 slightly higher than the ground voltage. When inverted, the boost signal Bst becomes inactive L.

  Specifically, as shown in FIG. 11B, first, the edge detection unit 710 detects the falling edge of the global shutter signal Shut (t10), and determines the operating current from the constant current source 717 and the capacitor 718. A one-shot pulse Edge having a pulse width (t12 to t14) determined by the capacitance value is generated, and this one-shot pulse Edge is input to the clock terminal CK of the D-FF 732 (see FIG. 12A). As a result, in synchronization with the rising edge of the one-shot pulse Edge, the non-inverted output terminal Q of the D-FF 732, that is, the boost signal Bst becomes H level (t13). Note that t10 to t13 are due to the operation delay of the circuit, and in practice, it may be considered that t10 = t12 = t13.

  At this time, since the entire solid-state imaging device 1 performs the global shutter operation, the load current of the local voltage supply unit 162 increases, so the absolute value of the output voltage Vout tends to decrease. Since the control loop responds to the change in the output voltage Vout, the output voltage Va (hereinafter also referred to as an amplifier output value) Va of the error amplifying unit 350 changes in a direction to suppress the change in the output voltage Vout. However, the absolute value of the output voltage Vout clearly decreases due to the delay in the response of the control loop (t20 to t22). For example, -1.1V in a steady state changes to about -0.8V. At this time, the amplifier output value Va changes in a direction to suppress the change in the output voltage Vout. In response to the change in the amplifier output value Va, the amount of charge supplied to the pump capacitor 302 is increased, and as a result, the absolute value of the output voltage Vout is restored (t22 to t28).

  In parallel with this operation, the stop timing determination unit 720 compares the amplifier output value Va with the reference voltage Vref2, and during the period when the amplifier output value Va is equal to or lower than the reference voltage Vref2, the reset pulse RST is activated H (T24 to t26). Thereby, in synchronization with the rising edge of the reset pulse RST, the non-inverting output terminal Q of the D-FF 732, that is, the boost signal Bst becomes L level (t24).

  As a result, the D-FF 732 can generate a pulse signal at the non-inverted output terminal Q as the boost signal Bst that makes the period from the fall of the global shutter signal Shut to the rise of the reset pulse RST H level.

  On the other hand, since the control loop of the power supply operates independently of the boost signal generation unit 362, when the boost signal Bst becomes H level, the selection unit 364 of the switching control unit 360 shown in FIG. Is switched from an operation based on the amplifier output value Va to an operation based on a fixed voltage (ground voltage in this example).

  When the boost signal Bst returns to the L level (t24), that is, when the amplifier output value Va exceeds the ground voltage vicinity (reference voltage Vref2), the selection unit 364 sets the control loop to a fixed voltage (in this example). The operation based on the ground voltage is switched from the operation based on the amplifier output value Va. As a result, the local voltage supply unit 162 can return to the normal operation.

  In such a configuration of the boost signal generation unit 362, the stop timing determination unit 720 is provided, and the optimum boost period according to the actual working state is dynamically determined by comparing the output voltage Va and the reference voltage Vref2. The boost period can be set to a fixed value, for example, by checking the time during which the output voltage Vout can be stably controlled with the least amount of damping by actual evaluation and setting it as the boost period.

  In order to generate the boost signal Bst having such a fixed boost period, for example, in the configuration shown in FIG. 11A, the constant current value of the constant current source 717 and the capacitance value of the capacitor 718 are adjusted. Thus, the pulse width of the one-shot pulse Edge can be determined, and the one-shot pulse Edge itself can be used as the boost signal Bst. In this case, although the optimum boost period according to the actual working state cannot be dynamically determined, the stop timing determination unit 720 and the pulse generation unit 730 are not required, and thus the circuit area can be reduced. is there.

<Configuration Example of Selection Unit; Part 1>
FIG. 13 is a diagram illustrating a configuration example of the selection unit 364 used in the local voltage supply unit 162 of the first example. As shown in the figure, the selection unit 364 of the first example includes two transistors 602 and 604 and an inverter 606. The boost signal Bst is supplied from the boost signal generator 362 to the gate of the transistor 602 and the inverter 606, and the boost signal NBst logically inverted by the inverter 606 is supplied to the gate of the transistor 604.

  In addition, the output voltage Va of the error amplifying unit 350 is supplied to the drain terminal of the transistor 604 via the input terminal IN1, and a fixed potential (ground voltage in this example) is supplied to the drain terminal of the transistor 602 via the input terminal IN2. The source terminals of the transistors 602 and 604 are commonly connected to the switch 314 of the charge pump switch group 310 via the control output terminal O1.

  With this configuration, the selection unit 364 of the first example selects the output voltage Va of the error amplification unit 350 by turning off the transistor 602 and turning on the transistor 604 when the boost signal Bst is inactive. Output to the control output terminal O1. On the other hand, when the boost signal Bst is active, the transistor 602 is turned on and the transistor 604 is turned off, so that a fixed potential (ground voltage in this example) different from the error amplifier 350 is selected and the control output terminal O1. Output. As a result, the control based on the output voltage Va of the error amplifying unit 350 and the control based on a fixed potential of another system can be switched under the control of the boost signal Bst.

  That is, the selection unit 364 of the first example is generated by the boost signal generation unit 362 in synchronization with the trigger signal (load fluctuation control signal) TRG indicating a trigger for performing an operation in which the load current of the local voltage supply unit 162 increases. Controlled by boost signal Bst. For example, when a sudden load fluctuation may occur, such as during a global shutter, the boost signal Bst is activated to control from a control loop based on the output voltage Va of the error amplifying unit 350 in a steady state with a fixed potential of another system. Switch to loop.

<Operation sequence>
FIG. 14 is a diagram illustrating an example of a control loop switching operation sequence by the selection unit 364 in the local voltage supply unit 162 of the first example. Here again, an example in which the boost signal Bst is activated during the global shutter is shown.

  The selection unit 364 is supplied from the boost signal generation unit 362 with a boost signal Bst of active H for a certain time (boost period; t10, t13 to t24) from the fall of the global shutter signal Shut to the control input terminal.

  Since the selector 364 selects the amplifier output value Va when the boost signal Bst is inactive L, the control loop is controlled by the amplifier output value Va, and the switching signal CB for driving the pump capacitor 302 is the power supply voltage VDD and the amplifier. The switching operation is performed with the output value Va, and the pump capacitor 302 is charged with a predetermined level of charge. As a result, a predetermined level of the output voltage Vout is obtained.

  On the other hand, the selection unit 364 selects a fixed potential (ground voltage in this example) when the boost signal Bst is active H. Therefore, the control loop is controlled by the ground voltage, and the switching signal CB for driving the pump capacitor 302 is The switching operation is performed by the power supply voltage VDD and the ground voltage, and the pump capacitor 302 can be charged with the maximum charge. As a result, the local voltage supply unit 162 has a maximum current output capability.

  Therefore, the current supply capability of the local power supply can be increased by increasing the charge supply capability of the local power supply (the local voltage supply unit 162 in this example) simultaneously with the load fluctuation to the charge pump that may occur during the global shutter that requires the entire simultaneous shutter. As shown by the solid line in the figure, the load fluctuation of the output voltage Vout can be minimized as compared with the case where the present embodiment shown by the dotted line in the figure is not applied. That is, the load transient response of the output voltage Vout can be improved.

  The output capacitor 304, which is an external capacitor, is a source of instantaneous current supply to the load. However, by increasing the current supply capability of the local power supply, the output capacitor 304 can be quickly charged, resulting in output. A smaller capacitance value can be selected as the capacitor 304, and improvement in cost and layout can be expected.

<Configuration example of local voltage supply unit; Part 2>
FIG. 15 is a diagram illustrating a second configuration example of the local voltage supply unit 162. Similar to the first example, the second configuration example of the local voltage supply unit 162 (also referred to as the local voltage supply unit 162 of the second example) has a configuration using a charge pump circuit and the configuration of the switching control unit 360. Is different from the first example.

  First, the charge pump switch group 310 of the second example newly includes a switch 315 between the capacitor connection terminal b and the ground.

  The switching control unit 360 of the second example includes a selection unit 365 corresponding to the selection unit 364 in addition to the boost signal generation unit 362 and the periodic signal generation unit 370 having the same functions as the first example, and further includes an inverter 366. Newly prepared.

  In the selection unit 365 of the second example, the periodic signal OSCB obtained by logically inverting the periodic signal OSC output from the periodic signal generation unit 370 by the inverter 366 is input to the input terminal IN3, and the boost signal generation unit 362 generates the control input terminal. The boost signal Bst is supplied, a control signal S1 for controlling the switch 314 of the charge pump switch group 310 is output from one control output terminal O3, and a switch 315 of the charge pump switch group 310 is output from the other control output terminal O4. The control signal S2 for controlling the control signal is output, and the control loop is switched under the control of the boost signal Bst.

  Here, so as to correspond to the selection unit 365, the connection mode of the switches 313 and 314 of the charge pump switch group 310 is different from that of the first example. Specifically, the other input / output terminals of the switches 313 and 314 are connected to the capacitor connection terminal b and grounded via the switch 315, and the output voltage Va of the error amplifying unit 350 is output as it is. The voltage control signal Sout is supplied to the switch 314.

  Further, the switch 312 is independently connected to the control output terminal O2 of the switching control unit 360 via the inverter 316, the switch 314 is independently controlled by the control signal S1 from the selection unit 365, and the switch 315 is independently selected. It is controlled by a control signal S2 from 365.

  Specifically, the selection unit 365 makes the control signal S2 inactive when the boost signal Bst is inactive, and the periodic signal obtained by logically inverting the periodic signal OSC output from the periodic signal generation unit 370 by the inverter 366. The switch 314 is driven using the OSCB as the control signal S1. In effect, the switches 312 and 314 are controlled in conjunction with the reverse polarity of the switches 311 and 313.

  In this case, when the charge charged in the pump capacitor 302 is transferred to the output capacitor 304, the output voltage control signal Sout is supplied from the error amplifying unit 350 to the capacitor connection terminal b via the switch 314. In b, it appears as a switching signal CB between the output voltage control signal Sout and the power supply voltage VDD. Therefore, the control loop is controlled by the amplifier output value Va, and the pump capacitor 302 is charged with a predetermined level of charge. As a result, a predetermined level of the output voltage Vout is obtained.

  On the other hand, when the boost signal Bst is active, the selection unit 365 makes the control signal S1 inactive, and controls the periodic signal OSCB obtained by logically inverting the periodic signal OSC output from the periodic signal generation unit 370 by the inverter 366. The switch 315 is driven as S2. In effect, the switches 312 and 315 are controlled in conjunction with the switches 311 and 313 in reverse polarity.

  In this case, when the charge charged in the pump capacitor 302 is transferred to the output capacitor 304, a fixed potential (ground voltage in this example) is supplied to the capacitor connection terminal b via the switch 315. The control is performed with the ground voltage, and the switching signal CB for driving the pump capacitor 302 is switched with the power supply voltage VDD and the ground voltage, so that the pump capacitor 302 can be charged with the maximum charge. As a result, the local voltage supply unit 162 has a maximum current output capability.

  Therefore, also in the configuration of the second example, the charge supply capability of the local power source (the local voltage supply unit 162 in this example) is increased simultaneously with the load fluctuation to the charge pump that may occur at the time of the global shutter that requires the simultaneous shutter. The current supply capability of the local power supply can be increased, and the load fluctuation of the output voltage Vout can be minimized.

  In the configuration of the second example, since the capacitor connection terminal b and the output of the error amplifying unit 350 are directly connected, switching from the amplifier output value Va can be achieved by eliminating the selection unit 364 existing in the case of the first example. An increase in on-resistance to the signal CB can be prevented. Since it is possible to solve the problem that charges are not easily accumulated in the pump capacitor 302 due to the time constant effect due to the resistance component, as a result, the control dynamic range when the boost signal Bst is inactive can be widened. .

<Configuration Example of Selection Unit; Part 2>
FIG. 16 is a diagram illustrating a configuration example of the selection unit 365 used in the local voltage supply unit 162 of the second example. As shown in the drawing, the selection unit 365 of the second example is configured to include two NAND gates 612 and 614 and inverters 616, 618, and 619. The boost signal Bst is supplied from the boost signal generation unit 362 to one input terminal of the NAND gate 612 and the inverter 616, and the boost signal NBst logically inverted by the inverter 616 is supplied to one input terminal of the NAND gate 614. It has become. A periodic signal OSCB obtained by logically inverting the periodic signal OSC output from the periodic signal generation unit 370 by the inverter 366 is input to the other input terminals of the NAND gates 612 and 614, and the respective outputs are connected to the corresponding inverters 618, The signals logically inverted at 619 are output as control signals S1 and S2, respectively.

  With such a configuration, when the boost signal Bst is inactive, the selection unit 365 of the second example effectively switches only the output of the NAND gate 614 to the periodic signal OSCB as it is as the control signal S1. On the other hand, when the boost signal Bst is active, only the output of the NAND gate 612 becomes effective, so that the switch 315 is driven using the periodic signal OSCB as it is as the control signal S2. Therefore, under the control of the boost signal Bst, the control by the output voltage Va of the error amplifying unit 350 and the control by the fixed potential of another system can be switched.

  Therefore, when a sudden load fluctuation can occur, for example, at the time of a global shutter, the boost signal Bst is activated, so that the control loop based on the output voltage Va of the error amplifying unit 350 in a steady state can be changed to a fixed potential of another system. You can switch to the control loop.

<Configuration example of local voltage supply unit; Part 3>
FIG. 17 is a diagram illustrating a third configuration example of the local voltage supply unit 162. Similar to the first example, the third configuration example of the local voltage supply unit 162 (also referred to as the local voltage supply unit 162 of the third example) has a configuration using a charge pump circuit, and the error amplification unit 350 is digitally configured. It is characterized in that it is changed to a configuration that operates by signal processing. In addition, regarding the point which changes the error amplification part 350 to the structure which operate | moves by digital signal processing, it is not restricted to adding a change with respect to a 1st example, but omits illustration, but it is the same also about a 2nd example. You can make changes to

  First, the error amplifying unit 350 of the third example receives the feedback voltage VFB obtained by dividing the output voltage Vout by the resistor divider 320 at the inverting input terminal (−) instead of the operational amplifier (the operational amplifier OP), and generates a reference voltage. A comparator (COMP) 352 that receives the reference voltage Vref0 from the unit 340 at the non-inverting input terminal (+), compares them, and outputs a comparison signal Vcomp is used.

  The error amplifier 350 of the third example includes an up / down counter (referred to as a U / D counter) 354 that counts the number of pulses of the periodic signal OSC output from the periodic signal generator 370, and a U / D counter 354. An N-bit DA converter (DAC) 356 that converts numerical values (digital data) into an analog signal, and an analog signal output from the DA converter 356 are buffered and supplied to one input terminal IN1 of the selector 364. And a buffer amplifier 358.

  The U / D counter 354 switches the count mode based on the comparison signal Vcomp that is the comparison result of the comparator 352. Specifically, the up-count operation is performed when the comparison signal Vcomp is at the H level, and the down-count operation is performed when the comparison signal Vcomp is at the L level.

  As the buffer amplifier 358, an operational amplifier (operational amplifier OP) is used, and a voltage follower configuration in which the inverting output terminal (−) and the output terminal are directly connected is adopted. The analog signal from the DA conversion unit 356 is received by the non-inverting output terminal (+), and the buffered analog signal output is supplied to the input terminal IN1 of the selection unit 364.

  In such a configuration of the error amplifying unit 350, the comparator 352 compares the feedback voltage VFB obtained by dividing the output voltage Vout by the resistance elements 322 and 324 of the resistance dividing unit 320 with the reference voltage Vref0 to determine whether H (high) or L The (low) comparison signal Vcomp is output.

  When the output voltage Vout does not reach the negative set voltage at the time of start-up or the like, the comparison signal Vcomp of the comparator 352 becomes L level, and the U / D counter 354 at the next stage functions as a down counter, and the periodic signal generator 370 The periodic signal OSC is used as a clock input and is counted down by N bits. As a result, the N-bit DA converter 356 outputs an analog signal that continuously decreases. The continuously decreasing analog signal is input to the input terminal IN1 of the selection unit 364 via the buffer amplifier 358.

  At this time, if the boost signal Bst supplied to the control input terminal of the selection unit 364 is inactive L, an analog signal that continuously decreases is supplied to the switch 314 as it is. Due to this operation, the pump capacitor 302 is charged with a larger amount of charge, so that the output voltage Vout approaches a negative set voltage. Since the comparison signal Vcomp of the comparator 352 is inverted when the output voltage Vout exceeds the negative set voltage, the U / D counter 354 switches to the up-count mode, and the local voltage supply unit 162 as a whole operates in reverse. That is, by performing an operation based on the continuously rising analog signal, the output voltage Vout is moved away from the negative set voltage. By repeating this operation, the local voltage supply unit 162 can supply a constant output voltage Vout to the load.

  As described above, the configuration in which the error amplifying unit 350 is operated by digital signal processing makes it easier to perform a stable operation without causing problems such as an oscillation phenomenon as compared with the case of operating by analog signal processing. Further, since the stop and start of the operation can be controlled relatively freely, noise generated by switching on / off of each of the switches 311 to 314 (also 315 in the second example) of the charge pump switch group 310 is imaged. It can be difficult to appear.

  That is, in the switched capacitor type (charge pump type) DC-DC converter, the pump capacitor 302 is connected to the input side power supply line VDD by switching on / off of the switch. Noise is generated at a high level on the side power supply line VDD, which can appear in the image. In order to avoid this, for example, by causing the U / D counter 354 to stop during the video period and to operate during the video blanking period, it is possible to prevent noise generation during switching from appearing in the video.

  Although the inversion operation charge pump has been described above as an example, it is expected that the load transient response of the output voltage Vout can be improved by configuring the charge pump in the boost operation in the same manner. In addition, the global shutter operation that drives all pixels has been described as an example of a sudden load fluctuation. However, the transfer transistor (read selection) is different from the normal shutter mode, such as the window mode in which a part of the image is cut out. Even in a mode in which the number of transistors 34) for driving is large, it is possible to suppress the fluctuation of the negative voltage by using the control described in the above embodiment. Other examples will be described below.

<Configuration example of local voltage supply unit; 4>
18 and 19 are diagrams illustrating a fourth configuration example of the local voltage supply unit 162. FIG. The fourth example is an example in which the local voltage supply unit 162 is applied to a reset power supply that supplies a predetermined power supply voltage to the reset transistor 36. Here, FIG. 18 is a diagram for explaining the relationship of the reset power supply. FIG. 19 is a diagram illustrating a configuration example of the local voltage supply unit 162 applied to the reset power source.

  As shown in FIG. 18A, the output terminal of the local voltage supply unit 162 is connected to the drain terminal of the reset transistor 36 so that a local voltage (hereinafter referred to as an internal voltage VINT) is supplied to the reset transistor 36. . As the internal voltage VINT, when the power supply voltage VDD is 3.0 V, a positive voltage (for example, 2.5 V) slightly lower than the power supply voltage VDD or a positive voltage (for example, 3.5 V) slightly higher than the power supply voltage VDD is used. Can be taken.

  Here, as a case of adopting a step-down type having a positive voltage slightly lower than the power supply voltage VDD, a case where a voltage lower than the power supply voltage VDD is used when the withstand voltage of the floating diffusion 38 is severe is considered. That is, since the voltage of the transfer gate (read selection transistor 34) is a negative voltage, if the potential difference between the floating diffusion 38 and the transfer gate becomes large, there is a concern about leakage or destruction of the oxide film in the floating diffusion 38, so only the reset voltage is used. Is kept lower than the power supply voltage VDD to solve the problem of withstand voltage.

  On the other hand, as a case of adopting a step-up type in which the positive voltage is slightly higher than the power supply voltage VDD, a case where a voltage higher than the power supply voltage VDD is used as the reset voltage can be considered when a dynamic range is desired. By making only the reset voltage higher than the power supply voltage VDD, the dynamic range can be improved by suppressing the influence of the drop in the threshold voltage Vth of the amplifying transistor 42 configured as the source follower.

  Here, at the time of the global shutter, the read selection transistor 34 and the reset transistor 36 are turned on at the same time, and a sudden load current flows to the reset power source. Therefore, the internal voltage VINT of the reset power supply changes due to a sudden load change, and this appears in the image.

  For example, the charge amount of all the pixels when the saturation signal max (10000e) is assumed is QA [e]. The charge amount QB in the output capacitor 304 (capacitance value Cout) is VDD * Cout * 6.02 * 10 ^ 18 [e], and QA / QB is a voltage drop due to load fluctuation. Reset power fluctuation of about 100 mV occurs at about 1A.

  In order to avoid this problem, by applying the local voltage supply unit 162 that performs the operation according to the operation described in the above embodiment as the reset power supply, even when a sudden load fluctuation occurs in the reset power supply during the global shutter, The load fluctuation of the internal voltage VINT can be minimized. That is, the load transient response of the internal voltage VINT can be improved.

  The local voltage supply unit 162 applied to such a reset power source may be configured as shown in FIG. 19, for example. The difference from the configuration of the first example shown in FIG. 5 is that the supply voltage to the input terminal IN2 of the selection unit 364 is changed in accordance with the fact that the output voltage Vout is not a negative voltage but a positive voltage, The connection mode of the switches 311 and 313 of the pump switch group 310 is changed. Here, the reference voltage generation unit 330 is removed and the second resistance element 324 of the resistance division unit 320 is directly grounded, but the reference voltage generation unit 330 may be provided.

  Specifically, first, the selection unit 364 causes the power supply voltage VDD to be supplied to the input terminal IN2. In addition, one input / output terminal of the switch 313 is grounded, and one input / output terminal of the switches 311 and 314 is common to the control output terminal O1 of the switching control unit 360, specifically, the output terminal of the selection unit 364. Connect. Other points are the same as in the first example.

  In this case, the timing at which the boost signal Bst is set to active H is when the read selection transistor 34 and the reset transistor 36 are simultaneously turned on. Specifically, as shown in FIG. A predetermined period from the rise of the global shutter signal Shut.

  As estimated from FIG. 18B, in this example, the active period width of the global shutter signal Shut, which is an example of the trigger signal TRG indicating the trigger of the load current fluctuation, and the active period of the boost signal Bst Depending on the width relationship, that is, if the active period widths of both are substantially the same, the global shutter signal Shut itself can be used as the boost signal Bst.

  In order to generate the boost signal Bst having such timing, the boost signal generation unit 362 detects the rising edge of the global shutter signal Shut in the configuration shown in FIG. What is necessary is just to change to the structure which outputs the one-shot pulse Edge synchronized with the edge, and what is necessary is just to change the NAND gate 715 to an OR gate (refer FIG. 12 (B)).

<Example of configuration of local voltage supply unit; Part 5>
FIG. 20 is a diagram illustrating a fifth configuration example of the local voltage supply unit 162. The fifth configuration example of the local voltage supply unit 162 (also referred to as the local voltage supply unit 162 of the fifth example) is characterized in that a chopper type (PWM control inversion type) DC-DC converter using a coil is used. Have.

  That is, as illustrated, the local voltage supply unit 162 of the fifth example is disposed between the switching transistor 402 made of a MOS-FET or the like, the coil 404, the flywheel diode 406, the output terminal, and the ground. And an output capacitor 408. The source terminal S of the switching transistor 402 is connected to the power supply VDD, and the drain terminal D is connected to the ground (GND) via the coil 404. The flywheel diode 406 has a cathode terminal connected to the drain terminal D of the switching transistor 402 and an anode terminal connected to the output terminal, that is, the output capacitor 408.

  The local voltage supply unit 162 of the fifth example includes a resistance dividing unit 420 including a first resistance element 422 (resistance value R1) and a second resistance element 424 (resistance value R2) that divides the output voltage Vout. And a reference voltage generator 430 that sets a reference voltage Vrefout for the resistor divider 420. The resistor divider 420 has the same function as the resistor divider 320, and the reference voltage generator 430 has the same function as the reference voltage generator 330.

  Further, the local voltage supply unit 162 of the fifth example has a reference voltage generation unit 440 that generates the reference voltage Vref0 and a feedback voltage VFB obtained by dividing the output voltage Vout by the resistance division unit 320 at the non-inverting input terminal (+). And an error amplification unit (error amplifier unit) 450 that receives the reference voltage Vref0 from the reference voltage generation unit 340 at the inverting input terminal (−) and amplifies or attenuates the difference between the feedback voltage VFB and the reference voltage Vref0. . The reference voltage generator 440 has the same function as the reference voltage generator 340, and the error amplifier 450 has the same function as the error amplifier 350.

  The local voltage supply unit 162 of the fifth example receives the output voltage or output current of the error amplification unit 450 at one inverting input terminal (−), and directly or indirectly turns on / off the switching transistor 402. A PWM (Pulse Width Modulation) controller 460 that functions as an on / off controller supplied as a control signal, and a period for supplying a predetermined periodic signal such as a triangular wave to the non-inverting input terminal (+) of the PWM controller 460 A signal generation unit 470 and a DTC generation unit 480 that supplies a DTC (dead time control) signal including a soft start function to the other inverting input terminal (−) of the PWM control unit 460 are provided.

  Furthermore, as a maximum feature point of this configuration example, a boost signal generation unit 462 having the same function as the boost signal generation unit 362 and a selection unit 464 having the same function as the selection unit 364 are provided. The selection unit 464 is disposed between the output of the error amplification unit 450 and one inverting input terminal (−) of the PWM control unit 460.

  By the boost signal generation unit 462 and the selection unit 464, the switching transistor 402, the coil 404, the flywheel diode 406, the output capacitance for generating the output voltage Vout as the local voltage based on the boost signal Bst corresponding to the trigger signal TRG An operating point switching unit that switches the operating point of the switching operation of the switching unit 408 is configured.

  In the selection unit 464 of the fifth example, the output voltage Va of the error amplification unit 450 is supplied to one input terminal IN1, and a fixed potential (power supply voltage VDD in this example) is supplied to the other input terminal IN2, and its control output The output voltage control signal Sout is supplied from the terminal O1 to the PWM controller 460.

  The selection unit 464 is supplied with the boost signal Bst generated by the boost signal generation unit 462 at its control input terminal, and is controlled by the output voltage Va of the error amplification unit 450 under the control of the boost signal Bst. Switching between control and control using a fixed potential of another system (in this example, the power supply voltage VDD) is switched.

  Specifically, when the boost signal Bst is inactive, the selection unit 464 of the fifth example selects and outputs the output voltage Va of the error amplification unit 450 to the control output terminal O1, while the boost signal Bst is active. In some cases, a fixed potential (in this example, the power supply voltage VDD) of a system different from that of the error amplifier 450 is selected and output to the control output terminal O1. In other words, based on the trigger signal TRG indicating the trigger of overload such as during global shutter, the control loop is changed from the operation based on the amplifier output value Va according to the boost signal Bst that is active H only for a predetermined period (boost period). The operation is switched to an operation based on an arbitrary fixed voltage (which may be an arbitrary voltage higher than the DTC level, which is the power supply voltage VDD in this example).

  Although not shown, the periodic signal generation unit 470 includes, for example, a cascade connection circuit of three resistance elements that perform a voltage dividing function with respect to the reference voltage Vrefout from the reference voltage generation unit 430, and a cascade connection circuit of the resistance elements. Two comparators that compare two voltage dividing points with the generated periodic signal OSC (for example, triangular wave), RS latch that receives each output of this comparator, cascaded between power supply and ground, and controlled by the output of RS latch Inverter, a power source for supplying a constant current to the inverter, two constant current power sources connected to the ground side, and a capacitor.

  Although not shown, the DTC generation unit 480 includes, for example, a cascade connection circuit of two resistance elements that perform a voltage dividing function with respect to the reference voltage Vrefout from the reference voltage generation unit 430, and a cascade connection circuit of resistance elements. The capacitor includes a capacitor connected between the voltage dividing point and the ground, and a switching transistor that receives the supply of the low voltage malfunction prevention release delay signal and controls the voltage dividing point of the cascade connection circuit of the resistor elements.

  The DTC level can be freely changed by adjusting the resistance division ratio of the two resistance elements. The soft start can be freely changed by adjusting the capacitance value of the capacitor. The two resistance elements and capacitors can be so-called external discrete parts, or can be actively adopted as external parts. By using external parts, the dead time and soft start can be adjusted externally.

  The PWM control unit 460 compares the output of the error amplification unit 450 with the periodic signal OSC such as a triangular wave supplied from the periodic signal generation unit 470 and the DTC voltage including the soft start function supplied from the DTC generation unit 480. The output of the pulse signal by controlling the duty width is constituted by a comparator as an example.

  The pulse signal with the controlled duty width output from the PWM control unit 460 is supplied to the gate terminal of the switching transistor 402 via the output buffer 490. The output buffer 490 can include a function of controlling the output of the pulse signal whose duty width is controlled based on the low voltage malfunction prevention signal.

  Although a detailed operation timing chart is omitted, the local voltage supply unit 162 of the fifth example having such a configuration functions as a DC-DC converter that performs a step-up operation by turning on / off the switching transistor 402 by PWM control. To do. At this time, the DTC control by the DTC generation unit 480 suppresses a change in the maximum duty ratio of the pulse to avoid a malfunction at the time of power-on.

  That is, the detection voltage obtained by dividing the output voltage Vout by the resistance divider 420 is used to perform the operation of outputting the voltage after adjusting the supplied voltage by changing the ratio of the ON / OFF period of the switching transistor 402. Any of the DTC voltage value that combines the output voltage of the error amplifier 450 that amplifies and outputs the difference of the feedback voltage VFB from the reference voltage Vref0 and the voltage value that determines the upper limit value of the duty ratio of the switching transistor 402 and the soft start time. The PWM control unit 460 compares the voltage on the lower side with the voltage value of the periodic signal OSC such as a triangular wave, and the chopper type boosting switching regulator adopts the PWM control technique for controlling the switching of the switching transistor 402. .

  In this chopper type step-up switching regulator, when the switching transistor 402 is turned on by a pulse PWM-controlled by the PWM controller 460, a switch is made from the input voltage (power supply voltage VDD in this example) to the coil 404. A current flows, energy is stored in the coil 404, and when the switching transistor 402 is turned off, a current that retains the energy stored in the coil 404 is rectified by the flywheel diode 406, and the output is output to the output capacitance. The step-up operation is performed by smoothing at 408.

  At this time, in the PWM switching regulator, a dead time control voltage (DTC voltage) is set for limiting the duty ratio of the output pulse in order to determine the maximum pulse width in order to determine the maximum ON time of the switching transistor 402. Is done.

  As a feature of the fifth example using such a chopper type DC-DC converter, it is not suitable for downsizing and low power consumption compared with a configuration using a charge pump circuit, but it has a relatively large power. Suitable for.

  In addition, the voltage (VH, VL) that determines the upper limit value and lower limit value of the periodic signal OSC such as a triangular wave and the voltage that determines the DTC voltage are determined by a cascade connection circuit of three resistance elements from the same reference voltage generation unit 430. Since it can be created by resistance voltage division, the periodic signal OSC and the maximum duty are synchronized, and variations in the maximum duty can be prevented.

  In addition, in order to prevent malfunction due to the low voltage malfunction prevention signal, if a low voltage malfunction prevention release delay signal having a certain delay is used as a circuit start signal, this low voltage malfunction prevention release delay signal When the switching transistor connected to the DTC voltage is turned off, the voltage gradually rises to perform a soft start function, and then reaches a voltage value that determines the maximum duty. That is, since the reference voltage that determines the upper and lower limits of the periodic signal OSC such as a triangular wave is not controlled by the low voltage malfunction prevention release delay signal, it rises before the low voltage malfunction prevention release delay signal, while the DTC voltage is released from the low voltage malfunction prevention release It rises after the delay signal, and becomes a voltage value that determines the maximum duty after the soft start period.

  Note that the configuration of the chopper-type local voltage supply unit 162 using the coil shown here is merely an example, and various modifications are possible (see, for example, JP-A-2004-40859).

<Operation sequence>
FIG. 21 is a diagram illustrating an example of an operation sequence of the local voltage supply unit 162 of the fifth example. Here, FIG. 21A shows an operation state when the selection unit 464 is not provided, and FIG. 21B shows an operation state when the selection unit 464 is provided. In both cases, the boost signal Bst is activated at the time of the global shutter.

  The local voltage supply unit 162 of the fifth example is a negative feedback circuit as a whole control amplifier configuration centering on the error amplification unit 450 and the PWM control unit 460, and is a resistance of the reference voltage Vref0 and the output voltage Vout. The divided voltage (feedback voltage VFB) by the dividing unit 420 is controlled to be equal. Therefore, by adjusting the division ratio of the reference voltage Vref0 by the reference voltage generator 440, the reference voltage Vrefout by the reference voltage generator 430, or the output voltage Vout by the resistor divider 420, the output current supply capability and the output voltage value can be adjusted. Can be changed.

  For example, the error amplifying unit 450 compares the feedback voltage VFB and the reference voltage Vref0 resistance-divided by the resistance dividing unit 420 between the output voltage Vout and the reference voltage Vrefout, and the output voltage Vout has not reached the set voltage. Sometimes the output voltage Va of the error amplifier 450 increases.

  When the selection unit 464 is not provided and the output of the error amplification unit 450 and one inverting input terminal (−) of the PWM control unit 460 are directly connected, as shown in FIG. The PWM control unit 460 compares the value Va with a DTC level that determines the maximum on-time of the switching transistor 402 and a periodic signal OSC such as a triangular wave, and the PWM signal as a result of the comparison is sent via the output buffer 490 to the switching transistor. The gate of 402 is driven. When the output voltage Vout is at the set voltage, the PWM control unit 460 drives the switching transistor 402 with a constant pulse width that is a constant frequency.

  Here, an operation when there is a sudden load change at the time of a global shutter or the like will be described. As shown in FIG. 21A, the output voltage Vout undergoes a change in which the absolute value decreases due to a rapid load fluctuation. However, due to the band of the error amplifying unit 450, the amplifier output value Va does not increase immediately, and the output voltage Vout is returned to the set voltage again with a slow fluctuation. As a result, the output voltage Vout fluctuates to a certain level, and the absolute value of the negative voltage becomes small. As a result, dark current increases and shading may occur.

  On the other hand, in the local voltage supply unit 162 of the fifth example, the selection unit 464 is provided, and the active voltage is set to active H during the boost period based on the trigger signal TRG indicating the trigger for overload such as during global shutter. The control loop can be switched from an operation based on the amplifier output value Va to an operation based on an arbitrary fixed voltage according to the boost signal Bst. As a result, the PWM control unit 460 selects the maximum width set by the DTC level for the ON time of the switching transistor 402.

  Therefore, also in the fifth example, the current supply of the local power supply is increased by increasing the charge supply capability of the local power supply (the local voltage supply unit 162 in this example) simultaneously with the load fluctuation that may occur at the time of the global shutter that requires the entire simultaneous shutter. The capacity can be increased instantaneously, and the load fluctuation of the output voltage Vout can be minimized as shown by the solid line in the figure, compared to the case where the present embodiment shown by the dotted line in the figure is not applied. That is, the load transient response of the output voltage Vout can be improved.

  Here, as in the first example, in order to prevent dark current of the transfer gate, a chopper type using a coil (PWM control inversion type) is applied to the case where the L level voltage for controlling the transfer gate is set to a negative voltage. The chopper type (PWM control inversion type) DC-DC converter using a coil is similar to the fourth example in that the internal voltage VINT connected to the reset transistor is used. The present invention can also be applied to a step-down type or step-up type reset power supply as a method for improving current supply capability, and the same effect as in the fourth example can be enjoyed.

<Window mode>
In the above embodiment, the case of performing a global shutter operation that satisfies the simultaneous synchronization by reading signals from all pixels simultaneously as a load current variation factor has been described. There are various things. In either case, the operation of the control loop is based on the boost signal Bst that is active for a predetermined period in synchronization with the trigger signal (load fluctuation control signal) TRG indicating the trigger for the operation of increasing the load current of the local voltage supply unit 162. By switching the voltage, the load fluctuation of the output voltage Vout can be minimized.

  For example, FIG. 23 is a diagram illustrating a window mode in which a part of an image is cut out and used. In this window mode, the center part of the figure is used as the actual use area. At this time, the shutter operation is performed for pixels other than the cut-out area (the hatched part including the actual use area) in the figure. The charge is swept away by performing all the pixels simultaneously. For this reason, although not as much as in the global shutter mode, a mode in which the transfer transistor (reading selection transistor 34) is driven more than in the normal shutter mode is set, and a load fluctuation of the output voltage Vout may occur. Therefore, the fluctuation of the output voltage Vout can be suppressed by using the control described in the above embodiment in the window mode.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, a sensor composed of unit pixels composed of NMOS has been described as an example. However, the present invention is not limited to this. By conversely, it is possible to enjoy the same operations and effects as described in the above embodiment. Of course, the signal charge is not limited to electrons (electrons) but may be holes. When the signal charges are holes, the dark current is reduced by setting the gate voltage of the transfer transistor to a positive voltage. To do.

  In the above-described embodiment, one photodiode and four transistors are described as an example. However, the present invention is not limited to this. For example, a reset transistor may be used for two photodiodes and two readout selection transistors. In principle, the same applies to pixels that operate in a similar manner.

  In the above embodiment, attention has been paid to the dark current suppression under the transfer gate in the pixels of the 4TR configuration. In order to improve the characteristics other than the dark current under the transfer gate, such as a local power supply for generating a driving voltage supplied to a predetermined transistor, the boost signal Bst described in the above embodiment is used. Thus, a mechanism for minimizing the load fluctuation of the output voltage Vout by switching the operation voltage of the control loop can be similarly applied.

  In short, in the case of adopting a configuration in which a local voltage is supplied to a predetermined terminal of a transistor in order to improve a predetermined characteristic, when the local voltage can change due to a rapid load fluctuation, the load fluctuation of the local voltage is minimized. In order to suppress this, a mechanism for switching the operation voltage of the control loop based on the boost signal Bst that is active for a predetermined period corresponding to the trigger signal TRG indicating the trigger of the load current fluctuation may be adopted.

  It should be noted that a mechanism for switching the operating voltage of the control loop based on the boost signal Bst that is active for a predetermined period corresponding to the trigger signal TRG indicating the trigger of the load current fluctuation may be adopted. Can also be used as Bst. The boost signal Bst in the present application includes the trigger signal TRG in such a case.

  Further, in the above embodiment, the negative feedback control is performed so that the boost signal Bst corresponding to the period in which the abrupt load current is generated is separated from the normal negative feedback control loop and switched with the maximum amplitude during the active period. However, dynamic control may be performed so that switching is performed with an amplitude having a magnitude corresponding to the load current at that time.

  In the above embodiment, the CMOS type solid-state imaging device that is sensitive to electromagnetic waves input from the outside such as light and radiation is exemplified. However, in any of the above embodiments, any device that detects a change in physical quantity can be used. The described mechanism can be applied, and is not limited to light or the like. For example, a fingerprint authentication device that detects fingerprint images based on changes in electrical characteristics or optical characteristics based on pressure for information related to fingerprints (Japanese Patent Application Laid-Open No. 2002-7984). In other mechanisms for detecting physical changes, such as JP-A-2001-125734, etc., in order to minimize the load fluctuation of the local voltage, a predetermined value corresponding to the trigger signal TRG indicating the trigger of the load current fluctuation is used. It is also possible to adopt a mechanism for switching the operating voltage of the control loop based on the boost signal Bst that is active during the period.

FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device which is an embodiment of an imaging device according to the present invention. It is a figure which shows the structural example of a unit pixel. It is a figure which shows the basic structural example for applying a local voltage. It is a figure explaining the method of driving a transistor so that a low level may become a negative voltage. It is a figure which shows the 1st structural example of a local voltage supply part. It is FIG. (1) explaining the exposure control (electronic shutter) function in an XY address type imaging device. It is FIG. (2) explaining the exposure control (electronic shutter) function in an XY address type imaging device. It is FIG. (1) explaining the global shutter function which used a mechanical shutter together. It is FIG. (2) explaining the global shutter function which used a mechanical shutter together. It is a figure which shows an example of the operation | movement sequence explaining the influence which acts on a local voltage supply part at the time of a global shutter. It is a figure explaining a boost signal generation part. It is a timing chart explaining operation of an edge detection part. It is a figure which shows one structural example of the selection part used for the local voltage supply part of a 1st example. It is a figure which shows an example of the switching operation sequence of the control loop by the selection part in the local voltage supply part of a 1st example. It is a figure which shows the 2nd structural example of a local voltage supply part. It is a figure which shows one structural example of the selection part used for the local voltage supply part of a 2nd example. It is a figure which shows the 3rd structural example of a local voltage supply part. It is FIG. (1) explaining the 4th structural example of a local voltage supply part. It is FIG. (2) explaining the 4th structural example of a local voltage supply part. It is a figure which shows the 5th structural example of a local voltage supply part. It is a figure which shows an example of the operation | movement sequence of the local voltage supply part of a 5th example. It is a figure which shows the structural example of the conventional local voltage supply part using a charge pump circuit. It is a figure explaining the window mode which cuts out and uses a part of image.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 3 ... Unit pixel, 5 ... Pixel signal generation part, 7 ... Drive control part, 10 ... Imaging part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 15 ... Vertical control line, 16 ... Drive Signal operation unit, 18 ... vertical signal line, 20 ... column processing unit, 22 ... column signal processing unit, 32 ... charge generation unit, 34 ... read selection transistor, 36 ... reset transistor, 38 ... floating diffusion, 40 ... vertical selection Transistor, 42 ... amplifying transistor, 86 ... horizontal signal line, 88 ... output circuit, 150 ... transfer drive buffer, 152 ... reset drive buffer, 154 ... selection drive buffer, 160 ... level shifter, 161 ... output buffer, 162 ... local Voltage supply unit 302 ... pump capacity 304 ... output capacity 310 ... charge pump switch group 311 to 314 ... , 320: resistance dividing unit, 330: reference voltage generating unit, 340 ... reference voltage generating unit, 350 ... error amplifying unit, 360 ... switching control unit, 362 ... boost signal generating unit, 364, 365 ... selection unit, 370 ... Periodic signal generation unit, 382 ... gain phase correction unit, 402 ... switching transistor, 404 ... coil, 406 ... flywheel diode, 408 ... output capacitance, 420 ... resistance division unit, 430 ... reference voltage generation unit, 440 ... reference voltage generation 450, error amplification unit, 460 ... PWM control unit, 462 ... boost signal generation unit, 464 ... selection unit, 470 ... periodic signal generation unit, 480 ... DTC generation unit, 490 ... output buffer

Claims (3)

Has a plurality of unit elements comprising a unit signal generator for outputting a unit signal on the basis of the physical quantity of change detected by the detecting section you detect a change in physical quantity and said detection portion, the plurality of unit components an imaging equipment disposed in a predetermined order,
A local voltage supply unit that generates and supplies a local voltage different from a normal operating voltage supplied to most other members to predetermined terminals of various members constituting the unit component,
The local voltage supply unit is configured to be able to switch an operation voltage of a control loop that generates the local voltage based on a boost signal that is active for a predetermined period corresponding to a trigger signal indicating a trigger of load current fluctuation ,
The local voltage supply unit
A switching unit that performs a switching operation;
A detection unit for detecting the magnitude of the local voltage generated by the switching operation of the switching unit;
A reference voltage generator for generating a reference voltage;
The magnitude of the local voltage detected by the detector is compared with the reference voltage generated by the reference voltage generator, and the magnitude of the local voltage is maintained at a predetermined value based on the comparison result. An error amplification unit to
An operating point switching unit that is arranged between the error amplifying unit and the switching unit and switches an operating point of the switching operation for generating the local voltage based on the boost signal;
Have
The operating point switching unit selects a voltage corresponding to a comparison result of the error amplifying unit as an operating voltage of a control loop that generates the local voltage during a period in which the boost signal is inactive, and the boost signal is active In this period, the operating point of the switching operation is switched by selecting a power supply voltage or a ground voltage as the operating voltage of the control loop that generates the local voltage.
Imaging device . The error amplifier is composed of a digital signal processing circuit.
The imaging device according to claim 1 . There are a plurality of unit components including a detection unit that detects a change in physical quantity and a unit signal generation unit that outputs a unit signal based on the change in physical quantity detected by the detection unit. A local voltage supply unit arranged in order and generating and supplying a local voltage different from a normal operating voltage supplied to most other members to predetermined terminals of various members constituting the unit component ,
The local voltage supply unit is configured to be able to switch an operation voltage of a control loop that generates the local voltage based on a boost signal that is active for a predetermined period corresponding to a trigger signal indicating a trigger of load current fluctuation,
The local voltage supply unit includes a switching unit that performs a switching operation, a detection unit that detects the magnitude of the local voltage generated by the switching operation of the switching unit, a reference voltage generation unit that generates a reference voltage, The magnitude of the local voltage detected by the detector is compared with the reference voltage generated by the reference voltage generator, and the magnitude of the local voltage is maintained at a predetermined value based on the comparison result. And an operating point switching unit that is disposed between the error amplifying unit and the switching unit and switches an operating point of the switching operation for generating the local voltage based on the boost signal.
A power supply method used in an imaging apparatus,
The operating point switching unit selects a voltage corresponding to a comparison result of the error amplifying unit as an operating voltage of the control loop that generates the local voltage during a period in which the boost signal is inactive, and the boost signal is active In this period, the operating point of the switching operation is switched by selecting a power supply voltage or a ground voltage as the operating voltage of the control loop that generates the local voltage.
Power supply method for an imaging device.

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