JP2020025249A - Solid-state imaging device, driving method of the same, and electronic apparatus - Google Patents

Abstract

To provide a solid-state imaging device capable of achieving high-speed charging and capable of reducing power consumption with a simpler circuit and smaller area, a driving method of the same, and an electronic apparatus.SOLUTION: A voltage supply unit 320 includes: an external capacitor Cext31 in which a first electrode EL31 is connected to a first node ND31 and a second electrode EL32 is connected to a second node ND32; a first switch SW31 connected between a first power supply potential vaa and the first node ND31; a second switch SW32 connected between the second power supply potential vgnd and the second node ND32; and a third switch SW33 connected between the first power supply potential vaa and the second node ND32. The first node ND31 is connected to a first power supply voltage terminal TVAA of a row driver 310.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus.

As a solid-state imaging device (image sensor) using a photoelectric conversion element that generates light by detecting light, a CMOS (Complementary Metal Oxide Semiconductor) image sensor has been put to practical use.
CMOS image sensors are widely applied as a part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones. I have.

  The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD: Floating Diffusion) for each pixel, and reads one row in the pixel array for reading. A column parallel output type in which these are simultaneously read in a column output direction is mainly used.

  FIG. 1 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a general column parallel output type solid-state imaging device (CMOS image sensor).

  The solid-state imaging device 1 in FIG. 1 includes a pixel unit 2 in which pixels PXL are arranged in a matrix, and a vertical scanning circuit (row scanning circuit) 3 that drives pixels through a row scanning control line in a shutter row and a reading row. Have been. FIG. 1 shows a one-row pixel array.

  Each pixel PXL of the pixel unit 2 basically includes, for example, a transfer transistor TG-Tr as a transfer element, a reset transistor RST-Tr as a reset element, and a source follower element (amplifying element) for one photodiode PD. ), And a source follower transistor SF-Tr as a selection element and a selection transistor SEL-Tr as a selection element.

  The transfer transistor TG-Tr is kept in a non-conductive state during the charge accumulation period of the photodiode PD, and has a gate through the control signal line LTG during the transfer period for transferring the accumulated charge of the photodiode PD to the floating diffusion FD. The DTG is applied and is kept in a conductive state, and transfers the charge photoelectrically converted by the photodiode PD to the floating diffusion FD.

  The reset transistor RST-Tr resets the potential of the floating diffusion FD to the potential VDD of the power supply line when a drive control signal (reset signal) DRST is supplied to the gate of the reset transistor RST-Tr through the control signal line LRST.

The gate of the source follower transistor SF-Tr is connected to the floating diffusion FD. The source follower transistor SF-Tr is connected to the vertical signal line LSGN via the selection transistor SEL-Tr, and forms a source follower with a constant current source of a load circuit outside the pixel unit.
Then, a drive control signal (address signal or select signal) DSEL is given to the gate of the select transistor SEL-Tr through the control signal line LSEL, and the select transistor SEL-Tr is turned on.
When the selection transistor SEL-Tr is turned on, the source follower transistor SF-Tr amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line LSGN. The voltage output from each pixel PXL via the vertical signal line LSGN is output to a column parallel processing unit as a pixel signal reading circuit.
In the column parallel processing, the image data is converted, for example, from an analog signal to a digital signal, and is transferred to a signal processing unit at a subsequent stage.

As shown in FIG. 1, the vertical scanning circuit 3 receives the control signal TG (RST, SEL) and converts the drive control signal DTG (DRST, DSEL) at the level of the positive power supply voltage to the corresponding control signal line LTG (LRST, LRST). LSEL), and a voltage supply unit 32 that supplies a voltage different from the positive power supply voltage vaa, for example, a voltage equal to or higher than the positive power supply voltage vaa, to the driver.
The voltage supply unit 32 includes an operational amplifier (op-amp) OPA32, an internal capacitor Cbst having an internal capacitance of about 100 pF, a capacitor bridge circuit CB32 including switches SW (1 to 4), and the like, and an external capacitor Cext having a capacitance of about 10 nF. It is comprised including.

By the way, in the CMOS image sensor as the solid-state imaging device 10, an operation of sequentially scanning and reading out the photocharges generated and accumulated by the photodiodes for each pixel or each row is performed.
In the case of this sequential scanning, that is, when a rolling shutter is employed as an electronic shutter, the start time and the end time of exposure for accumulating photocharges cannot be matched in all pixels. Therefore, in the case of sequential scanning, there is a problem that a captured image is distorted when capturing a moving subject.

  Therefore, in image sensing of a fast-moving subject in which image distortion is unacceptable, or in sensing applications that require synchronization of captured images, an electronic shutter is used to start exposure of all pixels in the pixel array unit at the same timing. A global shutter for executing the end of exposure is adopted.

In a CMOS image sensor employing a global shutter as an electronic shutter, for example, a signal holding unit for holding a signal read from a photoelectric conversion reading unit in a signal holding capacitor is provided in a pixel.
In a CMOS image sensor that employs a global shutter, charges from the photodiodes are simultaneously stored as voltage signals in a signal holding capacitor of a signal holding unit, and then sequentially read out, thereby ensuring the simultaneity of the entire image (for example, , Non-Patent Document 1).

J. Aoki, et al., "A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node" ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3.

The vertical scanning circuit 3 including the voltage supply unit 32 and the row driver 31 of the CMOS image sensor with the rolling shutter operation needs to drive only one row of the pixel array.
The conventional voltage supply unit 32 uses the operational amplifier OPA32 to charge the capacitor Cbst in the chip to a desired reference voltage vref, and pumps up with the power supply voltage vaa to generate an overvoltage or undervoltage power supply voltage. Then, the charge is transferred to the external capacitor Cext many times.

  However, in order to charge the internal capacitor Cbst and the external capacitor Cext within a required time, a large slew rate and a high-speed response are required, so that the area and power of the operational amplifier OPA32 need to be increased.

Further, the booster of the vertical scanning circuit 3 of the CMOS image sensor with the global shutter operation needs to drive the entire pixel array of the pixel unit 2, and therefore has a very large load capacitance. For example, the load capacity is about 1000 times that of the rolling shutter operation.
When a booster having the same configuration as the CMOS image sensor with the rolling shutter function is used, the charge-up time needs to be increased up to 1000 times.
Alternatively, the capacity of the internal capacitor Cbst needs to be ~ 1000x.
Alternatively, the operating speed (charging and transfer cycle) needs to be ~ 1000x.

In order to satisfy the conditions of the capacity of the internal capacitor Cbst and the operation speed among these conditions, the operational amplifier OPA32 needs to have a very large slew rate.
Therefore, at present, it is very difficult to design a voltage supply unit (booster) of a CMOS image sensor having a global shutter function on a silicon substrate.

  The present invention provides a solid-state imaging device, a solid-state imaging device driving method, and an electronic device that can achieve low power consumption with a simpler circuit and a smaller area, and that can realize high-speed charging. To provide.

  A solid-state imaging device according to a first aspect of the present invention includes a pixel portion in which a plurality of pixels are arranged in a matrix, and a drive control signal having a predetermined level corresponding to a control signal applied to a predetermined control signal line, and And a readout unit for reading out pixel signals in units of one row or a plurality of rows from the unit, wherein the readout unit receives the control signal and supplies the control signal corresponding to the drive control signal at a voltage level supplied thereto. A driver applied to the line, and a voltage supply unit for supplying a voltage different from a first power supply voltage or a voltage different from a second power supply voltage to the driver, wherein the voltage supply unit includes: a first node; A second node, a capacitor having a first electrode connected to the first node, and a second electrode connected to the second node; a first power supply potential; a second power supply potential; , The first power supply potential and the first node Alternatively, a first switch for selectively connecting the second node in accordance with a first signal, and a second signal for connecting the second power supply potential and the second node or the first node to a second signal And a second switch selectively connecting the first power supply potential and the second node in response to a third signal. A fourth switch for selectively connecting the second power supply potential and the first node in accordance with a fourth signal, and including the third switch, When the first node is connected to a first power supply voltage terminal of the driver and includes the fourth switch, the second node is connected to a second power supply voltage terminal of the driver.

  According to a second aspect of the present invention, there is provided a pixel section in which a plurality of pixels are arranged in a matrix, and a drive control signal of a predetermined level corresponding to a control signal is applied to a predetermined control signal line, so that one row from the pixel section. A readout unit that reads out pixel signals in units of a plurality of rows, wherein the readout unit receives the control signal and applies the drive control signal having a voltage level supplied thereto to the corresponding control signal line. A driver and a voltage supply unit for supplying a voltage different from a first power supply voltage or a voltage different from a second power supply voltage to the driver, wherein the voltage supply unit includes a first node and a second node A capacitor having a first electrode connected to the first node and a second electrode connected to the second node; a first power supply potential; a second power supply potential; Power supply potential and the first node or the second And a second switch for selectively connecting the second power supply potential and the second power supply potential to the second node or the first node in response to a second signal. And a third switch for selectively connecting the first power supply potential and the second node to each other in accordance with a third signal, wherein the first node A method of driving a solid-state imaging device connected to a first power supply voltage terminal of the driver, wherein the first switch and the second switch are activated by a first signal and a second signal that are active during a first period. Turning on a second switch, turning off the third switch in response to the inactive third signal, setting the potential of the first node to the first power supply potential, The potential of the node is set to the second power supply potential, which is the reference potential. Alternatively, the potential of the first node is set to the second power supply potential, which is a reference potential, and the potential of the second node is set to the first power supply potential. Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the third signal and turning on the third switch, Setting the potential of the first node to a potential higher than the first power supply potential up to twice the potential of the first power supply, or setting the potential of the first node to the first power supply potential A potential is set to a potential lower by a predetermined potential, and the driver receives the control signal while receiving a voltage higher than the first power supply voltage generated in the second period. Driving at a voltage level higher than the power supply voltage of A first power supply receiving the control signal while applying a control signal to the corresponding control signal line or receiving a voltage lower than a first power supply voltage generated during the second period; The drive control signal having a voltage level lower than a voltage is applied to the corresponding control signal line.

  According to a second aspect of the present invention, there is provided a pixel unit in which a plurality of pixels are arranged in a matrix, and a drive control signal having a predetermined level corresponding to a control signal applied to a predetermined control signal line, and A readout unit that reads out pixel signals in units of one or more rows, wherein the readout unit transmits the drive control signal of a voltage level supplied in response to the control signal to the corresponding control signal line. A voltage supply unit for supplying a voltage different from the first power supply voltage or a voltage different from the second power supply voltage to the driver, the voltage supply unit comprising: a first node; A capacitor having a first electrode connected to the first node, a second electrode connected to the second node, a first power supply potential, a second power supply potential, A first power supply potential and the first node or A first switch for selectively connecting the second node to a second signal in accordance with a first signal; and a second signal for connecting the second power supply potential and the second node or the first node to a second signal. A second switch for selectively connecting the second power supply potential and the first node in response to a fourth signal, and a second switch for selectively connecting the second power supply potential and the first node in response to a fourth signal. 2 is a method for driving a solid-state imaging device in which a second node is connected to a second power supply voltage terminal of the driver, wherein the first signal and the second signal are active during a first period. And the second switch is turned on, the fourth switch is turned off by the inactive fourth signal, and the potential of the first node is set to the first power supply potential. The potential of the second node is the second potential which is a reference potential. Setting the potential of the first node to the second power supply potential which is a reference potential, setting the potential of the second node to the first power supply potential, In the period, the first signal and the second signal are deactivated, the first switch and the second switch are turned off, and the fourth signal is activated to activate the fourth switch. ON to set the potential of the second node to be lower than the second power supply potential and to a potential up to the first power supply potential level on the negative side, or to set the potential of the second node to the second power supply potential. 2 is set to a potential higher than the power supply potential of the second power supply and to a predetermined potential on the positive side, and the control is performed in a state where the driver receives a voltage lower than the second power supply voltage generated during the second period. A voltage lower than the second power supply voltage upon receiving the signal Applying the drive control signal of a level to the corresponding control signal line, or receiving the control signal while receiving a voltage higher than a second power supply voltage generated in the second period The drive control signal having a voltage level higher than a second power supply voltage is applied to the corresponding control signal line.

  An electronic apparatus according to a third aspect of the present invention includes a solid-state imaging device, and an optical system that forms a subject image on the solid-state imaging device, wherein the solid-state imaging device includes a plurality of pixels arranged in a matrix. A readout unit that applies a drive control signal of a predetermined level corresponding to the control signal to a predetermined control signal line and reads out pixel signals from the pixel unit in units of one or more rows. And a driver that applies the drive control signal of a voltage level supplied in response to the control signal to the corresponding control signal line, and a driver that is different from a first power supply voltage or a second power supply voltage. And a voltage supply unit that supplies a voltage different from the first voltage to the driver. The voltage supply unit includes a first node, a second node, and a first electrode connected to the first node. Two electrodes are connected to the second node A capacitor, a first power supply potential, a second power supply potential, and a first power supply for selectively connecting the first power supply potential to the first node or the second node in accordance with a first signal. And a second switch for selectively connecting the second power supply potential and the second node or the first node in response to a second signal, further comprising: A third switch for selectively connecting a power supply potential and the second node according to a third signal, and selecting the second power supply potential and the first node according to a fourth signal; And at least one of a fourth switch and a third switch, the first node is connected to a first power supply voltage terminal of the driver, and If a switch is included, the second node is connected to the second power supply of the driver. It is connected to the voltage terminal.

  According to the present invention, power consumption can be reduced with a simpler circuit and a smaller area, and high-speed charging can be realized.

FIG. 2 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a general column parallel output type solid-state imaging device (CMOS image sensor). FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration example of a column output readout system of a pixel unit of the solid-state imaging device according to the embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a specific configuration example of a driver and a voltage supply unit of the vertical scanning circuit in the solid-state imaging device according to the first embodiment of the present invention. 5 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in the vertical scanning circuit of the solid-state imaging device according to the first embodiment. FIG. 6 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a second embodiment of the present invention. 9 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of the solid-state imaging device according to the second embodiment. FIG. 11 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a third embodiment of the present invention. 15 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a third embodiment. FIG. 14 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fourth embodiment of the present invention. 15 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a fourth embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning a 5th embodiment of the present invention. 15 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a fifth embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning a 6th embodiment of the present invention. 15 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a sixth embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning a 7th embodiment of the present invention. 15 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a seventh embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning an 8th embodiment of the present invention. 21 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to an eighth embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning a 9th embodiment of the present invention. 33 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a ninth embodiment. It is a figure showing the example of composition of the pixel part and the vertical scanning circuit of the solid-state imaging device concerning a 10th embodiment of the present invention. 33 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in the vertical scanning circuit of the solid-state imaging device according to the tenth embodiment. FIG. 21 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to an eleventh embodiment of the present invention. 33 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of the solid-state imaging device according to the eleventh embodiment. FIG. 21 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a twelfth embodiment of the present invention. 33 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a twelfth embodiment. FIG. 21 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a thirteenth embodiment of the present invention. 33 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a thirteenth embodiment. FIG. 21 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fourteenth embodiment of the present invention. FIG. 39 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in a vertical scanning circuit of a solid-state imaging device according to a fourteenth embodiment. FIG. 39 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fifteenth embodiment of the present invention. 35 is a timing chart of a voltage generation operation and the like of a voltage supply unit and a row driver in the vertical scanning circuit of the solid-state imaging device according to the fifteenth embodiment. FIG. 39 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a sixteenth embodiment of the present invention. 33 is a timing chart of a voltage supply unit and a low driver in a vertical scanning circuit of a solid-state imaging device according to a sixteenth embodiment, such as a voltage generation operation. 1 is a diagram illustrating an example of a configuration of an electronic apparatus to which a solid-state imaging device according to an embodiment of the present invention is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device according to the first embodiment of the present invention.
In the present embodiment, the solid-state imaging device 10 is configured by, for example, a CMOS image sensor.

As shown in FIG. 2, the solid-state imaging device 10 includes a pixel unit 20 as an imaging unit, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, and a horizontal scanning circuit (column scanning circuit) 50. , And the timing control circuit 60 as main components.
Among these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout unit 70.

In the first embodiment, the solid-state imaging device 10 supplies a voltage different from the positive power supply voltage, for example, a voltage higher or lower than the positive power supply voltage (or The voltage supply unit that supplies a voltage different from the negative power supply voltage (for example, a voltage lower or higher than the negative power supply voltage) basically includes a first power supply potential vaa and a second power supply potential in the semiconductor substrate (chip). vgnd, three switches SW, and an external capacitor Cext31, a simpler circuit, a smaller area, lower power consumption, high-speed charging, and a rolling shutter. It is configured to be applicable to a CMOS image sensor having a function and a global shutter function.
The voltage supply unit of the present embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging and discharging the capacitor, and does not require an internal capacitor that consumes area and power. The high-speed operation as an external capacitor is charged by an external power supply having a very small output impedance. The output voltage of the voltage supply unit is determined by using a level judgment unit (voltage detection circuit) Can be adjusted when controlling.

  Hereinafter, an outline of the configuration and function of each unit of the solid-state imaging device 10, particularly, the configuration and function of the pixel unit 20, a readout unit 70 associated therewith, particularly, a voltage supply unit as a low driver and a booster in the vertical scanning circuit 30 and the like Will be described in detail.

(Configuration of Pixel and Pixel Section 20)
FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device 10 according to the first embodiment of the present invention.

The pixel PXL20 has, for example, a photodiode (PD) that is a photoelectric conversion element.
The photodiode PD21 has one transfer transistor TG21-Tr, one reset transistor RST21-Tr, one source follower transistor SF21-Tr, and one selection transistor SEL21-Tr.

The photodiode PD21 generates and accumulates signal charges (here, electrons) in an amount corresponding to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described. However, the signal charge may be a hole or each transistor may be a p-type transistor.
The present embodiment is also effective when a plurality of photodiodes share each transistor, or when a three-transistor (3Tr) pixel having no selection transistor is employed.

The transfer transistor TG21-Tr is connected between the photodiode PD21 and a floating diffusion (FD) 21 and is controlled by a drive control signal DTG21 supplied to a gate through a drive control line LTG21.
The transfer transistor TG21-Tr is turned on when the drive control signal DTG21 applied to the drive control line LTG21 is at the high level (H), and transfers the electrons photoelectrically converted by the photodiode PD21 to the floating diffusion FD21. I do.

The reset transistor RST21-Tr is connected between the power supply line VRst and the floating diffusion FD21, and is controlled by a drive control signal DRST21 supplied to a gate through a drive control line LRST21.
Note that the reset transistor RST21-Tr may be connected between the power supply line VDD and the floating diffusion FD21, and may be configured to be controlled through the drive control line LRST21.
The reset transistor RST21-Tr is turned on when the drive control signal DRST21 applied to the drive control line LRST21 is at the H level, and resets the floating diffusion FD21 to the potential of the power supply line VRst (or VDD).

The source follower transistor SF21-Tr and the selection transistor SEL21-Tr are connected in series between the power supply line VDD and the vertical signal line LSGN21.
The floating diffusion FD21 is connected to the gate of the source follower transistor SF21-Tr.
The selection transistor SEL21-Tr is controlled by a drive control signal DSEL21 supplied to a gate through a drive control line LSEL21.
The select transistor SEL21-Tr is turned on when the drive control signal DSEL21 applied to the drive control line LSEL21 is selected during the H period. Thus, the source follower transistor SF21-Tr outputs a column output analog signal VSL corresponding to the potential of the floating diffusion FD21 to the vertical signal line LSGN21.
These operations are performed, for example, in parallel in parallel for each pixel of one row because the gates of the transfer transistor TG21-Tr, the reset transistor RST21-Tr, and the selection transistor SEL21-Tr are connected in row units. Will be

In the pixel section 20, for example, the pixels PXL21 are arranged in n rows × m columns, so that each of the drive control lines LTG21, LRST21, and LSEL21 has n lines and the vertical signal line LSGN21 has m lines.
In FIG. 2, each drive control line LTG21, LRST21, LSEL21 is represented as one row scan drive control line.

The vertical scanning circuit 30 drives a pixel through a row scanning drive control line in a shutter row and a readout row under the control of the timing control circuit 60.
In addition, the vertical scanning circuit 30 outputs a row selection signal of a row address of a read row from which a signal is read out and a row address of a shutter row for resetting charges accumulated in the photodiode PD21 in accordance with the address signal.
The specific configuration and function of the row driver and voltage supply unit of the vertical scanning circuit 30 will be described later.

  The readout circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel unit 20, and is configured to be able to perform column parallel processing by the plurality of column signal processing circuits. Good.

  The readout circuit 40 can be configured to include a correlated double sampling (CDS) circuit, an ADC (analog / digital converter; AD converter), an amplifier (AMP, amplifier), a sample hold (S / H) circuit, and the like. It is.

As described above, the readout circuit 40 may be configured to include the ADC 41 that converts each column output analog signal VSL of the pixel unit 20 into a digital signal, for example, as illustrated in FIG.
Alternatively, the read circuit 40 may be provided with an amplifier (AMP) 42 for amplifying each column output analog signal VSL of the pixel unit 20, as shown in FIG. 4B, for example.
Further, in the readout circuit 40, for example, as shown in FIG. 4C, a sample and hold (S / H) circuit 43 for sampling and holding each column output analog signal VSL of the pixel unit 20 may be arranged.
The readout circuit 40 may include an SRAM as a column memory that stores a signal obtained by performing a predetermined process on a pixel signal output from each column of the pixel unit 20.

  The horizontal scanning circuit 50 scans signals processed by a plurality of column signal processing circuits such as ADCs of the readout circuit 40, transfers the signals in the horizontal direction, and outputs the signals to the signal processing circuit 70.

  The timing control circuit 60 generates a timing signal required for signal processing of the pixel unit 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

  In the first embodiment, the reading unit 70 controls the vertical scanning circuit 30 and the like in the rolling shutter mode or the global shutter mode, and sends a control signal TG21 (RST21) to a predetermined control signal line LTG21 (LRST21, LSEL21). , SEL21) to read out pixel signals from the pixel unit 20 in units of one row or a plurality of rows (all rows in the global shutter mode) by applying a drive control signal DTG21 (DRST21, DSEL21) of a predetermined level according to.

(Specific Configuration and Function of Row Driver and Voltage Supply Unit of Vertical Scanning Circuit 30)
Hereinafter, specific configurations and functions of the driver and the voltage supply unit of the characteristic vertical scanning circuit 30 in the solid-state imaging device 10 of the first embodiment will be described.

  FIG. 5 is a circuit diagram illustrating a specific configuration example of the driver and the voltage supply unit of the vertical scanning circuit 30 in the solid-state imaging device 10 according to the first embodiment of the present invention.

  As shown in FIG. 5, the vertical scanning circuit 30 includes a plurality of row drivers 310 and a voltage supply unit 320.

  The row driver 310 receives the control signal TG21 (RST21, SEL21) and receives a voltage different from the first power supply voltage (positive power supply voltage) va supplied from the voltage supply unit 320, for example, a voltage higher than the positive power supply voltage vaa. For example, a drive control signal DTG21 (DRST21, DSEL21) having a level of (vaa + vref) is applied to a corresponding drive control line LTG21 (LRST21, LSEL21).

In the row driver 310 of FIG. 5, two inverters 311 and 312 are connected in series to an input line of a control signal TG21 (RST21 and SEL21), and a first power supply voltage terminal TVAA is connected to a voltage supply unit 320. It is connected to a line (first node ND31).
For example, the two inverters 311 and 312 are constituted by CMOS inverters (the latter stage is illustrated by a specific circuit in FIG. 5).

CMOS inverter 312 is configured such that p-channel MOS (PMOS) transistor PT31 and n-channel MOS (NMOS) transistor NT31 are connected in series between first power supply voltage terminal TVAA and reference potential VSS (for example, ground potential GND). Have been.
Specifically, the source of the PMOS transistor PT31 is connected to the first power supply voltage terminal TVAA, and the source of the NMOS transistor NT31 is connected to the reference potential VSS. The drain of the PMOS transistor PT31 and the drain of the NMOS transistor NT31 are connected to form an output node NDOT, and the output node NDOT is connected to the corresponding drive control line LTG21 (LRST21, LSEL21).
An input node is formed by the gate of the PMOS transistor PT31 and the gate of the NMOS transistor NT31, and is connected to the output terminal of the inverter 311 in the preceding stage.

  The voltage supply unit 320 generates a voltage higher than the first power supply voltage (positive power supply voltage) vaa, for example, (vaa + vref), and supplies it to the row driver 310.

In the voltage supply unit 320, the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 is connected to the first node ND31. It has an external capacitor Cext31 connected to the second node ND32 via the second connection terminal T32.
The voltage supply unit 320 includes a first power supply potential line Lvaa of a first power supply potential (positive power supply potential) vaa, a second power supply potential line Lvgnd of a second power supply potential (negative power supply potential) vgnd, and a first power supply potential line Lvgnd. , A second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination unit 321.

The first switch SW31 is formed of, for example, an NMOS transistor, and selectively connects the first power supply potential line Lvaa and the first node ND31 according to the first signal S31.
The second switch SW32 is formed of, for example, an NMOS transistor, and selectively connects the second power supply potential line Lvgnd and the second node ND32 in accordance with the second signal S32.
The third switch SW33 is formed of, for example, an NMOS transistor, and selectively connects the first power supply potential line Lvaa and the second node ND32 according to a third signal S33.
As described above, the voltage supply unit 320 including the third switch SW33 has the first node ND31 connected to the first power supply voltage terminal TVAA of the row driver 310.
Further, the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects the first node ND31 and the second node ND32 according to a fifth signal S35.

When determining that the potential level VND31 of the first node ND31 is lower than the arbitrarily set reference voltage vref, the level determination unit 321 activates the first signal S31, for example, sets the first signal S31 to a high (H) level and sets the first signal S31 to a high (H) level. The signal is output to the first switch SW31 to turn on the first switch SW31.
When determining that the potential level VND31 of the first node ND31 has reached the reference voltage vref, the level determination section 321 outputs the first signal S1 to the inactive state, in this example, to the first switch SW31 at a low level. The first switch SW31 is turned off.

  The level determination unit 321 of the first embodiment includes a comparator CMP31 in which a non-inverting input (+) is connected to a supply line of a reference voltage vref, and an inverting input terminal (-) is connected to a first node ND31. It is configured.

The comparator CMP31 compares the potential level VND31 of the first node ND31 with the reference voltage vref. When the potential level VND31 of the first node ND31 is lower than the reference voltage vref, the comparator CMP31 activates the first signal S31. An H level is output to the first switch SW31 to turn on the first switch SW31.
When the potential level VND31 of the first node ND31 reaches the reference voltage vref, the comparator CMP31 outputs the first signal S31 to the first switch SW31 at the inactive L level to output the first switch SW31. Off.

In the first embodiment, the comparator CMP31 serving as the level determination unit 321 outputs the enable signal CMP When ENA is at the active H level, it is in an operable state and performs level determination processing.

  The voltage supply unit 320 having the above-described configuration includes the first node ND31, the second node ND32, and the first power supply potential line Lvaa of the first power supply potential (positive power supply potential) vaa, excluding the external capacitor Cext31. , A second power supply potential line Lvgnd of a second power supply potential (negative power supply potential) vgnd, a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination unit. A booster (booster) 322 is configured by the comparator CMP31 as 321.

  When generating the voltage (vaa + vref) higher than the positive power supply voltage supplied to the row driver 310, the voltage supply unit 320 according to the first embodiment resets the reset period PRST, the first period PFST, and the second period PSCD. , A voltage (vaa + vref) higher than the desired level of the positive power supply voltage vaa is generated and supplied to the row driver 310.

  When the reference voltage vref changes, the potential level VND31 (vaa + vref) of the first node ND31 can be adjusted.

(Operation such as voltage generation of vertical scanning circuit 30)
The characteristic configurations and functions of the row driver 310 and the voltage supply unit 320 of the vertical scanning circuit 30 of the solid-state imaging device 10 have been described above.
Next, the voltage generation operation of the voltage supply unit 320 and the row driver 310 in the vertical scanning circuit 30 of the solid-state imaging device 10 according to the first embodiment will be described.
Here, for ease of understanding, a case will be described as an example where the transfer transistor TG21-Tr of the pixel PXL20 is driven to perform pixel reading.

  FIGS. 6A to 6J are timing charts of a voltage generation operation and the like of the voltage supply unit 320 and the row driver 310 in the vertical scanning circuit 30 of the solid-state imaging device 10 according to the first embodiment.

FIG. 6A shows a control signal TG for the transfer transistors TG21-Tr of the pixel PXL20. FIG. 6B shows a second signal S32 for turning on and off the second switch SW32 of the voltage supply unit 320. FIG. 6C shows a fifth signal S35 for turning on and off the fifth switch SW35 of the voltage supply unit 320. FIG. 6D shows an enable signal CMP for the comparator CMP31 of the voltage supply unit 320. ENA is shown.
FIG. 6E shows a first signal S31 for turning on and off the first switch SW31 of the voltage supply unit 320. FIG. 6F shows a third signal S33 for turning on and off the third switch SW33 of the voltage supply unit 320.
FIG. 6G illustrates a level transition of the first node ND31 of the voltage supply unit 320. FIG. 6H illustrates a level transition of the second node ND32 of the voltage supply unit 320.
FIG. 6I shows the level transition of the first node ND31 of the voltage supply unit 320. FIG. 6J shows a drive control signal DTG applied from the row driver 310 of the voltage supply unit 320 to the drive control line LTG21.

(Operation of the reset period PRST)
In the voltage supply unit 320, a reset period PRST is set before the first period PFST for generating a voltage.
In the reset period PRST, the enable signal CMP ENA is set to the inactive L level, and comparator CMP31 is held in the inactive state. Since the comparator CMP31 is in the non-operation state, the output of the first signal S31 is held at the inactive L level, and accordingly, the first switch SW31 is held in the off state.
In the reset period PRST, the third signal S33 is set to the inactive L level, and the third switch SW33 is held in the off state.
Thus, in the reset period PRST, the first switch is activated.

With the switch SW31 and the third switch SW33 turned off, the second signal S32 is set to the active H level, the second switch SW32 is kept on, and the second node ND32 is turned on. Connected to power supply potential line Lvgnd.
In parallel with this, the fifth signal S35 is set to the active H level, the fifth switch SW35 is kept in the ON state, and the first node ND31 and the second node ND32 are connected.
Thus, the first node ND31 and the second node ND32 are set to the second power supply potential vgnd and reset (discharged).

In the reset period PRST, when the first node ND31 and the second node ND32 are reset to the second power supply potential vgnd, the fifth signal S35 is set to the inactive L level, and the fifth switch SW35 is turned on. The state is switched to the off state, and the first node ND31 and the second node ND32 are disconnected.
Note that the second signal S32 is maintained at the active H level until immediately before the end of the first period PFST that continues even after the reset period PRST ends, and accordingly, the second switch SW32 is turned on during the second period. The on state is maintained until just before the PSCD is started, and the second node ND32 is maintained in a state of being connected to the second power supply potential line Lvgnd.
Therefore, the second node ND32 is maintained at the second power supply potential vgnd until immediately before the start of the second period PSCD.

(Operation of the first period PFST)
When the processing in the reset period PRST ends, the processing in the first period PFST is subsequently performed.
In the first period PFST, the enable signal CMP ENA is switched to the active H level, and comparator CMP31 is switched to the operating state.
When the comparator CMP31 is switched to the operation state, a comparison process between the potential level VND31 of the first node ND31 and the reference voltage vref is started. At the start of the comparison, since the potential level VND31 of the first node ND31 is lower than the reference voltage vref, the first signal S31 is output to the first switch SW31 at the active H level and the first switch SW31 is turned on. .

When the first switch SW31 is turned on, the first node ND31 is connected to the first power supply potential line Lvaa, the first node ND31 is charged, and the potential level VND31 is changed to the second power supply potential. The potential increases from the potential vgnd toward the reference voltage vref.
When the potential level VND31 of the first node ND31 rises and reaches the reference voltage vref, the comparator CMP31 detects that the potential level VND31 of the first node ND31 has reached the reference voltage vref, and the first signal S31 Is switched to the inactive L level and output to the first switch SW31, and the first switch SW31 is turned off.
As a result, the first node ND31 is disconnected from the first power supply potential line Lvaa.

Next, in the first period PFST, the enable signal CMP ENA is set to the inactive L level, and comparator CMP31 is switched to the inactive state.
Next, the second signal S32 is switched to the L level, the second switch SW32 is switched off, and the second node ND32 is disconnected from the second power supply potential line Lvgnd.

(Operation of PSCD in Second Period)
When the processing in the first period PFST ends, the processing in the second period PSCD is subsequently performed.
In the second period PSCD, the first signal S31 and the second signal S32 are set to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the third signal S33 is switched to the active H level.
As a result, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 is boosted to the potential (vaa + vref) by the capacitive coupling of the external capacitor Cext31. You.
This boosted voltage (vaa + vref) is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310 as a voltage to be supplied higher than the positive power supply voltage (first power supply voltage).

  In response to the control signal TG21, the row driver 310 drives the corresponding drive control signal DTG21 at a level (vaa + vref) higher than the first power supply voltage (positive power supply voltage) vaa supplied from the voltage supply unit 320. It is applied to the control line LTG21.

  Note that the charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the voltage of the drive control signal DTG21 (vout1p) is slightly lower than the boosted voltage (vaa + vref).

As described above, according to the first embodiment, the vertical scanning circuit 30 outputs a voltage different from the first power supply voltage (positive power supply voltage) vaa, for example, a voltage higher than the positive power supply voltage vaa (for example, vaa + vref). ) Is generated and supplied to the row driver 310.
Then, the voltage supply unit 320 is configured such that the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 Has an external capacitor Cext31 connected to the second node ND32 via the second connection terminal T32. Further, the voltage supply unit 320 includes a first power supply potential line Lvaa of a first power supply potential (positive power supply potential) vaa, a second power supply potential line Lvgnd of a second power supply potential (negative power supply potential) vgnd, It has a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a comparator CMP31 as a level determination unit 321.
The comparator CMP31 compares the potential level VND31 of the first node ND31 with the reference voltage vref. When the potential level VND31 of the first node ND31 is lower than the reference voltage vref, the comparator CMP31 activates the first signal S31. The signal is output to the first switch SW31 at the H level to turn on the first switch SW31. When the potential level VND31 of the first node ND31 reaches the reference voltage vref, the first signal S31 is changed to the inactive L level. The level is output to the first switch SW31 to turn off the first switch SW31.

That is, the voltage supply unit 320 that supplies a higher voltage than the positive power supply voltage (or a voltage lower than the negative power supply voltage) to the row driver in the vertical scanning circuit 30 of the first embodiment is basically a semiconductor substrate ( A first power supply potential vaa, a second power supply potential vgnd, three switches SW31, SW32, SW33, and an external capacitor Cext31 in the chip), and a simpler circuit and a smaller area for lower power consumption. And a high-speed charge can be realized, and the present invention can be applied to a CMOS image sensor having a rolling shutter function and a global shutter function.
The voltage supply unit of the first embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging / discharging the capacitor, and consumes area and power. A capacitor is not required, and high-speed operation as an external capacitor is charged by an external power supply having an extremely small output impedance, and an output voltage of a voltage supply unit is compared with a comparator CMP31 serving as a level determination unit (voltage detection circuit). It can be adjusted when using or when controlling the charging time.

(Second embodiment)
FIG. 7 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a second embodiment of the present invention.
FIGS. 8A to 8J are timing charts of the voltage supply unit 320A and the row driver 310A in the vertical scanning circuit 30A of the solid-state imaging device 10A according to the second embodiment, and the like, and are timing charts.

The solid-state imaging device 10A according to the second embodiment is different from the solid-state imaging device 10 according to the above-described first embodiment in the following points.
In the solid-state imaging device 10A according to the second embodiment, the level determination unit 321A is configured by the counter CNT31 instead of the comparator.

The counter CNT31 is provided with an enable signal COUNT. ENA is received at the active H level, and the operable state (enabled state) of the clock CLK0 is counted. The count value is a target value, in this example, the potential level VND31 of the first node ND31 is lower than the reference voltage vref. In the case (<vx) corresponding to the case (when the reference voltage is not reached), the first signal S31 is output to the first switch SW31 at the active H level to turn on the first switch SW31.
When the potential level VND31 of the first node ND31 reaches the value (vx) corresponding to the case where the potential level VND31 of the first node ND31 has reached the reference voltage vref, the counter CNT31 sends the first signal S31 to the first switch SW31 at an inactive L level. Output to turn off the first switch SW31.

Also in the second embodiment, in the second period PSCD, the first signal S31 and the second signal S32 are set to the inactive L level to turn off the first switch SW31 and the second switch SW32. In this state, the third signal S33 is switched to the active high H level.
As a result, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 has the potential (vaa + vx (for example, vref)) due to the capacitive coupling of the external capacitor Cext31. ).
The boosted voltage (vaa + vx (vref)) is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310A as a voltage to be supplied higher than the positive power supply voltage (first power supply voltage).

  In response to the control signal TG21, the row driver 310A drives the corresponding drive control signal DTG21 at a voltage (vaa + vx) higher than the first power supply voltage (positive power supply voltage) va supplied from the voltage supply unit 320. It is applied to the control line LTG21.

  In the second embodiment, when the count value, that is, the number of clocks CLK0 changes, the potential level VND31 (vaa + vx) of the first node ND31 can be adjusted.

Other configurations are the same as those of the first embodiment.
According to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Third embodiment)
FIG. 9 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a third embodiment of the present invention.
FIGS. 10A to 10G are timing charts of a voltage generation operation and the like of the voltage supply unit 320B and the row driver 310B in the vertical scanning circuit 30B of the solid-state imaging device 10B according to the third embodiment.

The solid-state imaging device 10B according to the third embodiment differs from the solid-state imaging devices 10 and 10A according to the first and second embodiments described above in the following points.
In the solid-state imaging device 10B according to the third embodiment, the level determination units 321 and 321A and the fifth switch SW35 are not provided, and the supply voltage to the row driver 310B is twice the first power supply voltage vaa. Is increased to 2 vaa.

In the solid-state imaging device 10B according to the third embodiment, the processing in the reset period is not performed, and the boost operation is performed in the processing in the first period PFST and the second period PSCD.
In this example, the first signal S31 and the second signal S32 are shared by the first switch SW31 and the second switch SW32, and the shared signal and the third signal S33 for the third switch SW33 are in opposite phases. It has become.

When the first signal S31 is switched to the H level and the first switch SW31 is turned on, the first node ND31 is connected to the first power supply potential line Lvaa and the positive power supply voltage vaa Level, the second node ND32 is connected to the second power supply potential line Lvgnd, and has a negative power supply voltage vgnd level.
Next, the first signal S31 is switched to the inactive L level, and the third signal S33 is switched to the active H level.
Switch to level. As a result, the second node ND32 has a positive power supply voltage vaa level, and the first node ND31 is boosted to a voltage (2vaa) level twice as high as the power supply voltage vaa.
This boosted voltage (2vaa) is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310B as a voltage to be supplied higher than the positive power supply voltage (first power supply voltage).

  In response to the control signal TG21, the row driver 310B drives the corresponding drive control signal DTG21 of a level (2vaa) higher than the first power supply voltage (positive power supply voltage) va supplied from the voltage supply unit 320B. It is applied to the control line LTG21.

  Note that also in the solid-state imaging device 10B according to the third embodiment, the electric charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the drive control signal DTG21 (vout1p) is generated. The voltage is slightly lower than the boosted voltage (2vaa).

  According to the third embodiment, the voltage supply unit 320B basically includes the first power supply potential Vaa, the second power supply potential Vgnd, and the three switches SW31, SW32, and SW33 in the semiconductor substrate (chip). And an external capacitor Cext31, which can achieve low power consumption with a simpler circuit and a smaller area, can realize high-speed charging, and has a rolling shutter function and a global shutter function. It becomes possible to apply to the CMOS image sensor which was used.

(Fourth embodiment)
FIG. 11 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fourth embodiment of the present invention.
FIGS. 12A to 12J are timing charts of a voltage generation operation and the like of the voltage supply unit 320C and the row driver 310C in the vertical scanning circuit 30C of the solid-state imaging device 10C according to the fourth embodiment.

The solid-state imaging device 10C according to the fourth embodiment is different from the solid-state imaging device 10 according to the above-described first embodiment in the following points.
In the voltage supply unit 320C of the solid-state imaging device 10C according to the fourth embodiment, instead of generating a voltage higher than the positive power supply voltage vaa, a voltage lower than the positive power supply voltage vaa is generated, and the It is configured to supply one power supply voltage terminal TVAA.
The solid-state imaging device 10C according to the fourth embodiment differs from the solid-state imaging device 10 according to the first embodiment in the configuration of the voltage supply unit 320C.

  The voltage supply unit 320C generates a voltage lower than the first power supply voltage (positive power supply voltage) vaa, for example, (vaa-vref), and supplies it to the row driver 310C.

In the voltage supply unit 320C, the first node ND31, the second node ND32, and the first electrode EL31 are connected to the first node ND31 via the first connection terminal T31, and the second electrode EL32 is connected to the first node ND31. It has an external capacitor Cext31 connected to the second node ND32 via the second connection terminal T32.
The voltage supply section 320C includes a first power supply potential line Lvaa of a first power supply potential (positive power supply potential) vaa, a second power supply potential line Lvgnd of a second power supply potential (negative power supply potential) vgnd, and a first power supply potential line Lvgnd. , A second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination unit 321C.

The first switch SW31 selectively connects the first power supply potential line Lvaa and the second node ND32 according to the first signal S31.
The second switch SW32 selectively connects the second power supply potential line Lvgnd to the first node ND31 according to the second signal S32.
The third switch SW33 selectively connects the first power supply potential line Lvaa and the second node ND32 according to the third signal S33.
As described above, in the voltage supply unit 320C including the third switch SW33, the first node ND31 is connected to the first power supply voltage terminal TVAA of the row driver 310.
Further, the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects the first node ND31 and the second node ND32 according to a fifth signal S35.

When determining that the potential level VND32 of the second node ND32 is lower than the arbitrarily set reference voltage vref, the level determination unit 321C activates the first signal S31, for example, sets the first signal S31 to a high (H) level and sets the first signal S31 to a high (H) level. The signal is output to the first switch SW31 to turn on the first switch SW31.
When determining that the potential level VND32 of the second node ND32 has reached the reference voltage vref, the level determination unit 321C outputs the first signal S1 to the inactive state, in this example, to the first switch SW31 at a low level. The first switch SW31 is turned off.

  The level determination unit 321C of the fourth embodiment includes a comparator CMP31C having a non-inverting input (+) connected to the supply line of the reference voltage vref and an inverting input terminal (-) connected to the second node ND32. It is configured.

The comparator CMP31C compares the potential level VND32 of the second node ND32 with the reference voltage vref, and when the potential level VND32 of the second node ND32 is lower than the reference voltage vref, activates the first signal S31. An H level is output to the first switch SW31 to turn on the first switch SW31.
When the potential level VND32 of the second node ND32 has reached the reference voltage vref, the comparator CMP31C outputs the first signal S31 to the first switch SW31 at the inactive L level to output the first switch SW31. Off.

In the fourth embodiment, as in the first embodiment, the comparator CMP31C serving as the level determination unit 321C outputs the enable signal CMP. When ENA is at the active H level, it is in an operable state and performs level determination processing.

  The voltage supply unit 320C having the above-described configuration includes the first node ND31, the second node ND32, and the first power supply potential line Lvaa of the first power supply potential (positive power supply potential) vaa, excluding the external capacitor Cext31. , A second power supply potential line Lvgnd of a second power supply potential (negative power supply potential) vgnd, a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a level determination unit. A booster (booster) 322C is configured by the comparator CMP31C serving as 321C.

  When generating a voltage (vaa-vref) lower than the positive power supply voltage supplied to the row driver 310C, the voltage supply unit 320C in the fourth embodiment includes a reset period PRST, a first period PFST, and a second period. After the period PSCD, a voltage (vaa-vref) lower than the desired level of the positive power supply voltage vaa is generated and supplied to the row driver 310C.

  Note that when the reference voltage vref changes, the potential level VND32 (vaa-vref) of the second node ND32 can be adjusted.

(Operation such as voltage generation of vertical scanning circuit 30C)
Next, the voltage generation operation of the voltage supply unit 320C and the row driver 310 in the vertical scanning circuit 30C of the solid-state imaging device 10C according to the fourth embodiment will be described.
Here, as in the case of the first embodiment, a case where the pixel is read by driving the transfer transistor TG21-Tr of the pixel PXL20 for easy understanding will be described.

  FIGS. 12A to 12J are timing charts of the voltage generation operation and the like of the voltage supply unit 320C and the row driver 310 in the vertical scanning circuit 30C of the solid-state imaging device 10C according to the fourth embodiment.

FIG. 12A shows a control signal TG for the transfer transistors TG21-Tr of the pixel PXL20. FIG. 12B shows a second signal S32 for turning on and off the second switch SW32 of the voltage supply unit 320C. FIG. 12C shows a fifth signal S35 for turning on and off the fifth switch SW35 of the voltage supply unit 320C. FIG. 12D shows an enable signal CMP for the comparator CMP31C of the voltage supply unit 320C. ENA is shown.
FIG. 12E shows a first signal S31 for turning on and off the first switch SW31 of the voltage supply unit 320C. FIG. 12F shows a third signal S33 for turning on and off the third switch SW33 of the voltage supply unit 320C.
FIG. 12G shows the level transition of the second node ND32 of the voltage supply unit 320C. FIG. 12H illustrates a level transition of the first node ND31 of the voltage supply unit 320.
FIG. 12I shows the level transition of the first node ND31 of the voltage supply unit 320C. FIG. 12J shows a drive control signal DTG applied to the drive control line LTG21 from the row driver 310 of the voltage supply unit 320C.

(Operation of the reset period PRST)
In the voltage supply unit 320C, a reset period PRST is set before the first period PFST for generating a voltage.
In the reset period PRST, the enable signal CMP ENA is set to the inactive L level, and comparator CMP31C is held in the inactive state. Since the comparator CMP31C is in the non-operation state, the output of the first signal S31 is held at the inactive L level, and accordingly, the first switch SW31 is held in the off state.
In the reset period PRST, the third signal S33 is set to the inactive L level, and the third switch SW33 is held in the off state.

As described above, in the reset period PRST, with the first switch SW31 and the third switch SW33 turned off, the second signal S32 is set to the active H level, and the second switch SW32 is turned on. And the first node ND31 is connected to the second power supply potential line Lvgnd.
In parallel with this, the fifth signal S35 is set to the active H level, the fifth switch SW35 is kept in the ON state, and the first node ND31 and the second node ND32 are connected.
Thus, the first node ND31 and the second node ND32 are set to the second power supply potential vgnd and reset (discharged).

In the reset period PRST, when the first node ND31 and the second node ND32 are reset to the second power supply potential vgnd, the fifth signal S35 is set to the inactive L level, and the fifth switch SW35 is turned on. The state is switched to the off state, and the first node ND31 and the second node ND32 are disconnected.
Note that the second signal S32 is maintained at the active H level until immediately before the end of the first period PFST that continues even after the reset period PRST ends, and accordingly, the second switch SW32 is turned on during the second period. The ON state is maintained until just before the PSCD is started, and the state in which the first node ND31 is connected to the second power supply potential line Lvgnd is maintained.
Therefore, the first node ND31 is maintained at the second power supply potential vgnd until immediately before the start of the second period PSCD.

(Operation of the first period PFST)
When the processing in the reset period PRST ends, the processing in the first period PFST is subsequently performed.
In the first period PFST, the enable signal CMP ENA is switched to the active H level, and comparator CMP31C is switched to the operating state.
When the comparator CMP31C is switched to the operation state, a comparison process between the potential level VND32 of the second node ND32 and the reference voltage vref is started. At the start of the comparison, since the potential level VND32 of the second node ND32 is lower than the reference voltage vref, the first signal S31 is output to the first switch SW31 at the active H level and the first switch SW31 is turned on. .

When the first switch SW31 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, the second node ND32 is charged, and the potential level VND32 is changed to the second power supply potential. The potential increases from the potential vgnd toward the reference voltage vref.
When the potential level VND32 of the second node ND32 rises and reaches the reference voltage vref, the comparator CMP31C detects that the potential level VND32 of the second node ND32 has reached the reference voltage vref, and detects the first signal S31. Is switched to the inactive L level and output to the first switch SW31, and the first switch SW31 is turned off.
Thus, the second node ND32 is disconnected from the first power supply potential line Lvaa.

Next, in the first period PFST, the enable signal CMP ENA is set to the inactive L level, and comparator CMP31C is switched to the inactive state.
Next, the second signal S32 is switched to the L level, the second switch SW32 is switched off, and the first node ND31 is disconnected from the second power supply potential line Lvgnd.

(Operation of PSCD in Second Period)
When the processing in the first period PFST ends, the processing in the second period PSCD is subsequently performed.
In the second period PSCD, the first signal S31 and the second signal S32 are set to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the third signal S33 is switched to the active H level.
As a result, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 reaches the potential (vaa-vref) due to capacitive coupling of the external capacitor Cext31. Step down.
This step-down voltage (vaa-vref) is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310C as a voltage to be supplied lower than the positive power supply voltage (first power supply voltage).

  In response to the control signal TG21, the row driver 310C responds to the drive control signal DTG21 having a voltage (vaa-vref) level lower than the first power supply voltage (positive power supply voltage) vaa supplied from the voltage supply unit 320. To the corresponding drive control line LTG21.

  Note that the charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the voltage of the drive control signal DTG21 (vout1p) is slightly lower than the step-down voltage (vaa-vref).

According to the fourth embodiment, the same effects as those of the first embodiment can be obtained.
That is, according to the fourth embodiment, the vertical scanning circuit 30 applies a voltage different from the first power supply voltage (positive power supply voltage) vaa, for example, a voltage lower than the positive power supply voltage vaa (for example, vaa-vref). It has a voltage supply section 320C that is generated and supplied to the row driver 310C.
The voltage supply unit 320C includes a first node ND31, a second node ND32, and a first electrode EL31 connected to the first node ND31 via a first connection terminal T31, and a second electrode EL32 Has an external capacitor Cext31 connected to the second node ND32 via the second connection terminal T32. Further, the voltage supply unit 320C includes a first power supply potential line Lvaa of the first power supply potential (positive power supply potential) vaa, a second power supply potential line Lvgnd of the second power supply potential (negative power supply potential) vgnd, It has a first switch SW31, a second switch SW32, a third switch SW33, a fifth switch SW35, and a comparator CMP31C as a level determination unit 321.
The comparator CMP31C compares the potential level VND32 of the second node ND32 with the reference voltage vref, and when the potential level VND32 of the second node ND32 is lower than the reference voltage vref, activates the first signal S31. The signal is output to the first switch SW31 at the H level to turn on the first switch SW31. When the potential level VND32 of the second node ND32 reaches the reference voltage vref, the first signal S31 is changed to the inactive L level. The level is output to the first switch SW31 to turn off the first switch SW31.

That is, the voltage supply unit 320C that supplies a voltage lower than the positive power supply voltage to the row driver in the vertical scanning circuit 30 according to the fourth embodiment basically includes the first power supply potential vaa in the semiconductor substrate (chip). , The second power supply potential vgnd, the three switches SW31, SW32, SW33, and the external capacitor Cext31. The power consumption can be reduced with a simpler circuit and a smaller area, and high-speed charging can be achieved. And can be applied to a CMOS image sensor having a rolling shutter function and a global shutter function.
The voltage supply unit of the fourth embodiment basically requires only a switch of silicon and one external capacitor, does not require an internal operational amplifier for charging / discharging the capacitor, and consumes area and power. A capacitor is not required, and high-speed operation as an external capacitor is charged by an external power supply having an extremely small output impedance, and the output voltage of the voltage supply unit is compared with a comparator CMP31C which is a level determination unit (voltage detection circuit). It can be adjusted when using or when controlling the charging time.

(Fifth embodiment)
FIG. 13 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fifth embodiment of the present invention.
FIGS. 14A to 14K are timing charts of a voltage generation operation and the like of the voltage supply unit 320D and the row driver 310D in the vertical scanning circuit 30D of the solid-state imaging device 10D according to the fifth embodiment.

The solid-state imaging device 10D according to the fifth embodiment is different from the solid-state imaging device 10 according to the above-described first embodiment in the following points.
In the voltage supply unit 320D of the solid-state imaging device 10D according to the fifth embodiment, the switch SW36D is connected between the first node ND31 and the first power supply voltage terminal TVAA of the row driver 310D, and Is connected between the power supply voltage terminal TVAA and the first power supply potential line Lvaa of the positive power supply potential vaa.
The switch SW36D is ON / OFF controlled by the third signal S33, similarly to the third switch SW33, and selectively switches the first node ND31 and the first power supply voltage terminal TVAA in accordance with the third signal S33. Connect to

That is, in the fifth embodiment, in the second period PSCD, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 is connected. The voltage is boosted to the potential (vaa + vref) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36D is turned on, and during the period when the switch SW36D is turned on, the boosted voltage (vaa + vref) is increased to the positive power supply voltage (first voltage). The first node ND31 supplies the first power supply voltage terminal TVAA of the row driver 310D as a voltage to be supplied higher than the power supply voltage).
Further, the voltage level of the first power supply voltage terminal TVAA is held at a stable level by the capacitor C32D.

Other configurations are the same as those of the first embodiment.
According to the fifth embodiment, according to the fifth embodiment, it is possible to obtain not only the same effects as those of the above-described first embodiment, but also a more favorable operation of supplying a boosted voltage. It can be realized.

(Sixth embodiment)
FIG. 15 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a sixth embodiment of the present invention.
FIGS. 16A to 16K are timing charts of the voltage generation operation and the like of the voltage supply unit 320E and the row driver 310E in the vertical scanning circuit 30E of the solid-state imaging device 10E according to the sixth embodiment.

The solid-state imaging device 10E according to the sixth embodiment differs from the solid-state imaging device 10A according to the above-described second embodiment in the following points.
In the voltage supply unit 320E of the solid-state imaging device 10E according to the sixth embodiment, the switch SW36E is connected between the first node ND31 and the first power supply voltage terminal TVAA of the row driver 310E. Is connected between the power supply voltage terminal TVAA and the first power supply potential line Lvaa of the positive power supply potential vaa.
The switch SW36E is turned on and off by the third signal S33, similarly to the third switch SW33, and selectively switches the first node ND31 and the first power supply voltage terminal TVAA in accordance with the third signal S33. Connect to

That is, in the sixth embodiment, in the second period PSCD, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 is connected. The voltage is boosted to the potential (vaa + vx (for example, vref)) by the capacitive coupling of the external capacitor Cext31, and in parallel with this, the switch SW36E is turned on, and the boosted voltage (vaa + vx (vref)) is positive while the switch SW36E is on. Is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310 as a voltage to be supplied higher than the power supply voltage (first power supply voltage).
In addition, the voltage level of the first power supply voltage terminal TVAA is held at a stable level by the capacitor C32E.

Other configurations are the same as those of the above-described second embodiment.
According to the sixth embodiment, not only the same effects as those of the above-described second embodiment can be obtained, but also it is possible to realize a more favorable boosted voltage supply operation.

(Seventh embodiment)
FIG. 17 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a seventh embodiment of the present invention.
FIGS. 18A to 18G are timing charts of the voltage generation operation and the like of the voltage supply unit 320F and the row driver 310F in the vertical scanning circuit 30F of the solid-state imaging device 10F according to the seventh embodiment.

The solid-state imaging device 10F according to the seventh embodiment is different from the solid-state imaging device 10B according to the third embodiment described above in the following points.
In the voltage supply unit 320F of the solid-state imaging device 10F according to the seventh embodiment, the switch SW36F is connected between the first node ND31 and the first power supply voltage terminal TVAA of the row driver 310F, and The capacitor C32F is connected between the power supply voltage terminal TVAA of the first power supply potential and the first power supply potential line Lvaa of the positive power supply potential vaa.
The switch SW36F is ON / OFF controlled by the third signal S33 similarly to the third switch SW33, and selectively switches the first node ND31 and the first power supply voltage terminal TVAA in accordance with the third signal S33. Connect to

That is, in the seventh embodiment, in the second period PSCD, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 is connected. The voltage is boosted to the potential (2vaa) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36F is turned on, and while the switch SW36F is on, the boosted voltage (2vaa) is raised to the positive power supply voltage (first voltage). The voltage to be supplied is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310F as a voltage to be supplied higher than the power supply voltage).
Also, the voltage level of the first power supply voltage terminal TVAA is held at a stable level by the capacitor C32F.

Note that the charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the voltage of the drive control signal DTG21 (vout1p) becomes slightly lower than the boosted voltage (2vaa).
Thereafter, the third signal S33 goes low, and the first signal S31 goes high again. At this time, the voltage level of the first node ND31 becomes vaa, but the node vhird (TVAA) is maintained at about 2 vaa.

Other configurations are the same as those of the third embodiment.
According to the seventh embodiment, not only the same effects as those of the above-described third embodiment can be obtained, but also a more favorable operation of supplying a step-down voltage can be realized.

(Eighth embodiment)
FIG. 19 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to an eighth embodiment of the present invention.
FIGS. 20A to 20K are timing charts of a voltage generation operation and the like of the voltage supply unit 320G and the row driver 310G in the vertical scanning circuit 30G of the solid-state imaging device 10G according to the eighth embodiment.

The solid-state imaging device 10G according to the eighth embodiment is different from the solid-state imaging device 10C according to the above-described fourth embodiment in the following points.
In the voltage supply unit 320G of the solid-state imaging device 10G according to the eighth embodiment, the switch SW36G is connected between the first node ND31 and the first power supply voltage terminal TVAA of the row driver 310G, and the first Is connected between the power supply voltage terminal TVAA and the first power supply potential line Lvaa of the positive power supply potential vaa.
The switch SW36G is ON / OFF controlled by the third signal S33 similarly to the third switch SW33, and selectively switches the first node ND31 and the first power supply voltage terminal TVAA in accordance with the third signal S33. Connect to

That is, in the eighth embodiment, in the second period PSCD, the third switch SW33 is turned on, the second node ND32 is connected to the first power supply potential line Lvaa, and the first node ND31 is connected. The voltage is reduced to the potential (vaa-vref) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36G is turned on, and during the period when the switch SW36 is turned on, the reduced voltage (vaa-vref) is set to the positive power supply voltage. The first power supply voltage is supplied from the first node ND31 to the first power supply voltage terminal TVAA of the row driver 310 as a voltage to be supplied lower than (first power supply voltage).
Also, the voltage level of the first power supply voltage terminal TVAA is held at a stable level by the capacitor C32G.

Other configurations are the same as those of the above-described fourth embodiment.
According to the eighth embodiment, not only the same effects as those of the above-described fourth embodiment can be obtained, but also a more favorable operation of supplying a step-down voltage can be realized.

(Ninth embodiment)
FIG. 21 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a ninth embodiment of the present invention.
FIGS. 22A to 22K are timing charts of a voltage generation operation and the like of the voltage supply unit 320H and the row driver 310H in the vertical scanning circuit 30H of the solid-state imaging device 10H according to the ninth embodiment.

The solid-state imaging device 10H according to the ninth embodiment is different from the solid-state imaging device 10B according to the above-described first embodiment in the following points.
In the voltage supply unit 320H of the solid-state imaging device 10H according to the ninth embodiment, instead of generating a voltage higher than the positive power supply voltage vaa, a voltage lower than the negative power supply voltage vgnd is generated, and the It is configured to supply power to the second power supply voltage terminal TVGND.
In the voltage supply unit 320H of the solid-state imaging device 10H according to the ninth embodiment, similarly to the first embodiment, a comparator CMP31H serving as a level determination unit 321H and a fifth switch SW35 are provided, and the low driver 310H is connected. Is configured to be adjustable to a voltage lower than the second power supply voltage (negative power supply voltage) vgnd.

In the solid-state imaging device 10H according to the ninth embodiment, similarly to the first embodiment, the reset period process is performed, and then the boost operation is performed in the first period PFST and the second period PSCD. Is performed.
Since the basic operation is the same as that of the first embodiment, a detailed description thereof will be omitted here.
The comparator CMP31H compares the potential level of the first node ND31 with the reference voltage vref2. If the potential level of the first node ND31 has not reached the reference voltage vref, the comparator CMP31H activates the first signal S31. The signal is output to the first switch SW31 at the H level to turn on the first switch SW31. When the potential level of the first node ND31 reaches the reference voltage vref2, the first signal S31 is changed to the inactive L level. Output to the first switch SW31 to turn off the first switch SW31.

Further, in the ninth embodiment, instead of providing the third switch SW33, the second power supply potential line Lvgnd of the second power supply potential vgnd and the first node ND31 are changed according to the fourth signal S34. A fourth switch SW34 that is selectively connected is provided.
When the fourth switch SW34 is included, the second node ND32 is connected to the second power supply voltage terminal TVGND of the row driver 310H.

  In the voltage supply unit 320H according to the ninth embodiment, the first switch SW31 and the second switch SW2 are activated by the active H-level first signal S31 and second signal S32 during the first period PFST after the reset period PRST. Is turned on, the fourth switch SW34 is turned off by the inactive L-level fourth signal S34, and the potential of the first node ND31 is set to the first power supply potential vaa. The potential of the node ND32 is set to a second power supply potential vgnd which is a reference potential.

Next, in the second period PSCD, the first signal S31 and the second signal S32 are switched to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the fourth signal S34 is turned off. The fourth switch SW34 is turned on by switching to the active H level.
As a result, the potential of the second node ND32 is lower than the second power supply potential vgnd, and is set to the potential −vref on the negative side up to the potential of the reference potential vref.

  In response to the control signal TG21, the row driver 310H applies a drive control signal DTG21 at the level of the voltage -vaa supplied from the voltage supply unit 320H to the corresponding drive control line LTG21.

  Note that the charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the voltage of the drive control signal DTG21 (vout1p) becomes slightly higher than the supply voltage -vref.

  According to the ninth embodiment, the same effects as those of the above-described first embodiment can be obtained.

(Tenth embodiment)
FIG. 23 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a tenth embodiment of the present invention.
FIGS. 24A to 24L are timing charts of the voltage supply unit 320I and the row driver 310I in the solid-state imaging device 10I according to the tenth embodiment.

The solid-state imaging device 10I according to the tenth embodiment differs from the solid-state imaging device 10H according to the ninth embodiment in the following points.
In the solid-state imaging device 10I according to the tenth embodiment, similarly to the relationship between the first embodiment and the ninth embodiment, the level determination unit 321I is configured by a counter CNT31I instead of the comparator.

In the tenth embodiment, as in the case of the above-described second embodiment, in the second period PSCD, the first signal S31 and the second signal S32 are set to the inactive L level, and With the first switch SW31 and the second switch SW32 turned off, the third signal S33 is switched to the active high H level.
As a result, the third switch SW33 is turned on, the second node ND32 is connected to the second power supply potential line Lvgnd, and the second node ND32 is connected to the potential (vgnd-vx (for example, by the capacitive coupling of the external capacitor Cext31). vref)).
This step-down voltage (vgnd-vx (vref)) is supplied from the second node ND31 to the second power supply voltage terminal TVGND of the row driver 310I as a voltage to be supplied lower than the negative power supply voltage (second power supply voltage). You.

  In the tenth embodiment, when the count value, that is, the number of clocks CLK0 changes, the potential level VND32 (vgnd-vx) of the second node ND32 can be adjusted.

Other configurations are the same as in the ninth embodiment.
According to the tenth embodiment, the same effects as those of the above-described first and ninth embodiments can be obtained.

(Eleventh embodiment)
FIG. 25 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to an eleventh embodiment of the present invention.
FIGS. 26A to 26G are timing charts of a voltage generation operation and the like of the voltage supply unit 320J and the row driver 310J in the vertical scanning circuit 30J of the solid-state imaging device 10J according to the eleventh embodiment.

The solid-state imaging device 10J according to the eleventh embodiment differs from the solid-state imaging device 10B according to the third embodiment described above in the following points.
The voltage supply unit 320J of the solid-state imaging device 10J according to the eleventh embodiment generates a voltage lower than the negative power supply voltage vgnd instead of generating a voltage higher than the positive power supply voltage vaa, and It is configured to supply power to the second power supply voltage terminal TVGND.

Specifically, instead of providing the third switch SW33, the second power supply potential line Lvgnd of the second power supply potential vgnd and the first node ND31 are selectively connected in accordance with the fourth signal S34. A fourth switch SW34 is provided.
When the fourth switch SW34 is included, the second node ND32 is connected to the second power supply voltage terminal TVGND of the row driver 310J.

  In the voltage supply unit 320J of the eleventh embodiment, the first switch SW31 and the second switch SW32 are turned on by the active H-level first signal S31 and second signal S32 during the first period PFST. Then, the fourth switch SW34 is turned off by the inactive L-level fourth signal S34, the potential of the first node ND31 is set to the first power supply potential vaa, and the potential of the second node ND32 is The second power supply potential vgnd, which is a reference potential, is set.

Next, in the second period PSCD, the first signal S31 and the second signal S32 are switched to the inactive L level to turn off the first switch SW31 and the second switch SW32, and the fourth signal S34 is turned off. The fourth switch SW34 is turned on by switching to the active H level.
As a result, the potential of the second node ND32 is set lower than the second power supply potential vgnd, and is set to the potential -vaa on the negative side up to the first power supply potential vaa.

  In response to the control signal TG21, the row driver 310J applies the drive control signal DTG21 at the level of the voltage -vaa supplied from the voltage supply unit 320C to the corresponding drive control line LTG21.

  Note that the charge of the external capacitor Cext31 is divided by the capacitor Cext31 and the load capacitance of the pixel array of the pixel unit 20, and the voltage of the drive control signal DTG21 (vout1p) becomes slightly higher than the supply voltage -vaa.

  According to the eleventh embodiment, the same effects as those of the third embodiment can be obtained.

(Twelfth embodiment)
FIG. 27 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a twelfth embodiment of the present invention.
FIGS. 28A to 28K are timing charts of the voltage generation operation and the like of the voltage supply unit 320K and the row driver 310K in the vertical scanning circuit 30K of the solid-state imaging device 10K according to the eleventh embodiment.

The solid-state imaging device 10K according to the twelfth embodiment is different from the solid-state imaging device 10H according to the ninth embodiment in the following points.
In the voltage supply unit 320K of the solid-state imaging device 10K according to the twelfth embodiment, instead of generating a voltage lower than the negative power supply voltage vgnd, a voltage higher than the negative power supply voltage vgnd is generated to generate a voltage higher than the negative power supply voltage vgnd. It is configured to supply power to the second power supply voltage terminal TVGND.
The solid-state imaging device 10K according to the twelfth embodiment differs from the solid-state imaging device 10 according to the ninth embodiment in the configuration of the voltage supply unit 320K.

  The voltage supply unit 320K generates a voltage higher than the second power supply voltage (negative power supply voltage) vgnd, for example, (vgnd + vref), and supplies it to the row driver 310K.

The first switch SW31 selectively connects the first power supply potential line Lvaa and the second node ND32 according to the first signal S31.
The second switch SW32 selectively connects the second power supply potential line Lvgnd to the first node ND31 according to the second signal S32.
The fourth switch SW34 selectively connects the second power supply potential line Lvgnd to the first node ND31 according to the fourth signal S34.
As described above, in the voltage supply unit 320K including the fourth switch SW34, the second node ND32 is connected to the second power supply voltage terminal TVGND of the row driver 310K.
Further, the fifth switch SW35 is formed of, for example, an NMOS transistor, and selectively connects the first node ND31 and the second node ND32 according to a fifth signal S35.

  The level determining unit 321K of the twelfth embodiment includes a comparator CMP31K having a non-inverting input (+) connected to a supply line for the reference voltage vref, and an inverting input terminal (-) connected to a second node ND32. It is configured.

The comparator CMP31K compares the potential level VND32 of the second node ND32 with the reference voltage vref, and when the potential level VND32 of the second node ND32 is lower than the reference voltage vref, activates the first signal S31. An H level is output to the first switch SW31 to turn on the first switch SW31.
When the potential level VND32 of the second node ND32 has reached the reference voltage vref, the comparator CMP31C outputs the first signal S31 to the first switch SW31 at the inactive L level to output the first switch SW31. Off.

  When generating the voltage (vgnd + vref) higher than the negative power supply voltage supplied to the row driver 310K, the voltage supply unit 320K in the twelfth embodiment includes a reset period PRST, a first period PFST, and a second period PSCD. , A voltage (vgnd + vref) higher than the desired level of the negative power supply voltage vgnd is generated and supplied to the row driver 310K.

The specific control timing is the same as in the case where the boosted voltage is -vref.
However, when the voltage level of the second node ND32 becomes + vref, the first node ND31 is connected to the second power supply voltage line LVGND, so it can be said that this operation is not pump-up.
The boost voltage + vref can be adjusted when the reference voltage vref changes.

  According to the twelfth embodiment, the same effects as those of the ninth embodiment can be obtained.

(Thirteenth embodiment)
FIG. 29 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a thirteenth embodiment of the present invention.
FIGS. 30A to 30K are timing charts of a voltage generation operation and the like of the voltage supply unit 320L and the row driver 310L in the vertical scanning circuit 30L of the solid-state imaging device 10L according to the thirteenth embodiment.

The difference between the solid-state imaging device 10L according to the thirteenth embodiment and the solid-state imaging device 10H according to the ninth embodiment is as follows.
In the voltage supply unit 320L of the solid-state imaging device 10L according to the thirteenth embodiment, the switch SW36L is connected between the second node ND32 and the second power supply voltage terminal TVGND of the row driver 310L. The capacitor C32L is connected between the power supply voltage terminal TVGND and the second power supply potential line Lvgnd of the negative power supply potential vgnd.
The switch SW36L is ON / OFF controlled by the fourth signal S34, similarly to the fourth switch SW34, and selectively switches the second node ND32 and the second power supply voltage terminal TVGND according to the fourth signal S34. Connect to

That is, in the thirteenth embodiment, in the second period PSCD, the fourth switch SW34 is turned on, the first node ND31 is connected to the second power supply potential line Lvgnd, and the second node ND32 is connected. The voltage is lowered to the negative potential (-vref) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36L is turned on, and during the period when the switch SW36L is turned on, the reduced voltage (-vref) is set to the negative power supply. The voltage to be supplied is lower than the voltage (second power supply voltage) and supplied from the second node ND32 to the second power supply voltage terminal TVGND of the row driver 310L.
Further, the voltage level of the second power supply voltage terminal TVGND is held at a stable level by the capacitor C32L.

Other configurations are the same as those of the ninth embodiment.
According to the thirteenth embodiment, not only the same effects as those of the ninth embodiment described above can be obtained, but also a more favorable operation of supplying a step-down voltage can be realized.

(14th embodiment)
FIG. 31 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fourteenth embodiment of the present invention.
FIGS. 32A to 32L are timing charts of a voltage generation operation and the like of the voltage supply unit 320M and the row driver 310M in the vertical scanning circuit 30M of the solid-state imaging device 10M according to the fourteenth embodiment.

The solid-state imaging device 10M according to the fourteenth embodiment is different from the solid-state imaging device 10I according to the above-described tenth embodiment in the following points.
In the voltage supply unit 320M of the solid-state imaging device 10M according to the fourteenth embodiment, the switch SW36M is connected between the second node ND32 and the second power supply voltage terminal TVGND of the row driver 310M, and Is connected between the power supply voltage terminal TVGND and the second power supply potential line Lvgnd of the negative power supply potential vgnd.
The switch SW36M is ON / OFF controlled by the fourth signal S34, similarly to the fourth switch SW34, and selectively switches the second node ND32 and the second power supply voltage terminal TVGND in accordance with the fourth signal S34. Connect to

That is, in the fourteenth embodiment, in the second period PSCD, the fourth switch SW34 is turned on, the first node ND31 is connected to the second power supply potential line Lvgnd, and the second node ND32 is connected. Due to the capacitive coupling of the external capacitor Cext31, the voltage is lowered to the negative potential (-vx (for example, vref)). In parallel with this, the switch SW36M is turned on, and the reduced voltage (-vx ( vref)) is supplied from the second node ND32 to the second power supply voltage terminal TVGND of the row driver 310M as a voltage to be supplied lower than the negative power supply voltage (second power supply voltage).
The voltage level of the second power supply voltage terminal TVGND is held at a stable level by the capacitor C32M.

Other configurations are the same as those of the above-described tenth embodiment.
According to the fourteenth embodiment, not only the same effects as those of the tenth embodiment described above can be obtained, but also a more favorable operation of supplying a step-down voltage can be realized.

(Fifteenth embodiment)
FIG. 33 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a fifteenth embodiment of the present invention.
FIGS. 34A to 34H are timing charts of the voltage generation operation and the like of the voltage supply unit 320N and the row driver 310N in the vertical scanning circuit 30N of the solid-state imaging device 10N according to the fifteenth embodiment.

The solid-state imaging device 10N according to the fifteenth embodiment is different from the solid-state imaging device 10M according to the eleventh embodiment in the following points.
In the voltage supply unit 320N of the solid-state imaging device 10N according to the fifteenth embodiment, the switch SW36N is connected between the second node ND32 and the second power supply voltage terminal TVGND of the row driver 310N, and Is connected between the power supply voltage terminal TVGND and the second power supply potential line Lvgnd of the negative power supply potential vgnd.
The switch SW36N is ON / OFF controlled by the fourth signal S34, similarly to the fourth switch SW34, and selectively switches the second node ND32 and the second power supply voltage terminal TVGND in accordance with the fourth signal S34. Connect to

That is, in the fifteenth embodiment, in the second period PSCD, the fourth switch SW34 is turned on, the first node ND31 is connected to the second power supply potential line Lvgnd, and the second node ND32 is connected. The voltage is stepped down to the negative potential (−vaa) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36N is turned on, and during the period when the switch SW36N is turned on, this stepped-down voltage (−vaa) is a negative power supply. A voltage to be supplied lower than the voltage (second power supply voltage) is supplied from the second node ND32 to the second power supply voltage terminal TVGND of the row driver 310N.
Further, the voltage level of the second power supply voltage terminal TVGND is held at a stable level by the capacitor C32N.

Other configurations are similar to those of the above-described eleventh embodiment.
According to the fifteenth embodiment, not only the same effects as those of the eleventh embodiment described above can be obtained, but also a more favorable operation of supplying a step-down voltage can be realized.

(Sixteenth embodiment)
FIG. 35 is a diagram illustrating a configuration example of a pixel unit and a vertical scanning circuit of a solid-state imaging device according to a sixteenth embodiment of the present invention.
FIGS. 36A to 36K are timing charts of the voltage generation operation of the voltage supply unit 320O and the row driver 310O in the vertical scanning circuit 300 of the solid-state imaging device 100 according to the sixteenth embodiment.

The solid-state imaging device 100 according to the sixteenth embodiment is different from the solid-state imaging device 10K according to the twelfth embodiment in the following points.
In the voltage supply unit 320O of the solid-state imaging device 100 according to the sixteenth embodiment, the switch SW36O is connected between the second node ND32 and the second power supply voltage terminal TVGND of the row driver 310O, and Is connected between the power supply voltage terminal TVGND and the second power supply potential line Lvgnd of the negative power supply potential vgnd.
The switch SW36O is turned on and off by the fourth signal S34, similarly to the fourth switch SW34, and selectively connects the second node ND32 and the second power supply voltage terminal TVGND in accordance with the fourth signal S34. Connect to

That is, in the sixteenth embodiment, in the second period PSCD, the fourth switch SW34 is turned on, the first node ND31 is connected to the second power supply potential line Lvgnd, and the second node ND32 is connected. The voltage is boosted to the positive potential (vref) by the capacitive coupling of the external capacitor Cext31. In parallel with this, the switch SW36O is turned on, and during the period when the switch SW36O is turned on, this boosted voltage (vref) becomes negative power supply voltage ( The second power supply voltage is supplied from the second node ND32 to the second power supply voltage terminal TVGND of the row driver 310O as a voltage to be supplied higher than the second power supply voltage).
Further, the voltage level of the second power supply voltage terminal TVGND is the capacitor C32O.
Is maintained at a more stable level.

Other configurations are the same as those of the twelfth embodiment.
According to the sixteenth embodiment, not only the same effects as those of the twelfth embodiment described above can be obtained, but also a more favorable boosted voltage supply operation can be realized.

  The solid-state imaging devices 10, 10A to 100 described above can be applied as imaging devices to digital cameras, video cameras, portable terminals, or electronic devices such as monitoring cameras and medical endoscope cameras.

  FIG. 37 is a diagram illustrating an example of a configuration of an electronic apparatus including a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

As shown in FIG. 37, the electronic device 800 includes a CMOS image sensor 810 to which the solid-state imaging device 10, 10A to 100 according to the present embodiment can be applied.
Further, the electronic device 800 has an optical system (such as a lens) 820 that guides incident light to the pixel region of the CMOS image sensor 810 (forms a subject image).
The electronic device 800 includes a signal processing circuit (PRC) 830 that processes an output signal of the CMOS image sensor 810.

The signal processing circuit 830 performs predetermined signal processing on the output signal of the CMOS image sensor 810.
The image signal processed by the signal processing circuit 830 can be displayed as a moving image on a monitor such as a liquid crystal display or output to a printer, or can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-described solid-state imaging devices 10 and 10A to 100 as the CMOS image sensor 810, it is possible to provide a high-performance, compact, and low-cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras used in applications where the requirements for camera installation are limited by mounting size, number of connectable cables, cable length, installation height, etc. Can be realized.

  10, 10A to 10O: solid-state imaging device, 20, 20A to 20O: pixel unit, PXL20: pixel, PD21: photodiode, TG21-Tr: transfer transistor, RST21-Tr ...・ Reset transistor, SF21-Tr ・ ・ ・ Source follower transistor, FD21 ・ ・ ・ Floating diffusion, 30 ・ ・ ・ Vertical scanning circuit, 310 ・ ・ ・ Low driver, 320 ・ ・ ・ Voltage supply unit, 321 ・ ・ ・ Level judgment , CMP31, CMP31D: comparator, CNT: counter, ND31: first node, ND32: second node, Cext31: capacitor, vaa: first power supply potential (Positive power supply potential), Lvaa ... first power supply potential line, vgnd ... second power supply potential (negative power supply potential) ), Lvgnd: second power supply potential line, SW31: first switch, SW32: second switch, SW33: third switch, SW34: fourth switch, SW35 ... Fifth switch, SW36D to SW36G, SW36L to SW36O ... Switch, C36D to C36G, C36L to C36O ... Capacitor, 40 ... Readout circuit (column readout circuit), 50 ... Horizontal scanning Circuit, 60 timing control circuit, 70 reading unit, 800 electronic equipment, 810 CMOS image sensor, 820 optical system, 830 signal processing circuit (PRC).

Claims (21)

A pixel portion in which a plurality of pixels are arranged in a matrix,
A read unit that applies a drive control signal of a predetermined level according to the control signal to a predetermined control signal line and reads pixel signals from the pixel unit in units of one or more rows,
The reading unit,
A driver for applying the drive control signal having a voltage level supplied in response to the control signal to the corresponding control signal line;
A voltage supply unit that supplies the driver with a voltage different from the first power supply voltage or a voltage different from the second power supply voltage,
The voltage supply unit includes:
A first node;
A second node;
A capacitor having a first electrode connected to the first node and a second electrode connected to the second node;
A first power supply potential;
A second power supply potential;
A first switch for selectively connecting the first power supply potential to the first node or the second node according to a first signal;
A second switch for selectively connecting the second power supply potential and the second node or the first node in accordance with a second signal, further comprising:
A third switch for selectively connecting the first power supply potential and the second node according to a third signal;
A fourth switch that selectively connects the second power supply potential and the first node in accordance with a fourth signal,
When including the third switch, the first node is connected to a first power supply voltage terminal of the driver;
In a case where the fourth switch is included, the second node is connected to a second power supply voltage terminal of the driver. The voltage supply unit includes:
A third switch for selectively connecting the first power supply potential and the second node in accordance with a third signal, and supplying a voltage higher than a positive first power supply voltage to the driver; If you do
In the first period,
The first switch and the second switch are turned on by the active first signal and the second signal, and the third switch is turned off by the inactive third signal, Setting the potential of one node to the first power supply potential, setting the potential of the second node to the second power supply potential that is a reference potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the third signal and turning on the third switch, Setting the potential of the first node to a potential higher by a predetermined potential than the first power supply potential;
The driver is
In a state in which a voltage higher than the first power supply voltage generated in the second period is supplied, the control signal is received, and the control corresponding to the drive control signal having a voltage level higher than the first power supply voltage is performed. The solid-state imaging device according to claim 1, wherein the voltage is applied to a signal line. The voltage supply unit includes:
A third switch for selectively connecting the first power supply potential and the second node in accordance with a third signal, and supplying a voltage lower than a positive first power supply voltage to the driver; If you do
In the first period,
The first switch and the second switch are turned on by the active first signal and the second signal, and the third switch is turned off by the inactive third signal, Setting the potential of one node to the second power supply potential as a reference potential, setting the potential of the second node to the first power supply potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the third signal and turning on the third switch, Setting the potential of the first node to a potential lower than the first power supply potential by a predetermined potential;
The driver is
In a state where a voltage lower than the first power supply voltage generated during the second period is supplied, the control signal is received and the control corresponding to the drive control signal having a voltage level lower than the first power supply voltage is performed. The solid-state imaging device according to claim 1, wherein the voltage is applied to a signal line. 4. The solid-state imaging device according to claim 1, further comprising a switch that selectively connects a first power supply voltage terminal on a positive side of the driver and the first node. 5. The solid-state imaging device according to claim 4, further comprising a capacitor connected to a first power supply voltage terminal on a positive side of the driver. The voltage supply unit includes:
And a fourth switch for selectively connecting the second power supply potential and the first node in accordance with a fourth signal, and supplying a voltage lower than a negative second power supply voltage to the driver. If you do
In the first period,
The first switch and the second switch are turned on by the active first signal and the second signal, and the fourth switch is turned off by the inactive fourth signal; Setting the potential of one node to the first power supply potential, setting the potential of the second node to the second power supply potential that is a reference potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the fourth signal to turn on the fourth switch, Setting the potential of the second node to a potential lower than the second power supply potential and up to a predetermined potential on the negative side;
The driver is
In a state where a voltage lower than a second power supply voltage generated during the second period is supplied, the control signal is received and the control corresponding to the drive control signal having a voltage level lower than the second power supply voltage is performed. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is applied to a signal line. The voltage supply unit includes:
And a fourth switch for selectively connecting the second power supply potential and the first node in accordance with a fourth signal, for supplying a voltage higher than a negative second power supply voltage to the driver. If you do
In the first period,
The first switch and the second switch are turned on by the active first signal and the second signal, and the fourth switch is turned off by the inactive fourth signal; Setting the potential of one node to the second power supply potential as a reference potential, setting the potential of the second node to the first power supply potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the fourth signal to turn on the fourth switch, Setting the potential of the second node to a potential higher than the second power supply potential and up to a predetermined potential on the positive side;
The driver is
In a state where a voltage higher than a second power supply voltage generated in the second period is supplied, the control signal is received, and the control corresponding to the drive control signal having a voltage level higher than the second power supply voltage is performed. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is applied to a signal line. The solid-state imaging device according to claim 1, further comprising a switch configured to selectively connect a second power supply voltage terminal on a negative side of the driver and the second node. The solid-state imaging device according to claim 8, further comprising a capacitor connected to a second power supply terminal on a negative side of the driver. The voltage supply unit includes:
When it is determined that the potential level of the first node or the second node has not reached the reference voltage, the first signal is actively output to the first switch and the first signal is output to the first switch. A switch is turned on, and when it is determined that the potential level of the first node or the second node has reached the reference voltage, the first signal is inactively output to the first switch to output the first signal to the first switch. The solid-state imaging device according to any one of claims 2 to 9, further comprising a level determination unit that turns off the first switch. The level determination unit includes:
The potential level of the first node is compared with a reference voltage. If the potential level of the first node or the second node does not reach the reference voltage, the first signal is activated. The first signal is output to the first switch to turn on the first switch, and when the potential level of the first node or the second node reaches the reference voltage, the first signal is deactivated. The solid-state imaging device according to claim 10, further comprising: a comparator that outputs to the first switch to turn off the first switch. The level determination unit includes:
Counting the clock, and when the count value is a value corresponding to the case where the potential level of the first node or the second node has not reached the reference voltage, the first signal is activated to activate the first signal. 1 to turn on the first switch. When the potential level of the first node or the second node reaches a value corresponding to the case where the potential level has reached the reference voltage, the first switch is turned on. The solid-state imaging device according to claim 10, further comprising a counter that inactively outputs a signal to the first switch to turn off the first switch. The level determination unit performs a level determination process when the enable signal is active,
The voltage supply unit includes:
A fifth switch that selectively connects the first node and the second node according to a fifth signal;
And a third switch for selectively connecting the first power supply potential and the second node in response to a third signal, wherein the driver has a higher voltage or a lower voltage than a positive first power supply voltage. When supplying voltage,
A reset period is set before the first period,
In the reset period,
In a state in which the enable signal is deactivated, the level determination unit is kept in an inactive state, and the first switch is turned off by the deactivated first signal,
The second switch and the fifth switch are turned on by the active second signal and the fifth signal, and the third switch is turned off by the inactive third signal, Setting and resetting the first node and the second node to the second power supply potential;
In the first period,
The solid-state imaging device according to any one of claims 10 to 12, wherein the enable signal is activated, the level determination unit is held in an operating state, and the first switch is turned on by the active first signal. The level determination unit performs a level determination process when the enable signal is active,
The voltage supply unit includes:
A fifth switch that selectively connects the first node and the second node according to a fifth signal;
A fourth switch for selectively connecting the second power supply potential and the first node in accordance with a fourth signal, wherein a lower voltage or a higher voltage than a negative second power supply voltage is supplied to the driver; When supplying voltage,
A reset period is set before the first period,
In the reset period,
In a state in which the enable signal is deactivated, the level determination unit is kept in an inactive state, and the first switch is turned off by the deactivated first signal,
The second switch and the fifth switch are turned on by the active second signal and the fifth signal, and the fourth switch is turned off by the inactive fourth signal; Setting the first node and the second node to the second power supply potential and resetting;
In the first period,
The solid-state imaging device according to any one of claims 10 to 12, wherein the enable signal is activated, the level determination unit is held in an operating state, and the first switch is turned on by the active first signal. The pixel is
A photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period;
A transfer element capable of transferring the charge accumulated in the photoelectric conversion element during a transfer period in which a transfer drive control signal is applied to the corresponding drive control line,
Floating diffusion in which the charge accumulated in the photoelectric conversion element is transferred through the transfer element,
A source follower element that converts the electric charge of the floating diffusion into a voltage signal according to the amount of electric charge, and outputs the converted signal to an output node,
The solid-state imaging device according to any one of claims 1 to 14, further comprising: a reset element configured to reset the floating diffusion to a predetermined potential during a reset period in which a reset drive control signal is applied to the corresponding drive control line. . A pixel portion in which a plurality of pixels are arranged in a matrix,
A read unit that applies a drive control signal of a predetermined level according to the control signal to a predetermined control signal line and reads pixel signals from the pixel unit in units of one or more rows,
The reading unit,
A driver for applying the drive control signal having a voltage level supplied in response to the control signal to the corresponding control signal line;
A voltage supply unit that supplies the driver with a voltage different from the first power supply voltage or a voltage different from the second power supply voltage,
The voltage supply unit includes:
A first node;
A second node;
A capacitor having a first electrode connected to the first node and a second electrode connected to the second node;
A first power supply potential;
A second power supply potential;
A first switch for selectively connecting the first power supply potential and the first node or the second node according to a first signal;
A second switch for selectively connecting the second power supply potential and the second node or the first node according to a second signal;
A third switch for selectively connecting the first power supply potential and the second node in accordance with a third signal, wherein the first node is a first power supply voltage terminal of the driver. A method for driving a solid-state imaging device connected to
In the first period,
Turning on the first switch and the second switch by the active first signal and the second signal, and turning off the third switch by the inactive third signal;
Setting the potential of the first node to the first power supply potential, setting the potential of the second node to the second power supply potential that is a reference potential, or
Setting the potential of the first node to the second power supply potential that is a reference potential, setting the potential of the second node to the first power supply potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the third signal to turn on the third switch,
Setting the potential of the first node to a potential higher than the first power supply potential by a predetermined potential, or
Setting the potential of the first node to a potential lower than the first power supply potential by a predetermined potential;
In the driver,
In a state in which a voltage higher than the first power supply voltage generated in the second period is supplied, the control signal is received, and the control corresponding to the drive control signal having a voltage level higher than the first power supply voltage is performed. Applied to the signal line, or
In a state where a voltage lower than the first power supply voltage generated during the second period is supplied, the control signal is received and the control corresponding to the drive control signal having a voltage level lower than the first power supply voltage is performed. A method for driving a solid-state imaging device to be applied to a signal line. A pixel portion in which a plurality of pixels are arranged in a matrix,
A read unit that applies a drive control signal of a predetermined level according to the control signal to a predetermined control signal line and reads pixel signals from the pixel unit in units of one or more rows,
The reading unit,
A driver for applying the drive control signal having a voltage level supplied in response to the control signal to the corresponding control signal line;
A voltage supply unit that supplies the driver with a voltage different from the first power supply voltage or a voltage different from the second power supply voltage,
The voltage supply unit includes:
A first node;
A second node;
A capacitor having a first electrode connected to the first node and a second electrode connected to the second node;
A first power supply potential;
A second power supply potential;
A first switch for selectively connecting the first power supply potential to the first node or the second node according to a first signal;
A second switch for selectively connecting the second power supply potential to the second node or the first node according to a second signal;
A fourth switch for selectively connecting the second power supply potential and the first node in response to a fourth signal, wherein the second node is a second power supply voltage terminal of the driver. A method for driving a solid-state imaging device connected to
In the first period,
Turning on the first switch and the second switch by the active first signal and the second signal, and turning off the fourth switch by the inactive fourth signal;
Setting the potential of the first node to the first power supply potential, setting the potential of the second node to the second power supply potential that is a reference potential, or
Setting the potential of the first node to the second power supply potential that is a reference potential, setting the potential of the second node to the first power supply potential,
In the second period,
Deactivating the first signal and the second signal to turn off the first switch and the second switch, activating the fourth signal to turn on the fourth switch, Setting the potential of the second node to be lower than the second power supply potential and a potential up to the first power supply potential level on the negative side; or
Setting the potential of the second node to a potential higher than the second power supply potential and up to a predetermined potential on the positive side;
In the driver,
In a state where a voltage lower than a second power supply voltage generated in the second period is supplied, the control signal is received, and the control corresponding to the drive control signal having a voltage level lower than the second power supply voltage is performed. Applied to the signal line, or
In a state where a voltage higher than a second power supply voltage generated during the second period is supplied, the control signal is received and the control corresponding to the drive control signal having a voltage level higher than the second power supply voltage is performed. A method for driving a solid-state imaging device to be applied to a signal line. Providing a level determination unit in the voltage supply unit,
In the level determination unit,
When it is determined that the potential level of the first node or the second node has not reached the reference voltage, the first signal is actively output to the first switch and the first signal is output to the first switch. A switch is turned on, and when it is determined that the potential level of the first node or the second node has reached the reference voltage, the first signal is inactively output to the first switch to output the first signal to the first switch. 18. The method for driving a solid-state imaging device according to claim 16, wherein the first switch is turned off. The level determination unit performs a level determination process when the enable signal is active,
In the voltage supply unit,
A fifth switch for selectively connecting the first node and the second node in accordance with a fifth signal;
Providing the third switch for selectively connecting the first power supply potential and the second node in accordance with a third signal, and supplying a voltage higher than a positive first power supply voltage to the driver; If you do
Setting a reset period before the first period;
In the reset period,
In a state in which the enable signal is deactivated, the level determination unit is kept in an inactive state, and the first switch is turned off by the deactivated first signal,
The second switch and the fifth switch are turned on by the active second signal and the fifth signal, and the third switch is turned off by the inactive third signal; Setting and resetting one node and the second node to the second power supply potential or the first power supply potential,
In the first period,
The drive of the solid-state imaging device according to claim 16, wherein the enable signal is activated, the level determination unit is held in an operation state, and the first switch is turned on by the active first signal. Method. The level determination unit performs a level determination process when the enable signal is active,
In the voltage supply unit,
A fifth switch for selectively connecting the first node and the second node in accordance with a fifth signal;
Providing the fourth switch for selectively connecting the second power supply potential and the first node in accordance with a fourth signal, supplying a voltage lower than a negative second power supply voltage to the driver; If you do
Setting a reset period before the first period;
In the reset period,
In a state in which the enable signal is deactivated, the level determination unit is kept in an inactive state, and the first switch is turned off by the deactivated first signal,
The second switch and the fifth switch are turned on by the active second signal and the fifth signal, and the fourth switch is turned off by the inactive fourth signal; Setting and resetting one node and the second node to the second power supply potential or the first power supply potential,
In the first period,
20. The driving method of a solid-state imaging device according to claim 18, wherein the enable signal is activated, the level determination unit is held in an operation state, and the first switch is turned on by the active first signal. A solid-state imaging device;
An optical system that forms a subject image on the solid-state imaging device,
The solid-state imaging device,
A pixel portion in which a plurality of pixels are arranged in a matrix,
A read unit that applies a drive control signal of a predetermined level according to the control signal to a predetermined control signal line and reads pixel signals from the pixel unit in units of one or more rows,
The reading unit,
A driver for applying the drive control signal having a voltage level supplied in response to the control signal to the corresponding control signal line;
A voltage supply unit that supplies the driver with a voltage different from the first power supply voltage or a voltage different from the second power supply voltage,
The voltage supply unit includes:
A first node;
A second node;
A capacitor having a first electrode connected to the first node and a second electrode connected to the second node;
A first power supply potential;
A second power supply potential;
A first switch for selectively connecting the first power supply potential to the first node or the second node according to a first signal;
A second switch for selectively connecting the second power supply potential and the second node or the first node in accordance with a second signal, further comprising:
A third switch for selectively connecting the first power supply potential and the second node according to a third signal;
A fourth switch that selectively connects the second power supply potential and the first node in accordance with a fourth signal,
When including the third switch, the first node is connected to a first power supply voltage terminal of the driver;
In the case where the electronic device includes the fourth switch, the second node is connected to a second power supply voltage terminal of the driver.

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